1 #define MR_SIZE 0x10 2 #define MR_BASE 0x0 3 #define MR_LIM 0x8 4 #define KRM_SIZE 0x28 5 #define KRM_CPU_STATE 0x0 6 #define KRM_PC 0x8 7 #define KRM_SP 0x10 8 #define KRM_TRAPNO 0x18 9 #define KRM_FLAG 0x20 10 #define DR_CTL 0x0 11 #define DR_STAT 0x8 12 #define DR_ADDR 0x10 13 #define DR_ADDR_INCR 0x8 14 #define MSR_SIZE 0x10 15 #define MSR_NUM 0x0 16 #define MSR_TYPE 0x4 17 #define MSR_VALP 0x8 18 #define MSR_VAL 0x8 19 #define KRS_SIZE 0x140 20 #define KRS_GREGS 0x0 21 #define KRS_DR 0x8 22 #define KRS_DRCTL 0x8 23 #define KRS_DRSTAT 0x10 24 #define KRS_GDT 0x38 25 #define KRS_IDT 0x40 26 #define KRS_CR0 0x48 27 #define KRS_MSR 0x50 28 #define KRS_CPU_STATE 0x58 29 #define KRS_CURCRUMBIDX 0x68 30 #define KRS_CURCRUMB 0x70 31 #define KRS_CRUMBS 0x78 32 #define KRS_CRUMBS_INCR 0x28 33 #define CPU_ID 0x0 34 #define KREG_SIZE 0x8 35 #define REG_SHIFT 3 36 #define DRADDR_IDX(num) _CONST(_MUL(num, DR_ADDR_INCR)) 37 #define DRADDR_OFF(num) _CONST(DRADDR_IDX(num) + DR_ADDR) 38 #define KRS_DROFF(num) _CONST(DRADDR_OFF(num) + KRS_DR) 39 #define REG_OFF(reg) _CONST(_CONST(reg) << REG_SHIFT) 40 #define KDIREG_OFF(reg) _CONST(_MUL(KREG_SIZE, reg) + KRS_GREGS) 41 #define T_AST 0x400 42 #define LOCK_LEVEL 0xa 43 #define CLOCK_LEVEL 0xa 44 #define DISP_LEVEL 0xb 45 #define PIL_MAX 0xf 46 #define HIGH_LEVELS 0x5 47 #define CPU_INTR_ACTV_HIGH_LEVEL_MASK 0xf800 48 #define PIC_NSEOI 0x20 49 #define PIC_SEOI_LVL7 0x67 50 #define NANOSEC 0x3b9aca00 51 #define ADJ_SHIFT 0x4 52 #define SSLEEP 0x1 53 #define SRUN 0x2 54 #define SONPROC 0x6 55 #define T_INTR_THREAD 0x1 56 #define FREE_THREAD 0x0 57 #define TS_FREE 0x0 58 #define TS_ZOMB 0x8 59 #define TP_MSACCT 0x100 60 #define TP_WATCHPT 0x400 61 #define ONPROC_THREAD 0x4 62 #define S_READ 0x1 63 #define S_WRITE 0x2 64 #define S_EXEC 0x3 65 #define S_OTHER 0x0 66 #define NORMALRETURN 0x0 67 #define LWP_USER 0x1 68 #define LWP_SYS 0x2 69 #define LMS_USER 0x0 70 #define LMS_SYSTEM 0x1 71 #define SSE_MXCSR_EFLAGS 0x3f 72 #define FP_487 0x6 73 #define FP_486 0x6 74 #define FPU_CW_INIT 0x133f 75 #define FPU_EN 0x1 76 #define FPU_VALID 0x2 77 #define FP_NO 0x0 78 #define FP_SW 0x1 79 #define FP_HW 0x2 80 #define FP_287 0x2 81 #define FP_387 0x3 82 #define __FP_SSE 0x100 83 #define FP_FNSAVE 0x1 84 #define FP_FXSAVE 0x2 85 #define FP_XSAVE 0x3 86 #define AV_INT_SPURIOUS 0xffffffff 87 #define CPU_READY 0x2 88 #define CPU_QUIESCED 0x4 89 #define MCMD_PORT 0x20 90 #define SCMD_PORT 0xa0 91 #define MIMR_PORT 0x21 92 #define SIMR_PORT 0xa1 93 #define DMP_NOSYNC 0xc0000000 94 #define RW_WRITER 0x0 95 #define RW_READER 0x1 96 #define NSYSCALL 0x100 97 #define SE_32RVAL1 0x0 98 #define SE_32RVAL2 0x1 99 #define SE_64RVAL 0x2 100 #define MAXSYSARGS 0x8 101 #define NSEC_PER_CLOCK_TICK 0x989680 102 #define NSEC_PER_COUNTER_TICK 0x346 103 #define PITCTR0_PORT 0x40 104 #define PITCTL_PORT 0x43 105 #define PIT_COUNTDOWN 0x34 106 #define NBPW 0x4 107 #define DDI_ACCATTR_IO_SPACE 0x2 108 #define DDI_ACCATTR_DIRECT 0x8 109 #define DDI_ACCATTR_CPU_VADDR 0x4 110 #define DDI_DEV_AUTOINCR 0x1 111 #define MMU_STD_PAGESIZE 0x1000 112 #define MMU_STD_PAGEMASK 0xfffff000 113 #define FOUR_MEG 0x400000 114 #define TRAPTR_NENT 0x80 115 #define CPU_DTRACE_NOFAULT 0x1 116 #define CPU_DTRACE_BADADDR 0x4 117 #define CPU_DTRACE_ILLOP 0x20 118 #define MODS_NOUNLOAD 0x2 119 #define MODS_WEAK 0x1 120 #define MODS_INSTALLED 0x10 121 #define KPREEMPT_SYNC 0xffffffff 122