1/* 2 * Device Tree Include file for Marvell Armada 38x family of SoCs. 3 * 4 * Copyright (C) 2014 Marvell 5 * 6 * Lior Amsalem <alior@marvell.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9 * 10 * This file is dual-licensed: you can use it either under the terms 11 * of the GPL or the X11 license, at your option. Note that this dual 12 * licensing only applies to this file, and not this project as a 13 * whole. 14 * 15 * a) This file is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of the 18 * License, or (at your option) any later version. 19 * 20 * This file is distributed in the hope that it will be useful 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * Or, alternatively 26 * 27 * b) Permission is hereby granted, free of charge, to any person 28 * obtaining a copy of this software and associated documentation 29 * files (the "Software"), to deal in the Software without 30 * restriction, including without limitation the rights to use 31 * copy, modify, merge, publish, distribute, sublicense, and/or 32 * sell copies of the Software, and to permit persons to whom the 33 * Software is furnished to do so, subject to the following 34 * conditions: 35 * 36 * The above copyright notice and this permission notice shall be 37 * included in all copies or substantial portions of the Software. 38 * 39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 46 * OTHER DEALINGS IN THE SOFTWARE. 47 * 48 * $FreeBSD$ 49 */ 50 51#include "skeleton.dtsi" 52#include <dt-bindings/interrupt-controller/arm-gic.h> 53#include <dt-bindings/interrupt-controller/irq.h> 54 55#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) 56 57/ { 58 model = "Marvell Armada 38x family SoC"; 59 compatible = "marvell,armada380"; 60 61 aliases { 62 gpio0 = &gpio0; 63 gpio1 = &gpio1; 64 serial0 = &uart0; 65 serial1 = &uart1; 66 }; 67 68 pmu { 69 compatible = "arm,cortex-a9-pmu"; 70 interrupts-extended = <&mpic 3>; 71 }; 72 73 soc { 74 compatible = "marvell,armada380-mbus", "simple-bus"; 75 #address-cells = <2>; 76 #size-cells = <1>; 77 controller = <&mbusc>; 78 interrupt-parent = <&gic>; 79 pcie-mem-aperture = <0xe0000000 0x8000000>; 80 pcie-io-aperture = <0xe8000000 0x100000>; 81 82 bootrom { 83 compatible = "marvell,bootrom"; 84 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; 85 }; 86 87 devbus-bootcs { 88 compatible = "marvell,mvebu-devbus"; 89 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; 90 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 clocks = <&coreclk 0>; 94 status = "disabled"; 95 }; 96 97 devbus-cs0 { 98 compatible = "marvell,mvebu-devbus"; 99 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; 100 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 clocks = <&coreclk 0>; 104 status = "disabled"; 105 }; 106 107 devbus-cs1 { 108 compatible = "marvell,mvebu-devbus"; 109 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; 110 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; 111 #address-cells = <1>; 112 #size-cells = <1>; 113 clocks = <&coreclk 0>; 114 status = "disabled"; 115 }; 116 117 devbus-cs2 { 118 compatible = "marvell,mvebu-devbus"; 119 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; 120 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 clocks = <&coreclk 0>; 124 status = "disabled"; 125 }; 126 127 devbus-cs3 { 128 compatible = "marvell,mvebu-devbus"; 129 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; 130 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; 131 #address-cells = <1>; 132 #size-cells = <1>; 133 clocks = <&coreclk 0>; 134 status = "disabled"; 135 }; 136 137 internal-regs { 138 compatible = "simple-bus"; 139 #address-cells = <1>; 140 #size-cells = <1>; 141 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; 142 143 L2: cache-controller@8000 { 144 compatible = "arm,pl310-cache"; 145 reg = <0x8000 0x1000>; 146 cache-unified; 147 cache-level = <2>; 148 }; 149 150 scu@c000 { 151 compatible = "arm,cortex-a9-scu"; 152 reg = <0xc000 0x58>; 153 }; 154 155 timer@c200 { 156 compatible = "arm,cortex-a9-global-timer"; 157 reg = <0xc200 0x20>; 158 interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 159 clock-frequency = <800000000>; 160 clocks = <&coreclk 2>; 161 }; 162 163 timer@c600 { 164 compatible = "arm,cortex-a9-twd-timer"; 165 reg = <0xc600 0x20>; 166 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 167 clock-frequency = <800000000>; 168 clocks = <&coreclk 2>; 169 }; 170 171 gic: interrupt-controller@d000 { 172 compatible = "arm,cortex-a9-gic"; 173 #interrupt-cells = <3>; 174 #size-cells = <0>; 175 interrupt-controller; 176 reg = <0xd000 0x1000>, 177 <0xc100 0x100>; 178 }; 179 180 spi0: spi@10600 { 181 compatible = "marvell,armada-380-spi", 182 "marvell,orion-spi"; 183 reg = <0x10600 0x50>; 184 #address-cells = <1>; 185 #size-cells = <0>; 186 cell-index = <0>; 187 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&coreclk 0>; 189 status = "disabled"; 190 }; 191 192 spi1: spi@10680 { 193 compatible = "marvell,armada-380-spi", 194 "marvell,orion-spi"; 195 reg = <0x10680 0x50>; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 cell-index = <1>; 199 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 200 clocks = <&coreclk 0>; 201 status = "disabled"; 202 }; 203 204 i2c0: i2c@11000 { 205 compatible = "marvell,mv64xxx-i2c"; 206 reg = <0x11000 0x20>; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 210 timeout-ms = <1000>; 211 clocks = <&coreclk 0>; 212 status = "disabled"; 213 }; 214 215 i2c1: i2c@11100 { 216 compatible = "marvell,mv64xxx-i2c"; 217 reg = <0x11100 0x20>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 221 timeout-ms = <1000>; 222 clocks = <&coreclk 0>; 223 status = "disabled"; 224 }; 225 226 uart0: serial@12000 { 227 compatible = "snps,dw-apb-uart"; 228 reg = <0x12000 0x100>; 229 reg-shift = <2>; 230 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 231 reg-io-width = <1>; 232 clocks = <&coreclk 0>; 233 status = "disabled"; 234 }; 235 236 uart1: serial@12100 { 237 compatible = "snps,dw-apb-uart"; 238 reg = <0x12100 0x100>; 239 reg-shift = <2>; 240 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 241 reg-io-width = <1>; 242 clocks = <&coreclk 0>; 243 status = "disabled"; 244 }; 245 246 pinctrl: pinctrl@18000 { 247 reg = <0x18000 0x20>; 248 249 ge0_rgmii_pins: ge-rgmii-pins-0 { 250 marvell,pins = "mpp6", "mpp7", "mpp8", 251 "mpp9", "mpp10", "mpp11", 252 "mpp12", "mpp13", "mpp14", 253 "mpp15", "mpp16", "mpp17"; 254 marvell,function = "ge0"; 255 }; 256 257 ge1_rgmii_pins: ge-rgmii-pins-1 { 258 marvell,pins = "mpp21", "mpp27", "mpp28", 259 "mpp29", "mpp30", "mpp31", 260 "mpp32", "mpp37", "mpp38", 261 "mpp39", "mpp40", "mpp41"; 262 marvell,function = "ge1"; 263 }; 264 265 i2c0_pins: i2c-pins-0 { 266 marvell,pins = "mpp2", "mpp3"; 267 marvell,function = "i2c0"; 268 }; 269 270 mdio_pins: mdio-pins { 271 marvell,pins = "mpp4", "mpp5"; 272 marvell,function = "ge"; 273 }; 274 275 ref_clk0_pins: ref-clk-pins-0 { 276 marvell,pins = "mpp45"; 277 marvell,function = "ref"; 278 }; 279 280 ref_clk1_pins: ref-clk-pins-1 { 281 marvell,pins = "mpp46"; 282 marvell,function = "ref"; 283 }; 284 285 spi0_pins: spi-pins-0 { 286 marvell,pins = "mpp22", "mpp23", "mpp24", 287 "mpp25"; 288 marvell,function = "spi0"; 289 }; 290 291 spi1_pins: spi-pins-1 { 292 marvell,pins = "mpp56", "mpp57", "mpp58", 293 "mpp59"; 294 marvell,function = "spi1"; 295 }; 296 297 uart0_pins: uart-pins-0 { 298 marvell,pins = "mpp0", "mpp1"; 299 marvell,function = "ua0"; 300 }; 301 302 uart1_pins: uart-pins-1 { 303 marvell,pins = "mpp19", "mpp20"; 304 marvell,function = "ua1"; 305 }; 306 307 sdhci_pins: sdhci-pins { 308 marvell,pins = "mpp48", "mpp49", "mpp50", 309 "mpp52", "mpp53", "mpp54", 310 "mpp55", "mpp57", "mpp58", 311 "mpp59"; 312 marvell,function = "sd0"; 313 }; 314 315 sata0_pins: sata-pins-0 { 316 marvell,pins = "mpp20"; 317 marvell,function = "sata0"; 318 }; 319 320 sata1_pins: sata-pins-1 { 321 marvell,pins = "mpp19"; 322 marvell,function = "sata1"; 323 }; 324 325 sata2_pins: sata-pins-2 { 326 marvell,pins = "mpp47"; 327 marvell,function = "sata2"; 328 }; 329 330 sata3_pins: sata-pins-3 { 331 marvell,pins = "mpp44"; 332 marvell,function = "sata3"; 333 }; 334 }; 335 336 gpio0: gpio@18100 { 337 compatible = "marvell,orion-gpio"; 338 reg = <0x18100 0x40>; 339 ngpios = <32>; 340 gpio-controller; 341 #gpio-cells = <2>; 342 interrupt-controller; 343 #interrupt-cells = <2>; 344 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 348 }; 349 350 gpio1: gpio@18140 { 351 compatible = "marvell,orion-gpio"; 352 reg = <0x18140 0x40>; 353 ngpios = <28>; 354 gpio-controller; 355 #gpio-cells = <2>; 356 interrupt-controller; 357 #interrupt-cells = <2>; 358 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 362 }; 363 364 system-controller@18200 { 365 compatible = "marvell,armada-380-system-controller", 366 "marvell,armada-370-xp-system-controller"; 367 reg = <0x18200 0x100>; 368 }; 369 370 gateclk: clock-gating-control@18220 { 371 compatible = "marvell,armada-380-gating-clock"; 372 reg = <0x18220 0x4>; 373 clocks = <&coreclk 0>; 374 #clock-cells = <1>; 375 }; 376 377 coreclk: mvebu-sar@18600 { 378 compatible = "marvell,armada-380-core-clock"; 379 reg = <0x18600 0x04>; 380 #clock-cells = <1>; 381 }; 382 383 mbusc: mbus-controller@20000 { 384 compatible = "marvell,mbus-controller"; 385 reg = <0x20000 0x100>, <0x20180 0x20>; 386 }; 387 388 mpic: interrupt-controller@20a00 { 389 compatible = "marvell,mpic"; 390 reg = <0x20a00 0x2d0>, <0x21070 0x58>; 391 #interrupt-cells = <1>; 392 #size-cells = <1>; 393 interrupt-controller; 394 msi-controller; 395 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 396 }; 397 398 timer@20300 { 399 compatible = "marvell,armada-380-timer", 400 "marvell,armada-xp-timer"; 401 reg = <0x20300 0x30>, <0x21040 0x30>; 402 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 403 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 404 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 405 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 406 <&mpic 5>, 407 <&mpic 6>; 408 clocks = <&coreclk 2>, <&refclk>; 409 clock-names = "nbclk", "fixed"; 410 }; 411 412 watchdog@20300 { 413 compatible = "marvell,armada-380-wdt"; 414 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; 415 clocks = <&coreclk 2>, <&refclk>; 416 clock-names = "nbclk", "fixed"; 417 }; 418 419 cpurst@20800 { 420 compatible = "marvell,armada-370-cpu-reset"; 421 reg = <0x20800 0x10>; 422 }; 423 424 mpcore-soc-ctrl@20d20 { 425 compatible = "marvell,armada-380-mpcore-soc-ctrl"; 426 reg = <0x20d20 0x6c>; 427 }; 428 429 coherency-fabric@21010 { 430 compatible = "marvell,armada-380-coherency-fabric"; 431 reg = <0x21010 0x1c>; 432 }; 433 434 pmsu@22000 { 435 compatible = "marvell,armada-380-pmsu"; 436 reg = <0x22000 0x1000>; 437 }; 438 439 eth1: ethernet@30000 { 440 compatible = "marvell,armada-370-neta"; 441 reg = <0x30000 0x4000>; 442 interrupts-extended = <&mpic 10>; 443 clocks = <&gateclk 3>; 444 status = "disabled"; 445 }; 446 447 eth2: ethernet@34000 { 448 compatible = "marvell,armada-370-neta"; 449 reg = <0x34000 0x4000>; 450 interrupts-extended = <&mpic 12>; 451 clocks = <&gateclk 2>; 452 status = "disabled"; 453 }; 454 455 usb@58000 { 456 compatible = "marvell,orion-ehci"; 457 reg = <0x58000 0x500>; 458 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&gateclk 18>; 460 status = "disabled"; 461 }; 462 463 xor@60800 { 464 compatible = "marvell,orion-xor"; 465 reg = <0x60800 0x100 466 0x60a00 0x100>; 467 clocks = <&gateclk 22>; 468 status = "okay"; 469 470 xor00 { 471 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 472 dmacap,memcpy; 473 dmacap,xor; 474 }; 475 xor01 { 476 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 477 dmacap,memcpy; 478 dmacap,xor; 479 dmacap,memset; 480 }; 481 }; 482 483 xor@60900 { 484 compatible = "marvell,orion-xor"; 485 reg = <0x60900 0x100 486 0x60b00 0x100>; 487 clocks = <&gateclk 28>; 488 status = "okay"; 489 490 xor10 { 491 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 492 dmacap,memcpy; 493 dmacap,xor; 494 }; 495 xor11 { 496 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 497 dmacap,memcpy; 498 dmacap,xor; 499 dmacap,memset; 500 }; 501 }; 502 503 eth0: ethernet@70000 { 504 compatible = "marvell,armada-370-neta"; 505 reg = <0x70000 0x4000>; 506 interrupts-extended = <&mpic 8>; 507 clocks = <&gateclk 4>; 508 status = "disabled"; 509 }; 510 511 mdio: mdio@72004 { 512 #address-cells = <1>; 513 #size-cells = <0>; 514 compatible = "marvell,orion-mdio"; 515 reg = <0x72004 0x4>; 516 clocks = <&gateclk 4>; 517 }; 518 519 rtc@a3800 { 520 compatible = "marvell,armada-380-rtc"; 521 reg = <0xa3800 0x20>, <0x184a0 0x0c>; 522 reg-names = "rtc", "rtc-soc"; 523 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 524 }; 525 526 sata@a8000 { 527 compatible = "marvell,armada-380-ahci"; 528 reg = <0xa8000 0x2000>; 529 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&gateclk 15>; 531 status = "disabled"; 532 }; 533 534 sata@e0000 { 535 compatible = "marvell,armada-380-ahci"; 536 reg = <0xe0000 0x2000>; 537 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&gateclk 30>; 539 status = "disabled"; 540 }; 541 542 coredivclk: clock@e4250 { 543 compatible = "marvell,armada-380-corediv-clock"; 544 reg = <0xe4250 0xc>; 545 #clock-cells = <1>; 546 clocks = <&mainpll>; 547 clock-output-names = "nand"; 548 }; 549 550 thermal@e8078 { 551 compatible = "marvell,armada380-thermal"; 552 reg = <0xe4078 0x4>, <0xe4074 0x4>; 553 status = "okay"; 554 }; 555 556 flash@d0000 { 557 compatible = "marvell,armada370-nand"; 558 reg = <0xd0000 0x54>; 559 #address-cells = <1>; 560 #size-cells = <1>; 561 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&coredivclk 0>; 563 status = "disabled"; 564 }; 565 566 sdhci@d8000 { 567 compatible = "marvell,armada-380-sdhci"; 568 reg-names = "sdhci", "mbus", "conf-sdio3"; 569 reg = <0xd8000 0x1000>, 570 <0xdc000 0x100>, 571 <0x18454 0x4>; 572 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&gateclk 17>; 574 mrvl,clk-delay-cycles = <0x1F>; 575 status = "disabled"; 576 }; 577 578 usb3@f0000 { 579 compatible = "marvell,armada-380-xhci"; 580 reg = <0xf0000 0x4000>,<0xf4000 0x4000>; 581 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&gateclk 9>; 583 status = "disabled"; 584 }; 585 586 usb3@f8000 { 587 compatible = "marvell,armada-380-xhci"; 588 reg = <0xf8000 0x4000>,<0xfc000 0x4000>; 589 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&gateclk 10>; 591 status = "disabled"; 592 }; 593 }; 594 }; 595 596 pci0: pcie@f1080000 { 597 compatible = "mrvl,pcie"; 598 status = "disabled"; 599 device_type = "pci"; 600 #interrupt-cells = <3>; 601 #size-cells = <2>; 602 #address-cells = <3>; 603 reg = <0xf1080000 0x2000>; 604 bus-range = <0 255>; 605 ranges = <0x42000000 0x0 0xf1200000 0xf1200000 0x0 0x00100000 606 0x41000000 0x0 0x00000000 0xf1300000 0x0 0x00100000>; 607 interrupt-parent = <&gic>; 608 interrupts = <GIC_SPI 91 0>; 609 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 610 interrupt-map = < 611 0x0000 0x0 0x0 0x1 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 612 >; 613 }; 614 615 clocks { 616 /* 2 GHz fixed main PLL */ 617 mainpll: mainpll { 618 compatible = "fixed-clock"; 619 #clock-cells = <0>; 620 clock-frequency = <1000000000>; 621 }; 622 623 /* 25 MHz reference crystal */ 624 refclk: oscillator { 625 compatible = "fixed-clock"; 626 #clock-cells = <0>; 627 clock-frequency = <25000000>; 628 }; 629 }; 630}; 631