xref: /titanic_52/usr/src/data/perfmon/SKL/skylake_fp_arith_inst_v42.json (revision 5fc40de04b67592be50772c772ace24a75df2712) 
1[
2  {
3    "BitName": "SCALAR_DOUBLE",
4    "BitIndex": "0",
5    "FlopsMultiplier": "1",
6    "Description": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element."
7  },
8  {
9    "BitName": "SCALAR_SINGLE",
10    "BitIndex": "1",
11    "FlopsMultiplier": "1",
12    "Description": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element."
13  },
14  {
15    "BitName": "128BIT_PACKED_DOUBLE",
16    "BitIndex": "2",
17    "FlopsMultiplier": "2",
18    "Description": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element."
19  },
20  {
21    "BitName": "128BIT_PACKED_SINGLE",
22    "BitIndex": "3",
23    "FlopsMultiplier": "4",
24    "Description": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element."
25  },
26  {
27    "BitName": "256BIT_PACKED_DOUBLE",
28    "BitIndex": "4",
29    "FlopsMultiplier": "4",
30    "Description": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element."
31  },
32  {
33    "BitName": "256BIT_PACKED_SINGLE",
34    "BitIndex": "5",
35    "FlopsMultiplier": "8",
36    "Description": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element."
37  }
38]