1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27/* 28 * eversholt rules for generic-sparc sparc cpu errors. 29 * 30 * Most propagations are generated by preprocessor macros. The event 31 * declarations are deliberately not part of the propagation macros 32 * so that we know we have full coverage - propagations defined without 33 * events, or events not used in propagations, will produce compiler 34 * whinges. 35 */ 36 37#define DIAGNOSE_ERPT (payloadprop_defined("diagnose") && \ 38 payloadprop("diagnose") != 0x0) 39 40#define SET_SERDT (!payloadprop_defined("serd_t") || \ 41 setserdt(payloadprop("serd_t"))) 42 43#define SET_SERDN (!payloadprop_defined("serd_n") || \ 44 setserdn(payloadprop("serd_n"))) 45 46#define SET_RATIO \ 47 ((payloadprop_defined("filter_ratio") && \ 48 payloadprop("filter_ratio") != 0x0) ? \ 49 (setserdincrement(payloadprop("filter_ratio"))) : 1) 50 51/* 52 * The ereport and fault events are declared at multiple levels: 53 * some set of @chip, @core, and @strand resources since this is 54 * a generic DE and must be flexible and handle present and future 55 * sun4v platforms. For example, one processor may have an L2 56 * cache per chip, another may have an L2 per core. 57 * 58 * For UE errors, faults are produced immediately. 59 * 60 * For CE errors, the errors are put through a SERD engine. If 61 * the SERD engine trips, the fault is produced. SERD engine 62 * names are of the format: 63 * serd.cpu.generic-sparc.<resource><suffix> 64 * Ex: serd.cpu.generic-sparc.chipitlb 65 * SERD N/T values are set to default values, but can be 66 * overridden via the ereport or the eft.conf file. The 67 * order or precedence of the SERD N/T values is: 68 * - the 'serd_override' tunable via eft.conf 69 * - the 'serd_n' and 'serd_t' payload members in the 70 * incoming ereport 71 * - the built-in default values 72 * 73 * The increment rate of the SERD engines can also be 74 * controlled via the ereport payload using the 'filter_ratio' 75 * payload member. N in incremented by the value of 76 * 'filter_ratio' if the payload member is present, 1 otherwise. 77 */ 78/* 79 * Ereport event for cpu errors 80 */ 81#define ERPT_EVENT(level, leafclass) \ 82 event ereport.cpu.generic-sparc.leafclass@level { within(1s) } 83 84/* 85 * Ereports for uncorrectable cpu errors 86 */ 87ERPT_EVENT(chip, itlb-uc); 88ERPT_EVENT(core, itlb-uc); 89ERPT_EVENT(strand, itlb-uc); 90ERPT_EVENT(chip, dtlb-uc); 91ERPT_EVENT(core, dtlb-uc); 92ERPT_EVENT(strand, dtlb-uc); 93ERPT_EVENT(chip, icache-uc); 94ERPT_EVENT(core, icache-uc); 95ERPT_EVENT(chip, dcache-uc); 96ERPT_EVENT(core, dcache-uc); 97ERPT_EVENT(chip, ireg-uc); 98ERPT_EVENT(core, ireg-uc); 99ERPT_EVENT(strand, ireg-uc); 100ERPT_EVENT(chip, freg-uc); 101ERPT_EVENT(core, freg-uc); 102ERPT_EVENT(strand, freg-uc); 103ERPT_EVENT(chip, mreg-uc); 104ERPT_EVENT(core, mreg-uc); 105ERPT_EVENT(strand, mreg-uc); 106ERPT_EVENT(chip, l2data-uc); 107ERPT_EVENT(core, l2data-uc); 108ERPT_EVENT(chip, l2tagctl-uc); 109ERPT_EVENT(core, l2tagctl-uc); 110ERPT_EVENT(chip, l3data-uc); 111ERPT_EVENT(core, l3data-uc); 112ERPT_EVENT(chip, l3tagctl-uc); 113ERPT_EVENT(core, l3tagctl-uc); 114ERPT_EVENT(chip, int-mem-ue); 115ERPT_EVENT(core, int-mem-ue); 116ERPT_EVENT(strand, int-mem-ue); 117ERPT_EVENT(chip, gchip-uc); 118ERPT_EVENT(core, gcore-uc); 119ERPT_EVENT(strand, gstrand-uc); 120 121/* 122 * Propagations for CPU UE errors 123 * A fault is produced immediately for a CPU UE errors. 124 */ 125#define FLT_CPU_UE(level, erptleaf, fltleaf) \ 126 event fault.cpu.generic-sparc.fltleaf@level; \ 127 \ 128 prop fault.cpu.generic-sparc.fltleaf@level \ 129 { DIAGNOSE_ERPT } (0)-> \ 130 ereport.cpu.generic-sparc.erptleaf@level; \ 131 \ 132 event upset.cpu.generic-sparc.fltleaf@level; \ 133 \ 134 prop upset.cpu.generic-sparc.fltleaf@level \ 135 { !DIAGNOSE_ERPT } (0)-> \ 136 ereport.cpu.generic-sparc.erptleaf@level 137 138 139FLT_CPU_UE(chip, itlb-uc, chip-uc); 140FLT_CPU_UE(core, itlb-uc, core-uc); 141FLT_CPU_UE(strand, itlb-uc, strand-uc); 142FLT_CPU_UE(chip, dtlb-uc, chip-uc); 143FLT_CPU_UE(core, dtlb-uc, core-uc); 144FLT_CPU_UE(strand, dtlb-uc, strand-uc); 145FLT_CPU_UE(chip, icache-uc, chip-uc); 146FLT_CPU_UE(core, icache-uc, core-uc); 147FLT_CPU_UE(chip, dcache-uc, chip-uc); 148FLT_CPU_UE(core, dcache-uc, core-uc); 149FLT_CPU_UE(chip, ireg-uc, chip-uc); 150FLT_CPU_UE(core, ireg-uc, core-uc); 151FLT_CPU_UE(strand, ireg-uc, strand-uc); 152FLT_CPU_UE(chip, mreg-uc, chip-uc); 153FLT_CPU_UE(core, mreg-uc, core-uc); 154FLT_CPU_UE(strand, mreg-uc, strand-uc); 155FLT_CPU_UE(chip, freg-uc, chip-uc); 156FLT_CPU_UE(core, freg-uc, core-uc); 157FLT_CPU_UE(strand, freg-uc, strand-uc); 158FLT_CPU_UE(chip, l2data-uc, chip-uc); 159FLT_CPU_UE(core, l2data-uc, core-uc); 160FLT_CPU_UE(chip, l2tagctl-uc, chip-uc); 161FLT_CPU_UE(core, l2tagctl-uc, core-uc); 162FLT_CPU_UE(chip, l3data-uc, chip-uc); 163FLT_CPU_UE(core, l3data-uc, core-uc); 164FLT_CPU_UE(chip, l3tagctl-uc, chip-uc); 165FLT_CPU_UE(core, l3tagctl-uc, core-uc); 166FLT_CPU_UE(chip, gchip-uc, chip-uc); 167FLT_CPU_UE(core, gcore-uc, core-uc); 168FLT_CPU_UE(strand, gstrand-uc, strand-uc); 169 170 171 172#define FLT_CPU_UE_UNRETIRED(level, erptleaf, fltleaf) \ 173 event fault.cpu.generic-sparc.fltleaf@level, \ 174 retire=0; \ 175 \ 176 prop fault.cpu.generic-sparc.fltleaf@level \ 177 { DIAGNOSE_ERPT } (0)-> \ 178 ereport.cpu.generic-sparc.erptleaf@level; \ 179 \ 180 event upset.cpu.generic-sparc.fltleaf@level; \ 181 \ 182 prop upset.cpu.generic-sparc.fltleaf@level \ 183 { !DIAGNOSE_ERPT } (0)-> \ 184 ereport.cpu.generic-sparc.erptleaf@level 185 186FLT_CPU_UE_UNRETIRED(chip, int-mem-ue, chip-uc-nr); 187FLT_CPU_UE_UNRETIRED(core, int-mem-ue, core-uc-nr); 188FLT_CPU_UE_UNRETIRED(strand, int-mem-ue, strand-uc-nr); 189 190/* 191 * Ereport events for corectable errors. 192 */ 193ERPT_EVENT(chip, itlb); 194ERPT_EVENT(core, itlb); 195ERPT_EVENT(strand, itlb); 196ERPT_EVENT(chip, dtlb); 197ERPT_EVENT(core, dtlb); 198ERPT_EVENT(strand, dtlb); 199ERPT_EVENT(chip, icache); 200ERPT_EVENT(core, icache); 201ERPT_EVENT(chip, dcache); 202ERPT_EVENT(core, dcache); 203ERPT_EVENT(chip, ireg); 204ERPT_EVENT(core, ireg); 205ERPT_EVENT(strand, ireg); 206ERPT_EVENT(chip, freg); 207ERPT_EVENT(core, freg); 208ERPT_EVENT(strand, freg); 209ERPT_EVENT(chip, mreg); 210ERPT_EVENT(core, mreg); 211ERPT_EVENT(strand, mreg); 212ERPT_EVENT(chip, l2data); 213ERPT_EVENT(core, l2data); 214ERPT_EVENT(chip, l2tagctl); 215ERPT_EVENT(core, l2tagctl); 216ERPT_EVENT(chip, l3data); 217ERPT_EVENT(core, l3data); 218ERPT_EVENT(chip, l3tagctl); 219ERPT_EVENT(core, l3tagctl); 220ERPT_EVENT(chip, int-mem); 221ERPT_EVENT(core, int-mem); 222ERPT_EVENT(strand, int-mem); 223ERPT_EVENT(chip, gchip); 224ERPT_EVENT(core, gcore); 225ERPT_EVENT(strand, gstrand); 226 227/* 228 * Propagations for CE errors 229 * Errors are serded and fault is generated when the SERD engine trips 230 * The serd name & the N & T values are set at the running time. 231 */ 232engine serd.cpu.generic-sparc.core@core, N=8, T=1week; 233engine serd.cpu.generic-sparc.strand@strand, N=8, T=1week; 234 235 236#define FLT_CPU_CE(erptleaf, level, fltleaf, n, t) \ 237 \ 238 /* Simple fault event */ \ 239 event fault.cpu.generic-sparc.fltleaf@level, \ 240 engine=serd.cpu.generic-sparc.fltleaf@level; \ 241 \ 242 /* When the correctable engine trips, diagnose a fault */ \ 243 prop fault.cpu.generic-sparc.fltleaf@level \ 244 { DIAGNOSE_ERPT && setserdsuffix("erptleaf") && \ 245 setserdn(n) && setserdt(t) && SET_SERDN && \ 246 SET_SERDT && SET_RATIO } (0) -> \ 247 ereport.cpu.generic-sparc.erptleaf@level; \ 248 \ 249 event upset.cpu.generic-sparc.fltleaf@level; \ 250 \ 251 prop upset.cpu.generic-sparc.fltleaf@level \ 252 { !DIAGNOSE_ERPT } (0) -> \ 253 ereport.cpu.generic-sparc.erptleaf@level 254 255FLT_CPU_CE(itlb, core, core, 8, 1week); 256FLT_CPU_CE(itlb, strand, strand, 8, 1week); 257FLT_CPU_CE(dtlb, core, core, 8, 1week); 258FLT_CPU_CE(dtlb, strand, strand, 8, 1week); 259FLT_CPU_CE(icache, core, core, 8, 1week); 260FLT_CPU_CE(dcache, core, core, 8, 1week); 261FLT_CPU_CE(ireg, core, core, 8, 1week); 262FLT_CPU_CE(ireg, strand, strand, 8, 1week); 263FLT_CPU_CE(freg, core, core, 8, 1week); 264FLT_CPU_CE(freg, strand, strand, 8, 1week); 265FLT_CPU_CE(mreg, core, core, 8, 1week); 266FLT_CPU_CE(mreg, strand, strand, 8, 1week); 267FLT_CPU_CE(l2data, core, core, 8, 1week); 268FLT_CPU_CE(l2tagctl, core, core, 8, 1week); 269FLT_CPU_CE(l3data, core, core, 8, 1week); 270FLT_CPU_CE(l3tagctl, core, core, 8, 1week); 271FLT_CPU_CE(gcore, core, core, 8, 1week); 272FLT_CPU_CE(gstrand, strand, strand, 8, 1week); 273 274engine serd.cpu.generic-sparc.chip-nr@chip, N=8, T=1week; 275engine serd.cpu.generic-sparc.core-nr@core, N=8, T=1week; 276engine serd.cpu.generic-sparc.strand-nr@strand, N=8, T=1week; 277 278#define FLT_CPU_CE_UNRETIRED(erptleaf, level, fltleaf, n, t) \ 279 \ 280 /* Simple fault event */ \ 281 event fault.cpu.generic-sparc.fltleaf@level, \ 282 retire=0, \ 283 engine=serd.cpu.generic-sparc.fltleaf@level; \ 284 \ 285 /* When the correctable engine trips, diagnose a fault */ \ 286 prop fault.cpu.generic-sparc.fltleaf@level \ 287 { DIAGNOSE_ERPT && setserdsuffix("erptleaf") && setserdn(n) && \ 288 setserdt(t) && SET_SERDN && SET_SERDT && SET_RATIO } (0) -> \ 289 ereport.cpu.generic-sparc.erptleaf@level; \ 290 \ 291 event upset.fault.cpu.generic-sparc.fltleaf@level; \ 292 \ 293 prop upset.fault.cpu.generic-sparc.fltleaf@level \ 294 { !DIAGNOSE_ERPT } (0)-> \ 295 ereport.cpu.generic-sparc.erptleaf@level 296 297FLT_CPU_CE_UNRETIRED(itlb, chip, chip-nr, 8, 1week); 298FLT_CPU_CE_UNRETIRED(dtlb, chip, chip-nr, 8, 1week); 299FLT_CPU_CE_UNRETIRED(icache, chip, chip-nr, 8, 1week); 300FLT_CPU_CE_UNRETIRED(dcache, chip, chip-nr, 8, 1week); 301FLT_CPU_CE_UNRETIRED(ireg, chip, chip-nr, 8, 1week); 302FLT_CPU_CE_UNRETIRED(freg, chip, chip-nr, 8, 1week); 303FLT_CPU_CE_UNRETIRED(mreg, chip, chip-nr, 8, 1week); 304FLT_CPU_CE_UNRETIRED(l2data, chip, chip-nr, 8, 2h); 305FLT_CPU_CE_UNRETIRED(l2tagctl, chip, chip-nr, 8, 2h); 306FLT_CPU_CE_UNRETIRED(l3data, chip, chip-nr, 8, 2h); 307FLT_CPU_CE_UNRETIRED(l3tagctl, chip, chip-nr, 8, 2h); 308FLT_CPU_CE_UNRETIRED(gchip, chip, chip-nr, 8, 1week); 309FLT_CPU_CE_UNRETIRED(int-mem, chip, chip-nr, 8, 1week); 310FLT_CPU_CE_UNRETIRED(int-mem, core, core-nr, 8, 1week); 311FLT_CPU_CE_UNRETIRED(int-mem, strand, strand-nr, 8, 1week); 312 313/* 314 * c2c-link-uc, c2c-prot-uc, c2c-failover errors 315 * The detector and sender are faulted immediately. 316 * If ereport does not have a sender, all chips are faulted 317 */ 318 319#define CONTAINS_SENDER (payloadprop_contains("sender", asru(chip))) 320#define HAS_SENDER (payloadprop_defined("sender")) 321#define HAS_C2C_FAULT(c) has_fault(c, "fault.cpu.generic-sparc.c2c") 322#define CONTAINS_DET (payloadprop_contains("detector", asru(chip))) 323 324event ereport.cpu.generic-sparc.c2c-link-uc@chip { within(1s) }; 325event ereport.cpu.generic-sparc.c2c-prot-uc@chip { within(1s) }; 326event ereport.cpu.generic-sparc.c2c-failover@chip { within(1s) }; 327 328event fault.cpu.generic-sparc.c2c-uc@chip, retire=0; 329event fault.cpu.generic-sparc.c2c-failover@chip, retire=0; 330event upset.cpu.generic-sparc.c2c-uc@chip; 331event upset.cpu.generic-sparc.c2c-failover@chip; 332 333prop fault.cpu.generic-sparc.c2c-uc@chip 334 { DIAGNOSE_ERPT && CONTAINS_SENDER } (0) -> 335 ereport.cpu.generic-sparc.c2c-link-uc@chip<x>; 336 337prop fault.cpu.generic-sparc.c2c-uc@chip 338 { DIAGNOSE_ERPT } (0) -> 339 ereport.cpu.generic-sparc.c2c-link-uc@chip; 340 341prop fault.cpu.generic-sparc.c2c-uc@chip 342 { DIAGNOSE_ERPT && !HAS_SENDER } (0) -> 343 ereport.cpu.generic-sparc.c2c-link-uc@chip<x>; 344 345prop fault.cpu.generic-sparc.c2c-uc@chip 346 { DIAGNOSE_ERPT && CONTAINS_SENDER } (0) -> 347 ereport.cpu.generic-sparc.c2c-prot-uc@chip<x>; 348 349prop fault.cpu.generic-sparc.c2c-uc@chip 350 { DIAGNOSE_ERPT } (0) -> 351 ereport.cpu.generic-sparc.c2c-prot-uc@chip; 352 353prop fault.cpu.generic-sparc.c2c-uc@chip 354 { DIAGNOSE_ERPT && !HAS_SENDER } (0) -> 355 ereport.cpu.generic-sparc.c2c-prot-uc@chip<x>; 356 357prop upset.cpu.generic-sparc.c2c-uc@chip 358 { !DIAGNOSE_ERPT } (0) -> 359 ereport.cpu.generic-sparc.c2c-prot-uc@chip, 360 ereport.cpu.generic-sparc.c2c-link-uc@chip; 361 362prop fault.cpu.generic-sparc.c2c-failover@chip 363 { DIAGNOSE_ERPT && CONTAINS_SENDER } (0) -> 364 ereport.cpu.generic-sparc.c2c-failover@chip<x>; 365 366prop fault.cpu.generic-sparc.c2c-failover@chip 367 { DIAGNOSE_ERPT } (0) -> 368 ereport.cpu.generic-sparc.c2c-failover@chip; 369 370prop fault.cpu.generic-sparc.c2c-failover@chip 371 { DIAGNOSE_ERPT && !HAS_SENDER } (0) -> 372 ereport.cpu.generic-sparc.c2c-failover@chip<x>; 373 374prop upset.cpu.generic-sparc.c2c-failover@chip 375 { !DIAGNOSE_ERPT } (0) -> 376 ereport.cpu.generic-sparc.c2c-failover@chip; 377 378/* 379 * c2c-link, c2c-prot. Errors are serded. When the serd trips, 380 * the detector & sender will be faulted. 381 * If ereport does not have a sender, all chips will be faulted 382 * If ereport sender or detector was faulted, discard ereport 383 */ 384event ereport.cpu.generic-sparc.c2c-link@chip { within(1s) }; 385event ereport.cpu.generic-sparc.c2c-prot@chip { within(1s) }; 386 387engine serd.cpu.generic-sparc.c2c@chip, N=120, T=30min; 388 389event fault.cpu.generic-sparc.c2c@chip, retire=0, 390 engine=serd.cpu.generic-sparc.c2c@chip; 391 392event upset.cpu.generic-sparc.c2c-link@chip; 393event upset.cpu.generic-sparc.c2c_discard@chip; 394 395prop fault.cpu.generic-sparc.c2c@chip 396 { DIAGNOSE_ERPT && CONTAINS_SENDER 397 && !HAS_C2C_FAULT(asru(chip)) && !HAS_C2C_FAULT(payloadprop("detector")) 398 && setserdsuffix("link") && SET_SERDN 399 && SET_SERDT && SET_RATIO } (0) -> 400 ereport.cpu.generic-sparc.c2c-link@chip<x>; 401 402prop fault.cpu.generic-sparc.c2c@chip 403 { DIAGNOSE_ERPT && !HAS_C2C_FAULT(asru(chip)) 404 && !HAS_C2C_FAULT(payloadprop("sender")) 405 && setserdsuffix("link") && SET_SERDN 406 && SET_SERDT && SET_RATIO } (0) -> 407 ereport.cpu.generic-sparc.c2c-link@chip; 408 409prop fault.cpu.generic-sparc.c2c@chip 410 { DIAGNOSE_ERPT && !HAS_SENDER && setserdsuffix("link") && 411 SET_SERDN && SET_SERDT && SET_RATIO } (0) -> 412 ereport.cpu.generic-sparc.c2c-link@chip<x>; 413 414prop fault.cpu.generic-sparc.c2c@chip 415 { DIAGNOSE_ERPT && CONTAINS_SENDER 416 && !HAS_C2C_FAULT(asru(chip)) && !HAS_C2C_FAULT(payloadprop("detector")) 417 && setserdsuffix("prot") && SET_SERDN 418 && SET_SERDT && SET_RATIO } (0) -> 419 ereport.cpu.generic-sparc.c2c-prot@chip<x>; 420 421prop fault.cpu.generic-sparc.c2c@chip 422 { DIAGNOSE_ERPT && !HAS_C2C_FAULT(asru(chip)) 423 && !HAS_C2C_FAULT(payloadprop("sender")) 424 && setserdsuffix("prot") && SET_SERDN 425 && SET_SERDT && SET_RATIO } (0) -> 426 ereport.cpu.generic-sparc.c2c-prot@chip; 427 428prop fault.cpu.generic-sparc.c2c@chip 429 { DIAGNOSE_ERPT && !HAS_SENDER && setserdsuffix("prot") && 430 SET_SERDN && SET_SERDT && SET_RATIO } (0) -> 431 ereport.cpu.generic-sparc.c2c-prot@chip<x>; 432 433prop upset.cpu.generic-sparc.c2c-link@chip 434 { !DIAGNOSE_ERPT } (0) -> 435 ereport.cpu.generic-sparc.c2c-prot@chip, 436 ereport.cpu.generic-sparc.c2c-link@chip; 437 438prop upset.cpu.generic-sparc.c2c_discard@chip (0) -> 439 ereport.cpu.generic-sparc.c2c-link@chip, 440 ereport.cpu.generic-sparc.c2c-prot@chip; 441 442/* 443 * addr-oob is a firmware error - there is no associated FRU/ASRU 444 * and firmware is not represented in topology. Rather than ignore 445 * the error, the DE generates a defect with no FRU or ASRU. It 446 * is generated @chassis so no location (label) is picked up out 447 * of the topology. The associated knowledge article can instruct 448 * users what steps to take to address the error. 449 */ 450fru NULL; 451asru NULL; 452 453event ereport.cpu.generic-sparc.addr-oob@chassis; 454event defect.fw.generic-sparc.addr-oob@chassis, 455 ASRU=NULL, 456 FRU=NULL; 457event upset.fw.generic-sparc.addr-oob@chassis; 458 459prop defect.fw.generic-sparc.addr-oob@chassis 460 { DIAGNOSE_ERPT } (0) -> 461 ereport.cpu.generic-sparc.addr-oob@chassis; 462 463prop upset.fw.generic-sparc.addr-oob@chassis 464 { !DIAGNOSE_ERPT } (0) -> 465 ereport.cpu.generic-sparc.addr-oob@chassis; 466 467event ereport.cpu.generic-sparc.inconsistent@chassis; 468event defect.fw.generic-sparc.erpt-gen@chassis, 469 ASRU=NULL, 470 FRU=NULL; 471event upset.fw.generic-sparc.erpt-gen@chassis; 472 473prop defect.fw.generic-sparc.erpt-gen@chassis 474 { DIAGNOSE_ERPT } (0) -> 475 ereport.cpu.generic-sparc.inconsistent@chassis; 476 477prop upset.fw.generic-sparc.erpt-gen@chassis 478 { !DIAGNOSE_ERPT } (0) -> 479 ereport.cpu.generic-sparc.inconsistent@chassis; 480/* 481 * bootbus-prot, bootbus-to and bootbus-par errors. Fault the detector. 482 */ 483event ereport.cpu.generic-sparc.bootbus-to@chip; 484event ereport.cpu.generic-sparc.bootbus-par@chip; 485event ereport.cpu.generic-sparc.bootbus-prot@chip; 486event upset.cpu.generic-sparc.bootbus@chip; 487 488event fault.cpu.generic-sparc.bootbus@chip, retire=0; 489 490prop fault.cpu.generic-sparc.bootbus@chip 491 { DIAGNOSE_ERPT } (0) -> 492 ereport.cpu.generic-sparc.bootbus-to@chip; 493 494prop fault.cpu.generic-sparc.bootbus@chip 495 { DIAGNOSE_ERPT } (0) -> 496 ereport.cpu.generic-sparc.bootbus-par@chip; 497 498prop fault.cpu.generic-sparc.bootbus@chip 499 { DIAGNOSE_ERPT } (0) -> 500 ereport.cpu.generic-sparc.bootbus-prot@chip; 501 502prop upset.cpu.generic-sparc.bootbus@chip 503 { !DIAGNOSE_ERPT } (0) -> 504 ereport.cpu.generic-sparc.bootbus-to@chip, 505 ereport.cpu.generic-sparc.bootbus-par@chip, 506 ereport.cpu.generic-sparc.bootbus-prot@chip; 507 508/* 509 * ignore the pio-read error. 510 */ 511event ereport.cpu.generic-sparc.pio-read@chip; 512event upset.cpu.generic-sparc.discard@chip; 513 514prop upset.cpu.generic-sparc.discard@chip (0) -> 515 ereport.cpu.generic-sparc.pio-read@chip; 516