xref: /titanic_50/usr/src/data/perfmon/HSW/haswell_matrix_bit_definitions_v28.json (revision 5fc40de04b67592be50772c772ace24a75df2712) 
1[
2  {
3    "BitName": "DEMAND_DATA_RD",
4    "BitIndex": "0",
5    "Type": "1",
6    "Description": "Counts demand data reads",
7    "MATRIX_REG": "0,1",
8    "BitsNotCombinedWith": "",
9    "Errata": "na"
10  },
11  {
12    "BitName": "DEMAND_RFO",
13    "BitIndex": "1",
14    "Type": "1",
15    "Description": "Counts all demand data writes (RFOs)",
16    "MATRIX_REG": "0,1",
17    "BitsNotCombinedWith": "",
18    "Errata": "na"
19  },
20  {
21    "BitName": "DEMAND_CODE_RD",
22    "BitIndex": "2",
23    "Type": "1",
24    "Description": "Counts all demand code reads",
25    "MATRIX_REG": "0,1",
26    "BitsNotCombinedWith": "",
27    "Errata": "na"
28  },
29  {
30    "BitName": "COREWB",
31    "BitIndex": "3",
32    "Type": "1",
33    "Description": null,
34    "MATRIX_REG": "0,1",
35    "BitsNotCombinedWith": "",
36    "Errata": "HSD150"
37  },
38  {
39    "BitName": "PF_L2_DATA_RD",
40    "BitIndex": "4",
41    "Type": "1",
42    "Description": "Counts prefetch (that bring data to L2) data reads",
43    "MATRIX_REG": "0,1",
44    "BitsNotCombinedWith": "",
45    "Errata": "na"
46  },
47  {
48    "BitName": "PF_L2_RFO",
49    "BitIndex": "5",
50    "Type": "1",
51    "Description": "Counts all prefetch (that bring data to L2) RFOs",
52    "MATRIX_REG": "0,1",
53    "BitsNotCombinedWith": "",
54    "Errata": "na"
55  },
56  {
57    "BitName": "PF_L2_CODE_RD",
58    "BitIndex": "6",
59    "Type": "1",
60    "Description": "Counts all prefetch (that bring data to LLC only) code reads",
61    "MATRIX_REG": "0,1",
62    "BitsNotCombinedWith": "",
63    "Errata": "na"
64  },
65  {
66    "BitName": "PF_L3_DATA_RD",
67    "BitIndex": "7",
68    "Type": "1",
69    "Description": "Counts all prefetch (that bring data to LLC only) data reads",
70    "MATRIX_REG": "0,1",
71    "BitsNotCombinedWith": "",
72    "Errata": "HSD150"
73  },
74  {
75    "BitName": "PF_L3_RFO",
76    "BitIndex": "8",
77    "Type": "1",
78    "Description": "Counts all prefetch (that bring data to LLC only) RFOs",
79    "MATRIX_REG": "0,1",
80    "BitsNotCombinedWith": "",
81    "Errata": "HSD150"
82  },
83  {
84    "BitName": "PF_L3_CODE_RD",
85    "BitIndex": "9",
86    "Type": "1",
87    "Description": "Counts prefetch (that bring data to LLC only) code reads",
88    "MATRIX_REG": "0,1",
89    "BitsNotCombinedWith": "",
90    "Errata": "HSD150"
91  },
92  {
93    "BitName": "SPLIT_LOCK_UC_LOCK",
94    "BitIndex": "10",
95    "Type": "1",
96    "Description": null,
97    "MATRIX_REG": "0,1",
98    "BitsNotCombinedWith": "",
99    "Errata": "HSD150"
100  },
101  {
102    "BitName": "STREAMING_STORES",
103    "BitIndex": "11",
104    "Type": "1",
105    "Description": null,
106    "MATRIX_REG": "0,1",
107    "BitsNotCombinedWith": "",
108    "Errata": "HSD150"
109  },
110  {
111    "BitName": "OTHER",
112    "BitIndex": "15",
113    "Type": "1",
114    "Description": "Counts any other requests",
115    "MATRIX_REG": "0,1",
116    "BitsNotCombinedWith": "",
117    "Errata": "na"
118  },
119  {
120    "BitName": "ALL_PF_DATA_RD",
121    "BitIndex": "4,7",
122    "Type": "1",
123    "Description": "Counts all prefetch data reads",
124    "MATRIX_REG": "0,1",
125    "BitsNotCombinedWith": "",
126    "Errata": "HSD150"
127  },
128  {
129    "BitName": "ALL_PF_RFO",
130    "BitIndex": "5,8",
131    "Type": "1",
132    "Description": "Counts prefetch RFOs",
133    "MATRIX_REG": "0,1",
134    "BitsNotCombinedWith": "",
135    "Errata": "HSD150"
136  },
137  {
138    "BitName": "ALL_PF_CODE_RD",
139    "BitIndex": "6,9",
140    "Type": "1",
141    "Description": "Counts all prefetch code reads",
142    "MATRIX_REG": "0,1",
143    "BitsNotCombinedWith": "",
144    "Errata": "HSD150"
145  },
146  {
147    "BitName": "ALL_DATA_RD",
148    "BitIndex": "0,4,7",
149    "Type": "1",
150    "Description": "Counts all demand & prefetch data reads",
151    "MATRIX_REG": "0,1",
152    "BitsNotCombinedWith": "",
153    "Errata": "HSD150"
154  },
155  {
156    "BitName": "ALL_RFO",
157    "BitIndex": "1,5,8",
158    "Type": "1",
159    "Description": "Counts all demand & prefetch RFOs",
160    "MATRIX_REG": "0,1",
161    "BitsNotCombinedWith": "",
162    "Errata": "HSD150"
163  },
164  {
165    "BitName": "ALL_CODE_RD",
166    "BitIndex": "2,6,9",
167    "Type": "1",
168    "Description": "Counts all demand & prefetch code reads",
169    "MATRIX_REG": "0,1",
170    "BitsNotCombinedWith": "",
171    "Errata": "HSD150"
172  },
173  {
174    "BitName": "ALL_READS",
175    "BitIndex": "0,1,2,4,5,6,7,8,9,10",
176    "Type": "1",
177    "Description": null,
178    "MATRIX_REG": "0,1",
179    "BitsNotCombinedWith": "",
180    "Errata": "HSD150"
181  },
182  {
183    "BitName": "ALL_REQUESTS",
184    "BitIndex": "0,1,2,3,4,5,6,7,8,9,10,11,15",
185    "Type": "1",
186    "Description": "Counts all requests",
187    "MATRIX_REG": "0,1",
188    "BitsNotCombinedWith": "",
189    "Errata": "HSD150"
190  },
191  {
192    "BitName": "ANY_RESPONSE",
193    "BitIndex": "16",
194    "Type": "2",
195    "Description": "have any response type.",
196    "MATRIX_REG": "0,1",
197    "BitsNotCombinedWith": "",
198    "Errata": "na"
199  },
200  {
201    "BitName": "SUPPLIER_NONE",
202    "BitIndex": "17",
203    "Type": "3",
204    "Description": null,
205    "MATRIX_REG": "0,1",
206    "BitsNotCombinedWith": "116,117,118,119,120,121,122,123,124",
207    "Errata": "na"
208  },
209  {
210    "BitName": "L3_HIT_M",
211    "BitIndex": "18",
212    "Type": "3",
213    "Description": null,
214    "MATRIX_REG": "0,1",
215    "BitsNotCombinedWith": "116,117,118,119,120,121,122,123,124",
216    "Errata": "na"
217  },
218  {
219    "BitName": "L3_HIT_E",
220    "BitIndex": "19",
221    "Type": "3",
222    "Description": null,
223    "MATRIX_REG": "0,1",
224    "BitsNotCombinedWith": "116,117,118,119,120,121,122,123,124",
225    "Errata": "na"
226  },
227  {
228    "BitName": "L3_HIT_S",
229    "BitIndex": "20",
230    "Type": "3",
231    "Description": null,
232    "MATRIX_REG": "0,1",
233    "BitsNotCombinedWith": "116,117,118,119,120,121,122,123,124",
234    "Errata": "na"
235  },
236  {
237    "BitName": "L3_HIT",
238    "BitIndex": "18,19,20",
239    "Type": "3",
240    "Description": null,
241    "MATRIX_REG": "0,1",
242    "BitsNotCombinedWith": "116,117,118,119,120,121,122,123,124",
243    "Errata": "na"
244  },
245  {
246    "BitName": "L3_MISS_LOCAL_DRAM",
247    "BitIndex": "22",
248    "Type": "3",
249    "Description": null,
250    "MATRIX_REG": "0,1",
251    "BitsNotCombinedWith": "116,117,118,119,120,121,122,123,124",
252    "Errata": "na"
253  },
254  {
255    "BitName": "SNOOP_NONE",
256    "BitIndex": "31",
257    "Type": "4",
258    "Description": null,
259    "MATRIX_REG": "0,1",
260    "BitsNotCombinedWith": "na",
261    "Errata": "na"
262  },
263  {
264    "BitName": "SNOOP_NOT_NEEDED",
265    "BitIndex": "32",
266    "Type": "4",
267    "Description": null,
268    "MATRIX_REG": "0,1",
269    "BitsNotCombinedWith": "na",
270    "Errata": "na"
271  },
272  {
273    "BitName": "SNOOP_MISS",
274    "BitIndex": "33",
275    "Type": "4",
276    "Description": null,
277    "MATRIX_REG": "0,1",
278    "BitsNotCombinedWith": "na",
279    "Errata": "na"
280  },
281  {
282    "BitName": "SNOOP_HIT_NO_FWD",
283    "BitIndex": "34",
284    "Type": "4",
285    "Description": null,
286    "MATRIX_REG": "0,1",
287    "BitsNotCombinedWith": "na",
288    "Errata": "na"
289  },
290  {
291    "BitName": "SNOOP_HIT_WITH_FWD",
292    "BitIndex": "35",
293    "Type": "4",
294    "Description": null,
295    "MATRIX_REG": "0,1",
296    "BitsNotCombinedWith": "na",
297    "Errata": "na"
298  },
299  {
300    "BitName": "SNOOP_HITM",
301    "BitIndex": "36",
302    "Type": "4",
303    "Description": null,
304    "MATRIX_REG": "0,1",
305    "BitsNotCombinedWith": "na",
306    "Errata": "na"
307  },
308  {
309    "BitName": "SNOOP_NON_DRAM",
310    "BitIndex": "37",
311    "Type": "4",
312    "Description": null,
313    "MATRIX_REG": "0,1",
314    "BitsNotCombinedWith": "na",
315    "Errata": "na"
316  },
317  {
318    "BitName": "ANY_SNOOP",
319    "BitIndex": "31,32,33,34,35,36,37",
320    "Type": "4",
321    "Description": null,
322    "MATRIX_REG": "0,1",
323    "BitsNotCombinedWith": "na",
324    "Errata": "na"
325  },
326  {
327    "BitName": "L3_HIT.NO_SNOOP_NEEDED",
328    "BitIndex": "18,19,20,21,32",
329    "Type": "2",
330    "Description": "hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
331    "MATRIX_REG": "0,1",
332    "BitsNotCombinedWith": "na",
333    "Errata": "na"
334  },
335  {
336    "BitName": "L3_HIT.HIT_OTHER_CORE_NO_FWD",
337    "BitIndex": "18,19,20,21,34",
338    "Type": "2",
339    "Description": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
340    "MATRIX_REG": "0,1",
341    "BitsNotCombinedWith": "na",
342    "Errata": "na"
343  },
344  {
345    "BitName": "L3_HIT.HITM_OTHER_CORE",
346    "BitIndex": "18,19,20,21,36",
347    "Type": "2",
348    "Description": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
349    "MATRIX_REG": "0,1",
350    "BitsNotCombinedWith": "na",
351    "Errata": "na"
352  },
353  {
354    "BitName": "L3_MISS.LOCAL_DRAM",
355    "BitIndex": "22,32",
356    "Type": "2",
357    "Description": "miss the L3 and the data is returned from local dram",
358    "MATRIX_REG": "0,1",
359    "BitsNotCombinedWith": "na",
360    "Errata": "na"
361  },
362  {
363    "BitName": "L3_MISS.ANY_DRAM",
364    "BitIndex": "22,23,24,25,26,27,28,29,30,33,34",
365    "Type": "2",
366    "Description": "miss the L3 and the data is returned from local or remote dram",
367    "MATRIX_REG": "0,1",
368    "BitsNotCombinedWith": "na",
369    "Errata": "na"
370  },
371  {
372    "BitName": "L3_HIT.ANY_RESPONSE",
373    "BitIndex": "18,19,20,21,31,32,33,34,35,36,37",
374    "Type": "2",
375    "Description": "hit in the L3",
376    "MATRIX_REG": "0,1",
377    "BitsNotCombinedWith": "na",
378    "Errata": "na"
379  },
380  {
381    "BitName": "L3_MISS.ANY_RESPONSE",
382    "BitIndex": "22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37",
383    "Type": "2",
384    "Description": "miss in the L3",
385    "MATRIX_REG": "0,1",
386    "BitsNotCombinedWith": "na",
387    "Errata": "na"
388  }
389]