1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* Copyright © 2003-2011 Emulex. All rights reserved. */ 23 24 /* 25 * Driver specific data structures and function prototypes 26 */ 27 28 #ifndef _OCE_IMPL_H_ 29 #define _OCE_IMPL_H_ 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/types.h> 36 #include <sys/dditypes.h> 37 #include <sys/kstat.h> 38 #include <sys/ddi_intr.h> 39 #include <sys/cmn_err.h> 40 #include <sys/byteorder.h> 41 #include <sys/mac_provider.h> 42 #include <sys/mac_ether.h> 43 #include <sys/gld.h> 44 #include <sys/bitmap.h> 45 #include <sys/ddidmareq.h> 46 #include <sys/kmem.h> 47 #include <sys/ddi.h> 48 #include <sys/sunddi.h> 49 #include <sys/modctl.h> 50 #include <sys/devops.h> 51 #include <sys/systm.h> 52 #include <sys/conf.h> 53 #include <sys/dlpi.h> 54 #include <sys/ethernet.h> 55 #include <sys/strsun.h> 56 #include <sys/pattr.h> 57 #include <sys/strsubr.h> 58 #include <sys/ddifm.h> 59 #include <sys/fm/protocol.h> 60 #include <sys/fm/util.h> 61 #include <sys/fm/io/ddi.h> 62 #include <sys/note.h> 63 #include <sys/pci.h> 64 #include <sys/random.h> 65 #include <oce_hw.h> 66 #include <oce_hw_eth.h> 67 #include <oce_io.h> 68 #include <oce_buf.h> 69 #include <oce_utils.h> 70 #include <oce_version.h> 71 72 #define SIZE_128 128 73 #define SIZE_256 256 74 #define SIZE_512 512 75 #define SIZE_1K 1024 76 #define SIZE_2K (2 * 1024) 77 #define SIZE_4K (4 * 1024) 78 #define SIZE_8K (8 * 1024) 79 80 #define END 0xdeadface 81 82 #define MAX_DEVS 32 83 #define MAX_RSS_PER_ADAPTER 2 84 85 #define OCE_MAX_ETH_FRAME_SIZE 1500 86 #define OCE_MAX_JUMBO_FRAME_SIZE 9018 87 #define OCE_MIN_ETH_FRAME_SIZE 64 88 #define OCE_LLC_SNAP_HDR_LEN 8 89 90 #define OCE_MIN_MTU 1500 91 #define OCE_MAX_MTU 9000 92 #define OCE_MAX_MCA 32 93 #define OCE_RQ_MAX_FRAME_SZ 9018 94 95 #define OCE_MAX_EQ 8 96 #define OCE_MAX_CQ 1024 97 #define OCE_MAX_WQ 8 98 #define OCE_MAX_RQ 5 99 #define OCE_MIN_RQ 1 100 101 #define OCE_WQ_NUM_BUFFERS 2048 102 #define OCE_WQ_BUF_SIZE 2048 103 #define OCE_LSO_MAX_SIZE (64 * 1024) 104 #define OCE_DEFAULT_TX_BCOPY_LIMIT 512 105 #define OCE_DEFAULT_RX_BCOPY_LIMIT 128 106 #define OCE_DEFAULT_WQ_EQD 16 107 108 #define OCE_DEFAULT_TX_RING_SIZE 2048 109 #define OCE_DEFAULT_RX_RING_SIZE 1024 110 #define OCE_DEFAULT_WQS 1 111 #if defined(__sparc) 112 #define OCE_DEFAULT_RQS OCE_MAX_RQ 113 #else 114 #define OCE_DEFAULT_RQS OCE_MIN_RQ 115 #endif 116 117 #define OCE_DEFAULT_RX_PKT_PER_INTR (OCE_DEFAULT_RX_RING_SIZE / 2) 118 #define OCE_DEFAULT_TX_RECLAIM_THRESHOLD 1024 119 #define OCE_MAX_RQ_POSTS 255 120 #define OCE_RQ_NUM_BUFFERS 2048 121 #define OCE_RQ_BUF_SIZE 8192 122 #define OCE_DEFAULT_RECHARGE_THRESHOLD OCE_MAX_RQ_POSTS 123 #define OCE_NUM_USED_VECTORS 2 124 #define OCE_ITBL_SIZE 64 125 #define OCE_HKEY_SIZE 40 126 #define OCE_DMA_ALIGNMENT 0x1000ull 127 128 #define OCE_MIN_VECTORS 1 129 130 #define OCE_CAPAB_FLAGS (MBX_RX_IFACE_FLAGS_BROADCAST | \ 131 MBX_RX_IFACE_FLAGS_PROMISCUOUS | \ 132 MBX_RX_IFACE_FLAGS_UNTAGGED | \ 133 MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS | \ 134 MBX_RX_IFACE_FLAGS_PASS_L3L4) 135 136 #define OCE_CAPAB_ENABLE (MBX_RX_IFACE_FLAGS_BROADCAST | \ 137 MBX_RX_IFACE_FLAGS_UNTAGGED | \ 138 MBX_RX_IFACE_FLAGS_PASS_L3L4) 139 140 #define OCE_FM_CAPABILITY (DDI_FM_EREPORT_CAPABLE | \ 141 DDI_FM_ACCCHK_CAPABLE | \ 142 DDI_FM_DMACHK_CAPABLE) 143 144 #define OCE_DEFAULT_RSS_TYPE (RSS_ENABLE_IPV4|RSS_ENABLE_TCP_IPV4) 145 146 /* flow control definitions */ 147 #define OCE_FC_NONE 0x00000000 148 #define OCE_FC_TX 0x00000001 149 #define OCE_FC_RX 0x00000002 150 #define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX) 151 152 /* PCI Information */ 153 #define OCE_DEV_CFG_BAR 0x01 154 #define OCE_PCI_CSR_BAR 0x02 155 #define OCE_PCI_DB_BAR 0x03 156 157 /* macros for device IO */ 158 #define OCE_READ_REG32(handle, addr) ddi_get32(handle, addr) 159 #define OCE_WRITE_REG32(handle, addr, value) ddi_put32(handle, addr, value) 160 161 #define OCE_CSR_READ32(dev, offset) \ 162 OCE_READ_REG32((dev)->csr_handle, \ 163 (uint32_t *)(void *)((dev)->csr_addr + offset)) 164 165 #define OCE_CSR_WRITE32(dev, offset, value) \ 166 OCE_WRITE_REG32((dev)->csr_handle, \ 167 (uint32_t *)(void *)((dev)->csr_addr + offset), value) 168 169 #define OCE_DB_READ32(dev, offset) \ 170 OCE_READ_REG32((dev)->db_handle, \ 171 (uint32_t *)(void *)((dev)->db_addr + offset)) 172 173 #define OCE_DB_WRITE32(dev, offset, value) \ 174 OCE_WRITE_REG32((dev)->db_handle, \ 175 (uint32_t *)(void *)((dev)->db_addr + offset), value) 176 177 #define OCE_CFG_READ32(dev, offset) \ 178 OCE_READ_REG32((dev)->dev_cfg_handle, \ 179 (uint32_t *)(void *)((dev)->dev_cfg_addr + offset)) 180 181 #define OCE_CFG_WRITE32(dev, offset, value) \ 182 OCE_WRITE_REG32((dev)->dev_cfg_handle, \ 183 (uint32_t *)(void *)((dev)->dev_cfg_addr + offset), value) 184 185 #define OCE_PCI_FUNC(dev) \ 186 ((OCE_CFG_READ32(dev, PCICFG_INTR_CTRL) \ 187 >> HOSTINTR_PFUNC_SHIFT) & HOSTINTR_PFUNC_MASK) 188 189 #define DEV_LOCK(dev) mutex_enter(&dev->dev_lock) 190 191 #define DEV_UNLOCK(dev) mutex_exit(&dev->dev_lock) 192 193 enum oce_ring_size { 194 RING_SIZE_256 = 256, 195 RING_SIZE_512 = 512, 196 RING_SIZE_1024 = 1024, 197 RING_SIZE_2048 = 2048 198 }; 199 200 enum oce_driver_state { 201 STATE_INIT = 0x2, 202 STATE_MAC_STARTED = 0x4, 203 STATE_QUIESCE = 0x8, 204 STATE_MAC_STOPPING = 0x10 205 }; 206 207 struct oce_dev { 208 kmutex_t bmbx_lock; /* Bootstrap Lock */ 209 kmutex_t dev_lock; /* lock for device */ 210 211 /* Queues relarted */ 212 struct oce_wq *wq[OCE_MAX_WQ]; /* TXQ Array */ 213 struct oce_rq *rq[OCE_MAX_RQ]; /* RXQ Array */ 214 struct oce_cq *cq[OCE_MAX_CQ]; /* Completion Queues */ 215 struct oce_eq *eq[OCE_MAX_EQ]; /* Event Queues */ 216 struct oce_mq *mq; /* MQ ring */ 217 218 /* driver state machine */ 219 enum oce_driver_state state; /* state */ 220 boolean_t suspended; /* CPR */ 221 uint32_t attach_state; /* attach progress */ 222 223 oce_dma_buf_t *bmbx; /* Bootstrap MailBox */ 224 225 uint32_t tx_bcopy_limit; /* TX BCOPY Limit */ 226 uint32_t rx_bcopy_limit; /* RX BCOPY Limit */ 227 uint32_t tx_reclaim_threshold; /* Tx reclaim */ 228 uint32_t rx_pkt_per_intr; /* Rx pkts processed per intr */ 229 230 /* BARS */ 231 int num_bars; 232 ddi_acc_handle_t pci_cfg_handle; /* Config space handle */ 233 ddi_acc_handle_t cfg_handle; /* MMIO PCI Config Space Regs */ 234 ddi_acc_handle_t csr_handle; /* MMIO Control Status Regs */ 235 caddr_t csr_addr; 236 caddr_t db_addr; 237 caddr_t dev_cfg_addr; 238 ddi_acc_handle_t db_handle; /* MMIO DoorBell Area */ 239 ddi_acc_handle_t dev_cfg_handle; /* MMIO CONFIG SPACE */ 240 mac_handle_t mac_handle; /* MAC HANDLE */ 241 242 /* device stats */ 243 kstat_t *oce_kstats; /* NIC STATS */ 244 oce_dma_buf_t *stats_dbuf; /* STATS BUFFER */ 245 struct mbx_get_nic_stats *hw_stats; 246 /* dev stats */ 247 uint32_t tx_errors; 248 uint32_t tx_noxmtbuf; 249 250 /* link status */ 251 link_state_t link_status; 252 int32_t link_speed; /* Link speed in Mbps */ 253 254 /* OS */ 255 uint32_t dev_id; /* device ID or instance number */ 256 dev_info_t *dip; /* device info structure for device tree node */ 257 258 /* Interrupt related */ 259 int intr_type; /* INTR TYPE USED */ 260 int num_vectors; /* number of vectors used */ 261 uint_t intr_pri; /* interrupt priority */ 262 int intr_cap; 263 ddi_intr_handle_t *htable; /* intr handler table */ 264 int32_t hsize; 265 266 /* device configuration */ 267 uint32_t rq_max_bufs; /* maximum prealloced buffers */ 268 uint32_t rq_frag_size; /* Rxq fragment size */ 269 enum oce_ring_size tx_ring_size; 270 enum oce_ring_size rx_ring_size; 271 uint32_t neqs; /* No of event queues */ 272 uint32_t nwqs; /* No of Work Queues */ 273 uint32_t nrqs; /* No of Receive Queues */ 274 uint32_t nifs; /* No of interfaces created */ 275 uint32_t tx_rings; 276 uint32_t rx_rings; 277 uint32_t pmac_id; /* used to add or remove mac */ 278 uint8_t unicast_addr[ETHERADDRL]; 279 uint32_t num_smac; 280 uint32_t mtu; 281 int32_t fm_caps; 282 boolean_t rss_enable; /* RSS support */ 283 boolean_t lso_capable; /* LSO */ 284 boolean_t promisc; /* PROMISC MODE */ 285 uint32_t if_cap_flags; /* IF CAPAB */ 286 uint32_t flow_control; /* flow control settings */ 287 uint8_t mac_addr[ETHERADDRL]; /* hardware mac address */ 288 uint16_t num_mca; /* MCA supported */ 289 struct ether_addr multi_cast[OCE_MAX_MCA]; /* MC TABLE */ 290 uint32_t cookie; /* used during fw download */ 291 292 /* fw config: only relevant fields */ 293 uint32_t config_number; 294 uint32_t asic_revision; 295 uint32_t port_id; 296 uint32_t function_mode; 297 uint32_t function_caps; 298 uint32_t chip_rev; /* Chip revision */ 299 uint32_t max_tx_rings; /* Max Rx rings available */ 300 uint32_t max_rx_rings; /* Max rx rings available */ 301 int32_t if_id; /* IF ID */ 302 uint8_t fn; /* function number */ 303 uint8_t fw_version[32]; /* fw version string */ 304 305 /* PCI related */ 306 uint16_t vendor_id; 307 uint16_t device_id; 308 uint16_t subsys_id; 309 uint16_t subvendor_id; 310 uint8_t pci_bus; 311 uint8_t pci_device; 312 uint8_t pci_function; 313 uint8_t dev_list_index; 314 315 /* Logging related */ 316 uint16_t mod_mask; /* Log Mask */ 317 int16_t severity; /* Log level */ 318 }; 319 320 /* GLD handler functions */ 321 int oce_m_start(void *arg); 322 void oce_m_stop(void *arg); 323 mblk_t *oce_m_send(void *arg, mblk_t *pkt); 324 int oce_m_promiscuous(void *arg, boolean_t enable); 325 int oce_m_multicast(void *arg, boolean_t add, const uint8_t *mca); 326 int oce_m_unicast(void *arg, const uint8_t *uca); 327 boolean_t oce_m_getcap(void *arg, mac_capab_t cap, void *data); 328 void oce_m_ioctl(void *arg, queue_t *wq, mblk_t *mp); 329 int oce_m_setprop(void *arg, const char *name, mac_prop_id_t id, 330 uint_t size, const void *val); 331 int oce_m_getprop(void *arg, const char *name, mac_prop_id_t id, 332 uint_t size, void *val); 333 void oce_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t pr_num, 334 mac_prop_info_handle_t prh); 335 336 int oce_m_stat(void *arg, uint_t stat, uint64_t *val); 337 338 /* Hardware start/stop functions */ 339 int oce_start(struct oce_dev *dev); 340 void oce_stop(struct oce_dev *dev); 341 int oce_identify_hw(struct oce_dev *dev); 342 int oce_get_bdf(struct oce_dev *dev); 343 344 /* FMA support Functions */ 345 void oce_fm_init(struct oce_dev *dev); 346 void oce_fm_fini(struct oce_dev *dev); 347 void oce_set_dma_fma_flags(int fm_caps); 348 void oce_set_reg_fma_flags(int fm_caps); 349 void oce_set_tx_map_dma_fma_flags(int fm_caps); 350 void oce_fm_ereport(struct oce_dev *dev, char *detail); 351 int oce_fm_check_acc_handle(struct oce_dev *dev, 352 ddi_acc_handle_t acc_handle); 353 int oce_fm_check_dma_handle(struct oce_dev *dev, 354 ddi_dma_handle_t dma_handle); 355 356 /* Interrupt handling */ 357 int oce_setup_intr(struct oce_dev *dev); 358 int oce_teardown_intr(struct oce_dev *dev); 359 int oce_setup_handlers(struct oce_dev *dev); 360 void oce_remove_handler(struct oce_dev *dev); 361 void oce_ei(struct oce_dev *dev); 362 void oce_di(struct oce_dev *dev); 363 void oce_chip_ei(struct oce_dev *dev); 364 void oce_chip_di(struct oce_dev *dev); 365 366 /* HW initialisation */ 367 int oce_hw_init(struct oce_dev *dev); 368 void oce_hw_fini(struct oce_dev *dev); 369 int oce_setup_adapter(struct oce_dev *dev); 370 void oce_unsetup_adapter(struct oce_dev *dev); 371 372 #ifdef __cplusplus 373 } 374 #endif 375 376 #endif /* _OCE_IMPL_H_ */ 377