1 /* 2 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2007, Intel Corporation 8 * All rights reserved. 9 */ 10 11 /* 12 * Sun elects to use this software under the BSD license. 13 */ 14 15 /* 16 * This file is provided under a dual BSD/GPLv2 license. When using or 17 * redistributing this file, you may do so under either license. 18 * 19 * GPL LICENSE SUMMARY 20 * 21 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved. 22 * 23 * This program is free software; you can redistribute it and/or modify 24 * it under the terms of version 2 of the GNU Geeral Public License as 25 * published by the Free Software Foundation. 26 * 27 * This program is distributed in the hope that it will be useful, but 28 * WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 * General Public License for more details. 31 * 32 * You should have received a copy of the GNU General Public License 33 * along with this program; if not, write to the Free Software 34 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 35 * USA 36 * 37 * The full GNU General Public License is included in this distribution 38 * in the file called LICENSE.GPL. 39 * 40 * Contact Information: 41 * James P. Ketrenos <ipw2100-admin@linux.intel.com> 42 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 43 * 44 * BSD LICENSE 45 * 46 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved. 47 * All rights reserved. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that the following conditions 51 * are met: 52 * 53 * * Redistributions of source code must retain the above copyright 54 * notice, this list of conditions and the following disclaimer. 55 * * Redistributions in binary form must reproduce the above copyright 56 * notice, this list of conditions and the following disclaimer in 57 * the documentation and/or other materials provided with the 58 * distribution. 59 * * Neither the name Intel Corporation nor the names of its 60 * contributors may be used to endorse or promote products derived 61 * from this software without specific prior written permission. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 64 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 65 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 66 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 67 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 68 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 69 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 70 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 71 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 72 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 73 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 74 */ 75 76 #ifndef _IWK_HW_H_ 77 #define _IWK_HW_H_ 78 79 #ifdef __cplusplus 80 extern "C" { 81 #endif 82 83 /* 84 * maximum scatter/gather 85 */ 86 #define IWK_MAX_SCATTER (10) 87 88 /* 89 * Flow Handler Definitions 90 */ 91 #define FH_MEM_LOWER_BOUND (0x1000) 92 #define FH_MEM_UPPER_BOUND (0x1EF0) 93 94 #define IWK_FH_REGS_LOWER_BOUND (0x1000) 95 #define IWK_FH_REGS_UPPER_BOUND (0x2000) 96 97 /* 98 * TFDB Area - TFDs buffer table 99 */ 100 #define FH_MEM_TFDB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x000) 101 #define FH_MEM_TFDB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x900) 102 103 /* 104 * channels 0 - 8 105 */ 106 #define FH_MEM_TFDB_CHNL_BUF0(x) (FH_MEM_TFDB_LOWER_BOUND + (x) * 0x100) 107 #define FH_MEM_TFDB_CHNL_BUF1(x) (FH_MEM_TFDB_LOWER_BOUND + 0x80 + (x) * 0x100) 108 109 /* 110 * TFDIB Area - TFD Immediate Buffer 111 */ 112 #define FH_MEM_TFDIB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x900) 113 #define FH_MEM_TFDIB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x958) 114 115 /* 116 * channels 0 - 10 117 */ 118 #define FH_MEM_TFDIB_CHNL(x) (FH_MEM_TFDIB_LOWER_BOUND + (x) * 0x8) 119 120 /* 121 * TFDIB registers used in Service Mode 122 */ 123 #define FH_MEM_TFDIB_CHNL9_REG0 (FH_MEM_TFDIB_CHNL(9)) 124 #define FH_MEM_TFDIB_CHNL9_REG1 (FH_MEM_TFDIB_CHNL(9) + 4) 125 #define FH_MEM_TFDIB_CHNL10_REG0 (FH_MEM_TFDIB_CHNL(10)) 126 #define FH_MEM_TFDIB_CHNL10_REG1 (FH_MEM_TFDIB_CHNL(10) + 4) 127 128 /* 129 * Tx service channels 130 */ 131 #define FH_MEM_TFDIB_DRAM_ADDR_LSB_MASK (0xFFFFFFFF) 132 #define FH_MEM_TFDIB_DRAM_ADDR_MSB_MASK (0xF00000000) 133 #define FH_MEM_TFDIB_TB_LENGTH_MASK (0x0001FFFF) /* bits 16:0 */ 134 135 #define FH_MEM_TFDIB_DRAM_ADDR_LSB_BITSHIFT (0) 136 #define FH_MEM_TFDIB_DRAM_ADDR_MSB_BITSHIFT (32) 137 #define FH_MEM_TFDIB_TB_LENGTH_BITSHIFT (0) 138 139 #define FH_MEM_TFDIB_REG0_ADDR_MASK (0xFFFFFFFF) 140 #define FH_MEM_TFDIB_REG1_ADDR_MASK (0xF0000000) 141 #define FH_MEM_TFDIB_REG1_LENGTH_MASK (0x0001FFFF) 142 143 #define FH_MEM_TFDIB_REG0_ADDR_BITSHIFT (0) 144 #define FH_MEM_TFDIB_REG1_ADDR_BITSHIFT (28) 145 #define FH_MEM_TFDIB_REG1_LENGTH_BITSHIFT (0) 146 147 /* 148 * TRB Area - Transmit Request Buffers 149 */ 150 #define FH_MEM_TRB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x0958) 151 #define FH_MEM_TRB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x0980) 152 153 /* 154 * channels 0 - 8 155 */ 156 #define FH_MEM_TRB_CHNL(x) (FH_MEM_TRB_LOWER_BOUND + (x) * 0x4) 157 158 /* 159 * Keep-Warm (KW) buffer base address. 160 * 161 * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the 162 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 163 * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host 164 * from going into a power-savings mode that would cause higher DRAM latency, 165 * and possible data over/under-runs, before all Tx/Rx is complete. 166 * 167 * Driver loads IWK_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 168 * of the buffer, which must be 4K aligned. Once this is set up, the 4965 169 * automatically invokes keep-warm accesses when normal accesses might not 170 * be sufficient to maintain fast DRAM response. 171 * 172 * Bit fields: 173 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 174 */ 175 #define IWK_FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C) 176 177 /* 178 * STAGB Area - Scheduler TAG Buffer 179 */ 180 #define FH_MEM_STAGB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x980) 181 #define FH_MEM_STAGB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) 182 183 /* 184 * channels 0 - 8 185 */ 186 #define FH_MEM_STAGB_0(x) (FH_MEM_STAGB_LOWER_BOUND + (x) * 0x8) 187 #define FH_MEM_STAGB_1(x) (FH_MEM_STAGB_LOWER_BOUND + 0x4 + (x) * 0x8) 188 189 /* 190 * Tx service channels 191 */ 192 #define FH_MEM_SRAM_ADDR_9 (FH_MEM_STAGB_LOWER_BOUND + 0x048) 193 #define FH_MEM_SRAM_ADDR_10 (FH_MEM_STAGB_LOWER_BOUND + 0x04C) 194 195 #define FH_MEM_STAGB_SRAM_ADDR_MASK (0x00FFFFFF) 196 197 /* 198 * TFD Circular Buffers Base (CBBC) addresses 199 * 200 * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident 201 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 202 * (see struct iwk_tfd_frame). These 16 pointer registers are offset by 0x04 203 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 204 * aligned (address bits 0-7 must be 0). 205 * 206 * Bit fields in each pointer register: 207 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 208 */ 209 #define FH_MEM_CBBC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) 210 #define FH_MEM_CBBC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10) 211 212 /* 213 * queues 0 - 15 214 */ 215 #define FH_MEM_CBBC_QUEUE(x) (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4) 216 217 /* 218 * TAGR Area - TAG reconstruct table 219 */ 220 #define FH_MEM_TAGR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xA10) 221 #define FH_MEM_TAGR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA70) 222 223 /* 224 * TDBGR Area - Tx Debug Registers 225 */ 226 #define FH_MEM_TDBGR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x0A70) 227 #define FH_MEM_TDBGR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x0B20) 228 229 /* 230 * channels 0 - 10 231 */ 232 #define FH_MEM_TDBGR_CHNL(x) (FH_MEM_TDBGR_LOWER_BOUND + (x) * 0x10) 233 234 #define FH_MEM_TDBGR_CHNL_REG_0(x) (FH_MEM_TDBGR_CHNL(x)) 235 #define FH_MEM_TDBGR_CHNL_REG_1(x) (FH_MEM_TDBGR_CHNL_REG_0(x) + 0x4) 236 237 #define FH_MEM_TDBGR_CHNL_BYTES_TO_FIFO_MASK (0x000FFFFF) 238 #define FH_MEM_TDBGR_CHNL_BYTES_TO_FIFO_BITSHIFT (0) 239 240 /* 241 * RDBUF Area 242 */ 243 #define FH_MEM_RDBUF_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xB80) 244 #define FH_MEM_RDBUF_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0) 245 #define FH_MEM_RDBUF_CHNL0 (FH_MEM_RDBUF_LOWER_BOUND) 246 247 /* 248 * Rx SRAM Control and Status Registers (RSCSR) 249 * 250 * These registers provide handshake between driver and 4965 for the Rx queue 251 * (this queue handles *all* command responses, notifications, Rx data, etc. 252 * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx 253 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 254 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 255 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 256 * mapping between RBDs and RBs. 257 * 258 * Driver must allocate host DRAM memory for the following, and set the 259 * physical address of each into 4965 registers: 260 * 261 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 262 * entries (although any power of 2, up to 4096, is selectable by driver). 263 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 264 * (typically 4K, although 8K or 16K are also selectable by driver). 265 * Driver sets up RB size and number of RBDs in the CB via Rx config 266 * register FH_MEM_RCSR_CHNL0_CONFIG_REG. 267 * 268 * Bit fields within one RBD: 269 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned. 270 * 271 * Driver sets physical address [35:8] of base of RBD circular buffer 272 * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 273 * 274 * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers 275 * (RBs) have been filled, via a "write pointer", actually the index of 276 * the RB's corresponding RBD within the circular buffer. Driver sets 277 * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 278 * 279 * Bit fields in lower dword of Rx status buffer (upper dword not used 280 * by driver; see struct iwk_shared, val0): 281 * 31-12: Not used by driver 282 * 11- 0: Index of last filled Rx buffer descriptor 283 * (4965 writes, driver reads this value) 284 * 285 * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must 286 * enter pointers to these RBs into contiguous RBD circular buffer entries, 287 * and update the 4965's "write" index register, FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 288 * 289 * This "write" index corresponds to the *next* RBD that the driver will make 290 * available, i.e. one RBD past the the tail of the ready-to-fill RBDs within 291 * the circular buffer. This value should initially be 0 (before preparing any 292 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 293 * wrap back to 0 at the end of the circular buffer (but don't wrap before 294 * "read" index has advanced past 1! See below). 295 * NOTE: 4965 EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 296 * 297 * As the 4965 fills RBs (referenced from contiguous RBDs within the circular 298 * buffer), it updates the Rx status buffer in DRAM, 2) described above, 299 * to tell the driver the index of the latest filled RBD. The driver must 300 * read this "read" index from DRAM after receiving an Rx interrupt from 4965. 301 * 302 * The driver must also internally keep track of a third index, which is the 303 * next RBD to process. When receiving an Rx interrupt, driver should process 304 * all filled but unprocessed RBs up to, but not including, the RB 305 * corresponding to the "read" index. For example, if "read" index becomes "1", 306 * driver may process the RB pointed to by RBD 0. Depending on volume of 307 * traffic, there may be many RBs to process. 308 * 309 * If read index == write index, 4965 thinks there is no room to put new data. 310 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 311 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 312 * and "read" indexes; that is, make sure that there are no more than 254 313 * buffers waiting to be filled. 314 */ 315 #define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0) 316 #define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 317 #define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND) 318 #define FH_MEM_RSCSR_CHNL1 (FH_MEM_RSCSR_LOWER_BOUND + 0x020) 319 320 /* 321 * Physical base address of 8-byte Rx Status buffer. 322 * Bit fields: 323 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 324 */ 325 326 #define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0) 327 328 /* 329 * Physical base address of Rx Buffer Descriptor Circular Buffer. 330 * Bit fields: 331 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 332 */ 333 #define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004) 334 335 /* 336 * Rx write pointer (index, really!). 337 * Bit fields: 338 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 339 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 340 */ 341 #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008) 342 #define FH_RSCSR_CHNL0_RBDCB_RPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x00c) 343 344 #define FH_RSCSR_FRAME_SIZE_MASK (0x00000FFF) /* bits 0-11 */ 345 346 /* 347 * RSCSR registers used in Service mode 348 */ 349 #define FH_RSCSR_CHNL1_RB_WPTR_REG (FH_MEM_RSCSR_CHNL1) 350 #define FH_RSCSR_CHNL1_RB_WPTR_OFFSET_REG (FH_MEM_RSCSR_CHNL1 + 0x004) 351 #define FH_RSCSR_CHNL1_RB_CHUNK_NUM_REG (FH_MEM_RSCSR_CHNL1 + 0x008) 352 #define FH_RSCSR_CHNL1_SRAM_ADDR_REG (FH_MEM_RSCSR_CHNL1 + 0x00C) 353 354 /* 355 * Rx Config/Status Registers (RCSR) 356 * Rx Config Reg for channel 0 (only channel used) 357 * 358 * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 359 * normal operation (see bit fields). 360 * 361 * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 362 * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for 363 * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 364 * 365 * Bit fields: 366 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 367 * '10' operate normally 368 * 29-24: reserved 369 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 370 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 371 * 19-18: reserved 372 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 373 * '10' 12K, '11' 16K. 374 * 15-14: reserved 375 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 376 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 377 * typical value 0x10 (about 1/2 msec) 378 * 3- 0: reserved 379 */ 380 #define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 381 #define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0) 382 #define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND) 383 #define FH_MEM_RCSR_CHNL1 (FH_MEM_RCSR_LOWER_BOUND + 0x020) 384 385 #define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0) 386 #define FH_MEM_RCSR_CHNL0_CREDIT_REG (FH_MEM_RCSR_CHNL0 + 0x004) 387 #define FH_MEM_RCSR_CHNL0_RBD_STTS_REG (FH_MEM_RCSR_CHNL0 + 0x008) 388 #define FH_MEM_RCSR_CHNL0_RB_STTS_REG (FH_MEM_RCSR_CHNL0 + 0x00C) 389 #define FH_MEM_RCSR_CHNL0_RXPD_STTS_REG (FH_MEM_RCSR_CHNL0 + 0x010) 390 391 #define FH_MEM_RCSR_CHNL0_RBD_STTS_FRAME_RB_CNT_MASK (0x7FFFFFF0) 392 393 /* 394 * RCSR registers used in Service mode 395 */ 396 #define FH_MEM_RCSR_CHNL1_CONFIG_REG (FH_MEM_RCSR_CHNL1) 397 #define FH_MEM_RCSR_CHNL1_RB_STTS_REG (FH_MEM_RCSR_CHNL1 + 0x00C) 398 #define FH_MEM_RCSR_CHNL1_RX_PD_STTS_REG (FH_MEM_RCSR_CHNL1 + 0x010) 399 400 /* 401 * Rx Shared Status Registers (RSSR) 402 * 403 * After stopping Rx DMA channel (writing 0 to FH_MEM_RCSR_CHNL0_CONFIG_REG), 404 * driver must poll FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 405 * 406 * Bit fields: 407 * 24: 1 = Channel 0 is idle 408 * 409 * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV contain 410 * default values that should not be altered by the driver. 411 */ 412 #define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40) 413 #define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) 414 #define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND) 415 #define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004) 416 #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV (FH_MEM_RSSR_LOWER_BOUND + 0x008) 417 418 /* 419 * Transmit DMA Channel Control/Status Registers (TCSR) 420 * 421 * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels 422 * supported in hardware; config regs are separated by 0x20 bytes. 423 * 424 * To use a Tx DMA channel, driver must initialize its 425 * IWK_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 426 * 427 * IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 428 * IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 429 * 430 * All other bits should be 0. 431 * 432 * Bit fields: 433 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 434 * '10' operate normally 435 * 29- 4: Reserved, set to "0" 436 * 3: Enable internal DMA requests (1, normal operation), disable (0) 437 * 2- 0: Reserved, set to "0" 438 */ 439 #define IWK_FH_TCSR_LOWER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0xD00) 440 #define IWK_FH_TCSR_UPPER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0xE60) 441 442 #define IWK_FH_TCSR_CHNL_NUM (7) 443 #define IWK_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 444 (IWK_FH_TCSR_LOWER_BOUND + 0x20 * _chnl) 445 #define IWK_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 446 (IWK_FH_TCSR_LOWER_BOUND + 0x20 * _chnl + 0x4) 447 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 448 (IWK_FH_TCSR_LOWER_BOUND + 0x20 * _chnl + 0x8) 449 450 /* 451 * Tx Shared Status Registers (TSSR) 452 * 453 * After stopping Tx DMA channel (writing 0 to 454 * IWK_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 455 * IWK_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 456 * (channel's buffers empty | no pending requests). 457 * 458 * Bit fields: 459 * 31-24: 1 = Channel buffers empty (channel 7:0) 460 * 23-16: 1 = No pending requests (channel 7:0) 461 */ 462 #define IWK_FH_TSSR_LOWER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0xEA0) 463 #define IWK_FH_TSSR_UPPER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0xEC0) 464 465 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG (IWK_FH_TSSR_LOWER_BOUND + 0x008) 466 #define IWK_FH_TSSR_TX_STATUS_REG (IWK_FH_TSSR_LOWER_BOUND + 0x010) 467 468 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000) 469 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000) 470 471 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_64B (0x00000000) 472 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400) 473 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_256B (0x00000800) 474 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_512B (0x00000C00) 475 476 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100) 477 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080) 478 479 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020) 480 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005) 481 482 #define IWK_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) \ 483 ((1 << (_chnl)) << 24) 484 #define IWK_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) \ 485 ((1 << (_chnl)) << 16) 486 487 #define IWK_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) \ 488 (IWK_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) | \ 489 IWK_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl)) 490 491 /* 492 * SRVC 493 */ 494 #define IWK_FH_SRVC_LOWER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0x9C8) 495 #define IWK_FH_SRVC_UPPER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0x9D0) 496 497 #define IWK_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 498 (IWK_FH_SRVC_LOWER_BOUND + (_chnl - 9) * 0x4) 499 500 /* 501 * TFDIB 502 */ 503 #define IWK_FH_TFDIB_LOWER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0x900) 504 #define IWK_FH_TFDIB_UPPER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0x958) 505 506 #define IWK_FH_TFDIB_CTRL0_REG(_chnl) \ 507 (IWK_FH_TFDIB_LOWER_BOUND + 0x8 * _chnl) 508 #define IWK_FH_TFDIB_CTRL1_REG(_chnl) \ 509 (IWK_FH_TFDIB_LOWER_BOUND + 0x8 * _chnl + 0x4) 510 511 #define IWK_FH_SRVC_CHNL (9) 512 #define IWK_FH_TFDIB_CTRL1_REG_POS_MSB (28) 513 514 /* 515 * Debug Monitor Area 516 */ 517 #define FH_MEM_DM_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEE0) 518 #define FH_MEM_DM_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEF0) 519 #define FH_MEM_DM_CONTROL_MASK_REG (FH_MEM_DM_LOWER_BOUND) 520 #define FH_MEM_DM_CONTROL_START_REG (FH_MEM_DM_LOWER_BOUND + 0x004) 521 #define FH_MEM_DM_CONTROL_STATUS_REG (FH_MEM_DM_LOWER_BOUND + 0x008) 522 #define FH_MEM_DM_MONITOR_REG (FH_MEM_DM_LOWER_BOUND + 0x00C) 523 524 #define FH_TB1_ADDR_LOW_MASK (0xFFFFFFFF) /* bits 31:0 */ 525 #define FH_TB1_ADDR_HIGH_MASK (0xF00000000) /* bits 35:32 */ 526 #define FH_TB2_ADDR_LOW_MASK (0x0000FFFF) /* bits 15:0 */ 527 #define FH_TB2_ADDR_HIGH_MASK (0xFFFFF0000) /* bits 35:16 */ 528 529 #define FH_TB1_ADDR_LOW_BITSHIFT (0) 530 #define FH_TB1_ADDR_HIGH_BITSHIFT (32) 531 #define FH_TB2_ADDR_LOW_BITSHIFT (0) 532 #define FH_TB2_ADDR_HIGH_BITSHIFT (16) 533 534 #define FH_TB1_LENGTH_MASK (0x00000FFF) /* bits 11:0 */ 535 #define FH_TB2_LENGTH_MASK (0x00000FFF) /* bits 11:0 */ 536 537 /* 538 * number of FH channels including 2 service mode 539 */ 540 #define NUM_OF_FH_CHANNELS (10) 541 542 /* 543 * ctrl field bitology 544 */ 545 #define FH_TFD_CTRL_PADDING_MASK (0xC0000000) /* bits 31:30 */ 546 #define FH_TFD_CTRL_NUMTB_MASK (0x1F000000) /* bits 28:24 */ 547 548 #define FH_TFD_CTRL_PADDING_BITSHIFT (30) 549 #define FH_TFD_CTRL_NUMTB_BITSHIFT (24) 550 551 #define FH_TFD_GET_NUM_TBS(ctrl) \ 552 ((ctrl & FH_TFD_CTRL_NUMTB_MASK) >> FH_TFD_CTRL_NUMTB_BITSHIFT) 553 #define FH_TFD_GET_PADDING(ctrl) \ 554 ((ctrl & FH_TFD_CTRL_PADDING_MASK) >> FH_TFD_CTRL_PADDING_BITSHIFT) 555 556 /* TCSR: tx_config register values */ 557 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 558 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001) 559 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_ARC (0x00000002) 560 561 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000) 562 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008) 563 564 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 565 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 566 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 567 568 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 569 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 570 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 571 572 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 573 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 574 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 575 576 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 577 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 578 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 579 580 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001) 581 582 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 583 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 584 585 /* 586 * CBB table 587 */ 588 #define FH_CBB_ADDR_MASK 0x0FFFFFFF /* bits 27:0 */ 589 #define FH_CBB_ADDR_BIT_SHIFT (8) 590 591 /* 592 * RCSR: channel 0 rx_config register defines 593 */ 594 #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */ 595 #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MASK (0x00F00000) /* bits 20-23 */ 596 #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MASK (0x00030000) /* bits 16-17 */ 597 #define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MASK (0x00008000) /* bit 15 */ 598 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MASK (0x00001000) /* bit 12 */ 599 #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MASK (0x00000FF0) /* bit 4-11 */ 600 601 #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20) 602 #define FH_RCSR_RX_CONFIG_RB_SIZE_BITSHIFT (16) 603 604 #define FH_RCSR_GET_RDBC_SIZE(reg) \ 605 ((reg & FH_RCSR_RX_CONFIG_RDBC_SIZE_MASK) >> \ 606 FH_RCSR_RX_CONFIG_RDBC_SIZE_BITSHIFT) 607 608 /* 609 * RCSR: channel 1 rx_config register defines 610 */ 611 #define FH_RCSR_CHNL1_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */ 612 #define FH_RCSR_CHNL1_RX_CONFIG_IRQ_DEST_MASK (0x00003000) /* bits 12-13 */ 613 614 /* 615 * RCSR: rx_config register values 616 */ 617 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 618 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 619 #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 620 #define FH_RCSR_RX_CONFIG_SINGLE_FRAME_MODE (0x00008000) 621 622 #define FH_RCSR_RX_CONFIG_RDRBD_DISABLE_VAL (0x00000000) 623 #define FH_RCSR_RX_CONFIG_RDRBD_ENABLE_VAL (0x20000000) 624 625 #define IWK_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 626 627 /* 628 * RCSR channel 0 config register values 629 */ 630 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 631 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 632 633 /* 634 * RCSR channel 1 config register values 635 */ 636 #define FH_RCSR_CHNL1_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 637 #define FH_RCSR_CHNL1_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 638 #define FH_RCSR_CHNL1_RX_CONFIG_IRQ_DEST_INT_RTC_VAL (0x00002000) 639 #define FH_RCSR_CHNL1_RX_CONFIG_IRQ_DEST_INT_HOST_RTC_VAL (0x00003000) 640 641 /* 642 * RCSR: rb status register defines 643 */ 644 #define FH_RCSR_RB_BYTE_TO_SEND_MASK (0x0001FFFF) /* bits 0-16 */ 645 646 /* 647 * RSCSR: defs used in normal mode 648 */ 649 #define FH_RSCSR_CHNL0_RBDCB_WPTR_MASK (0x00000FFF) /* bits 0-11 */ 650 651 /* 652 * RSCSR: defs used in service mode 653 */ 654 #define FH_RSCSR_CHNL1_SRAM_ADDR_MASK (0x00FFFFFF) /* bits 0-23 */ 655 #define FH_RSCSR_CHNL1_RB_WPTR_MASK (0x0FFFFFFF) /* bits 0-27 */ 656 #define FH_RSCSR_CHNL1_RB_WPTR_OFFSET_MASK (0x000000FF) /* bits 0-7 */ 657 658 /* 659 * RSSR: RX Enable Error IRQ to Driver register defines 660 */ 661 #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV_NO_RBD (0x00400000) /* bit 22 */ 662 663 #define FH_DRAM2SRAM_DRAM_ADDR_HIGH_MASK (0xFFFFFFF00) /* bits 8-35 */ 664 #define FH_DRAM2SRAM_DRAM_ADDR_LOW_MASK (0x000000FF) /* bits 0-7 */ 665 666 #define FH_DRAM2SRAM_DRAM_ADDR_HIGH_BITSHIFT (8) /* bits 8-35 */ 667 668 /* 669 * RX DRAM status regs definitions 670 */ 671 #define FH_RX_RB_NUM_MASK (0x00000FFF) /* bits 0-11 */ 672 #define FH_RX_FRAME_NUM_MASK (0x0FFF0000) /* bits 16-27 */ 673 674 #define FH_RX_RB_NUM_BITSHIFT (0) 675 #define FH_RX_FRAME_NUM_BITSHIFT (16) 676 677 /* 678 * Tx Scheduler 679 * 680 * The Tx Scheduler selects the next frame to be transmitted, chosing TFDs 681 * (Transmit Frame Descriptors) from up to 16 circular queues resident in 682 * host DRAM. It steers each frame's Tx command (which contains the frame 683 * data) through one of up to 7 prioritized Tx DMA FIFO channels within the 684 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 685 * but one DMA channel may take input from several queues. 686 * 687 * Tx DMA channels have dedicated purposes. For 4965, and are used as follows: 688 * BMC TODO: CONFIRM channel assignments, esp for 0/1 689 * 690 * 0 -- EDCA BK (background) frames, lowest priority 691 * 1 -- EDCA BE (best effort) frames, normal priority 692 * 2 -- EDCA VI (video) frames, higher priority 693 * 3 -- EDCA VO (voice) and management frames, highest priority 694 * 4 -- Commands (e.g. RXON, etc.) 695 * 5 -- HCCA short frames 696 * 6 -- HCCA long frames 697 * 7 -- not used by driver (device-internal only) 698 * 699 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 700 * In addition, driver can map queues 7-15 to Tx DMA/FIFO channels 0-3 to 701 * support 11n aggregation via EDCA DMA channels. BMC confirm. 702 * 703 * The driver sets up each queue to work in one of two modes: 704 * 705 * 1) Scheduler-Ack, in which the scheduler automatically supports a 706 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 707 * contains TFDs for a unique combination of Recipient Address (RA) 708 * and Traffic Identifier (TID), that is, traffic of a given 709 * Quality-Of-Service (QOS) priority, destined for a single station. 710 * 711 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 712 * each frame within the BA window, including whether it's been transmitted, 713 * and whether it's been acknowledged by the receiving station. The device 714 * automatically processes block-acks received from the receiving STA, 715 * and reschedules un-acked frames to be retransmitted (successful 716 * Tx completion may end up being out-of-order). 717 * 718 * The driver must maintain the queue's Byte Count table in host DRAM 719 * (struct iwk_sched_queue_byte_cnt_tbl) for this mode. 720 * This mode does not support fragmentation. 721 * 722 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 723 * The device may automatically retry Tx, but will retry only one frame 724 * at a time, until receiving ACK from receiving station, or reaching 725 * retry limit and giving up. 726 * 727 * The command queue (#4) must use this mode! 728 * This mode does not require use of the Byte Count table in host DRAM. 729 * 730 * Driver controls scheduler operation via 3 means: 731 * 1) Scheduler registers 732 * 2) Shared scheduler data base in internal 4956 SRAM 733 * 3) Shared data in host DRAM 734 * 735 * Initialization: 736 * 737 * When loading, driver should allocate memory for: 738 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 739 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 740 * (1024 bytes for each queue). 741 * 742 * After receiving "Alive" response from uCode, driver must initialize 743 * the following (especially for queue #4, the command queue, otherwise 744 * the driver can't issue commands!): 745 * 746 * 1) 4965's scheduler data base area in SRAM: 747 * a) Read SRAM address of data base area from SCD_SRAM_BASE_ADDR 748 * b) Clear and Init SCD_CONTEXT_DATA_OFFSET area (size 128 bytes) 749 * c) Clear SCD_TX_STTS_BITMAP_OFFSET area (size 256 bytes) 750 * d) Clear (BMC and init?) SCD_TRANSLATE_TBL_OFFSET (size 32 bytes) 751 * 752 * 2) Init SCD_DRAM_BASE_ADDR with physical base of Tx byte count circular 753 * buffer array, allocated by driver in host DRAM. 754 * 755 * 3) 756 */ 757 758 /* 759 * Max Tx window size is the max number of contiguous TFDs that the scheduler 760 * can keep track of at one time when creating block-ack chains of frames. 761 * Note that "64" matches the number of ack bits in a block-ack. 762 * Driver should use SCD_WIN_SIZE and SCD_FRAME_LIMIT values to initialize 763 * SCD_CONTEXT_QUEUE_OFFSET(x) values. 764 */ 765 #define SCD_WIN_SIZE 64 766 #define SCD_FRAME_LIMIT 10 767 768 /* 769 * Memory mapped registers ... access via HBUS_TARG_PRPH regs 770 */ 771 #define SCD_START_OFFSET 0xa02c00 772 773 /* 774 * 4965 tells driver SRAM address for internal scheduler structs via this reg. 775 * Value is valid only after "Alive" response from uCode. 776 */ 777 #define SCD_SRAM_BASE_ADDR (SCD_START_OFFSET + 0x0) 778 779 /* 780 * Driver may need to update queue-empty bits after changing queue's 781 * write and read pointers (indexes) during (re-)initialization (i.e. when 782 * scheduler is not tracking what's happening). 783 * Bit fields: 784 * 31-16: Write mask -- 1: update empty bit, 0: don't change empty bit 785 * 15-00: Empty state, one for each queue -- 1: empty, 0: non-empty 786 * NOTE BMC: THIS REGISTER NOT USED BY LINUX DRIVER. 787 */ 788 #define SCD_EMPTY_BITS (SCD_START_OFFSET + 0x4) 789 790 /* 791 * Physical base address of array of byte count (BC) circular buffers (CBs). 792 * Each Tx queue has a BC CB in host DRAM to support Scheduler-ACK mode. 793 * This register points to BC CB for queue 0, must be on 1024-byte boundary. 794 * Others are spaced by 1024 bytes. 795 * Each BC CB is 2 bytes * (256 + 64) = 740 bytes, followed by 384 bytes pad. 796 * (Index into a queue's BC CB) = (index into queue's TFD CB) = (SSN & 0xff). 797 * Bit fields: 798 * 25-00: Byte Count CB physical address [35:10], must be 1024-byte aligned. 799 */ 800 #define SCD_DRAM_BASE_ADDR (SCD_START_OFFSET + 0x10) 801 #define SCD_AIT (SCD_START_OFFSET + 0x18) 802 803 /* 804 * Enables any/all Tx DMA/FIFO channels. 805 * Scheduler generates requests for only the active channels. 806 * Set this to 0xff to enable all 8 channels (normal usage). 807 * Bit fields: 808 * 7- 0: Enable (1), disable (0), one bit for each channel 0-7 809 */ 810 #define SCD_TXFACT (SCD_START_OFFSET + 0x1c) 811 812 /* 813 * Queue (x) Write Pointers (indexes, really!), one for each Tx queue. 814 * Initialized and updated by driver as new TFDs are added to queue. 815 * NOTE: If using Block Ack, index must correspond to frame's 816 * Start Sequence Number; index = (SSN & 0xff) 817 * NOTE BMC: Alternative to HBUS_TARG_WRPTR, which is what Linux driver uses? 818 */ 819 #define SCD_QUEUE_WRPTR(x) (SCD_START_OFFSET + 0x24 + (x) * 4) 820 821 /* 822 * Queue (x) Read Pointers (indexes, really!), one for each Tx queue. 823 * For FIFO mode, index indicates next frame to transmit. 824 * For Scheduler-ACK mode, index indicates first frame in Tx window. 825 * Initialized by driver, updated by scheduler. 826 */ 827 #define SCD_QUEUE_RDPTR(x) (SCD_START_OFFSET + 0x64 + (x) * 4) 828 #define SCD_SETQUEUENUM (SCD_START_OFFSET + 0xa4) 829 #define SCD_SET_TXSTAT_TXED (SCD_START_OFFSET + 0xa8) 830 #define SCD_SET_TXSTAT_DONE (SCD_START_OFFSET + 0xac) 831 #define SCD_SET_TXSTAT_NOT_SCHD (SCD_START_OFFSET + 0xb0) 832 #define SCD_DECREASE_CREDIT (SCD_START_OFFSET + 0xb4) 833 #define SCD_DECREASE_SCREDIT (SCD_START_OFFSET + 0xb8) 834 #define SCD_LOAD_CREDIT (SCD_START_OFFSET + 0xbc) 835 #define SCD_LOAD_SCREDIT (SCD_START_OFFSET + 0xc0) 836 #define SCD_BAR (SCD_START_OFFSET + 0xc4) 837 #define SCD_BAR_DW0 (SCD_START_OFFSET + 0xc8) 838 #define SCD_BAR_DW1 (SCD_START_OFFSET + 0xcc) 839 840 /* 841 * Select which queues work in chain mode (1) vs. not (0). 842 * Use chain mode to build chains of aggregated frames. 843 * Bit fields: 844 * 31-16: Reserved 845 * 15-00: Mode, one bit for each queue -- 1: Chain mode, 0: one-at-a-time 846 * NOTE: If driver sets up queue for chain mode, it should be also set up 847 * Scheduler-ACK mode as well, via SCD_QUEUE_STATUS_BITS(x). 848 */ 849 #define SCD_QUEUECHAIN_SEL (SCD_START_OFFSET + 0xd0) 850 #define SCD_QUERY_REQ (SCD_START_OFFSET + 0xd8) 851 #define SCD_QUERY_RES (SCD_START_OFFSET + 0xdc) 852 #define SCD_PENDING_FRAMES (SCD_START_OFFSET + 0xe0) 853 854 /* 855 * Select which queues interrupt driver when read pointer (index) increments. 856 * Bit fields: 857 * 31-16: Reserved 858 * 15-00: Interrupt enable, one bit for each queue -- 1: enabled, 0: disabled 859 * NOTE BMC: THIS FUNCTIONALITY IS APPARENTLY A NO-OP. 860 */ 861 #define SCD_INTERRUPT_MASK (SCD_START_OFFSET + 0xe4) 862 #define SCD_INTERRUPT_THRESHOLD (SCD_START_OFFSET + 0xe8) 863 #define SCD_QUERY_MIN_FRAME_SIZE (SCD_START_OFFSET + 0x100) 864 865 /* 866 * Queue search status registers. One for each queue. 867 * Sets up queue mode and assigns queue to Tx DMA channel. 868 * Bit fields: 869 * 19-10: Write mask/enable bits for bits 0-9 870 * 9: Driver should init to "0" 871 * 8: Scheduler-ACK mode (1), non-Scheduler-ACK (i.e. FIFO) mode (0). 872 * Driver should init to "1" for aggregation mode, or "0" otherwise. 873 * 7-6: Driver should init to "0" 874 * 5: Window Size Left; indicates whether scheduler can request 875 * another TFD, based on window size, etc. Driver should init 876 * this bit to "1" for aggregation mode, or "0" for non-agg. 877 * 4-1: Tx FIFO to use (range 0-7). 878 * 0: Queue is active (1), not active (0). 879 * Other bits should be written as "0" 880 * 881 * NOTE: If enabling Scheduler-ACK mode, chain mode should also be enabled 882 * via SCD_QUEUECHAIN_SEL. 883 */ 884 #define SCD_QUEUE_STATUS_BITS(x) (SCD_START_OFFSET + 0x104 + (x) * 4) 885 886 /* 887 * 4965 internal SRAM structures for scheduler, shared with driver ... 888 * Driver should clear and initialize the following areas after receiving 889 * "Alive" response from 4965 uCode, i.e. after initial 890 * uCode load, or after a uCode load done for error recovery: 891 * 892 * SCD_CONTEXT_DATA_OFFSET (size 128 bytes) 893 * SCD_TX_STTS_BITMAP_OFFSET (size 256 bytes) 894 * SCD_TRANSLATE_TBL_OFFSET (size 32 bytes) 895 * 896 * Driver reads base address of this scheduler area from SCD_SRAM_BASE_ADDR. 897 * All OFFSET values must be added to this base address. 898 * Use HBUS_TARG_MEM_* registers to access SRAM. 899 */ 900 901 /* 902 * Queue context. One 8-byte entry for each of 16 queues. 903 * 904 * Driver should clear this entire area (size 0x80) to 0 after receiving 905 * "Alive" notification from uCode. Additionally, driver should init 906 * each queue's entry as follows: 907 * 908 * LS Dword bit fields: 909 * 0-06: Max Tx window size for Scheduler-ACK. Driver should init to 64. 910 * 911 * MS Dword bit fields: 912 * 16-22: Frame limit. Driver should init to 10 (0xa). 913 * 914 * Driver should init all other bits to 0. 915 * 916 * Init must be done after driver receives "Alive" response from 4965 uCode, 917 * and when setting up queue for aggregation. 918 */ 919 #define SCD_CONTEXT_DATA_OFFSET 0x380 920 921 /* 922 * Tx Status Bitmap 923 * 924 * Driver should clear this entire area (size 0x100) to 0 after receiving 925 * "Alive" notification from uCode. Area is used only by device itself; 926 * no other support (besides clearing) is required from driver. 927 */ 928 #define SCD_TX_STTS_BITMAP_OFFSET 0x400 929 930 /* 931 * RAxTID to queue translation mapping. 932 * 933 * When queue is in Scheduler-ACK mode, frames placed in a that queue must be 934 * for only one combination of receiver address (RA) and traffic ID (TID), i.e. 935 * one QOS priority level destined for one station (for this link, not final 936 * destination). The SCD_TRANSLATE_TABLE area provides 16 16-bit mappings, 937 * one for each of the 16 queues. If queue is not in Scheduler-ACK mode, the 938 * device ignores the mapping value. 939 * 940 * Bit fields, for each 16-bit map: 941 * 15-9: Reserved, set to 0 942 * 8-4: Index into device's station table for recipient station 943 * 3-0: Traffic ID (tid), range 0-15 944 * 945 * Driver should clear this entire area (size 32 bytes) to 0 after receiving 946 * "Alive" notification from uCode. To update a 16-bit map value, driver 947 * must read a dword-aligned value from device SRAM, replace the 16-bit map 948 * value of interest, and write the dword value back into device SRAM. 949 */ 950 #define SCD_TRANSLATE_TBL_OFFSET 0x500 951 #define SCD_CONTEXT_QUEUE_OFFSET(x) (SCD_CONTEXT_DATA_OFFSET + ((x) * 8)) 952 #define SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \ 953 ((SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc) 954 955 /* 956 * Mask to enable contiguous Tx DMA/FIFO channels between "lo" and "hi". 957 */ 958 #define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \ 959 ((1<<(hi))|((1<<(hi))-(1<<(lo)))) 960 961 #define SCD_MODE_REG_BIT_SEARCH_MODE (1<<0) 962 #define SCD_MODE_REG_BIT_SBYP_MODE (1<<1) 963 964 #define SCD_TXFIFO_POS_TID (0) 965 #define SCD_TXFIFO_POS_RA (4) 966 #define SCD_QUEUE_STTS_REG_POS_ACTIVE (0) 967 #define SCD_QUEUE_STTS_REG_POS_TXF (1) 968 #define SCD_QUEUE_STTS_REG_POS_WSL (5) 969 #define SCD_QUEUE_STTS_REG_POS_SCD_ACK (8) 970 #define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10) 971 #define SCD_QUEUE_STTS_REG_MSK (0x0007FC00) 972 973 #define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 974 975 #define SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0) 976 #define SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F) 977 #define SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 978 #define SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 979 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 980 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 981 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 982 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 983 984 #define CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R (0x00000010) 985 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00) 986 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 987 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 988 #define CSR_HW_IF_CONFIG_REG_EEP_SEM (0x00200000) 989 990 /* IWK-END */ 991 992 #define RX_RES_PHY_CNT 14 993 994 #define STATISTICS_FLG_CLEAR (0x1) 995 #define STATISTICS_FLG_DISABLE_NOTIFICATION (0x2) 996 997 #define STATISTICS_REPLY_FLG_CLEAR (0x1) 998 #define STATISTICS_REPLY_FLG_BAND_24G_MSK (0x2) 999 #define STATISTICS_REPLY_FLG_TGJ_NARROW_BAND_MSK (0x4) 1000 #define STATISTICS_REPLY_FLG_FAT_MODE_MSK (0x8) 1001 #define RX_PHY_FLAGS_ANTENNAE_OFFSET (4) 1002 #define RX_PHY_FLAGS_ANTENNAE_MASK (0x70) 1003 1004 /* 1005 * Register and values 1006 */ 1007 #define CSR_BASE (0x0) 1008 #define HBUS_BASE (0x400) 1009 1010 #define HBUS_TARG_MBX_C (HBUS_BASE+0x030) 1011 1012 /* 1013 * CSR (control and status registers) 1014 */ 1015 #define CSR_SW_VER (CSR_BASE+0x000) 1016 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ 1017 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ 1018 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ 1019 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ 1020 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack */ 1021 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ 1022 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc */ 1023 #define CSR_GP_CNTRL (CSR_BASE+0x024) 1024 /* 0x028 - reserved */ 1025 #define CSR_EEPROM_REG (CSR_BASE+0x02c) 1026 #define CSR_EEPROM_GP (CSR_BASE+0x030) 1027 #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) 1028 #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) 1029 #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) 1030 #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) 1031 #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) 1032 #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) 1033 #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) 1034 1035 /* 1036 * BSM (Bootstrap State Machine) 1037 */ 1038 #define BSM_BASE (CSR_BASE + 0x3400) 1039 1040 #define BSM_WR_CTRL_REG (BSM_BASE + 0x000) /* ctl and status */ 1041 #define BSM_WR_MEM_SRC_REG (BSM_BASE + 0x004) /* source in BSM mem */ 1042 #define BSM_WR_MEM_DST_REG (BSM_BASE + 0x008) /* dest in SRAM mem */ 1043 #define BSM_WR_DWCOUNT_REG (BSM_BASE + 0x00C) /* bytes */ 1044 #define BSM_WR_STATUS_REG (BSM_BASE + 0x010) /* bit 0: 1 == done */ 1045 1046 /* 1047 * pointers and size regs for bootstrap load and data SRAM save 1048 */ 1049 #define BSM_DRAM_INST_PTR_REG (BSM_BASE + 0x090) 1050 #define BSM_DRAM_INST_BYTECOUNT_REG (BSM_BASE + 0x094) 1051 #define BSM_DRAM_DATA_PTR_REG (BSM_BASE + 0x098) 1052 #define BSM_DRAM_DATA_BYTECOUNT_REG (BSM_BASE + 0x09C) 1053 1054 /* 1055 * BSM special memory, stays powered during power-save sleeps 1056 */ 1057 #define BSM_SRAM_LOWER_BOUND (CSR_BASE + 0x3800) 1058 #define BSM_SRAM_SIZE (1024) 1059 1060 1061 /* 1062 * card static random access memory (SRAM) for processor data and instructs 1063 */ 1064 #define RTC_INST_LOWER_BOUND (0x00000) 1065 #define ALM_RTC_INST_UPPER_BOUND (0x14000) 1066 1067 #define RTC_DATA_LOWER_BOUND (0x800000) 1068 #define ALM_RTC_DATA_UPPER_BOUND (0x808000) 1069 1070 /* 1071 * HBUS (Host-side bus) 1072 */ 1073 #define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) 1074 #define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) 1075 #define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) 1076 #define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) 1077 #define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) 1078 #define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) 1079 #define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) 1080 #define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) 1081 #define HBUS_TARG_WRPTR (HBUS_BASE+0x060) 1082 1083 /* 1084 * HW I/F configuration 1085 */ 1086 #define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB (0x00000100) 1087 #define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM (0x00000200) 1088 #define CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400) 1089 #define CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800) 1090 #define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000) 1091 #define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000) 1092 1093 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 1094 #define CSR_UCODE_SW_BIT_RFKILL (0x00000002) 1095 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 1096 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 1097 1098 #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 1099 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 1100 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 1101 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 1102 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER 1103 1104 #define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000) 1105 1106 /* 1107 * interrupt flags in INTA, set by uCode or hardware (e.g. dma), 1108 * acknowledged (reset) by host writing "1" to flagged bits. 1109 */ 1110 #define BIT_INT_FH_RX \ 1111 (((uint32_t)1) << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 1112 #define BIT_INT_ERR (1<<29) /* DMA hardware error FH_INT[31] */ 1113 #define BIT_INT_FH_TX (1<<27) /* Tx DMA FH_INT[1:0] */ 1114 #define BIT_INT_MAC_CLK_ACTV (1<<26) /* NIC controller's clock toggled on/off */ 1115 #define BIT_INT_SWERROR (1<<25) /* uCode error */ 1116 #define BIT_INT_RF_KILL (1<<7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 1117 #define BIT_INT_CT_KILL (1<<6) /* Critical temp (chip too hot) rfkill */ 1118 #define BIT_INT_SW_RX (1<<3) /* Rx, command responses, 3945 */ 1119 #define BIT_INT_WAKEUP (1<<1) /* NIC controller waking up (pwr mgmt) */ 1120 #define BIT_INT_ALIVE (1<<0) /* uCode interrupts once it initializes */ 1121 1122 #define CSR_INI_SET_MASK (BIT_INT_FH_RX | \ 1123 BIT_INT_ERR | \ 1124 BIT_INT_FH_TX | \ 1125 BIT_INT_SWERROR | \ 1126 BIT_INT_RF_KILL | \ 1127 BIT_INT_SW_RX | \ 1128 BIT_INT_WAKEUP | \ 1129 BIT_INT_ALIVE) 1130 1131 /* 1132 * interrupt flags in FH (flow handler) (PCI busmaster DMA) 1133 */ 1134 #define BIT_FH_INT_ERR (((uint32_t)1) << 31) /* Error */ 1135 #define BIT_FH_INT_HI_PRIOR (1<<30) /* High priority Rx,bypass coalescing */ 1136 #define BIT_FH_INT_RX_CHNL2 (1<<18) /* Rx channel 2 (3945 only) */ 1137 #define BIT_FH_INT_RX_CHNL1 (1<<17) /* Rx channel 1 */ 1138 #define BIT_FH_INT_RX_CHNL0 (1<<16) /* Rx channel 0 */ 1139 #define BIT_FH_INT_TX_CHNL6 (1<<6) /* Tx channel 6 (3945 only) */ 1140 #define BIT_FH_INT_TX_CHNL1 (1<<1) /* Tx channel 1 */ 1141 #define BIT_FH_INT_TX_CHNL0 (1<<0) /* Tx channel 0 */ 1142 1143 #define FH_INT_RX_MASK (BIT_FH_INT_HI_PRIOR | \ 1144 BIT_FH_INT_RX_CHNL2 | \ 1145 BIT_FH_INT_RX_CHNL1 | \ 1146 BIT_FH_INT_RX_CHNL0) 1147 1148 #define FH_INT_TX_MASK (BIT_FH_INT_TX_CHNL6 | \ 1149 BIT_FH_INT_TX_CHNL1 | \ 1150 BIT_FH_INT_TX_CHNL0) 1151 1152 /* 1153 * RESET 1154 */ 1155 #define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 1156 #define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 1157 #define CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 1158 #define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 1159 #define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 1160 1161 /* 1162 * GP (general purpose) CONTROL 1163 */ 1164 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 1165 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 1166 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 1167 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 1168 1169 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 1170 1171 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 1172 #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 1173 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 1174 1175 /* 1176 * APMG (power management) constants 1177 */ 1178 #define APMG_CLK_CTRL_REG (0x003000) 1179 #define ALM_APMG_CLK_EN (0x003004) 1180 #define ALM_APMG_CLK_DIS (0x003008) 1181 #define ALM_APMG_PS_CTL (0x00300c) 1182 #define ALM_APMG_PCIDEV_STT (0x003010) 1183 #define ALM_APMG_RFKILL (0x003014) 1184 #define ALM_APMG_LARC_INT (0x00301c) 1185 #define ALM_APMG_LARC_INT_MSK (0x003020) 1186 1187 #define APMG_CLK_REG_VAL_DMA_CLK_RQT (0x00000200) 1188 #define APMG_CLK_REG_VAL_BSM_CLK_RQT (0x00000800) 1189 1190 #define APMG_PS_CTRL_REG_VAL_ALM_R_RESET_REQ (0x04000000) 1191 1192 #define APMG_DEV_STATE_REG_VAL_L1_ACTIVE_DISABLE (0x00000800) 1193 1194 #define APMG_PS_CTRL_REG_MSK_POWER_SRC (0x03000000) 1195 #define APMG_PS_CTRL_REG_VAL_POWER_SRC_VMAIN (0x00000000) 1196 #define APMG_PS_CTRL_REG_VAL_POWER_SRC_VAUX (0x01000000) 1197 1198 /* 1199 * BSM (bootstrap state machine) 1200 */ 1201 /* 1202 * start boot load now 1203 */ 1204 #define BSM_WR_CTRL_REG_BIT_START (0x80000000) 1205 /* 1206 * enable boot after power up 1207 */ 1208 #define BSM_WR_CTRL_REG_BIT_START_EN (0x40000000) 1209 1210 /* 1211 * DBM 1212 */ 1213 #define ALM_FH_SRVC_CHNL (6) 1214 1215 #define ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20) 1216 #define ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4) 1217 1218 #define ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000) 1219 1220 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000) 1221 1222 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000) 1223 1224 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000) 1225 1226 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000) 1227 1228 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000) 1229 1230 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1231 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001) 1232 1233 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000) 1234 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008) 1235 1236 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1237 1238 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1239 1240 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1241 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1242 1243 #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000) 1244 1245 #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001) 1246 1247 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000) 1248 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000) 1249 1250 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400) 1251 1252 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100) 1253 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080) 1254 1255 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020) 1256 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005) 1257 1258 #define ALM_TB_MAX_BYTES_COUNT (0xFFF0) 1259 1260 #define ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) \ 1261 ((1LU << _channel) << 24) 1262 #define ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel) \ 1263 ((1LU << _channel) << 16) 1264 1265 #define ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_channel) \ 1266 (ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) | \ 1267 ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel)) 1268 #define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */ 1269 #define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */ 1270 1271 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 1272 1273 #define TFD_QUEUE_MIN 0 1274 #define TFD_QUEUE_MAX 6 1275 #define TFD_QUEUE_SIZE_MAX (256) 1276 1277 /* 1278 * spectrum and channel data structures 1279 */ 1280 #define IWK_NUM_SCAN_RATES (2) 1281 1282 #define IWK_SCAN_FLAG_24GHZ (1<<0) 1283 #define IWK_SCAN_FLAG_52GHZ (1<<1) 1284 #define IWK_SCAN_FLAG_ACTIVE (1<<2) 1285 #define IWK_SCAN_FLAG_DIRECT (1<<3) 1286 1287 #define IWK_MAX_CMD_SIZE 1024 1288 1289 #define IWK_DEFAULT_TX_RETRY 15 1290 #define IWK_MAX_TX_RETRY 16 1291 1292 #define RFD_SIZE 4 1293 #define NUM_TFD_CHUNKS 4 1294 1295 #define RX_QUEUE_SIZE 256 1296 #define RX_QUEUE_SIZE_LOG 8 1297 1298 /* 1299 * TX Queue Flag Definitions 1300 */ 1301 /* 1302 * use short preamble 1303 */ 1304 #define DCT_FLAG_LONG_PREAMBLE 0x00 1305 #define DCT_FLAG_SHORT_PREAMBLE 0x04 1306 1307 /* 1308 * ACK rx is expected to follow 1309 */ 1310 #define DCT_FLAG_ACK_REQD 0x80 1311 1312 #define IWK_MB_DISASSOCIATE_THRESHOLD_DEFAULT 24 1313 #define IWK_MB_ROAMING_THRESHOLD_DEFAULT 8 1314 #define IWK_REAL_RATE_RX_PACKET_THRESHOLD 300 1315 1316 /* 1317 * QoS definitions 1318 */ 1319 #define CW_MIN_OFDM 15 1320 #define CW_MAX_OFDM 1023 1321 #define CW_MIN_CCK 31 1322 #define CW_MAX_CCK 1023 1323 1324 #define QOS_TX0_CW_MIN_OFDM CW_MIN_OFDM 1325 #define QOS_TX1_CW_MIN_OFDM CW_MIN_OFDM 1326 #define QOS_TX2_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 2 - 1) 1327 #define QOS_TX3_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 4 - 1) 1328 1329 #define QOS_TX0_CW_MIN_CCK CW_MIN_CCK 1330 #define QOS_TX1_CW_MIN_CCK CW_MIN_CCK 1331 #define QOS_TX2_CW_MIN_CCK ((CW_MIN_CCK + 1) / 2 - 1) 1332 #define QOS_TX3_CW_MIN_CCK ((CW_MIN_CCK + 1) / 4 - 1) 1333 1334 #define QOS_TX0_CW_MAX_OFDM CW_MAX_OFDM 1335 #define QOS_TX1_CW_MAX_OFDM CW_MAX_OFDM 1336 #define QOS_TX2_CW_MAX_OFDM CW_MIN_OFDM 1337 #define QOS_TX3_CW_MAX_OFDM ((CW_MIN_OFDM + 1) / 2 - 1) 1338 1339 #define QOS_TX0_CW_MAX_CCK CW_MAX_CCK 1340 #define QOS_TX1_CW_MAX_CCK CW_MAX_CCK 1341 #define QOS_TX2_CW_MAX_CCK CW_MIN_CCK 1342 #define QOS_TX3_CW_MAX_CCK ((CW_MIN_CCK + 1) / 2 - 1) 1343 1344 #define QOS_TX0_AIFS (3) 1345 #define QOS_TX1_AIFS (7) 1346 #define QOS_TX2_AIFS (2) 1347 #define QOS_TX3_AIFS (2) 1348 1349 #define QOS_TX0_ACM 0 1350 #define QOS_TX1_ACM 0 1351 #define QOS_TX2_ACM 0 1352 #define QOS_TX3_ACM 0 1353 1354 #define QOS_TX0_TXOP_LIMIT_CCK 0 1355 #define QOS_TX1_TXOP_LIMIT_CCK 0 1356 #define QOS_TX2_TXOP_LIMIT_CCK 6016 1357 #define QOS_TX3_TXOP_LIMIT_CCK 3264 1358 1359 #define QOS_TX0_TXOP_LIMIT_OFDM 0 1360 #define QOS_TX1_TXOP_LIMIT_OFDM 0 1361 #define QOS_TX2_TXOP_LIMIT_OFDM 3008 1362 #define QOS_TX3_TXOP_LIMIT_OFDM 1504 1363 1364 #define DEF_TX0_CW_MIN_OFDM CW_MIN_OFDM 1365 #define DEF_TX1_CW_MIN_OFDM CW_MIN_OFDM 1366 #define DEF_TX2_CW_MIN_OFDM CW_MIN_OFDM 1367 #define DEF_TX3_CW_MIN_OFDM CW_MIN_OFDM 1368 1369 #define DEF_TX0_CW_MIN_CCK CW_MIN_CCK 1370 #define DEF_TX1_CW_MIN_CCK CW_MIN_CCK 1371 #define DEF_TX2_CW_MIN_CCK CW_MIN_CCK 1372 #define DEF_TX3_CW_MIN_CCK CW_MIN_CCK 1373 1374 #define DEF_TX0_CW_MAX_OFDM CW_MAX_OFDM 1375 #define DEF_TX1_CW_MAX_OFDM CW_MAX_OFDM 1376 #define DEF_TX2_CW_MAX_OFDM CW_MAX_OFDM 1377 #define DEF_TX3_CW_MAX_OFDM CW_MAX_OFDM 1378 1379 #define DEF_TX0_CW_MAX_CCK CW_MAX_CCK 1380 #define DEF_TX1_CW_MAX_CCK CW_MAX_CCK 1381 #define DEF_TX2_CW_MAX_CCK CW_MAX_CCK 1382 #define DEF_TX3_CW_MAX_CCK CW_MAX_CCK 1383 1384 #define DEF_TX0_AIFS (2) 1385 #define DEF_TX1_AIFS (2) 1386 #define DEF_TX2_AIFS (2) 1387 #define DEF_TX3_AIFS (2) 1388 1389 #define DEF_TX0_ACM (0) 1390 #define DEF_TX1_ACM (0) 1391 #define DEF_TX2_ACM (0) 1392 #define DEF_TX3_ACM (0) 1393 1394 #define DEF_TX0_TXOP_LIMIT_CCK (0) 1395 #define DEF_TX1_TXOP_LIMIT_CCK (0) 1396 #define DEF_TX2_TXOP_LIMIT_CCK (0) 1397 #define DEF_TX3_TXOP_LIMIT_CCK (0) 1398 1399 #define DEF_TX0_TXOP_LIMIT_OFDM (0) 1400 #define DEF_TX1_TXOP_LIMIT_OFDM (0) 1401 #define DEF_TX2_TXOP_LIMIT_OFDM (0) 1402 #define DEF_TX3_TXOP_LIMIT_OFDM (0) 1403 1404 #define QOS_QOS_SETS (3) 1405 #define QOS_PARAM_SET_ACTIVE (0) 1406 #define QOS_PARAM_SET_DEF_CCK (1) 1407 #define QOS_PARAM_SET_DEF_OFDM (2) 1408 1409 #define CTRL_QOS_NO_ACK (0x0020) 1410 #define DCT_FLAG_EXT_QOS_ENABLED (0x10) 1411 1412 #define IWK_TX_QUEUE_AC0 (0) 1413 #define IWK_TX_QUEUE_AC1 (1) 1414 #define IWK_TX_QUEUE_AC2 (2) 1415 #define IWK_TX_QUEUE_AC3 (3) 1416 #define IWK_TX_QUEUE_HCCA_1 (5) 1417 #define IWK_TX_QUEUE_HCCA_2 (6) 1418 1419 #define U32_PAD(n) ((4-(n%4))%4) 1420 1421 #define AC_BE_TID_MASK 0x9 /* TID 0 and 3 */ 1422 #define AC_BK_TID_MASK 0x6 /* TID 1 and 2 */ 1423 1424 /* 1425 * Generic queue structure 1426 * 1427 * Contains common data for Rx and Tx queues 1428 */ 1429 #define TFD_CTL_COUNT_SET(n) (n<<24) 1430 #define TFD_CTL_COUNT_GET(ctl) ((ctl>>24) & 7) 1431 #define TFD_CTL_PAD_SET(n) (n<<28) 1432 #define TFD_CTL_PAD_GET(ctl) (ctl>>28) 1433 1434 #define TFD_TX_CMD_SLOTS 64 1435 #define TFD_CMD_SLOTS 32 1436 1437 /* 1438 * Tx/Rx Queues 1439 * 1440 * Most communication between driver and 4965 is via queues of data buffers. 1441 * For example, all commands that the driver issues to device's embedded 1442 * controller (uCode) are via the command queue (one of the Tx queues). All 1443 * uCode command responses/replies/notifications, including Rx frames, are 1444 * conveyed from uCode to driver via the Rx queue. 1445 * 1446 * Most support for these queues, including handshake support, resides in 1447 * structures in host DRAM, shared between the driver and the device. When 1448 * allocating this memory, the driver must make sure that data written by 1449 * the host CPU updates DRAM immediately (and does not get "stuck" in CPU's 1450 * cache memory), so DRAM and cache are consistent, and the device can 1451 * immediately see changes made by the driver. 1452 * 1453 * 4965 supports up to 16 DRAM-based Tx queues, and services these queues via 1454 * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array 1455 * in DRAM containing 256 Transmit Frame Descriptors (TFDs). 1456 */ 1457 #define IWK_MAX_WIN_SIZE 64 1458 #define IWK_QUEUE_SIZE 256 1459 #define IWK_NUM_FIFOS 7 1460 #define IWK_NUM_QUEUES 6 1461 #define IWK_CMD_QUEUE_NUM 4 1462 #define IWK_KW_SIZE 0x1000 /* 4k */ 1463 1464 struct iwk_rate { 1465 union { 1466 struct { 1467 uint8_t rate; 1468 uint8_t flags; 1469 uint16_t ext_flags; 1470 } s; 1471 uint32_t rate_n_flags; 1472 } r; 1473 }; 1474 1475 struct iwk_dram_scratch { 1476 uint8_t try_cnt; 1477 uint8_t bt_kill_cnt; 1478 uint16_t reserved; 1479 }; 1480 1481 /* 1482 * START TEMPERATURE 1483 */ 1484 /* 1485 * 4965 temperature calculation. 1486 * 1487 * The driver must calculate the device temperature before calculating 1488 * a txpower setting (amplifier gain is temperature dependent). The 1489 * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration 1490 * values used for the life of the driver, and one of which (R4) is the 1491 * real-time temperature indicator. 1492 * 1493 * uCode provides all 4 values to the driver via the "initialize alive" 1494 * notification (see struct iwk_init_alive_resp). After the runtime uCode 1495 * image loads, uCode updates the R4 value via statistics notifications 1496 * (see STATISTICS_NOTIFICATION), which occur after each received beacon 1497 * when associated, or can be requested via REPLY_STATISTICS_CMD. 1498 * 1499 * NOTE: uCode provides the R4 value as a 23-bit signed value. Driver 1500 * must sign-extend to 32 bits before applying formula below. 1501 * 1502 * Formula: 1503 * 1504 * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8 1505 * 1506 * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is 1507 * an additional correction, which should be centered around 0 degrees 1508 * Celsius (273 degrees Kelvin). The 8 (3 percent of 273) compensates for 1509 * centering the 97/100 correction around 0 degrees K. 1510 * 1511 * Add 273 to Kelvin value to find degrees Celsius, for comparing current 1512 * temperature with factory-measured temperatures when calculating txpower 1513 * settings. 1514 */ 1515 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8 1516 #define TEMPERATURE_CALIB_A_VAL 259 1517 1518 /* 1519 * Limit range of calculated temperature to be between these Kelvin values 1520 */ 1521 #define IWK_TX_POWER_TEMPERATURE_MIN (263) 1522 #define IWK_TX_POWER_TEMPERATURE_MAX (410) 1523 1524 #define IWK_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \ 1525 (((t) < IWK_TX_POWER_TEMPERATURE_MIN) || \ 1526 ((t) > IWK_TX_POWER_TEMPERATURE_MAX)) 1527 1528 /* 1529 * END TEMPERATURE 1530 */ 1531 1532 /* 1533 * START TXPOWER 1534 */ 1535 /* 1536 * 4965 txpower calculations rely on information from three sources: 1537 * 1538 * 1) EEPROM 1539 * 2) "initialize" alive notification 1540 * 3) statistics notifications 1541 * 1542 * EEPROM data consists of: 1543 * 1544 * 1) Regulatory information (max txpower and channel usage flags) is provided 1545 * separately for each channel that can possibly supported by 4965. 1546 * 40 MHz wide (.11n fat) channels are listed separately from 20 MHz 1547 * (legacy) channels. 1548 * 1549 * See struct iwk_eeprom_channel for format, and struct iwk_eeprom for 1550 * locations in EEPROM. 1551 * 1552 * 2) Factory txpower calibration information is provided separately for 1553 * sub-bands of contiguous channels. 2.4GHz has just one sub-band, 1554 * but 5 GHz has several sub-bands. 1555 * 1556 * In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided. 1557 * 1558 * See struct iwk_eeprom_calib_info (and the tree of structures contained 1559 * within it) for format, and struct iwk_eeprom for locations in EEPROM. 1560 * 1561 * "Initialization alive" notification (see struct iwk_init_alive_resp) 1562 * consists of: 1563 * 1564 * 1) Temperature calculation parameters. 1565 * 1566 * 2) Power supply voltage measurement. 1567 * 1568 * 3) Tx gain compensation to balance 2 transmitters for MIMO use. 1569 * 1570 * Statistics notifications deliver: 1571 * 1572 * 1) Current values for temperature param R4. 1573 */ 1574 1575 /* 1576 * To calculate a txpower setting for a given desired target txpower, channel, 1577 * modulation bit rate, and transmitter chain (4965 has 2 transmitters to 1578 * support MIMO and transmit diversity), driver must do the following: 1579 * 1580 * 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel. 1581 * Do not exceed regulatory limit; reduce target txpower if necessary. 1582 * 1583 * If setting up txpowers for MIMO rates (rate indexes 8-15, 24-31), 1584 * 2 transmitters will be used simultaneously; driver must reduce the 1585 * regulatory limit by 3 dB (half-power) for each transmitter, so the 1586 * combined total output of the 2 transmitters is within regulatory limits. 1587 * 1588 * 1589 * 2) Compare target txpower vs. (EEPROM) saturation txpower *reduced by 1590 * backoff for this bit rate*. Do not exceed (saturation - backoff[rate]); 1591 * reduce target txpower if necessary. 1592 * 1593 * Backoff values below are in 1/2 dB units (equivalent to steps in 1594 * txpower gain tables): 1595 * 1596 * OFDM 6 - 36 MBit: 10 steps (5 dB) 1597 * OFDM 48 MBit: 15 steps (7.5 dB) 1598 * OFDM 54 MBit: 17 steps (8.5 dB) 1599 * OFDM 60 MBit: 20 steps (10 dB) 1600 * CCK all rates: 10 steps (5 dB) 1601 * 1602 * Backoff values apply to saturation txpower on a per-transmitter basis; 1603 * when using MIMO (2 transmitters), each transmitter uses the same 1604 * saturation level provided in EEPROM, and the same backoff values; 1605 * no reduction (such as with regulatory txpower limits) is required. 1606 * 1607 * Saturation and Backoff values apply equally to 20 Mhz (legacy) channel 1608 * widths and 40 Mhz (.11n fat) channel widths; there is no separate 1609 * factory measurement for fat channels. 1610 * 1611 * The result of this step is the final target txpower. The rest of 1612 * the steps figure out the proper settings for the device. 1613 * 1614 * 1615 * 3) Determine (EEPROM) calibration subband for the target channel, by 1616 * comparing against first and last channels in each subband 1617 * (see struct iwk_eeprom_calib_subband_info). 1618 * 1619 * 1620 * 4) Linearly interpolate (EEPROM) factory calibration measurement sets, 1621 * referencing the 2 factory-measured (sample) channels within the subband. 1622 * 1623 * Interpolation is based on difference between target channel's frequency 1624 * and the sample channels' frequencies. Since channel numbers are based 1625 * on frequency (5 MHz between each channel number), this is equivalent 1626 * to interpolating based on channel number differences. 1627 * 1628 * Note that the sample channels may or may not be the channels at the 1629 * edges of the subband. The target channel may be "outside" of the 1630 * span of the sampled channels. 1631 * 1632 * Driver may choose the pair (for 2 Tx chains) of measurements (see 1633 * struct iwk_eeprom_calib_ch_info) for which the actual measured 1634 * txpower comes closest to the desired txpower. Usually, though, 1635 * the middle set of measurements is closest to the regulatory limits, 1636 * and is therefore a good choice for all txpower calculations. 1637 * 1638 * Driver should interpolate both members of the chosen measurement pair, 1639 * i.e. for both Tx chains (radio transmitters), unless the driver knows 1640 * that only one of the chains will be used (e.g. only one tx antenna 1641 * connected, but this should be unusual). 1642 * 1643 * Driver should interpolate factory values for temperature, gain table 1644 * index, and actual power. The power amplifier detector values are 1645 * not used by the driver. 1646 * 1647 * If the target channel happens to be one of the sample channels, the 1648 * results should agree with the sample channel's measurements! 1649 * 1650 * 1651 * 5) Find difference between desired txpower and (interpolated) 1652 * factory-measured txpower. Using (interpolated) factory gain table index 1653 * as a starting point, adjust this index lower to increase txpower, 1654 * or higher to decrease txpower, until the target txpower is reached. 1655 * Each step in the gain table is 1/2 dB. 1656 * 1657 * For example, if factory measured txpower is 16 dBm, and target txpower 1658 * is 13 dBm, add 6 steps to the factory gain index to reduce txpower 1659 * by 3 dB. 1660 * 1661 * 1662 * 6) Find difference between current device temperature and (interpolated) 1663 * factory-measured temperature for sub-band. Factory values are in 1664 * degrees Celsius. To calculate current temperature, see comments for 1665 * "4965 temperature calculation". 1666 * 1667 * If current temperature is higher than factory temperature, driver must 1668 * increase gain (lower gain table index), and vice versa. 1669 * 1670 * Temperature affects gain differently for different channels: 1671 * 1672 * 2.4 GHz all channels: 3.5 degrees per half-dB step 1673 * 5 GHz channels 34-43: 4.5 degrees per half-dB step 1674 * 5 GHz channels >= 44: 4.0 degrees per half-dB step 1675 * 1676 * NOTE: Temperature can increase rapidly when transmitting, especially 1677 * with heavy traffic at high txpowers. Driver should update 1678 * temperature calculations often under these conditions to 1679 * maintain strong txpower in the face of rising temperature. 1680 * 1681 * 1682 * 7) Find difference between current power supply voltage indicator 1683 * (from "initialize alive") and factory-measured power supply voltage 1684 * indicator (EEPROM). 1685 * 1686 * If the current voltage is higher (indicator is lower) than factory 1687 * voltage, gain should be reduced (gain table index increased) by: 1688 * 1689 * (eeprom - current) / 7 1690 * 1691 * If the current voltage is lower (indicator is higher) than factory 1692 * voltage, gain should be increased (gain table index decreased) by: 1693 * 1694 * 2 * (current - eeprom) / 7 1695 * 1696 * If number of index steps in either direction turns out to be > 2, 1697 * something is wrong ... just use 0. 1698 * 1699 * NOTE: Voltage compensation is independent of band/channel. 1700 * 1701 * NOTE: "Initialize" uCode measures current voltage, which is assumed 1702 * to be constant after this initial measurement. Voltage 1703 * compensation for txpower (number of steps in gain table) 1704 * may be calculated once and used until the next uCode bootload. 1705 * 1706 * 1707 * 8) If setting up txpowers for MIMO rates (rate indexes 8-15, 24-31), 1708 * adjust txpower for each transmitter chain, so txpower is balanced 1709 * between the two chains. There are 5 pairs of tx_atten[group][chain] 1710 * values in "initialize alive", one pair for each of 5 channel ranges: 1711 * 1712 * Group 0: 5 GHz channel 34-43 1713 * Group 1: 5 GHz channel 44-70 1714 * Group 2: 5 GHz channel 71-124 1715 * Group 3: 5 GHz channel 125-200 1716 * Group 4: 2.4 GHz all channels 1717 * 1718 * Add the tx_atten[group][chain] value to the index for the target chain. 1719 * The values are signed, but are in pairs of 0 and a non-negative number, 1720 * so as to reduce gain (if necessary) of the "hotter" channel. This 1721 * avoids any need to double-check for regulatory compliance after 1722 * this step. 1723 * 1724 * 1725 * 9) If setting up for a CCK rate, lower the gain by adding a CCK compensation 1726 * value to the index: 1727 * 1728 * Hardware rev B: 9 steps (4.5 dB) 1729 * Hardware rev C: 5 steps (2.5 dB) 1730 * 1731 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG, 1732 * bits [3:2], 1 = B, 2 = C. 1733 * 1734 * NOTE: This compensation is in addition to any saturation backoff that 1735 * might have been applied in an earlier step. 1736 * 1737 * 1738 * 10) Select the gain table, based on band (2.4 vs 5 GHz). 1739 * 1740 * Limit the adjusted index to stay within the table! 1741 * 1742 * 1743 * 11) Read gain table entries for DSP and radio gain, place into appropriate 1744 * location(s) in command. 1745 */ 1746 1747 enum { 1748 HT_IE_EXT_CHANNEL_NONE = 0, 1749 HT_IE_EXT_CHANNEL_ABOVE, 1750 HT_IE_EXT_CHANNEL_INVALID, 1751 HT_IE_EXT_CHANNEL_BELOW, 1752 HT_IE_EXT_CHANNEL_MAX 1753 }; 1754 1755 enum { 1756 CALIB_CH_GROUP_1 = 0, 1757 CALIB_CH_GROUP_2 = 1, 1758 CALIB_CH_GROUP_3 = 2, 1759 CALIB_CH_GROUP_4 = 3, 1760 CALIB_CH_GROUP_5 = 4, 1761 CALIB_CH_GROUP_MAX 1762 }; 1763 1764 #define POWER_TABLE_NUM_HT_OFDM_ENTRIES (32) 1765 1766 /* 1767 * Temperature calibration offset is 3% 0C in Kelvin 1768 */ 1769 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8 1770 #define TEMPERATURE_CALIB_A_VAL 259 1771 1772 #define IWK_TX_POWER_TEMPERATURE_MIN (263) 1773 #define IWK_TX_POWER_TEMPERATURE_MAX (410) 1774 1775 #define IWK_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \ 1776 (((t) < IWK_TX_POWER_TEMPERATURE_MIN) || \ 1777 ((t) > IWK_TX_POWER_TEMPERATURE_MAX)) 1778 1779 #define IWK_TX_POWER_ILLEGAL_TEMPERATURE (300) 1780 1781 #define IWK_TX_POWER_TEMPERATURE_DIFFERENCE (2) 1782 1783 /* 1784 * When MIMO is used (2 transmitters operating simultaneously), driver should 1785 * limit each transmitter to deliver a max of 3 dB below the regulatory limit 1786 * for the device. That is, half power for each transmitter, so total power 1787 * is within regulatory limits. 1788 * 1789 * The value "6" represents number of steps in gain table to reduce power. 1790 * Each step is 1/2 dB. 1791 */ 1792 #define IWK_TX_POWER_MIMO_REGULATORY_COMPENSATION (6) 1793 1794 /* 1795 * Limit range of txpower output target to be between these values 1796 */ 1797 #define IWK_TX_POWER_TARGET_POWER_MIN (0) /* 0 dBm = 1 milliwatt */ 1798 #define IWK_TX_POWER_TARGET_POWER_MAX (16) /* 16 dBm */ 1799 1800 /* 1801 * timeout equivalent to 3 minutes 1802 */ 1803 #define IWK_TX_POWER_TIMELIMIT_NOCALIB 1800000000 1804 1805 /* 1806 * CCK gain compensation. 1807 * 1808 * When calculating txpowers for CCK, after making sure that the target power 1809 * is within regulatory and saturation limits, driver must additionally 1810 * back off gain by adding these values to the gain table index. 1811 */ 1812 #define IWK_TX_POWER_CCK_COMPENSATION (9) 1813 #define IWK_TX_POWER_CCK_COMPENSATION_B_STEP (9) 1814 #define IWK_TX_POWER_CCK_COMPENSATION_C_STEP (5) 1815 1816 /* 1817 * 4965 power supply voltage compensation 1818 */ 1819 #define TX_POWER_IWK_VOLTAGE_CODES_PER_03V (7) 1820 1821 /* 1822 * Gain tables. 1823 * 1824 * The following tables contain pair of values for setting txpower, i.e. 1825 * gain settings for the output of the device's digital signal processor (DSP), 1826 * and for the analog gain structure of the transmitter. 1827 * 1828 * Each entry in the gain tables represents a step of 1/2 dB. Note that these 1829 * are *relative* steps, not indications of absolute output power. Output 1830 * power varies with temperature, voltage, and channel frequency, and also 1831 * requires consideration of average power (to satisfy regulatory constraints), 1832 * and peak power (to avoid distortion of the output signal). 1833 * 1834 * Each entry contains two values: 1835 * 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained 1836 * linear value that multiplies the output of the digital signal processor, 1837 * before being sent to the analog radio. 1838 * 2) Radio gain. This sets the analog gain of the radio Tx path. 1839 * It is a coarser setting, and behaves in a logarithmic (dB) fashion. 1840 * 1841 * EEPROM contains factory calibration data for txpower. This maps actual 1842 * measured txpower levels to gain settings in the "well known" tables 1843 * below ("well-known" means here that both factory calibration *and* the 1844 * driver work with the same table). 1845 * 1846 * There are separate tables for 2.4 GHz and 5 GHz bands. The 5 GHz table 1847 * has an extension (into negative indexes), in case the driver needs to 1848 * boost power setting for high device temperatures (higher than would be 1849 * present during factory calibration). A 5 Ghz EEPROM index of "40" 1850 * corresponds to the 49th entry in the table used by the driver. 1851 */ 1852 #define MIN_TX_GAIN_INDEX (0) 1853 #define MIN_TX_GAIN_INDEX_52GHZ_EXT (-9) 1854 #define MAX_TX_GAIN_INDEX_52GHZ (98) 1855 #define MIN_TX_GAIN_52GHZ (98) 1856 #define MAX_TX_GAIN_INDEX_24GHZ (98) 1857 #define MIN_TX_GAIN_24GHZ (98) 1858 #define MAX_TX_GAIN (0) 1859 #define MAX_TX_GAIN_52GHZ_EXT (-9) 1860 1861 /* 1862 * 2.4 GHz gain table 1863 * 1864 * Index Dsp gain Radio gain 1865 * 0 110 0x3f 1866 * 1 104 0x3f 1867 * 2 98 0x3f 1868 * 3 110 0x3e 1869 * 4 104 0x3e 1870 * 5 98 0x3e 1871 * 6 110 0x3d 1872 * 7 104 0x3d 1873 * 8 98 0x3d 1874 * 9 110 0x3c 1875 * 10 104 0x3c 1876 * 11 98 0x3c 1877 * 12 110 0x3b 1878 * 13 104 0x3b 1879 * 14 98 0x3b 1880 * 15 110 0x3a 1881 * 16 104 0x3a 1882 * 17 98 0x3a 1883 * 18 110 0x39 1884 * 19 104 0x39 1885 * 20 98 0x39 1886 * 21 110 0x38 1887 * 22 104 0x38 1888 * 23 98 0x38 1889 * 24 110 0x37 1890 * 25 104 0x37 1891 * 26 98 0x37 1892 * 27 110 0x36 1893 * 28 104 0x36 1894 * 29 98 0x36 1895 * 30 110 0x35 1896 * 31 104 0x35 1897 * 32 98 0x35 1898 * 33 110 0x34 1899 * 34 104 0x34 1900 * 35 98 0x34 1901 * 36 110 0x33 1902 * 37 104 0x33 1903 * 38 98 0x33 1904 * 39 110 0x32 1905 * 40 104 0x32 1906 * 41 98 0x32 1907 * 42 110 0x31 1908 * 43 104 0x31 1909 * 44 98 0x31 1910 * 45 110 0x30 1911 * 46 104 0x30 1912 * 47 98 0x30 1913 * 48 110 0x6 1914 * 49 104 0x6 1915 * 50 98 0x6 1916 * 51 110 0x5 1917 * 52 104 0x5 1918 * 53 98 0x5 1919 * 54 110 0x4 1920 * 55 104 0x4 1921 * 56 98 0x4 1922 * 57 110 0x3 1923 * 58 104 0x3 1924 * 59 98 0x3 1925 * 60 110 0x2 1926 * 61 104 0x2 1927 * 62 98 0x2 1928 * 63 110 0x1 1929 * 64 104 0x1 1930 * 65 98 0x1 1931 * 66 110 0x0 1932 * 67 104 0x0 1933 * 68 98 0x0 1934 * 69 97 0 1935 * 70 96 0 1936 * 71 95 0 1937 * 72 94 0 1938 * 73 93 0 1939 * 74 92 0 1940 * 75 91 0 1941 * 76 90 0 1942 * 77 89 0 1943 * 78 88 0 1944 * 79 87 0 1945 * 80 86 0 1946 * 81 85 0 1947 * 82 84 0 1948 * 83 83 0 1949 * 84 82 0 1950 * 85 81 0 1951 * 86 80 0 1952 * 87 79 0 1953 * 88 78 0 1954 * 89 77 0 1955 * 90 76 0 1956 * 91 75 0 1957 * 92 74 0 1958 * 93 73 0 1959 * 94 72 0 1960 * 95 71 0 1961 * 96 70 0 1962 * 97 69 0 1963 * 98 68 0 1964 */ 1965 1966 /* 1967 * 5 GHz gain table 1968 * 1969 * Index Dsp gain Radio gain 1970 * -9 123 0x3F 1971 * -8 117 0x3F 1972 * -7 110 0x3F 1973 * -6 104 0x3F 1974 * -5 98 0x3F 1975 * -4 110 0x3E 1976 * -3 104 0x3E 1977 * -2 98 0x3E 1978 * -1 110 0x3D 1979 * 0 104 0x3D 1980 * 1 98 0x3D 1981 * 2 110 0x3C 1982 * 3 104 0x3C 1983 * 4 98 0x3C 1984 * 5 110 0x3B 1985 * 6 104 0x3B 1986 * 7 98 0x3B 1987 * 8 110 0x3A 1988 * 9 104 0x3A 1989 * 10 98 0x3A 1990 * 11 110 0x39 1991 * 12 104 0x39 1992 * 13 98 0x39 1993 * 14 110 0x38 1994 * 15 104 0x38 1995 * 16 98 0x38 1996 * 17 110 0x37 1997 * 18 104 0x37 1998 * 19 98 0x37 1999 * 20 110 0x36 2000 * 21 104 0x36 2001 * 22 98 0x36 2002 * 23 110 0x35 2003 * 24 104 0x35 2004 * 25 98 0x35 2005 * 26 110 0x34 2006 * 27 104 0x34 2007 * 28 98 0x34 2008 * 29 110 0x33 2009 * 30 104 0x33 2010 * 31 98 0x33 2011 * 32 110 0x32 2012 * 33 104 0x32 2013 * 34 98 0x32 2014 * 35 110 0x31 2015 * 36 104 0x31 2016 * 37 98 0x31 2017 * 38 110 0x30 2018 * 39 104 0x30 2019 * 40 98 0x30 2020 * 41 110 0x25 2021 * 42 104 0x25 2022 * 43 98 0x25 2023 * 44 110 0x24 2024 * 45 104 0x24 2025 * 46 98 0x24 2026 * 47 110 0x23 2027 * 48 104 0x23 2028 * 49 98 0x23 2029 * 50 110 0x22 2030 * 51 104 0x18 2031 * 52 98 0x18 2032 * 53 110 0x17 2033 * 54 104 0x17 2034 * 55 98 0x17 2035 * 56 110 0x16 2036 * 57 104 0x16 2037 * 58 98 0x16 2038 * 59 110 0x15 2039 * 60 104 0x15 2040 * 61 98 0x15 2041 * 62 110 0x14 2042 * 63 104 0x14 2043 * 64 98 0x14 2044 * 65 110 0x13 2045 * 66 104 0x13 2046 * 67 98 0x13 2047 * 68 110 0x12 2048 * 69 104 0x08 2049 * 70 98 0x08 2050 * 71 110 0x07 2051 * 72 104 0x07 2052 * 73 98 0x07 2053 * 74 110 0x06 2054 * 75 104 0x06 2055 * 76 98 0x06 2056 * 77 110 0x05 2057 * 78 104 0x05 2058 * 79 98 0x05 2059 * 80 110 0x04 2060 * 81 104 0x04 2061 * 82 98 0x04 2062 * 83 110 0x03 2063 * 84 104 0x03 2064 * 85 98 0x03 2065 * 86 110 0x02 2066 * 87 104 0x02 2067 * 88 98 0x02 2068 * 89 110 0x01 2069 * 90 104 0x01 2070 * 91 98 0x01 2071 * 92 110 0x00 2072 * 93 104 0x00 2073 * 94 98 0x00 2074 * 95 93 0x00 2075 * 96 88 0x00 2076 * 97 83 0x00 2077 * 98 78 0x00 2078 */ 2079 2080 /* 2081 * Sanity checks and default values for EEPROM regulatory levels. 2082 * If EEPROM values fall outside MIN/MAX range, use default values. 2083 * 2084 * Regulatory limits refer to the maximum average txpower allowed by 2085 * regulatory agencies in the geographies in which the device is meant 2086 * to be operated. These limits are SKU-specific (i.e. geography-specific), 2087 * and channel-specific; each channel has an individual regulatory limit 2088 * listed in the EEPROM. 2089 * 2090 * Units are in half-dBm (i.e. "34" means 17 dBm). 2091 */ 2092 #define IWK_TX_POWER_DEFAULT_REGULATORY_24 (34) 2093 #define IWK_TX_POWER_DEFAULT_REGULATORY_52 (34) 2094 #define IWK_TX_POWER_REGULATORY_MIN (0) 2095 #define IWK_TX_POWER_REGULATORY_MAX (34) 2096 2097 /* 2098 * Sanity checks and default values for EEPROM saturation levels. 2099 * If EEPROM values fall outside MIN/MAX range, use default values. 2100 * 2101 * Saturation is the highest level that the output power amplifier can produce 2102 * without significant clipping distortion. This is a "peak" power level. 2103 * Different types of modulation (i.e. various "rates", and OFDM vs. CCK) 2104 * require differing amounts of backoff, relative to their average power output, 2105 * in order to avoid clipping distortion. 2106 * 2107 * Driver must make sure that it is violating neither the saturation limit, 2108 * nor the regulatory limit, when calculating Tx power settings for various 2109 * rates. 2110 * 2111 * Units are in half-dBm (i.e. "38" means 19 dBm). 2112 */ 2113 #define IWK_TX_POWER_DEFAULT_SATURATION_24 (38) 2114 #define IWK_TX_POWER_DEFAULT_SATURATION_52 (38) 2115 #define IWK_TX_POWER_SATURATION_MIN (20) 2116 #define IWK_TX_POWER_SATURATION_MAX (50) 2117 2118 /* 2119 * dv *0.4 = dt; so that 5 degrees temperature diff equals 2120 * 12.5 in voltage diff 2121 */ 2122 #define IWK_TX_TEMPERATURE_UPDATE_LIMIT 9 2123 2124 #define IWK_INVALID_CHANNEL (0xffffffff) 2125 #define IWK_TX_POWER_REGITRY_BIT (2) 2126 2127 #define MIN_IWK_TX_POWER_CALIB_DUR (100) 2128 #define IWK_CCK_FROM_OFDM_POWER_DIFF (-5) 2129 #define IWK_CCK_FROM_OFDM_INDEX_DIFF (9) 2130 2131 /* 2132 * Number of entries in the gain table 2133 */ 2134 #define POWER_GAIN_NUM_ENTRIES 78 2135 #define TX_POW_MAX_SESSION_NUM 5 2136 2137 /* 2138 * timeout equivalent to 3 minutes 2139 */ 2140 #define TX_IWK_TIMELIMIT_NOCALIB 1800000000 2141 2142 /* 2143 * Kedron TX_CALIB_STATES 2144 */ 2145 #define IWK_TX_CALIB_STATE_SEND_TX 0x00000001 2146 #define IWK_TX_CALIB_WAIT_TX_RESPONSE 0x00000002 2147 #define IWK_TX_CALIB_ENABLED 0x00000004 2148 #define IWK_TX_CALIB_XVT_ON 0x00000008 2149 #define IWK_TX_CALIB_TEMPERATURE_CORRECT 0x00000010 2150 #define IWK_TX_CALIB_WORKING_WITH_XVT 0x00000020 2151 #define IWK_TX_CALIB_XVT_PERIODICAL 0x00000040 2152 2153 #define NUM_IWK_TX_CALIB_SETTINS 5 /* Number of tx correction groups */ 2154 2155 #define IWK_MIN_POWER_IN_VP_TABLE 1 /* 0.5dBm multiplied by 2 */ 2156 /* 20dBm - multiplied by 2 - because entries are for each 0.5dBm */ 2157 #define IWK_MAX_POWER_IN_VP_TABLE 40 2158 #define IWK_STEP_IN_VP_TABLE 1 /* 0.5dB - multiplied by 2 */ 2159 #define IWK_NUM_POINTS_IN_VPTABLE \ 2160 (1 + IWK_MAX_POWER_IN_VP_TABLE - IWK_MIN_POWER_IN_VP_TABLE) 2161 2162 #define MIN_TX_GAIN_INDEX (0) 2163 #define MAX_TX_GAIN_INDEX_52GHZ (98) 2164 #define MIN_TX_GAIN_52GHZ (98) 2165 #define MAX_TX_GAIN_INDEX_24GHZ (98) 2166 #define MIN_TX_GAIN_24GHZ (98) 2167 #define MAX_TX_GAIN (0) 2168 2169 /* 2170 * Channel groups used for Tx Attenuation calibration (MIMO tx channel balance) 2171 * and thermal Txpower calibration. 2172 * 2173 * When calculating txpower, driver must compensate for current device 2174 * temperature; higher temperature requires higher gain. Driver must calculate 2175 * current temperature (see "4965 temperature calculation"), then compare vs. 2176 * factory calibration temperature in EEPROM; if current temperature is higher 2177 * than factory temperature, driver must *increase* gain by proportions shown 2178 * in table below. If current temperature is lower than factory, driver must 2179 * *decrease* gain. 2180 * 2181 * Different frequency ranges require different compensation, as shown below. 2182 */ 2183 /* 2184 * Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. 2185 */ 2186 #define CALIB_IWK_TX_ATTEN_GR1_FCH 34 2187 #define CALIB_IWK_TX_ATTEN_GR1_LCH 43 2188 2189 /* 2190 * Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. 2191 */ 2192 #define CALIB_IWK_TX_ATTEN_GR2_FCH 44 2193 #define CALIB_IWK_TX_ATTEN_GR2_LCH 70 2194 2195 /* 2196 * Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. 2197 */ 2198 #define CALIB_IWK_TX_ATTEN_GR3_FCH 71 2199 #define CALIB_IWK_TX_ATTEN_GR3_LCH 124 2200 2201 /* 2202 * Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. 2203 */ 2204 #define CALIB_IWK_TX_ATTEN_GR4_FCH 125 2205 #define CALIB_IWK_TX_ATTEN_GR4_LCH 200 2206 2207 /* 2208 * Group 4, 2.4 GHz all channels: 3.5 degrees per 1/2 dB. 2209 */ 2210 #define CALIB_IWK_TX_ATTEN_GR5_FCH 1 2211 #define CALIB_IWK_TX_ATTEN_GR5_LCH 20 2212 2213 struct iwk_tx_power { 2214 uint8_t tx_gain; /* gain for analog radio */ 2215 uint8_t dsp_atten; /* gain for DSP */ 2216 }; 2217 2218 struct tx_power_dual_stream { 2219 uint16_t ramon_tx_gain; 2220 uint16_t dsp_predis_atten; 2221 }; 2222 2223 union tx_power_dual_stream_u { 2224 struct tx_power_dual_stream s; 2225 uint32_t dw; 2226 }; 2227 2228 struct iwk_tx_power_db { 2229 union tx_power_dual_stream_u 2230 ht_ofdm_power[POWER_TABLE_NUM_HT_OFDM_ENTRIES]; 2231 union tx_power_dual_stream_u legacy_cck_power; 2232 2233 }; 2234 2235 typedef struct iwk_tx_power_table_cmd { 2236 uint8_t band; 2237 uint8_t channel_normal_width; 2238 uint16_t channel; 2239 struct iwk_tx_power_db tx_power; 2240 } iwk_tx_power_table_cmd_t; 2241 2242 typedef struct iwk_channel_switch_cmd { 2243 uint8_t band; 2244 uint8_t expect_beacon; 2245 uint16_t channel; 2246 uint32_t rxon_flags; 2247 uint32_t rxon_filter_flags; 2248 uint32_t switch_time; 2249 struct iwk_tx_power_db tx_power; 2250 } iwk_channel_switch_cmd_t; 2251 2252 struct iwk_channel_switch_notif { 2253 uint16_t band; 2254 uint16_t channel; 2255 uint32_t status; 2256 }; 2257 2258 /* 2259 * END TXPOWER 2260 */ 2261 2262 /* 2263 * HT flags 2264 */ 2265 #define RXON_FLG_CONTROL_CHANNEL_LOCATION_MSK 0x400000 2266 #define RXON_FLG_CONTROL_CHANNEL_LOC_LOW_MSK 0x000000 2267 #define RXON_FLG_CONTROL_CHANNEL_LOC_HIGH_MSK 0x400000 2268 2269 #define RXON_FLG_HT_OPERATING_MODE_POS (23) 2270 #define RXON_FLG_HT_PROT_MSK 0x800000 2271 #define RXON_FLG_FAT_PROT_MSK 0x1000000 2272 2273 #define RXON_FLG_CHANNEL_MODE_POS (25) 2274 #define RXON_FLG_CHANNEL_MODE_MSK 0x06000000 2275 #define RXON_FLG_CHANNEL_MODE_LEGACY_MSK 0x00000000 2276 #define RXON_FLG_CHANNEL_MODE_PURE_40_MSK 0x02000000 2277 #define RXON_FLG_CHANNEL_MODE_MIXED_MSK 0x04000000 2278 2279 #define RXON_RX_CHAIN_DRIVER_FORCE_MSK (0x1<<0) 2280 #define RXON_RX_CHAIN_VALID_MSK (0x7<<1) 2281 #define RXON_RX_CHAIN_VALID_POS (1) 2282 #define RXON_RX_CHAIN_FORCE_SEL_MSK (0x7<<4) 2283 #define RXON_RX_CHAIN_FORCE_SEL_POS (4) 2284 #define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK (0x7<<7) 2285 #define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2286 #define RXON_RX_CHAIN_CNT_MSK (0x3<<10) 2287 #define RXON_RX_CHAIN_CNT_POS (10) 2288 #define RXON_RX_CHAIN_MIMO_CNT_MSK (0x3<<12) 2289 #define RXON_RX_CHAIN_MIMO_CNT_POS (12) 2290 #define RXON_RX_CHAIN_MIMO_FORCE_MSK (0x1<<14) 2291 #define RXON_RX_CHAIN_MIMO_FORCE_POS (14) 2292 2293 #define MCS_DUP_6M_PLCP 0x20 2294 2295 /* 2296 * OFDM HT rate masks 2297 */ 2298 #define R_MCS_6M_MSK 0x1 2299 #define R_MCS_12M_MSK 0x2 2300 #define R_MCS_18M_MSK 0x4 2301 #define R_MCS_24M_MSK 0x8 2302 #define R_MCS_36M_MSK 0x10 2303 #define R_MCS_48M_MSK 0x20 2304 #define R_MCS_54M_MSK 0x40 2305 #define R_MCS_60M_MSK 0x80 2306 #define R_MCS_12M_DUAL_MSK 0x100 2307 #define R_MCS_24M_DUAL_MSK 0x200 2308 #define R_MCS_36M_DUAL_MSK 0x400 2309 #define R_MCS_48M_DUAL_MSK 0x800 2310 2311 #define RATE_MCS_CODE_MSK 0x7 2312 #define RATE_MCS_MIMO_POS 3 2313 #define RATE_MCS_MIMO_MSK 0x8 2314 #define RATE_MCS_HT_DUP_POS 5 2315 #define RATE_MCS_HT_DUP_MSK 0x20 2316 #define RATE_MCS_FLAGS_POS 8 2317 #define RATE_MCS_HT_POS 8 2318 #define RATE_MCS_HT_MSK 0x100 2319 #define RATE_MCS_CCK_POS 9 2320 #define RATE_MCS_CCK_MSK 0x200 2321 #define RATE_MCS_GF_POS 10 2322 #define RATE_MCS_GF_MSK 0x400 2323 2324 #define RATE_MCS_FAT_POS 11 2325 #define RATE_MCS_FAT_MSK 0x800 2326 #define RATE_MCS_DUP_POS 12 2327 #define RATE_MCS_DUP_MSK 0x1000 2328 #define RATE_MCS_SGI_POS 13 2329 #define RATE_MCS_SGI_MSK 0x2000 2330 2331 #define EEPROM_SEM_TIMEOUT 10 2332 #define EEPROM_SEM_RETRY_LIMIT 1000 2333 2334 /* 2335 * Antenna masks: 2336 * bit14:15 01 B inactive, A active 2337 * 10 B active, A inactive 2338 * 11 Both active 2339 */ 2340 #define RATE_MCS_ANT_A_POS 14 2341 #define RATE_MCS_ANT_B_POS 15 2342 #define RATE_MCS_ANT_A_MSK 0x4000 2343 #define RATE_MCS_ANT_B_MSK 0x8000 2344 #define RATE_MCS_ANT_AB_MSK 0xc000 2345 2346 #define is_legacy(tbl) (((tbl) == LQ_G) || ((tbl) == LQ_A)) 2347 #define is_siso(tbl) (((tbl) == LQ_SISO)) 2348 #define is_mimo(tbl) (((tbl) == LQ_MIMO)) 2349 #define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl)) 2350 #define is_a_band(tbl) (((tbl) == LQ_A)) 2351 #define is_g_and(tbl) (((tbl) == LQ_G)) 2352 2353 /* 2354 * RS_NEW_API: only TLC_RTS remains and moved to bit 0 2355 */ 2356 #define LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK (1<<0) 2357 2358 #define LINK_QUAL_AC_NUM 4 2359 #define LINK_QUAL_MAX_RETRY_NUM 16 2360 2361 #define LINK_QUAL_ANT_A_MSK (1<<0) 2362 #define LINK_QUAL_ANT_B_MSK (1<<1) 2363 #define LINK_QUAL_ANT_MSK (LINK_QUAL_ANT_A_MSK|LINK_QUAL_ANT_B_MSK) 2364 2365 struct iwk_link_qual_general_params { 2366 uint8_t flags; 2367 uint8_t mimo_delimiter; 2368 uint8_t single_stream_ant_msk; 2369 uint8_t dual_stream_ant_msk; 2370 uint8_t start_rate_index[LINK_QUAL_AC_NUM]; 2371 }; 2372 2373 struct iwk_link_qual_agg_params { 2374 uint16_t agg_time_limit; 2375 uint8_t agg_dis_start_th; 2376 uint8_t agg_frame_cnt_limit; 2377 uint32_t reserved; 2378 }; 2379 2380 typedef struct iwk_link_quality_cmd { 2381 uint8_t sta_id; 2382 uint8_t reserved1; 2383 uint16_t control; 2384 struct iwk_link_qual_general_params general_params; 2385 struct iwk_link_qual_agg_params agg_params; 2386 uint32_t rate_n_flags[LINK_QUAL_MAX_RETRY_NUM]; 2387 uint32_t reserved2; 2388 } iwk_link_quality_cmd_t; 2389 2390 typedef struct iwk_rx_phy_res { 2391 uint8_t non_cfg_phy_cnt; /* non configurable DSP phy data byte count */ 2392 uint8_t cfg_phy_cnt; /* configurable DSP phy data byte count */ 2393 uint8_t stat_id; /* configurable DSP phy data set ID */ 2394 uint8_t reserved1; 2395 uint32_t timestampl; /* TSF at on air rise */ 2396 uint32_t timestamph; 2397 uint32_t beacon_time_stamp; /* beacon at on-air rise */ 2398 uint16_t phy_flags; /* general phy flags: band, modulation, ... */ 2399 uint16_t channel; /* channel number */ 2400 uint16_t non_cfg_phy[RX_RES_PHY_CNT]; /* upto 14 phy entries */ 2401 uint32_t reserved2; 2402 struct iwk_rate rate; /* rate in ucode internal format */ 2403 uint16_t byte_count; /* frame's byte-count */ 2404 uint16_t reserved3; 2405 } iwk_rx_phy_res_t; 2406 2407 struct iwk_rx_mpdu_res_start { 2408 uint16_t byte_count; 2409 uint16_t reserved; 2410 }; 2411 2412 #define IWK_AGC_DB_MASK (0x3f80) /* MASK(7,13) */ 2413 #define IWK_AGC_DB_POS (7) 2414 2415 /* 2416 * Fixed (non-configurable) rx data from phy 2417 */ 2418 struct iwk_rx_non_cfg_phy { 2419 uint16_t ant_selection; /* ant A bit 4, ant B bit 5, ant C bit 6 */ 2420 uint16_t agc_info; /* agc code 0:6, agc dB 7:13, reserved 14:15 */ 2421 uint8_t rssi_info[6]; /* we use even entries, 0/2/4 for A/B/C rssi */ 2422 uint8_t pad[2]; 2423 }; 2424 2425 /* 2426 * Byte Count Table Entry 2427 * 2428 * Bit fields: 2429 * 15-12: reserved 2430 * 11- 0: total to-be-transmitted byte count of frame (does not include command) 2431 */ 2432 struct iwk_queue_byte_cnt_entry { 2433 uint16_t val; 2434 }; 2435 2436 /* 2437 * Byte Count table 2438 * 2439 * Each Tx queue uses a byte-count table containing 320 entries: 2440 * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that 2441 * duplicate the first 64 entries (to avoid wrap-around within a Tx window; 2442 * max Tx window is 64 TFDs). 2443 * 2444 * When driver sets up a new TFD, it must also enter the total byte count 2445 * of the frame to be transmitted into the corresponding entry in the byte 2446 * count table for the chosen Tx queue. If the TFD index is 0-63, the driver 2447 * must duplicate the byte count entry in corresponding index 256-319. 2448 * 2449 * "dont_care" padding puts each byte count table on a 1024-byte boundary; 2450 * 4965 assumes tables are separated by 1024 bytes. 2451 */ 2452 struct iwk_sched_queue_byte_cnt_tbl { 2453 struct iwk_queue_byte_cnt_entry tfd_offset[IWK_QUEUE_SIZE + 2454 IWK_MAX_WIN_SIZE]; 2455 uint8_t dont_care[1024 - (IWK_QUEUE_SIZE + IWK_MAX_WIN_SIZE) * 2456 sizeof (uint16_t)]; 2457 }; 2458 2459 /* 2460 * struct iwk_shared, handshake area for Tx and Rx 2461 * 2462 * For convenience in allocating memory, this structure combines 2 areas of 2463 * DRAM which must be shared between driver and 4965. These do not need to 2464 * be combined, if better allocation would result from keeping them separate: 2465 * TODO: Split these; carried over from 3945, doesn't work well for 4965. 2466 * 2467 * 1) The Tx byte count tables occupy 1024 bytes each (16 KBytes total for 2468 * 16 queues). Driver uses SCD_DRAM_BASE_ADDR to tell 4965 where to find 2469 * the first of these tables. 4965 assumes tables are 1024 bytes apart. 2470 * 2471 * 2) The Rx status (val0 and val1) occupies only 8 bytes. Driver uses 2472 * FH_RSCSR_CHNL0_STTS_WPTR_REG to tell 4965 where to find this area. 2473 * Driver reads val0 to determine the latest Receive Buffer Descriptor (RBD) 2474 * that has been filled by the 4965. 2475 * 2476 * Bit fields val0: 2477 * 31-12: Not used 2478 * 11- 0: Index of last filled Rx buffer descriptor (4965 writes, driver reads) 2479 * 2480 * Bit fields val1: 2481 * 31- 0: Not used 2482 */ 2483 typedef struct iwk_shared { 2484 struct iwk_sched_queue_byte_cnt_tbl 2485 queues_byte_cnt_tbls[IWK_NUM_QUEUES]; 2486 uint32_t val0; 2487 uint32_t val1; 2488 uint32_t padding1; /* so that allocation will be aligned to 16B */ 2489 uint32_t padding2; 2490 } iwk_shared_t; 2491 2492 2493 /* 2494 * struct iwk_tfd_frame_data 2495 * 2496 * Describes up to 2 buffers containing (contiguous) portions of a Tx frame. 2497 * Each buffer must be on dword boundary. 2498 * Up to 10 iwk_tfd_frame_data structures, describing up to 20 buffers, 2499 * may be filled within a TFD (iwk_tfd_frame). 2500 * 2501 * Bit fields in tb1_addr: 2502 * 31- 0: Tx buffer 1 address bits [31:0] 2503 * 2504 * Bit fields in val1: 2505 * 31-16: Tx buffer 2 address bits [15:0] 2506 * 15- 4: Tx buffer 1 length (bytes) 2507 * 3- 0: Tx buffer 1 address bits [32:32] 2508 * 2509 * Bit fields in val2: 2510 * 31-20: Tx buffer 2 length (bytes) 2511 * 19- 0: Tx buffer 2 address bits [35:16] 2512 */ 2513 struct iwk_tfd_frame_data { 2514 uint32_t tb1_addr; 2515 uint32_t val1; 2516 uint32_t val2; 2517 }; 2518 2519 typedef struct iwk_tx_desc { 2520 uint32_t val0; 2521 struct iwk_tfd_frame_data pa[10]; 2522 uint32_t reserved; 2523 } iwk_tx_desc_t; 2524 2525 typedef struct iwk_tx_stat { 2526 uint8_t frame_count; 2527 uint8_t bt_kill_count; 2528 uint8_t nrts; 2529 uint8_t ntries; 2530 struct iwk_rate rate; 2531 uint16_t duration; 2532 uint16_t reserved; 2533 uint32_t pa_power1; 2534 uint32_t pa_power2; 2535 uint32_t status; 2536 } iwk_tx_stat_t; 2537 2538 struct iwk_cmd_header { 2539 uint8_t type; 2540 uint8_t flags; 2541 uint8_t idx; 2542 uint8_t qid; 2543 }; 2544 2545 typedef struct iwk_rx_desc { 2546 uint32_t len; 2547 struct iwk_cmd_header hdr; 2548 } iwk_rx_desc_t; 2549 2550 typedef struct iwk_rx_stat { 2551 uint8_t len; 2552 uint8_t id; 2553 uint8_t rssi; /* received signal strength */ 2554 uint8_t agc; /* access gain control */ 2555 uint16_t signal; 2556 uint16_t noise; 2557 } iwk_rx_stat_t; 2558 2559 typedef struct iwk_rx_head { 2560 uint16_t chan; 2561 uint16_t flags; 2562 uint8_t reserved; 2563 uint8_t rate; 2564 uint16_t len; 2565 } iwk_rx_head_t; 2566 2567 typedef struct iwk_rx_tail { 2568 uint32_t flags; 2569 uint32_t timestampl; 2570 uint32_t timestamph; 2571 uint32_t tbeacon; 2572 } iwk_rx_tail_t; 2573 2574 enum { 2575 IWK_AP_ID = 0, 2576 IWK_MULTICAST_ID, 2577 IWK_STA_ID, 2578 IWK_BROADCAST_ID = 31, 2579 IWK_STATION_COUNT = 32, 2580 IWK_INVALID_STATION 2581 }; 2582 2583 /* 2584 * key flags 2585 */ 2586 enum { 2587 STA_KEY_FLG_ENCRYPT_MSK = 0x7, 2588 STA_KEY_FLG_NO_ENC = 0x0, 2589 STA_KEY_FLG_WEP = 0x1, 2590 STA_KEY_FLG_CCMP = 0x2, 2591 STA_KEY_FLG_TKIP = 0x3, 2592 2593 STA_KEY_FLG_KEYID_POS = 8, 2594 STA_KEY_FLG_INVALID = 0x0800, 2595 }; 2596 2597 /* 2598 * modify flags 2599 */ 2600 enum { 2601 STA_MODIFY_KEY_MASK = 0x01, 2602 STA_MODIFY_TID_DISABLE_TX = 0x02, 2603 STA_MODIFY_TX_RATE_MSK = 0x04 2604 }; 2605 2606 enum { 2607 RX_RES_STATUS_NO_CRC32_ERROR = (1 << 0), 2608 RX_RES_STATUS_NO_RXE_OVERFLOW = (1 << 1), 2609 }; 2610 2611 enum { 2612 RX_RES_PHY_FLAGS_BAND_24_MSK = (1 << 0), 2613 RX_RES_PHY_FLAGS_MOD_CCK_MSK = (1 << 1), 2614 RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK = (1 << 2), 2615 RX_RES_PHY_FLAGS_NARROW_BAND_MSK = (1 << 3), 2616 RX_RES_PHY_FLAGS_ANTENNA_MSK = 0xf0, 2617 2618 RX_RES_STATUS_SEC_TYPE_MSK = (0x7 << 8), 2619 RX_RES_STATUS_SEC_TYPE_NONE = (STA_KEY_FLG_NO_ENC << 8), 2620 RX_RES_STATUS_SEC_TYPE_WEP = (STA_KEY_FLG_WEP << 8), 2621 RX_RES_STATUS_SEC_TYPE_TKIP = (STA_KEY_FLG_TKIP << 8), 2622 RX_RES_STATUS_SEC_TYPE_CCMP = (STA_KEY_FLG_CCMP << 8), 2623 2624 RX_RES_STATUS_DECRYPT_TYPE_MSK = (0x3 << 11), 2625 RX_RES_STATUS_NOT_DECRYPT = (0x0 << 11), 2626 RX_RES_STATUS_DECRYPT_OK = (0x3 << 11), 2627 RX_RES_STATUS_BAD_ICV_MIC = (0x1 << 11), 2628 RX_RES_STATUS_BAD_KEY_TTAK = (0x2 << 11), 2629 }; 2630 2631 enum { 2632 REPLY_ALIVE = 0x1, 2633 REPLY_ERROR = 0x2, 2634 2635 /* RXON state commands */ 2636 REPLY_RXON = 0x10, 2637 REPLY_RXON_ASSOC = 0x11, 2638 REPLY_QOS_PARAM = 0x13, 2639 REPLY_RXON_TIMING = 0x14, 2640 2641 /* Multi-Station support */ 2642 REPLY_ADD_STA = 0x18, 2643 REPLY_REMOVE_ALL_STA = 0x1a, 2644 2645 /* RX, TX */ 2646 2647 REPLY_TX = 0x1c, 2648 2649 /* timers commands */ 2650 REPLY_BCON = 0x27, 2651 2652 REPLY_SHUTDOWN = 0x40, 2653 2654 /* MISC commands */ 2655 REPLY_RATE_SCALE = 0x47, 2656 REPLY_LEDS_CMD = 0x48, 2657 REPLY_TX_LINK_QUALITY_CMD = 0x4e, 2658 2659 /* 802.11h related */ 2660 RADAR_NOTIFICATION = 0x70, 2661 REPLY_QUIET_CMD = 0x71, 2662 REPLY_CHANNEL_SWITCH = 0x72, 2663 CHANNEL_SWITCH_NOTIFICATION = 0x73, 2664 REPLY_SPECTRUM_MEASUREMENT_CMD = 0x74, 2665 SPECTRUM_MEASURE_NOTIFICATION = 0x75, 2666 2667 /* Power Management *** */ 2668 POWER_TABLE_CMD = 0x77, 2669 PM_SLEEP_NOTIFICATION = 0x7A, 2670 PM_DEBUG_STATISTIC_NOTIFIC = 0x7B, 2671 2672 /* Scan commands and notifications */ 2673 REPLY_SCAN_CMD = 0x80, 2674 REPLY_SCAN_ABORT_CMD = 0x81, 2675 2676 SCAN_START_NOTIFICATION = 0x82, 2677 SCAN_RESULTS_NOTIFICATION = 0x83, 2678 SCAN_COMPLETE_NOTIFICATION = 0x84, 2679 2680 /* IBSS/AP commands */ 2681 BEACON_NOTIFICATION = 0x90, 2682 REPLY_TX_BEACON = 0x91, 2683 WHO_IS_AWAKE_NOTIFICATION = 0x94, 2684 2685 QUIET_NOTIFICATION = 0x96, 2686 REPLY_TX_PWR_TABLE_CMD = 0x97, 2687 MEASURE_ABORT_NOTIFICATION = 0x99, 2688 2689 REPLY_CALIBRATION_TUNE = 0x9a, 2690 2691 /* BT config command */ 2692 REPLY_BT_CONFIG = 0x9b, 2693 REPLY_STATISTICS_CMD = 0x9c, 2694 STATISTICS_NOTIFICATION = 0x9d, 2695 2696 /* RF-KILL commands and notifications *** */ 2697 REPLY_CARD_STATE_CMD = 0xa0, 2698 CARD_STATE_NOTIFICATION = 0xa1, 2699 2700 /* Missed beacons notification */ 2701 MISSED_BEACONS_NOTIFICATION = 0xa2, 2702 MISSED_BEACONS_NOTIFICATION_TH_CMD = 0xa3, 2703 2704 REPLY_CT_KILL_CONFIG_CMD = 0xa4, 2705 SENSITIVITY_CMD = 0xa8, 2706 REPLY_PHY_CALIBRATION_CMD = 0xb0, 2707 REPLY_4965_RX = 0xc3, 2708 REPLY_RX_PHY_CMD = 0xc0, 2709 REPLY_RX_MPDU_CMD = 0xc1, 2710 REPLY_COMPRESSED_BA = 0xc5, 2711 REPLY_MAX = 0xff 2712 }; 2713 2714 typedef struct iwk_cmd { 2715 struct iwk_cmd_header hdr; 2716 uint8_t data[1024]; 2717 } iwk_cmd_t; 2718 2719 /* 2720 * Alive Command & Response 2721 */ 2722 #define UCODE_VALID_OK (0x1) 2723 #define INITIALIZE_SUBTYPE (9) 2724 2725 struct iwk_alive_resp { 2726 uint8_t ucode_minor; 2727 uint8_t ucode_major; 2728 uint16_t reserved1; 2729 uint8_t sw_rev[8]; 2730 uint8_t ver_type; 2731 uint8_t ver_subtype; 2732 uint16_t reserved2; 2733 uint32_t log_event_table_ptr; 2734 uint32_t error_event_table_ptr; 2735 uint32_t timestamp; 2736 uint32_t is_valid; 2737 }; 2738 2739 struct iwk_init_alive_resp { 2740 struct iwk_alive_resp s; 2741 /* calibration values from "initialize" uCode */ 2742 uint32_t voltage; /* signed */ 2743 uint32_t therm_r1[2]; /* signed 1st for normal, 2nd for FAT channel */ 2744 uint32_t therm_r2[2]; /* signed */ 2745 uint32_t therm_r3[2]; /* signed */ 2746 uint32_t therm_r4[2]; /* signed */ 2747 /* 2748 * signed MIMO gain comp, 5 freq groups, 2 Tx chains 2749 */ 2750 uint32_t tx_atten[5][2]; 2751 }; 2752 2753 /* 2754 * Rx config defines & structure 2755 */ 2756 /* 2757 * rx_config device types 2758 */ 2759 enum { 2760 RXON_DEV_TYPE_AP = 1, 2761 RXON_DEV_TYPE_ESS = 3, 2762 RXON_DEV_TYPE_IBSS = 4, 2763 RXON_DEV_TYPE_SNIFFER = 6, 2764 }; 2765 2766 /* 2767 * rx_config flags 2768 */ 2769 enum { 2770 /* band & modulation selection */ 2771 RXON_FLG_BAND_24G_MSK = (1 << 0), 2772 RXON_FLG_CCK_MSK = (1 << 1), 2773 /* auto detection enable */ 2774 RXON_FLG_AUTO_DETECT_MSK = (1 << 2), 2775 /* TGg protection when tx */ 2776 RXON_FLG_TGG_PROTECT_MSK = (1 << 3), 2777 /* cck short slot & preamble */ 2778 RXON_FLG_SHORT_SLOT_MSK = (1 << 4), 2779 RXON_FLG_SHORT_PREAMBLE_MSK = (1 << 5), 2780 /* antenna selection */ 2781 RXON_FLG_DIS_DIV_MSK = (1 << 7), 2782 RXON_FLG_ANT_SEL_MSK = 0x0f00, 2783 RXON_FLG_ANT_A_MSK = (1 << 8), 2784 RXON_FLG_ANT_B_MSK = (1 << 9), 2785 /* radar detection enable */ 2786 RXON_FLG_RADAR_DETECT_MSK = (1 << 12), 2787 RXON_FLG_TGJ_NARROW_BAND_MSK = (1 << 13), 2788 /* 2789 * rx response to host with 8-byte TSF 2790 * (according to ON_AIR deassertion) 2791 */ 2792 RXON_FLG_TSF2HOST_MSK = (1 << 15) 2793 }; 2794 2795 /* 2796 * rx_config filter flags 2797 */ 2798 enum { 2799 /* accept all data frames */ 2800 RXON_FILTER_PROMISC_MSK = (1 << 0), 2801 /* pass control & management to host */ 2802 RXON_FILTER_CTL2HOST_MSK = (1 << 1), 2803 /* accept multi-cast */ 2804 RXON_FILTER_ACCEPT_GRP_MSK = (1 << 2), 2805 /* don't decrypt uni-cast frames */ 2806 RXON_FILTER_DIS_DECRYPT_MSK = (1 << 3), 2807 /* don't decrypt multi-cast frames */ 2808 RXON_FILTER_DIS_GRP_DECRYPT_MSK = (1 << 4), 2809 /* STA is associated */ 2810 RXON_FILTER_ASSOC_MSK = (1 << 5), 2811 /* transfer to host non bssid beacons in associated state */ 2812 RXON_FILTER_BCON_AWARE_MSK = (1 << 6) 2813 }; 2814 2815 2816 /* 2817 * structure for RXON Command & Response 2818 */ 2819 typedef struct iwk_rxon_cmd { 2820 uint8_t node_addr[IEEE80211_ADDR_LEN]; 2821 uint16_t reserved1; 2822 uint8_t bssid[IEEE80211_ADDR_LEN]; 2823 uint16_t reserved2; 2824 uint8_t wlap_bssid[IEEE80211_ADDR_LEN]; 2825 uint16_t reserved3; 2826 uint8_t dev_type; 2827 uint8_t air_propagation; 2828 uint16_t rx_chain; 2829 uint8_t ofdm_basic_rates; 2830 uint8_t cck_basic_rates; 2831 uint16_t assoc_id; 2832 uint32_t flags; 2833 uint32_t filter_flags; 2834 uint16_t chan; 2835 uint8_t ofdm_ht_single_stream_basic_rates; 2836 uint8_t ofdm_ht_dual_stream_basic_rates; 2837 } iwk_rxon_cmd_t; 2838 2839 typedef struct iwk_compressed_ba_resp { 2840 uint32_t sta_addr_lo32; 2841 uint16_t sta_addr_hi16; 2842 uint16_t reserved; 2843 uint8_t sta_id; 2844 uint8_t tid; 2845 uint16_t ba_seq_ctl; 2846 uint32_t ba_bitmap0; 2847 uint32_t ba_bitmap1; 2848 uint16_t scd_flow; 2849 uint16_t scd_ssn; 2850 } iwk_compressed_ba_resp_t; 2851 2852 #define PHY_CALIBRATE_DIFF_GAIN_CMD (7) 2853 #define HD_TABLE_SIZE (11) 2854 2855 /* 2856 * Param table within SENSITIVITY_CMD 2857 */ 2858 #define HD_MIN_ENERGY_CCK_DET_INDEX (0) 2859 #define HD_MIN_ENERGY_OFDM_DET_INDEX (1) 2860 #define HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX (2) 2861 #define HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX (3) 2862 #define HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX (4) 2863 #define HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX (5) 2864 #define HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX (6) 2865 #define HD_BARKER_CORR_TH_ADD_MIN_INDEX (7) 2866 #define HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX (8) 2867 #define HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX (9) 2868 #define HD_OFDM_ENERGY_TH_IN_INDEX (10) 2869 2870 typedef struct iwk_sensitivity_cmd { 2871 uint16_t control; 2872 uint16_t table[HD_TABLE_SIZE]; 2873 } iwk_sensitivity_cmd_t; 2874 2875 typedef struct iwk_calibration_cmd { 2876 uint8_t opCode; 2877 uint8_t flags; 2878 uint16_t reserved; 2879 char diff_gain_a; 2880 char diff_gain_b; 2881 char diff_gain_c; 2882 uint8_t reserved1; 2883 } iwk_calibation_cmd_t; 2884 2885 typedef struct iwk_missed_beacon_notif { 2886 uint32_t consequtive_missed_beacons; 2887 uint32_t total_missed_becons; 2888 uint32_t num_expected_beacons; 2889 uint32_t num_recvd_beacons; 2890 } iwk_missed_beacon_notif_t; 2891 2892 typedef struct iwk_ct_kill_config { 2893 uint32_t reserved; 2894 uint32_t critical_temperature_M; 2895 uint32_t critical_temperature_R; 2896 } iwk_ct_kill_config_t; 2897 2898 /* 2899 * structure for command IWK_CMD_ASSOCIATE 2900 */ 2901 typedef struct iwk_assoc { 2902 uint32_t flags; 2903 uint32_t filter; 2904 uint8_t ofdm_mask; 2905 uint8_t cck_mask; 2906 uint8_t ofdm_ht_single_stream_basic_rates; 2907 uint8_t ofdm_ht_dual_stream_basic_rates; 2908 uint16_t rx_chain_select_flags; 2909 uint16_t reserved; 2910 } iwk_assoc_t; 2911 2912 /* 2913 * structure for command IWK_CMD_SET_WME 2914 */ 2915 typedef struct iwk_wme_setup { 2916 uint32_t flags; 2917 struct { 2918 uint16_t cwmin; 2919 uint16_t cwmax; 2920 uint8_t aifsn; 2921 uint8_t reserved; 2922 uint16_t txop; 2923 } ac[WME_NUM_AC]; 2924 } iwk_wme_setup_t; 2925 2926 /* 2927 * structure for command IWK_CMD_TSF 2928 */ 2929 typedef struct iwk_cmd_tsf { 2930 uint32_t timestampl; 2931 uint32_t timestamph; 2932 uint16_t bintval; 2933 uint16_t atim; 2934 uint32_t binitval; 2935 uint16_t lintval; 2936 uint16_t reserved; 2937 } iwk_cmd_tsf_t; 2938 2939 /* 2940 * structure for IWK_CMD_ADD_NODE 2941 */ 2942 typedef struct iwk_add_sta { 2943 uint8_t control; 2944 uint8_t reserved1[3]; 2945 uint8_t bssid[IEEE80211_ADDR_LEN]; 2946 uint16_t reserved2; 2947 uint8_t id; 2948 uint8_t sta_mask; 2949 uint16_t reserved3; 2950 uint16_t key_flags; 2951 uint8_t tkip; 2952 uint8_t reserved4; 2953 uint16_t ttak[5]; 2954 uint8_t keyp; 2955 uint8_t reserved5; 2956 uint8_t key[16]; 2957 uint32_t flags; 2958 uint32_t mask; 2959 uint16_t tid; 2960 union { 2961 struct { 2962 uint8_t rate; 2963 uint8_t flags; 2964 } s; 2965 uint16_t rate_n_flags; 2966 } tx_rate; 2967 uint8_t add_imm; 2968 uint8_t del_imm; 2969 uint16_t add_imm_start; 2970 uint32_t reserved7; 2971 } iwk_add_sta_t; 2972 2973 /* 2974 * Tx flags 2975 */ 2976 enum { 2977 TX_CMD_FLG_RTS_MSK = (1 << 1), 2978 TX_CMD_FLG_CTS_MSK = (1 << 2), 2979 TX_CMD_FLG_ACK_MSK = (1 << 3), 2980 TX_CMD_FLG_STA_RATE_MSK = (1 << 4), 2981 TX_CMD_FLG_IMM_BA_RSP_MASK = (1 << 6), 2982 TX_CMD_FLG_FULL_TXOP_PROT_MSK = (1 << 7), 2983 TX_CMD_FLG_ANT_SEL_MSK = 0xf00, 2984 TX_CMD_FLG_ANT_A_MSK = (1 << 8), 2985 TX_CMD_FLG_ANT_B_MSK = (1 << 9), 2986 2987 /* ucode ignores BT priority for this frame */ 2988 TX_CMD_FLG_BT_DIS_MSK = (1 << 12), 2989 2990 /* ucode overrides sequence control */ 2991 TX_CMD_FLG_SEQ_CTL_MSK = (1 << 13), 2992 2993 /* signal that this frame is non-last MPDU */ 2994 TX_CMD_FLG_MORE_FRAG_MSK = (1 << 14), 2995 2996 /* calculate TSF in outgoing frame */ 2997 TX_CMD_FLG_TSF_MSK = (1 << 16), 2998 2999 /* activate TX calibration. */ 3000 TX_CMD_FLG_CALIB_MSK = (1 << 17), 3001 3002 /* 3003 * signals that 2 bytes pad was inserted 3004 * after the MAC header 3005 */ 3006 TX_CMD_FLG_MH_PAD_MSK = (1 << 20), 3007 3008 /* HCCA-AP - disable duration overwriting. */ 3009 TX_CMD_FLG_DUR_MSK = (1 << 25), 3010 }; 3011 3012 /* 3013 * TX command security control 3014 */ 3015 #define TX_CMD_SEC_CCM 0x2 3016 #define TX_CMD_SEC_TKIP 0x3 3017 3018 /* 3019 * structure for command IWK_CMD_TX_DATA 3020 */ 3021 typedef struct iwk_tx_cmd { 3022 uint16_t len; 3023 uint16_t next_frame_len; 3024 uint32_t tx_flags; 3025 struct iwk_dram_scratch scratch; 3026 struct iwk_rate rate; 3027 uint8_t sta_id; 3028 uint8_t sec_ctl; 3029 uint8_t initial_rate_index; 3030 uint8_t reserved; 3031 uint8_t key[16]; 3032 uint16_t next_frame_flags; 3033 uint16_t reserved2; 3034 union { 3035 uint32_t life_time; 3036 uint32_t attempt; 3037 } stop_time; 3038 uint32_t dram_lsb_ptr; 3039 uint8_t dram_msb_ptr; 3040 uint8_t rts_retry_limit; 3041 uint8_t data_retry_limit; 3042 uint8_t tid_tspec; 3043 union { 3044 uint16_t pm_frame_timeout; 3045 uint16_t attempt_duration; 3046 } timeout; 3047 uint16_t driver_txop; 3048 } iwk_tx_cmd_t; 3049 3050 /* 3051 * structure for command "TX beacon" 3052 */ 3053 typedef struct iwk_tx_beacon_cmd { 3054 iwk_tx_cmd_t config; 3055 uint16_t tim_idx; 3056 uint8_t tim_size; 3057 uint8_t reserved; 3058 uint8_t bcon_frame[2342]; 3059 } iwk_tx_beacon_cmd_t; 3060 3061 /* 3062 * LEDs Command & Response 3063 * REPLY_LEDS_CMD = 0x48 (command, has simple generic response) 3064 * 3065 * For each of 3 possible LEDs (Activity/Link/Tech, selected by "id" field), 3066 * this command turns it on or off, or sets up a periodic blinking cycle. 3067 */ 3068 typedef struct iwk_led_cmd { 3069 uint32_t interval; /* "interval" in uSec */ 3070 uint8_t id; /* 1: Activity, 2: Link, 3: Tech */ 3071 /* 3072 * # intervals off while blinking; 3073 * "0", with > 0 "on" value, turns LED on 3074 */ 3075 uint8_t off; 3076 /* 3077 * # intervals on while blinking; 3078 * "0", regardless of "off", turns LED off 3079 */ 3080 uint8_t on; 3081 uint8_t reserved; 3082 } iwk_led_cmd_t; 3083 3084 /* 3085 * structure for IWK_CMD_SET_POWER_MODE 3086 */ 3087 typedef struct iwk_powertable_cmd { 3088 uint16_t flags; 3089 uint8_t keep_alive_seconds; 3090 uint8_t debug_flags; 3091 uint32_t rx_timeout; 3092 uint32_t tx_timeout; 3093 uint32_t sleep[5]; 3094 uint32_t keep_alive_beacons; 3095 } iwk_powertable_cmd_t; 3096 3097 struct iwk_ssid_ie { 3098 uint8_t id; 3099 uint8_t len; 3100 uint8_t ssid[32]; 3101 }; 3102 /* 3103 * structure for command IWK_CMD_SCAN 3104 */ 3105 typedef struct iwk_scan_hdr { 3106 uint16_t len; 3107 uint8_t reserved1; 3108 uint8_t nchan; 3109 /* 3110 * dwell only this long on quiet chnl 3111 * (active scan) 3112 */ 3113 uint16_t quiet_time; 3114 uint16_t quiet_plcp_th; /* quiet chnl is < this # pkts (typ. 1) */ 3115 uint16_t good_crc_th; /* passive -> active promotion threshold */ 3116 uint16_t rx_chain; 3117 /* 3118 * max usec to be out of associated (service) 3119 * chnl 3120 */ 3121 uint32_t max_out_time; 3122 /* 3123 * pause scan this long when returning to svc 3124 * chnl. 3125 * 3945 -- 31:24 # beacons, 19:0 additional usec, 3126 * 4965 -- 31:22 # beacons, 21:0 additional usec. 3127 */ 3128 uint32_t suspend_time; 3129 uint32_t flags; 3130 uint32_t filter_flags; 3131 struct iwk_tx_cmd tx_cmd; 3132 struct iwk_ssid_ie direct_scan[4]; 3133 /* followed by probe request body */ 3134 /* followed by nchan x iwk_scan_chan */ 3135 } iwk_scan_hdr_t; 3136 3137 typedef struct iwk_scan_chan { 3138 uint8_t type; 3139 uint8_t chan; 3140 struct iwk_tx_power tpc; 3141 uint16_t active_dwell; /* dwell time */ 3142 uint16_t passive_dwell; /* dwell time */ 3143 } iwk_scan_chan_t; 3144 3145 /* 3146 * structure for IWK_CMD_BLUETOOTH 3147 */ 3148 typedef struct iwk_bt_cmd { 3149 uint8_t flags; 3150 uint8_t lead_time; 3151 uint8_t max_kill; 3152 uint8_t reserved; 3153 uint32_t kill_ack_mask; 3154 uint32_t kill_cts_mask; 3155 } iwk_bt_cmd_t; 3156 3157 /* 3158 * firmware image header 3159 */ 3160 typedef struct iwk_firmware_hdr { 3161 uint32_t version; 3162 uint32_t textsz; 3163 uint32_t datasz; 3164 uint32_t init_textsz; 3165 uint32_t init_datasz; 3166 uint32_t bootsz; 3167 } iwk_firmware_hdr_t; 3168 3169 /* 3170 * structure for IWK_START_SCAN notification 3171 */ 3172 typedef struct iwk_start_scan { 3173 uint32_t timestampl; 3174 uint32_t timestamph; 3175 uint32_t tbeacon; 3176 uint8_t chan; 3177 uint8_t band; 3178 uint16_t reserved; 3179 uint32_t status; 3180 } iwk_start_scan_t; 3181 3182 3183 #define IWK_READ(sc, reg) \ 3184 ddi_get32((sc)->sc_handle, (uint32_t *)((sc)->sc_base + (reg))) 3185 3186 #define IWK_WRITE(sc, reg, val) \ 3187 ddi_put32((sc)->sc_handle, (uint32_t *)((sc)->sc_base + (reg)), (val)) 3188 3189 #ifdef __cplusplus 3190 } 3191 #endif 3192 3193 #endif /* _IWK_HW_H_ */ 3194