1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26 /*
27 * PCI nexus utility routines:
28 * property and config routines for attach()
29 * reg/intr/range/assigned-address property routines for bus_map()
30 * init_child()
31 * fault handling
32 */
33
34 #include <sys/types.h>
35 #include <sys/kmem.h>
36 #include <sys/async.h>
37 #include <sys/sysmacros.h>
38 #include <sys/sunddi.h>
39 #include <sys/sunndi.h>
40 #include <sys/ddi_impldefs.h>
41 #include "px_obj.h"
42 #include <sys/pcie_pwr.h>
43
44 /*LINTLIBRARY*/
45
46 /*
47 * px_get_props
48 *
49 * This function is called from the attach routine to get the key
50 * properties of the pci nodes.
51 *
52 * used by: px_attach()
53 *
54 * return value: DDI_FAILURE on failure
55 */
56 int
px_get_props(px_t * px_p,dev_info_t * dip)57 px_get_props(px_t *px_p, dev_info_t *dip)
58 {
59 int i, no_of_intrs;
60
61 /*
62 * Get the bus-ranges property.
63 */
64 i = sizeof (px_p->px_bus_range);
65 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
66 "bus-range", (caddr_t)&px_p->px_bus_range, &i) != DDI_SUCCESS) {
67 cmn_err(CE_WARN, "%s%d: no bus-range property\n",
68 ddi_driver_name(dip), ddi_get_instance(dip));
69 return (DDI_FAILURE);
70 }
71 DBG(DBG_ATTACH, dip, "get_px_properties: bus-range (%x,%x)\n",
72 px_p->px_bus_range.lo, px_p->px_bus_range.hi);
73
74 /*
75 * Get the interrupts property.
76 */
77 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
78 "interrupts", (caddr_t)&px_p->px_inos,
79 &px_p->px_inos_len) != DDI_SUCCESS) {
80
81 cmn_err(CE_WARN, "%s%d: no interrupts property\n",
82 ddi_driver_name(dip), ddi_get_instance(dip));
83 return (DDI_FAILURE);
84 }
85
86 /*
87 * figure out number of interrupts in the "interrupts" property
88 * and convert them all into ino.
89 */
90 i = ddi_getprop(DDI_DEV_T_ANY, dip, 0, "#interrupt-cells", 1);
91 i = CELLS_1275_TO_BYTES(i);
92 no_of_intrs = px_p->px_inos_len / i;
93 for (i = 0; i < no_of_intrs; i++)
94 px_p->px_inos[i] = px_p->px_inos[i] & 0x3F;
95
96 /*
97 * Get the ranges property.
98 */
99 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "ranges",
100 (caddr_t)&px_p->px_ranges_p, &px_p->px_ranges_length) !=
101 DDI_SUCCESS) {
102
103 cmn_err(CE_WARN, "%s%d: no ranges property\n",
104 ddi_driver_name(dip), ddi_get_instance(dip));
105 kmem_free(px_p->px_inos, px_p->px_inos_len);
106 return (DDI_FAILURE);
107 }
108
109 return (DDI_SUCCESS);
110 }
111
112 /*
113 * px_free_props:
114 *
115 * This routine frees the memory used to cache the "interrupts"
116 * and "ranges" properties of the pci bus device node.
117 *
118 * used by: px_detach()
119 *
120 * return value: none
121 */
122 void
px_free_props(px_t * px_p)123 px_free_props(px_t *px_p)
124 {
125 kmem_free(px_p->px_inos, px_p->px_inos_len);
126 kmem_free(px_p->px_ranges_p, px_p->px_ranges_length);
127 }
128
129 /*
130 * px_reloc_reg
131 *
132 * If the "reg" entry (*px_rp) is relocatable, lookup "assigned-addresses"
133 * property to fetch corresponding relocated address.
134 *
135 * used by: px_map()
136 *
137 * return value:
138 *
139 * DDI_SUCCESS - on success
140 * DDI_ME_INVAL - regspec is invalid
141 */
142 int
px_reloc_reg(dev_info_t * dip,dev_info_t * rdip,px_t * px_p,pci_regspec_t * rp)143 px_reloc_reg(dev_info_t *dip, dev_info_t *rdip, px_t *px_p,
144 pci_regspec_t *rp)
145 {
146 int assign_len, assign_entries, i;
147 pci_regspec_t *assign_p;
148 uint32_t phys_hi = rp->pci_phys_hi;
149 uint32_t space_type = phys_hi & PCI_REG_ADDR_M; /* 28-bit */
150
151 DBG(DBG_MAP | DBG_CONT, dip, "\tpx_reloc_reg fr: %x.%x.%x %x.%x\n",
152 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low,
153 rp->pci_size_hi, rp->pci_size_low);
154
155 if (space_type == PCI_ADDR_CONFIG || phys_hi & PCI_RELOCAT_B)
156 return (DDI_SUCCESS);
157
158 /*
159 * Hot plug will be taken care of later
160 * if (px_p->hotplug_capable == B_FALSE)
161 */
162 {
163 uint32_t bus = PCI_REG_BUS_G(phys_hi);
164 if (bus < px_p->px_bus_range.lo ||
165 bus > px_p->px_bus_range.hi) {
166 DBG(DBG_MAP | DBG_CONT, dip, "bad bus# (%x)\n", bus);
167 return (DDI_ME_INVAL);
168 }
169 }
170
171 i = ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS,
172 "assigned-addresses", (caddr_t)&assign_p, &assign_len);
173
174 if (i) {
175 DBG(DBG_MAP | DBG_CONT, dip, "%s%d: assigned-addresses %d\n",
176 ddi_driver_name(rdip), ddi_get_instance(rdip), i);
177 return (DDI_ME_INVAL);
178 }
179
180 assign_entries = assign_len / sizeof (pci_regspec_t);
181 for (i = 0; i < assign_entries; i++, assign_p++) {
182 uint32_t assign_type = assign_p->pci_phys_hi & PCI_REG_ADDR_M;
183 uint32_t assign_addr = PCI_REG_BDFR_G(assign_p->pci_phys_hi);
184
185 if (PCI_REG_BDFR_G(phys_hi) != assign_addr)
186 continue;
187 if (space_type == assign_type) { /* exact match */
188 rp->pci_phys_low += assign_p->pci_phys_low;
189 if (space_type == PCI_ADDR_MEM64)
190 rp->pci_phys_mid += assign_p->pci_phys_mid;
191 break;
192 }
193 if (space_type == PCI_ADDR_MEM64 &&
194 assign_type == PCI_ADDR_MEM32) {
195 rp->pci_phys_low += assign_p->pci_phys_low;
196 rp->pci_phys_hi ^= PCI_ADDR_MEM64 ^ PCI_ADDR_MEM32;
197 break;
198 }
199 }
200 kmem_free(assign_p - i, assign_len);
201 DBG(DBG_MAP | DBG_CONT, dip, "\tpx_reloc_reg to: %x.%x.%x %x.%x <%d>\n",
202 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low,
203 rp->pci_size_hi, rp->pci_size_low, i);
204 return (i < assign_entries ? DDI_SUCCESS : DDI_ME_INVAL);
205 }
206
207 /*
208 * use "ranges" to translate relocated pci regspec into parent space
209 */
210 int
px_xlate_reg(px_t * px_p,pci_regspec_t * px_rp,struct regspec * new_rp)211 px_xlate_reg(px_t *px_p, pci_regspec_t *px_rp, struct regspec *new_rp)
212 {
213 int n;
214 pci_ranges_t *rng_p = px_p->px_ranges_p;
215 int rng_n = px_p->px_ranges_length / sizeof (pci_ranges_t);
216 uint32_t space_type = PCI_REG_ADDR_G(px_rp->pci_phys_hi);
217 uint64_t reg_begin, reg_end, reg_sz;
218 uint64_t rng_begin, rng_end, rng_sz;
219 uint64_t addr;
220
221 reg_begin = (uint64_t)px_rp->pci_phys_mid << 32 | px_rp->pci_phys_low;
222 reg_sz = (uint64_t)px_rp->pci_size_hi << 32 | px_rp->pci_size_low;
223 if (space_type == PCI_REG_ADDR_G(PCI_ADDR_CONFIG)) {
224 if (reg_begin > PCI_CONF_HDR_SIZE)
225 return (DDI_ME_INVAL);
226 reg_sz = reg_sz ? MIN(reg_sz, PCI_CONF_HDR_SIZE) :
227 PCI_CONF_HDR_SIZE;
228 reg_begin += px_rp->pci_phys_hi << 4;
229 }
230 reg_end = reg_begin + reg_sz - 1;
231
232 for (n = 0; n < rng_n; n++, rng_p++) {
233 if (space_type != PCI_REG_ADDR_G(rng_p->child_high))
234 continue; /* not the same space type */
235
236 rng_begin = (uint64_t)rng_p->child_mid << 32 | rng_p->child_low;
237 rng_sz = (uint64_t)rng_p->size_high << 32 | rng_p->size_low;
238 if (space_type == PCI_REG_ADDR_G(PCI_ADDR_CONFIG))
239 rng_begin += rng_p->child_high;
240
241 rng_end = rng_begin + rng_sz - 1;
242 if (reg_begin >= rng_begin && reg_end <= rng_end)
243 break;
244 }
245 if (n >= rng_n)
246 return (DDI_ME_REGSPEC_RANGE);
247
248 addr = reg_begin - rng_begin + ((uint64_t)rng_p->parent_high << 32 |
249 rng_p->parent_low);
250 new_rp->regspec_addr = (uint32_t)addr;
251 new_rp->regspec_bustype = (uint32_t)(addr >> 32);
252 new_rp->regspec_size = (uint32_t)reg_sz;
253 DBG(DBG_MAP | DBG_CONT, px_p->px_dip,
254 "\tpx_xlate_reg: entry %d new_rp %x.%x %x\n",
255 n, new_rp->regspec_bustype, new_rp->regspec_addr, reg_sz);
256
257 return (DDI_SUCCESS);
258 }
259
260 /*
261 * px_report_dev
262 *
263 * This function is called from our control ops routine on a
264 * DDI_CTLOPS_REPORTDEV request.
265 *
266 * The display format is
267 *
268 * <name><inst> at <pname><pinst> device <dev> function <func>
269 *
270 * where
271 *
272 * <name> this device's name property
273 * <inst> this device's instance number
274 * <name> parent device's name property
275 * <inst> parent device's instance number
276 * <dev> this device's device number
277 * <func> this device's function number
278 */
279 int
px_report_dev(dev_info_t * dip)280 px_report_dev(dev_info_t *dip)
281 {
282 if (dip == (dev_info_t *)0)
283 return (DDI_FAILURE);
284 cmn_err(CE_CONT, "?PCI Express-device: %s@%s, %s%d\n",
285 ddi_node_name(dip), ddi_get_name_addr(dip),
286 ddi_driver_name(dip),
287 ddi_get_instance(dip));
288 return (DDI_SUCCESS);
289 }
290
291
292 /*
293 * reg property for pcimem nodes that covers the entire address
294 * space for the node: config, io, or memory.
295 */
296 pci_regspec_t pci_pcimem_reg[3] =
297 {
298 {PCI_ADDR_CONFIG, 0, 0, 0, 0x800000 },
299 {(uint_t)(PCI_ADDR_IO|PCI_RELOCAT_B), 0, 0, 0, PX_IO_SIZE },
300 {(uint_t)(PCI_ADDR_MEM32|PCI_RELOCAT_B), 0, 0, 0, PX_MEM_SIZE }
301 };
302
303 /*
304 * px_name_child
305 *
306 * This function is called from init_child to name a node. It is
307 * also passed as a callback for node merging functions.
308 *
309 * return value: DDI_SUCCESS, DDI_FAILURE
310 */
311 static int
px_name_child(dev_info_t * child,char * name,int namelen)312 px_name_child(dev_info_t *child, char *name, int namelen)
313 {
314 pci_regspec_t *pci_rp;
315 int reglen;
316 uint_t func;
317 char **unit_addr;
318 uint_t n;
319
320 /*
321 * Set the address portion of the node name based on
322 * unit-address property, if it exists.
323 * The interpretation of the unit-address is DD[,F]
324 * where DD is the device id and F is the function.
325 */
326 if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, child,
327 DDI_PROP_DONTPASS, "unit-address", &unit_addr, &n) ==
328 DDI_PROP_SUCCESS) {
329 if (n != 1 || *unit_addr == NULL || **unit_addr == 0) {
330 cmn_err(CE_WARN, "unit-address property in %s.conf"
331 " not well-formed", ddi_driver_name(child));
332 ddi_prop_free(unit_addr);
333 return (DDI_FAILURE);
334 }
335 (void) snprintf(name, namelen, "%s", *unit_addr);
336 ddi_prop_free(unit_addr);
337 return (DDI_SUCCESS);
338 }
339
340 /*
341 * The unit-address property is does not exist. Set the address
342 * portion of the node name based on the function and device number.
343 */
344 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS,
345 "reg", (int **)&pci_rp, (uint_t *)®len) == DDI_SUCCESS) {
346 if (((reglen * sizeof (int)) % sizeof (pci_regspec_t)) != 0) {
347 cmn_err(CE_WARN, "reg property not well-formed");
348 return (DDI_FAILURE);
349 }
350
351 func = PCI_REG_FUNC_G(pci_rp[0].pci_phys_hi);
352 if (func != 0)
353 (void) snprintf(name, namelen, "%x,%x",
354 PCI_REG_DEV_G(pci_rp[0].pci_phys_hi), func);
355 else
356 (void) snprintf(name, namelen, "%x",
357 PCI_REG_DEV_G(pci_rp[0].pci_phys_hi));
358 ddi_prop_free(pci_rp);
359 return (DDI_SUCCESS);
360 }
361
362 cmn_err(CE_WARN, "cannot name pci child '%s'", ddi_node_name(child));
363 return (DDI_FAILURE);
364 }
365
366 int
px_uninit_child(px_t * px_p,dev_info_t * child)367 px_uninit_child(px_t *px_p, dev_info_t *child)
368 {
369 DBG(DBG_INIT_CLD, px_p->px_dip,
370 "DDI_CTLOPS_UNINITCHILD: arg=%s%d\n",
371 ddi_driver_name(child), ddi_get_instance(child));
372
373 ddi_set_name_addr(child, NULL);
374 ddi_remove_minor_node(child, NULL);
375
376 /*
377 * XXX Clear parent private data used as a flag to disable
378 * iommu BDF protection
379 */
380 if ((intptr_t)ddi_get_parent_data(child) == 1)
381 ddi_set_parent_data(child, NULL);
382
383 impl_rem_dev_props(child);
384
385 DBG(DBG_PWR, ddi_get_parent(child), "\n\n");
386
387 pcie_uninitchild(child);
388
389 return (DDI_SUCCESS);
390 }
391
392 /*
393 * px_init_child
394 *
395 * This function is called from our control ops routine on a
396 * DDI_CTLOPS_INITCHILD request. It builds and sets the device's
397 * parent private data area.
398 *
399 * used by: pci_ctlops()
400 *
401 * return value: none
402 */
403 int
px_init_child(px_t * px_p,dev_info_t * child)404 px_init_child(px_t *px_p, dev_info_t *child)
405 {
406 dev_info_t *parent_dip = px_p->px_dip;
407 pci_regspec_t *pci_rp;
408 char name[10];
409 int i, no_config;
410 intptr_t ppd = NULL;
411
412 /*
413 * The following is a special case for pcimem nodes.
414 * For these nodes we create a reg property with a
415 * single entry that covers the entire address space
416 * for the node (config, io or memory).
417 */
418 if (strcmp(ddi_driver_name(child), "pcimem") == 0) {
419 (void) ddi_prop_create(DDI_DEV_T_NONE, child,
420 DDI_PROP_CANSLEEP, "reg", (caddr_t)pci_pcimem_reg,
421 sizeof (pci_pcimem_reg));
422 ddi_set_name_addr(child, "0");
423 ddi_set_parent_data(child, NULL);
424 return (DDI_SUCCESS);
425 }
426
427 /*
428 * Check whether the node has config space or is a hard decode
429 * node (possibly created by a driver.conf file).
430 */
431 no_config = ddi_prop_get_int(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS,
432 "no-config", 0);
433
434 /*
435 * XXX set ppd to 1 to disable iommu BDF protection
436 * It relies on unused parent private data for PCI devices.
437 */
438 if (ddi_prop_exists(DDI_DEV_T_NONE, child, DDI_PROP_DONTPASS,
439 "dvma-share"))
440 ppd = 1;
441
442 /*
443 * Pseudo nodes indicate a prototype node with per-instance
444 * properties to be merged into the real h/w device node.
445 * However, do not merge if the no-config property is set
446 * (see PSARC 2000/088).
447 */
448 if ((ndi_dev_is_persistent_node(child) == 0) && (no_config == 0)) {
449 extern int pci_allow_pseudo_children;
450
451 if (ddi_getlongprop(DDI_DEV_T_ANY, child,
452 DDI_PROP_DONTPASS, "reg", (caddr_t)&pci_rp, &i) ==
453 DDI_SUCCESS) {
454 cmn_err(CE_WARN, "cannot merge prototype from %s.conf",
455 ddi_driver_name(child));
456 kmem_free(pci_rp, i);
457 return (DDI_NOT_WELL_FORMED);
458 }
459 /*
460 * Name the child
461 */
462 if (px_name_child(child, name, 10) != DDI_SUCCESS)
463 return (DDI_FAILURE);
464
465 ddi_set_name_addr(child, name);
466 ddi_set_parent_data(child, (void *)ppd);
467
468 /*
469 * Try to merge the properties from this prototype
470 * node into real h/w nodes.
471 */
472 if (ndi_merge_node(child, px_name_child) == DDI_SUCCESS) {
473 /*
474 * Merged ok - return failure to remove the node.
475 */
476 ddi_set_name_addr(child, NULL);
477 return (DDI_FAILURE);
478 }
479
480 /* workaround for ddivs to run under PCI */
481 if (pci_allow_pseudo_children)
482 return (DDI_SUCCESS);
483
484 cmn_err(CE_WARN, "!%s@%s: %s.conf properties not merged",
485 ddi_driver_name(child), ddi_get_name_addr(child),
486 ddi_driver_name(child));
487 ddi_set_name_addr(child, NULL);
488 return (DDI_NOT_WELL_FORMED);
489 }
490
491 if (px_name_child(child, name, 10) != DDI_SUCCESS)
492 return (DDI_FAILURE);
493 ddi_set_name_addr(child, name);
494
495 if (no_config != 0) {
496 /*
497 * There is no config space so there's nothing more to do.
498 */
499 return (DDI_SUCCESS);
500 }
501
502 if (pcie_pm_hold(parent_dip) != DDI_SUCCESS) {
503 DBG(DBG_PWR, parent_dip,
504 "INITCHILD: px_pm_hold failed\n");
505 return (DDI_FAILURE);
506 }
507 /* Any return of DDI_FAILURE after this must call px_pm_release */
508
509 /*
510 * If configuration registers were previously saved by
511 * child (before it went to D3), then let the child do the
512 * restore to set up the config regs as it'll first need to
513 * power the device out of D3.
514 */
515 if (ddi_prop_exists(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS,
516 "config-regs-saved-by-child") == 1) {
517 DBG(DBG_PWR, child,
518 "INITCHILD: config regs to be restored by child\n");
519
520 return (DDI_SUCCESS);
521 }
522
523 DBG(DBG_PWR, parent_dip,
524 "INITCHILD: config regs setup for %s@%s\n",
525 ddi_node_name(child), ddi_get_name_addr(child));
526
527 ddi_set_parent_data(child, (void *)ppd);
528 pcie_init_dom(child);
529 (void) pcie_initchild(child);
530
531 /*
532 * Handle chip specific init-child tasks.
533 */
534 pcie_pm_release(parent_dip);
535
536 return (DDI_SUCCESS);
537 }
538
539 /*
540 * px_get_reg_set_size
541 *
542 * Given a dev info pointer to a pci child and a register number, this
543 * routine returns the size element of that reg set property.
544 *
545 * used by: pci_ctlops() - DDI_CTLOPS_REGSIZE
546 *
547 * return value: size of reg set on success, 0 on error
548 */
549 off_t
px_get_reg_set_size(dev_info_t * child,int rnumber)550 px_get_reg_set_size(dev_info_t *child, int rnumber)
551 {
552 pci_regspec_t *pci_rp;
553 off_t size = 0;
554 int i;
555
556 if (rnumber < 0)
557 return (0);
558
559 /*
560 * Get the reg property for the device.
561 */
562 if (ddi_getlongprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, "reg",
563 (caddr_t)&pci_rp, &i) != DDI_SUCCESS)
564 return (0);
565
566 if (rnumber >= (i / (int)sizeof (pci_regspec_t)))
567 goto done;
568
569 size = pci_rp[rnumber].pci_size_low |
570 ((uint64_t)pci_rp[rnumber].pci_size_hi << 32);
571 done:
572 kmem_free(pci_rp, i);
573 return (size);
574 }
575
576
577 /*
578 * px_get_nreg_set
579 *
580 * Given a dev info pointer to a pci child, this routine returns the
581 * number of sets in its "reg" property.
582 *
583 * used by: pci_ctlops() - DDI_CTLOPS_NREGS
584 *
585 * return value: # of reg sets on success, zero on error
586 */
587 uint_t
px_get_nreg_set(dev_info_t * child)588 px_get_nreg_set(dev_info_t *child)
589 {
590 pci_regspec_t *pci_rp;
591 int i, n;
592
593 /*
594 * Get the reg property for the device.
595 */
596 if (ddi_getlongprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, "reg",
597 (caddr_t)&pci_rp, &i) != DDI_SUCCESS)
598 return (0);
599
600 n = i / (int)sizeof (pci_regspec_t);
601 kmem_free(pci_rp, i);
602 return (n);
603 }
604
605
606 /*
607 * px_get_nintr
608 *
609 * Given a dev info pointer to a pci child, this routine returns the
610 * number of items in its "interrupts" property.
611 *
612 * used by: pci_ctlops() - DDI_CTLOPS_NREGS
613 *
614 * return value: # of interrupts on success, zero on error
615 */
616 uint_t
px_get_nintr(dev_info_t * child)617 px_get_nintr(dev_info_t *child)
618 {
619 int *pci_ip;
620 int i, n;
621
622 if (ddi_getlongprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS,
623 "interrupts", (caddr_t)&pci_ip, &i) != DDI_SUCCESS)
624 return (0);
625
626 n = i / (int)sizeof (uint_t);
627 kmem_free(pci_ip, i);
628 return (n);
629 }
630
631 uint64_t
px_get_cfg_pabase(px_t * px_p)632 px_get_cfg_pabase(px_t *px_p)
633 {
634 int i;
635 pci_ranges_t *rangep = px_p->px_ranges_p;
636 int nrange = px_p->px_ranges_length / sizeof (pci_ranges_t);
637 uint32_t cfg_space_type = PCI_REG_ADDR_G(PCI_ADDR_CONFIG);
638
639 ASSERT(cfg_space_type == 0);
640
641 for (i = 0; i < nrange; i++, rangep++) {
642 if (PCI_REG_ADDR_G(rangep->child_high) == cfg_space_type)
643 break;
644 }
645
646 if (i >= nrange)
647 cmn_err(CE_PANIC, "no cfg space in px(%p) ranges prop.\n",
648 px_p);
649
650 return (((uint64_t)rangep->parent_high << 32) | rangep->parent_low);
651 }
652
653 /*
654 * decodes standard PCI config space 16bit error status reg
655 */
656 int
px_log_cfg_err(dev_info_t * dip,ushort_t status_reg,char * err_msg)657 px_log_cfg_err(dev_info_t *dip, ushort_t status_reg, char *err_msg)
658 {
659 int nerr = ddi_get_instance(dip); /* temp for instance */
660 uint64_t perr_fatal = px_perr_fatal & (1 << nerr);
661 uint64_t serr_fatal = px_serr_fatal & (1 << nerr);
662 nerr = 0;
663
664 if ((status_reg & PCI_STAT_PERROR) && perr_fatal)
665 nerr++;
666 if ((status_reg & PCI_STAT_S_SYSERR) && serr_fatal)
667 nerr++;
668 if (status_reg & PCI_STAT_R_MAST_AB)
669 nerr++;
670 if ((status_reg & PCI_STAT_S_PERROR) && perr_fatal)
671 nerr++;
672
673 cmn_err(CE_WARN, "%s%d: %sPCI Express config space CSR=0x%b",
674 ddi_driver_name(dip), ddi_get_instance(dip), err_msg,
675 (uint32_t)status_reg, PX_STATUS_BITS);
676
677 return (nerr);
678 }
679