xref: /titanic_41/usr/src/uts/intel/sys/fp.h (revision 03831d35f7499c87d51205817c93e9a8d42c4bae)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 /*	Copyright (c) 1990, 1991 UNIX System Laboratories, Inc.	*/
28 /*	Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T	*/
29 /*		All Rights Reserved				*/
30 
31 #ifndef _SYS_FP_H
32 #define	_SYS_FP_H
33 
34 #pragma ident	"%Z%%M%	%I%	%E% SMI"
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
40 /*
41  * 80287/80387 and SSE/SSE2 floating point processor definitions
42  */
43 
44 /*
45  * values that go into fp_kind
46  */
47 #define	FP_NO	0	/* no fp chip, no emulator (no fp support)	*/
48 #define	FP_SW	1	/* no fp chip, using software emulator		*/
49 #define	FP_HW	2	/* chip present bit				*/
50 #define	FP_287	2	/* 80287 chip present				*/
51 #define	FP_387	3	/* 80387 chip present				*/
52 #define	FP_487	6	/* 80487 chip present				*/
53 #define	FP_486	6	/* 80486 chip present				*/
54 #define	__FP_SSE 0x103	/* x87 plus SSE-capable CPU			*/
55 
56 /*
57  * masks for 80387 control word
58  */
59 #define	FPIM	0x00000001	/* invalid operation			*/
60 #define	FPDM	0x00000002	/* denormalized operand			*/
61 #define	FPZM	0x00000004	/* zero divide				*/
62 #define	FPOM	0x00000008	/* overflow				*/
63 #define	FPUM	0x00000010	/* underflow				*/
64 #define	FPPM	0x00000020	/* precision				*/
65 #define	FPPC	0x00000300	/* precision control			*/
66 #define	FPRC	0x00000C00	/* rounding control			*/
67 #define	FPIC	0x00001000	/* infinity control			*/
68 #define	WFPDE	0x00000080	/* data chain exception			*/
69 
70 /*
71  * (Old symbol compatibility)
72  */
73 #define	FPINV	FPIM
74 #define	FPDNO	FPDM
75 #define	FPZDIV	FPZM
76 #define	FPOVR	FPOM
77 #define	FPUNR	FPUM
78 #define	FPPRE	FPPM
79 
80 /*
81  * precision, rounding, and infinity options in control word
82  */
83 #define	FPSIG24 0x00000000	/* 24-bit significand precision (short) */
84 #define	FPSIG53 0x00000200	/* 53-bit significand precision (long)	*/
85 #define	FPSIG64 0x00000300	/* 64-bit significand precision (temp)	*/
86 #define	FPRTN	0x00000000	/* round to nearest or even		*/
87 #define	FPRD	0x00000400	/* round down				*/
88 #define	FPRU	0x00000800	/* round up				*/
89 #define	FPCHOP	0x00000C00	/* chop (truncate toward zero)		*/
90 #define	FPP	0x00000000	/* projective infinity			*/
91 #define	FPA	0x00001000	/* affine infinity			*/
92 #define	WFPB17	0x00020000	/* bit 17				*/
93 #define	WFPB24	0x00040000	/* bit 24				*/
94 
95 /*
96  * masks for 80387 status word
97  */
98 #define	FPS_IE	0x00000001	/* invalid operation			*/
99 #define	FPS_DE	0x00000002	/* denormalized operand			*/
100 #define	FPS_ZE	0x00000004	/* zero devide				*/
101 #define	FPS_OE	0x00000008	/* overflow				*/
102 #define	FPS_UE	0x00000010	/* underflow				*/
103 #define	FPS_PE	0x00000020	/* precision				*/
104 #define	FPS_SF	0x00000040	/* stack fault				*/
105 #define	FPS_ES	0x00000080	/* error summary bit			*/
106 #define	FPS_C0	0x00000100	/* C0 bit				*/
107 #define	FPS_C1	0x00000200	/* C1 bit				*/
108 #define	FPS_C2	0x00000400	/* C2 bit				*/
109 #define	FPS_TOP	0x00003800	/* top of stack pointer			*/
110 #define	FPS_C3	0x00004000	/* C3 bit				*/
111 #define	FPS_B	0x00008000	/* busy bit				*/
112 
113 /*
114  * Exception flags manually cleared during x87 exception handling.
115  */
116 #define	FPS_SW_EFLAGS	\
117 	(FPS_IE|FPS_DE|FPS_ZE|FPS_OE|FPS_UE|FPS_PE|FPS_SF|FPS_ES|FPS_B)
118 
119 /*
120  * Initial value of FPU control word as per 4th ed. ABI document
121  * - affine infinity
122  * - round to nearest or even
123  * - 64-bit double precision
124  * - all exceptions masked
125  */
126 #define	FPU_CW_INIT	0x133f
127 
128 /*
129  * masks and flags for SSE/SSE2 MXCSR
130  */
131 #define	SSE_IE 	0x00000001	/* invalid operation			*/
132 #define	SSE_DE 	0x00000002	/* denormalized operand			*/
133 #define	SSE_ZE	0x00000004	/* zero divide				*/
134 #define	SSE_OE	0x00000008	/* overflow				*/
135 #define	SSE_UE	0x00000010	/* underflow				*/
136 #define	SSE_PE	0x00000020	/* precision				*/
137 #define	SSE_DAZ	0x00000040	/* denormals are zero			*/
138 #define	SSE_IM	0x00000080	/* invalid op exception mask		*/
139 #define	SSE_DM	0x00000100	/* denormalize exception mask		*/
140 #define	SSE_ZM	0x00000200	/* zero-divide exception mask		*/
141 #define	SSE_OM	0x00000400	/* overflow exception mask		*/
142 #define	SSE_UM	0x00000800	/* underflow exception mask		*/
143 #define	SSE_PM	0x00001000	/* precision exception mask		*/
144 #define	SSE_RC	0x00006000	/* rounding control			*/
145 #define	SSE_RD	0x00002000	/* rounding control: round down		*/
146 #define	SSE_RU	0x00004000	/* rounding control: round up		*/
147 #define	SSE_FZ	0x00008000	/* flush to zero for masked underflow 	*/
148 
149 #define	SSE_MXCSR_EFLAGS	\
150 	(SSE_IE|SSE_DE|SSE_ZE|SSE_OE|SSE_UE|SSE_PE)	/* 0x3f */
151 
152 #define	SSE_MXCSR_INIT	\
153 	(SSE_IM|SSE_DM|SSE_ZM|SSE_OM|SSE_UM|SSE_PM)	/* 0x1f80 */
154 
155 #define	SSE_MXCSR_MASK_DEFAULT	\
156 	(0xffff & ~SSE_DAZ)				/* 0xffbf */
157 
158 #define	SSE_FMT_MXCSR	\
159 	"\20\20fz\17ru\16rd\15pm\14um\13om\12zm\11dm"	\
160 	"\10im\7daz\6pe\5ue\4oe\3ze\2de\1ie"
161 
162 extern int fp_kind;		/* kind of fp support			*/
163 extern int fpu_exists;		/* FPU hw exists			*/
164 
165 #ifdef _KERNEL
166 
167 extern uint32_t sse_mxcsr_mask;
168 
169 extern void fpu_probe(void);
170 
171 extern void fpnsave_begin(void *);
172 extern void fpxsave_begin(void *);
173 extern void (*fpsave_begin)(void *);
174 
175 extern void fpsave(struct fnsave_state *);
176 extern void fprestore(struct fnsave_state *);
177 extern void fpxsave(struct fxsave_state *);
178 extern void fpxrestore(struct fxsave_state *);
179 
180 extern void fpenable(void);
181 extern void fpdisable(void);
182 extern void fpinit(void);
183 
184 extern uint32_t fperr_reset(void);
185 extern uint32_t fpxerr_reset(void);
186 
187 extern uint32_t fpgetcwsw(void);
188 extern uint32_t fpgetmxcsr(void);
189 
190 struct regs;
191 extern int fpnoextflt(struct regs *);
192 extern int fpextovrflt(struct regs *);
193 extern int fpexterrflt(struct regs *);
194 extern int fpsimderrflt(struct regs *);
195 extern void fpsetcw(uint16_t, uint32_t);
196 
197 #endif	/* _KERNEL */
198 
199 #ifdef __cplusplus
200 }
201 #endif
202 
203 #endif	/* _SYS_FP_H */
204