1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 25 /* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */ 26 /* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */ 27 /* All Rights Reserved */ 28 29 #ifndef _SYS_FP_H 30 #define _SYS_FP_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * 80287/80387 and SSE/SSE2 floating point processor definitions 38 */ 39 40 /* 41 * values that go into fp_kind 42 */ 43 #define FP_NO 0 /* no fp chip, no emulator (no fp support) */ 44 #define FP_SW 1 /* no fp chip, using software emulator */ 45 #define FP_HW 2 /* chip present bit */ 46 #define FP_287 2 /* 80287 chip present */ 47 #define FP_387 3 /* 80387 chip present */ 48 #define FP_487 6 /* 80487 chip present */ 49 #define FP_486 6 /* 80486 chip present */ 50 /* 51 * The following values are bit flags instead of actual values. 52 * E.g. to know if we are using SSE, test (value & __FP_SSE) instead 53 * of (value == __FP_SSE). 54 */ 55 #define __FP_SSE 0x100 /* .. plus SSE-capable CPU */ 56 #define __FP_AVX 0x200 /* .. plus AVX-capable CPU */ 57 58 /* 59 * values that go into fp_save_mech 60 */ 61 #define FP_FNSAVE 1 /* fnsave/frstor instructions */ 62 #define FP_FXSAVE 2 /* fxsave/fxrstor instructions */ 63 #define FP_XSAVE 3 /* xsave/xrstor instructions */ 64 65 /* 66 * masks for 80387 control word 67 */ 68 #define FPIM 0x00000001 /* invalid operation */ 69 #define FPDM 0x00000002 /* denormalized operand */ 70 #define FPZM 0x00000004 /* zero divide */ 71 #define FPOM 0x00000008 /* overflow */ 72 #define FPUM 0x00000010 /* underflow */ 73 #define FPPM 0x00000020 /* precision */ 74 #define FPPC 0x00000300 /* precision control */ 75 #define FPRC 0x00000C00 /* rounding control */ 76 #define FPIC 0x00001000 /* infinity control */ 77 #define WFPDE 0x00000080 /* data chain exception */ 78 79 /* 80 * (Old symbol compatibility) 81 */ 82 #define FPINV FPIM 83 #define FPDNO FPDM 84 #define FPZDIV FPZM 85 #define FPOVR FPOM 86 #define FPUNR FPUM 87 #define FPPRE FPPM 88 89 /* 90 * precision, rounding, and infinity options in control word 91 */ 92 #define FPSIG24 0x00000000 /* 24-bit significand precision (short) */ 93 #define FPSIG53 0x00000200 /* 53-bit significand precision (long) */ 94 #define FPSIG64 0x00000300 /* 64-bit significand precision (temp) */ 95 #define FPRTN 0x00000000 /* round to nearest or even */ 96 #define FPRD 0x00000400 /* round down */ 97 #define FPRU 0x00000800 /* round up */ 98 #define FPCHOP 0x00000C00 /* chop (truncate toward zero) */ 99 #define FPP 0x00000000 /* projective infinity */ 100 #define FPA 0x00001000 /* affine infinity */ 101 #define WFPB17 0x00020000 /* bit 17 */ 102 #define WFPB24 0x00040000 /* bit 24 */ 103 104 /* 105 * masks for 80387 status word 106 */ 107 #define FPS_IE 0x00000001 /* invalid operation */ 108 #define FPS_DE 0x00000002 /* denormalized operand */ 109 #define FPS_ZE 0x00000004 /* zero divide */ 110 #define FPS_OE 0x00000008 /* overflow */ 111 #define FPS_UE 0x00000010 /* underflow */ 112 #define FPS_PE 0x00000020 /* precision */ 113 #define FPS_SF 0x00000040 /* stack fault */ 114 #define FPS_ES 0x00000080 /* error summary bit */ 115 #define FPS_C0 0x00000100 /* C0 bit */ 116 #define FPS_C1 0x00000200 /* C1 bit */ 117 #define FPS_C2 0x00000400 /* C2 bit */ 118 #define FPS_TOP 0x00003800 /* top of stack pointer */ 119 #define FPS_C3 0x00004000 /* C3 bit */ 120 #define FPS_B 0x00008000 /* busy bit */ 121 122 /* 123 * Exception flags manually cleared during x87 exception handling. 124 */ 125 #define FPS_SW_EFLAGS \ 126 (FPS_IE|FPS_DE|FPS_ZE|FPS_OE|FPS_UE|FPS_PE|FPS_SF|FPS_ES|FPS_B) 127 128 /* 129 * Initial value of FPU control word as per 4th ed. ABI document 130 * - affine infinity 131 * - round to nearest or even 132 * - 64-bit double precision 133 * - all exceptions masked 134 */ 135 #define FPU_CW_INIT 0x133f 136 137 /* 138 * masks and flags for SSE/SSE2 MXCSR 139 */ 140 #define SSE_IE 0x00000001 /* invalid operation */ 141 #define SSE_DE 0x00000002 /* denormalized operand */ 142 #define SSE_ZE 0x00000004 /* zero divide */ 143 #define SSE_OE 0x00000008 /* overflow */ 144 #define SSE_UE 0x00000010 /* underflow */ 145 #define SSE_PE 0x00000020 /* precision */ 146 #define SSE_DAZ 0x00000040 /* denormals are zero */ 147 #define SSE_IM 0x00000080 /* invalid op exception mask */ 148 #define SSE_DM 0x00000100 /* denormalize exception mask */ 149 #define SSE_ZM 0x00000200 /* zero-divide exception mask */ 150 #define SSE_OM 0x00000400 /* overflow exception mask */ 151 #define SSE_UM 0x00000800 /* underflow exception mask */ 152 #define SSE_PM 0x00001000 /* precision exception mask */ 153 #define SSE_RC 0x00006000 /* rounding control */ 154 #define SSE_RD 0x00002000 /* rounding control: round down */ 155 #define SSE_RU 0x00004000 /* rounding control: round up */ 156 #define SSE_FZ 0x00008000 /* flush to zero for masked underflow */ 157 158 #define SSE_MXCSR_EFLAGS \ 159 (SSE_IE|SSE_DE|SSE_ZE|SSE_OE|SSE_UE|SSE_PE) /* 0x3f */ 160 161 #define SSE_MXCSR_INIT \ 162 (SSE_IM|SSE_DM|SSE_ZM|SSE_OM|SSE_UM|SSE_PM) /* 0x1f80 */ 163 164 #define SSE_MXCSR_MASK_DEFAULT \ 165 (0xffff & ~SSE_DAZ) /* 0xffbf */ 166 167 #define SSE_FMT_MXCSR \ 168 "\20\20fz\17ru\16rd\15pm\14um\13om\12zm\11dm" \ 169 "\10im\7daz\6pe\5ue\4oe\3ze\2de\1ie" 170 171 extern int fp_kind; /* kind of fp support */ 172 extern int fp_save_mech; /* fp save/restore mechanism */ 173 extern int fpu_exists; /* FPU hw exists */ 174 175 #ifdef _KERNEL 176 177 extern int fpu_ignored; 178 extern int fpu_pentium_fdivbug; 179 180 extern uint32_t sse_mxcsr_mask; 181 182 extern void fpu_probe(void); 183 extern uint_t fpu_initial_probe(void); 184 extern int fpu_probe_pentium_fdivbug(void); 185 186 extern void fpnsave_ctxt(void *); 187 extern void fpxsave_ctxt(void *); 188 extern void xsave_ctxt(void *); 189 extern void (*fpsave_ctxt)(void *); 190 191 struct fnsave_state; 192 struct fxsave_state; 193 struct xsave_state; 194 extern void fxsave_insn(struct fxsave_state *); 195 extern void fpsave(struct fnsave_state *); 196 extern void fprestore(struct fnsave_state *); 197 extern void fpxsave(struct fxsave_state *); 198 extern void fpxrestore(struct fxsave_state *); 199 extern void xsave(struct xsave_state *, uint64_t); 200 extern void xrestore(struct xsave_state *, uint64_t); 201 202 extern void fpenable(void); 203 extern void fpdisable(void); 204 extern void fpinit(void); 205 206 extern uint32_t fperr_reset(void); 207 extern uint32_t fpxerr_reset(void); 208 209 extern uint32_t fpgetcwsw(void); 210 extern uint32_t fpgetmxcsr(void); 211 212 struct regs; 213 extern int fpnoextflt(struct regs *); 214 extern int fpextovrflt(struct regs *); 215 extern int fpexterrflt(struct regs *); 216 extern int fpsimderrflt(struct regs *); 217 extern void fpsetcw(uint16_t, uint32_t); 218 219 #endif /* _KERNEL */ 220 221 #ifdef __cplusplus 222 } 223 #endif 224 225 #endif /* _SYS_FP_H */ 226