1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 NetXen, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _NIC_PHAN_REG_H_ 28 #define _NIC_PHAN_REG_H_ 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #define NIC_CRB_BASE UNM_CAM_RAM(0x200) 35 #define NIC_CRB_BASE_2 UNM_CAM_RAM(0x700) 36 #define UNM_NIC_REG(X) (NIC_CRB_BASE+(X)) 37 #define UNM_NIC_REG_2(X) (NIC_CRB_BASE_2+(X)) 38 39 #define CRB_CUT_THRU_PAGE_SIZE UNM_CAM_RAM(0x170) 40 41 #define CRB_CMD_PRODUCER_OFFSET UNM_NIC_REG(0x08) 42 #define CRB_CMD_CONSUMER_OFFSET UNM_NIC_REG(0x0c) 43 /* C0 EPG BUG */ 44 #define CRB_PAUSE_ADDR_LO UNM_NIC_REG(0x10) 45 #define CRB_PAUSE_ADDR_HI UNM_NIC_REG(0x14) 46 #define NX_CDRP_CRB_OFFSET UNM_NIC_REG(0x18) 47 #define NX_ARG1_CRB_OFFSET UNM_NIC_REG(0x1c) 48 #define NX_ARG2_CRB_OFFSET UNM_NIC_REG(0x20) 49 #define NX_ARG3_CRB_OFFSET UNM_NIC_REG(0x24) 50 #define NX_SIGN_CRB_OFFSET UNM_NIC_REG(0x28) 51 #define CRB_CMDPEG_CMDRING UNM_NIC_REG(0x38) 52 #define CRB_HOST_DUMMY_BUF_ADDR_HI UNM_NIC_REG(0x3c) 53 #define CRB_HOST_DUMMY_BUF_ADDR_LO UNM_NIC_REG(0x40) 54 #define CRB_CMDPEG_STATE UNM_NIC_REG(0x50) 55 /* interrupt coalescing */ 56 #define CRB_GLOBAL_INT_COAL UNM_NIC_REG(0x64) 57 #define CRB_INT_COAL_MODE UNM_NIC_REG(0x68) 58 #define CRB_MAX_RCV_BUFS UNM_NIC_REG(0x6c) 59 #define CRB_TX_INT_THRESHOLD UNM_NIC_REG(0x70) 60 #define CRB_RX_PKT_TIMER UNM_NIC_REG(0x74) 61 #define CRB_TX_PKT_TIMER UNM_NIC_REG(0x78) 62 #define CRB_RX_PKT_CNT UNM_NIC_REG(0x7c) 63 #define CRB_RX_TMR_CNT UNM_NIC_REG(0x80) 64 #define CRB_RCV_INTR_COUNT UNM_NIC_REG(0x84) 65 /* XG Link status */ 66 #define CRB_XG_STATE UNM_NIC_REG(0x94) 67 /* XG PF Link status */ 68 #define CRB_XG_STATE_P3 UNM_NIC_REG(0x98) 69 /* Debug -performance */ 70 #define CRB_TX_STATE UNM_NIC_REG(0xac) 71 #define CRB_TX_COUNT UNM_NIC_REG(0xb0) 72 #define CRB_RX_STATE UNM_NIC_REG(0xb4) 73 #define CRB_RX_PERF_DEBUG_1 UNM_NIC_REG(0xb8) 74 /* LRO On/OFF */ 75 #define CRB_RX_LRO_CONTROL UNM_NIC_REG(0xbc) 76 /* Multiport Mode */ 77 #define CRB_MPORT_MODE UNM_NIC_REG(0xc4) 78 #define CRB_INT_VECTOR UNM_NIC_REG(0xd4) 79 #define CRB_PF_LINK_SPEED_1 UNM_NIC_REG(0xe8) 80 #define CRB_PF_LINK_SPEED_2 UNM_NIC_REG(0xec) 81 #define CRB_HOST_DUMMY_BUF UNM_NIC_REG(0xfc) 82 83 #define CRB_SCRATCHPAD_TEST UNM_NIC_REG(0x280) 84 85 #define CRB_RCVPEG_STATE UNM_NIC_REG(0x13c) 86 87 /* 12 registers to store MAC addresses for 8 PCI functions */ 88 #define CRB_MAC_BLOCK_START UNM_CAM_RAM(0x1c0) 89 90 #define CRB_CMD_PRODUCER_OFFSET_1 UNM_NIC_REG(0x1ac) 91 #define CRB_CMD_CONSUMER_OFFSET_1 UNM_NIC_REG(0x1b0) 92 #define CRB_TEMP_STATE UNM_NIC_REG(0x1b4) 93 #define CRB_CMD_PRODUCER_OFFSET_2 UNM_NIC_REG(0x1b8) 94 #define CRB_CMD_CONSUMER_OFFSET_2 UNM_NIC_REG(0x1bc) 95 96 #define CRB_CMD_PRODUCER_OFFSET_3 UNM_NIC_REG(0x1d0) 97 #define CRB_CMD_CONSUMER_OFFSET_3 UNM_NIC_REG(0x1d4) 98 /* sw int status/mask registers */ 99 #define CRB_SW_INT_MASK_OFFSET_0 0x1d8 100 #define CRB_SW_INT_MASK_OFFSET_1 0x1e0 101 #define CRB_SW_INT_MASK_OFFSET_2 0x1e4 102 #define CRB_SW_INT_MASK_OFFSET_3 0x1e8 103 #define CRB_SW_INT_MASK_OFFSET_4 0x450 104 #define CRB_SW_INT_MASK_OFFSET_5 0x454 105 #define CRB_SW_INT_MASK_OFFSET_6 0x458 106 #define CRB_SW_INT_MASK_OFFSET_7 0x45c 107 #define CRB_SW_INT_MASK_0 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_0) 108 #define CRB_SW_INT_MASK_1 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_1) 109 #define CRB_SW_INT_MASK_2 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_2) 110 #define CRB_SW_INT_MASK_3 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_3) 111 #define CRB_SW_INT_MASK_4 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_4) 112 #define CRB_SW_INT_MASK_5 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_5) 113 #define CRB_SW_INT_MASK_6 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_6) 114 #define CRB_SW_INT_MASK_7 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_7) 115 116 #define CRB_NIC_DEBUG_STRUCT_BASE UNM_NIC_REG(0x288) 117 118 /* 119 * capabilities register, can be used to selectively enable/disable features 120 * for backward compability 121 */ 122 #define CRB_NIC_CAPABILITIES_HOST UNM_NIC_REG(0x1a8) 123 #define CRB_NIC_MSI_MODE_HOST UNM_NIC_REG(0x270) 124 #define INTR_SCHEME_PERPORT 0x1 125 #define MSI_MODE_MULTIFUNC 0x1 126 127 #define CRB_EPG_QUEUE_BUSY_COUNT UNM_NIC_REG(0x200) 128 129 #define CRB_V2P_0 UNM_NIC_REG(0x290) 130 #define CRB_V2P_1 UNM_NIC_REG(0x294) 131 #define CRB_V2P_2 UNM_NIC_REG(0x298) 132 #define CRB_V2P_3 UNM_NIC_REG(0x29c) 133 #define CRB_V2P(port) (CRB_V2P_0+((port)*4)) 134 #define CRB_DRIVER_VERSION UNM_NIC_REG(0x2a0) 135 136 #define CRB_CNT_DBG1 UNM_NIC_REG(0x2a4) 137 #define CRB_CNT_DBG2 UNM_NIC_REG(0x2a8) 138 #define CRB_CNT_DBG3 UNM_NIC_REG(0x2ac) 139 140 /* 141 * Driver must set the version number register as follows: 142 * (major << 16) | (minor << 8) | (subminor) 143 */ 144 145 /* last -> 0x2a0 */ 146 147 /* Upper 16 bits of CRB_TEMP_STATE:temperature value. Lower 16 bits: state */ 148 #define nx_get_temp_val(x) ((x) >> 16) 149 #define nx_get_temp_state(x) ((x) & 0xffff) 150 #define nx_encode_temp(val, state) (((val) << 16) | (state)) 151 152 #define lower32(x) ((__uint32_t)((x) & 0xffffffff)) 153 #define upper32(x) ((__uint32_t)(((unsigned long long)(x) >> 32) & \ 154 0xffffffff)) 155 156 /* 157 * Temperature control. 158 */ 159 enum { 160 NX_TEMP_NORMAL = 0x1, /* Normal operating range */ 161 NX_TEMP_WARN, /* Sound alert, temperature getting high */ 162 NX_TEMP_PANIC /* Fatal error, hardware has shut down. */ 163 }; 164 165 #define D3_CRB_REG_FUN2 (UNM_PCIX_PS_REG(0x2084)) 166 #define D3_CRB_REG_FUN3 (UNM_PCIX_PS_REG(0x3084)) 167 168 #ifdef __cplusplus 169 } 170 #endif 171 172 #endif /* !_NIC_PHAN_REG_H_ */ 173