1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "bge_impl.h" 30 31 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 32 33 /* 34 * Future features ... ? 35 */ 36 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 37 #define BGE_IND_IO32 0 /* indirect access code */ 38 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 39 #define BGE_FLASH_IO32 1 /* FLASH access code */ 40 41 /* 42 * BGE MSI tunable: 43 * 44 * By default MSI is enabled on all supported platforms but it is disabled 45 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 46 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 47 */ 48 #if defined(__sparc) 49 boolean_t bge_enable_msi = B_TRUE; 50 #else 51 boolean_t bge_enable_msi = B_FALSE; 52 #endif 53 54 /* 55 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 56 */ 57 boolean_t bge_relaxed_ordering = B_TRUE; 58 59 /* 60 * Property names 61 */ 62 static char knownids_propname[] = "bge-known-subsystems"; 63 64 /* 65 * Patchable globals: 66 * 67 * bge_autorecover 68 * Enables/disables automatic recovery after fault detection 69 * 70 * bge_mlcr_default 71 * Value to program into the MLCR; controls the chip's GPIO pins 72 * 73 * bge_dma_{rd,wr}prio 74 * Relative priorities of DMA reads & DMA writes respectively. 75 * These may each be patched to any value 0-3. Equal values 76 * will give "fair" (round-robin) arbitration for PCI access. 77 * Unequal values will give one or the other function priority. 78 * 79 * bge_dma_rwctrl 80 * Value to put in the Read/Write DMA control register. See 81 * the Broadcom PRM for things you can fiddle with in this 82 * register ... 83 * 84 * bge_{tx,rx}_{count,ticks}_{norm,intr} 85 * Send/receive interrupt coalescing parameters. Counts are 86 * #s of descriptors, ticks are in microseconds. *norm* values 87 * apply between status updates/interrupts; the *intr* values 88 * refer to the 'during-interrupt' versions - see the PRM. 89 * 90 * NOTE: these values have been determined by measurement. They 91 * differ significantly from the values recommended in the PRM. 92 */ 93 static uint32_t bge_autorecover = 1; 94 static uint32_t bge_mlcr_default = MLCR_DEFAULT; 95 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 96 97 static uint32_t bge_dma_rdprio = 1; 98 static uint32_t bge_dma_wrprio = 0; 99 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 100 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 101 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 102 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 103 104 uint32_t bge_rx_ticks_norm = 128; 105 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 106 uint32_t bge_rx_count_norm = 8; 107 uint32_t bge_tx_count_norm = 128; 108 109 static uint32_t bge_rx_ticks_intr = 128; 110 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 111 static uint32_t bge_rx_count_intr = 2; 112 static uint32_t bge_tx_count_intr = 0; 113 114 /* 115 * Memory pool configuration parameters. 116 * 117 * These are generally specific to each member of the chip family, since 118 * each one may have a different memory size/configuration. 119 * 120 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 121 * the driver from programming the various registers; instead they are left 122 * at their hardware defaults. This is the preferred option for later chips 123 * (5705+), whereas the older chips *required* these registers to be set, 124 * since the h/w default was 0 ;-( 125 */ 126 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 127 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 128 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 129 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 130 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 131 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 132 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 133 static uint32_t bge_mbuf_pool_len_5721 = 0; 134 135 /* 136 * Various high and low water marks, thresholds, etc ... 137 * 138 * Note: these are taken from revision 7 of the PRM, and some are different 139 * from both the values in earlier PRMs *and* those determined experimentally 140 * and used in earlier versions of this driver ... 141 */ 142 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 143 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 144 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 145 146 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 147 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 148 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 149 150 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 151 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 152 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 153 154 static uint32_t bge_watchdog_count = 1 << 16; 155 static uint16_t bge_dma_miss_limit = 20; 156 157 static uint32_t bge_stop_start_on_sync = 0; 158 159 boolean_t bge_jumbo_enable = B_TRUE; 160 static uint32_t bge_default_jumbo_size = BGE_JUMBO_BUFF_SIZE; 161 162 /* 163 * ========== Low-level chip & ring buffer manipulation ========== 164 */ 165 166 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 167 168 169 /* 170 * Config space read-modify-write routines 171 */ 172 173 #if BGE_CFG_IO8 174 175 /* 176 * 8- and 16-bit set/clr operations are not used; all the config registers 177 * that we need to do bit-twiddling on are 32 bits wide. I'll leave the 178 * code here, though, in case we ever find that we do want it after all ... 179 */ 180 181 static void bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 182 #pragma inline(bge_cfg_set8) 183 184 static void 185 bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 186 { 187 uint8_t regval; 188 189 BGE_TRACE(("bge_cfg_set8($%p, 0x%lx, 0x%x)", 190 (void *)bgep, regno, bits)); 191 192 regval = pci_config_get8(bgep->cfg_handle, regno); 193 194 BGE_DEBUG(("bge_cfg_set8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 195 (void *)bgep, regno, bits, regval, regval | bits)); 196 197 regval |= bits; 198 pci_config_put8(bgep->cfg_handle, regno, regval); 199 } 200 201 static void bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 202 #pragma inline(bge_cfg_clr8) 203 204 static void 205 bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 206 { 207 uint8_t regval; 208 209 BGE_TRACE(("bge_cfg_clr8($%p, 0x%lx, 0x%x)", 210 (void *)bgep, regno, bits)); 211 212 regval = pci_config_get8(bgep->cfg_handle, regno); 213 214 BGE_DEBUG(("bge_cfg_clr8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 215 (void *)bgep, regno, bits, regval, regval & ~bits)); 216 217 regval &= ~bits; 218 pci_config_put8(bgep->cfg_handle, regno, regval); 219 } 220 221 static void bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 222 #pragma inline(bge_cfg_set16) 223 224 static void 225 bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 226 { 227 uint16_t regval; 228 229 BGE_TRACE(("bge_cfg_set16($%p, 0x%lx, 0x%x)", 230 (void *)bgep, regno, bits)); 231 232 regval = pci_config_get16(bgep->cfg_handle, regno); 233 234 BGE_DEBUG(("bge_cfg_set16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 235 (void *)bgep, regno, bits, regval, regval | bits)); 236 237 regval |= bits; 238 pci_config_put16(bgep->cfg_handle, regno, regval); 239 } 240 241 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 242 #pragma inline(bge_cfg_clr16) 243 244 static void 245 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 246 { 247 uint16_t regval; 248 249 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 250 (void *)bgep, regno, bits)); 251 252 regval = pci_config_get16(bgep->cfg_handle, regno); 253 254 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 255 (void *)bgep, regno, bits, regval, regval & ~bits)); 256 257 regval &= ~bits; 258 pci_config_put16(bgep->cfg_handle, regno, regval); 259 } 260 261 #endif /* BGE_CFG_IO8 */ 262 263 static void bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 264 #pragma inline(bge_cfg_set32) 265 266 static void 267 bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 268 { 269 uint32_t regval; 270 271 BGE_TRACE(("bge_cfg_set32($%p, 0x%lx, 0x%x)", 272 (void *)bgep, regno, bits)); 273 274 regval = pci_config_get32(bgep->cfg_handle, regno); 275 276 BGE_DEBUG(("bge_cfg_set32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 277 (void *)bgep, regno, bits, regval, regval | bits)); 278 279 regval |= bits; 280 pci_config_put32(bgep->cfg_handle, regno, regval); 281 } 282 283 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 284 #pragma inline(bge_cfg_clr32) 285 286 static void 287 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 288 { 289 uint32_t regval; 290 291 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 292 (void *)bgep, regno, bits)); 293 294 regval = pci_config_get32(bgep->cfg_handle, regno); 295 296 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 297 (void *)bgep, regno, bits, regval, regval & ~bits)); 298 299 regval &= ~bits; 300 pci_config_put32(bgep->cfg_handle, regno, regval); 301 } 302 303 #if BGE_IND_IO32 304 305 /* 306 * Indirect access to registers & RISC scratchpads, using config space 307 * accesses only. 308 * 309 * This isn't currently used, but someday we might want to use it for 310 * restoring the Subsystem Device/Vendor registers (which aren't directly 311 * writable in Config Space), or for downloading firmware into the RISCs 312 * 313 * In any case there are endian issues to be resolved before this code is 314 * enabled; the bizarre way that bytes get twisted by this chip AND by 315 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 316 * it's been thoroughly tested for all access sizes on all supported 317 * architectures (SPARC *and* x86!). 318 */ 319 static uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 320 #pragma inline(bge_ind_get32) 321 322 static uint32_t 323 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 324 { 325 uint32_t val; 326 327 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 328 329 ASSERT(mutex_owned(bgep->genlock)); 330 331 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 332 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 333 334 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 335 (void *)bgep, regno, val)); 336 337 return (val); 338 } 339 340 static void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 341 #pragma inline(bge_ind_put32) 342 343 static void 344 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 345 { 346 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 347 (void *)bgep, regno, val)); 348 349 ASSERT(mutex_owned(bgep->genlock)); 350 351 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 352 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 353 } 354 355 #endif /* BGE_IND_IO32 */ 356 357 #if BGE_DEBUGGING 358 359 static void bge_pci_check(bge_t *bgep); 360 #pragma no_inline(bge_pci_check) 361 362 static void 363 bge_pci_check(bge_t *bgep) 364 { 365 uint16_t pcistatus; 366 367 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 368 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 369 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 370 (void *)bgep, pcistatus)); 371 } 372 373 #endif /* BGE_DEBUGGING */ 374 375 /* 376 * Perform first-stage chip (re-)initialisation, using only config-space 377 * accesses: 378 * 379 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 380 * returning the data in the structure pointed to by <idp>. 381 * + Configure the target-mode endianness (swap) options. 382 * + Disable interrupts and enable Memory Space accesses. 383 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 384 * 385 * This sequence is adapted from Broadcom document 570X-PG102-R, 386 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 387 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 388 * 389 * This function MUST be called before any non-config-space accesses 390 * are made; on this first call <enable_dma> is B_FALSE, and it 391 * effectively performs steps 3-1(!) of the initialisation sequence 392 * (the rest are not required but should be harmless). 393 * 394 * It MUST also be called after a chip reset, as this disables 395 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 396 * it is effectively performing steps 6-8. 397 */ 398 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 399 #pragma no_inline(bge_chip_cfg_init) 400 401 void 402 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 403 { 404 ddi_acc_handle_t handle; 405 uint16_t command; 406 uint32_t mhcr; 407 uint16_t value16; 408 int i; 409 410 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 411 (void *)bgep, (void *)cidp, enable_dma)); 412 413 /* 414 * Step 3: save PCI cache line size and subsystem vendor ID 415 * 416 * Read all the config-space registers that characterise the 417 * chip, specifically vendor/device/revision/subsystem vendor 418 * and subsystem device id. We expect (but don't check) that 419 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 420 * 421 * Also save all bus-transaction related registers (cache-line 422 * size, bus-grant/latency parameters, etc). Some of these are 423 * cleared by reset, so we'll have to restore them later. This 424 * comes from the Broadcom document 570X-PG102-R ... 425 * 426 * Note: Broadcom document 570X-PG102-R seems to be in error 427 * here w.r.t. the offsets of the Subsystem Vendor ID and 428 * Subsystem (Device) ID registers, which are the opposite way 429 * round according to the PCI standard. For good measure, we 430 * save/restore both anyway. 431 */ 432 handle = bgep->cfg_handle; 433 434 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 435 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 436 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 437 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 438 439 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 440 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 441 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 442 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 443 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 444 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 445 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 446 447 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 448 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 449 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 450 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 451 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 452 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 453 cidp->vendor, cidp->device, cidp->revision)); 454 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 455 cidp->subven, cidp->subdev, cidp->asic_rev)); 456 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 457 cidp->clsize, cidp->latency, cidp->command)); 458 459 /* 460 * Step 2 (also step 6): disable and clear interrupts. 461 * Steps 11-13: configure PIO endianness options, and enable 462 * indirect register access. We'll also select any other 463 * options controlled by the MHCR (e.g. tagged status, mask 464 * interrupt mode) at this stage ... 465 * 466 * Note: internally, the chip is 64-bit and BIG-endian, but 467 * since it talks to the host over a (LITTLE-endian) PCI bus, 468 * it normally swaps bytes around at the PCI interface. 469 * However, the PCI host bridge on SPARC systems normally 470 * swaps the byte lanes around too, since SPARCs are also 471 * BIG-endian. So it turns out that on SPARC, the right 472 * option is to tell the chip to swap (and the host bridge 473 * will swap back again), whereas on x86 we ask the chip 474 * NOT to swap, so the natural little-endianness of the 475 * PCI bus is assumed. Then the only thing that doesn't 476 * automatically work right is access to an 8-byte register 477 * by a little-endian host; but we don't want to set the 478 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 479 * accesses don't go where expected ;-( So we live with 480 * that, and perform word-swaps in software in the few cases 481 * where a chip register is defined as an 8-byte value -- 482 * see the code below for details ... 483 * 484 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 485 * very clear in the register description in the PRM, but 486 * Broadcom document 570X-PG104-R page 248 explains a little 487 * more (under "Broadcom Mask Mode"). The bit changes the way 488 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 489 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 490 * way as the 5700 did, which isn't very convenient. Setting 491 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 492 * bit do just what its name says -- MASK the PCI #INTA output 493 * (i.e. deassert the signal at the pin) leaving all internal 494 * state unchanged. This is much more convenient for our 495 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 496 * 497 * Note: the inconvenient semantics of the interrupt mailbox 498 * (nonzero disables and acknowledges/clears the interrupt, 499 * zero enables AND CLEARS it) would make race conditions 500 * likely in the interrupt handler: 501 * 502 * (1) acknowledge & disable interrupts 503 * (2) while (more to do) 504 * process packets 505 * (3) enable interrupts -- also clears pending 506 * 507 * If the chip received more packets and internally generated 508 * an interrupt between the check at (2) and the mbox write 509 * at (3), this interrupt would be lost :-( 510 * 511 * The best way to avoid this is to use TAGGED STATUS mode, 512 * where the chip includes a unique tag in each status block 513 * update, and the host, when re-enabling interrupts, passes 514 * the last tag it saw back to the chip; then the chip can 515 * see whether the host is truly up to date, and regenerate 516 * its interrupt if not. 517 */ 518 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 519 MHCR_ENABLE_TAGGED_STATUS_MODE | 520 MHCR_MASK_INTERRUPT_MODE | 521 MHCR_CLEAR_INTERRUPT_INTA; 522 523 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 524 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 525 526 #ifdef _BIG_ENDIAN 527 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 528 #endif /* _BIG_ENDIAN */ 529 530 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 531 532 #ifdef BGE_IPMI_ASF 533 bgep->asf_wordswapped = B_FALSE; 534 #endif 535 /* 536 * Step 1 (also step 7): Enable PCI Memory Space accesses 537 * Disable Memory Write/Invalidate 538 * Enable or disable Bus Mastering 539 * 540 * Note that all other bits are taken from the original value saved 541 * the first time through here, rather than from the current register 542 * value, 'cos that will have been cleared by a soft RESET since. 543 * In this way we preserve the OBP/nexus-parent's preferred settings 544 * of the parity-error and system-error enable bits across multiple 545 * chip RESETs. 546 */ 547 command = bgep->chipid.command | PCI_COMM_MAE; 548 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 549 if (enable_dma) 550 command |= PCI_COMM_ME; 551 /* 552 * on BCM5714 revision A0, false parity error gets generated 553 * due to a logic bug. Provide a workaround by disabling parity 554 * error. 555 */ 556 if (((cidp->device == DEVICE_ID_5714C) || 557 (cidp->device == DEVICE_ID_5714S)) && 558 (cidp->revision == REVISION_ID_5714_A0)) { 559 command &= ~PCI_COMM_PARITY_DETECT; 560 } 561 pci_config_put16(handle, PCI_CONF_COMM, command); 562 563 /* 564 * On some PCI-E device, there were instances when 565 * the device was still link training. 566 */ 567 if (bgep->chipid.pci_type == BGE_PCI_E) { 568 i = 0; 569 value16 = pci_config_get16(handle, PCI_CONF_COMM); 570 while ((value16 != command) && (i < 100)) { 571 drv_usecwait(200); 572 value16 = pci_config_get16(handle, PCI_CONF_COMM); 573 ++i; 574 } 575 } 576 577 /* 578 * Clear any remaining error status bits 579 */ 580 pci_config_put16(handle, PCI_CONF_STAT, ~0); 581 582 /* 583 * Do following if and only if the device is NOT BCM5714C OR 584 * BCM5715C 585 */ 586 if (!((cidp->device == DEVICE_ID_5714C) || 587 (cidp->device == DEVICE_ID_5715C))) { 588 /* 589 * Make sure these indirect-access registers are sane 590 * rather than random after power-up or reset 591 */ 592 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 593 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 594 } 595 /* 596 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 597 */ 598 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 599 600 if (cidp->pci_type == BGE_PCI_E) 601 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 602 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 603 } 604 605 #ifdef __amd64 606 /* 607 * Distinguish CPU types 608 * 609 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 610 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 611 * for PCI-Express based network interface card. This is the work-around 612 * for those nics. 613 */ 614 static boolean_t bge_get_em64t_type(void); 615 #pragma inline(bge_get_em64t_type) 616 617 static boolean_t 618 bge_get_em64t_type(void) 619 { 620 621 return (x86_vendor == X86_VENDOR_Intel); 622 } 623 #endif 624 625 /* 626 * Operating register get/set access routines 627 */ 628 629 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 630 #pragma inline(bge_reg_get32) 631 632 uint32_t 633 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 634 { 635 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 636 (void *)bgep, regno)); 637 638 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 639 } 640 641 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 642 #pragma inline(bge_reg_put32) 643 644 void 645 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 646 { 647 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 648 (void *)bgep, regno, data)); 649 650 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 651 BGE_PCICHK(bgep); 652 } 653 654 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 655 #pragma inline(bge_reg_set32) 656 657 void 658 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 659 { 660 uint32_t regval; 661 662 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 663 (void *)bgep, regno, bits)); 664 665 regval = bge_reg_get32(bgep, regno); 666 regval |= bits; 667 bge_reg_put32(bgep, regno, regval); 668 } 669 670 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 671 #pragma inline(bge_reg_clr32) 672 673 void 674 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 675 { 676 uint32_t regval; 677 678 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 679 (void *)bgep, regno, bits)); 680 681 regval = bge_reg_get32(bgep, regno); 682 regval &= ~bits; 683 bge_reg_put32(bgep, regno, regval); 684 } 685 686 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 687 #pragma inline(bge_reg_get64) 688 689 static uint64_t 690 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 691 { 692 uint64_t regval; 693 694 #ifdef __amd64 695 if (bge_get_em64t_type()) { 696 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 697 regval <<= 32; 698 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 699 } else { 700 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 701 } 702 #else 703 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 704 #endif 705 706 #ifdef _LITTLE_ENDIAN 707 regval = (regval >> 32) | (regval << 32); 708 #endif /* _LITTLE_ENDIAN */ 709 710 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 711 (void *)bgep, regno, regval)); 712 713 return (regval); 714 } 715 716 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 717 #pragma inline(bge_reg_put64) 718 719 static void 720 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 721 { 722 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 723 (void *)bgep, regno, data)); 724 725 #ifdef _LITTLE_ENDIAN 726 data = ((data >> 32) | (data << 32)); 727 #endif /* _LITTLE_ENDIAN */ 728 729 #ifdef __amd64 730 if (bge_get_em64t_type()) { 731 ddi_put32(bgep->io_handle, 732 PIO_ADDR(bgep, regno), (uint32_t)data); 733 BGE_PCICHK(bgep); 734 ddi_put32(bgep->io_handle, 735 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 736 737 } else { 738 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 739 } 740 #else 741 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 742 #endif 743 744 BGE_PCICHK(bgep); 745 } 746 747 /* 748 * The DDI doesn't provide get/put functions for 128 bit data 749 * so we put RCBs out as two 64-bit chunks instead. 750 */ 751 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 752 #pragma inline(bge_reg_putrcb) 753 754 static void 755 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 756 { 757 uint64_t *p; 758 759 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 760 (void *)bgep, addr, rcbp->host_ring_addr, 761 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 762 763 ASSERT((addr % sizeof (*rcbp)) == 0); 764 765 p = (void *)rcbp; 766 bge_reg_put64(bgep, addr, *p++); 767 bge_reg_put64(bgep, addr+8, *p); 768 } 769 770 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 771 #pragma inline(bge_mbx_put) 772 773 void 774 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 775 { 776 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 777 (void *)bgep, regno, data)); 778 779 /* 780 * Mailbox registers are nominally 64 bits on the 5701, but 781 * the MSW isn't used. On the 5703, they're only 32 bits 782 * anyway. So here we just write the lower(!) 32 bits - 783 * remembering that the chip is big-endian, even though the 784 * PCI bus is little-endian ... 785 */ 786 #ifdef _BIG_ENDIAN 787 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 788 #else 789 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 790 #endif /* _BIG_ENDIAN */ 791 BGE_PCICHK(bgep); 792 } 793 794 #if BGE_DEBUGGING 795 796 void bge_led_mark(bge_t *bgep); 797 #pragma no_inline(bge_led_mark) 798 799 void 800 bge_led_mark(bge_t *bgep) 801 { 802 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 803 LED_CONTROL_1000MBPS_LED | 804 LED_CONTROL_100MBPS_LED | 805 LED_CONTROL_10MBPS_LED; 806 807 /* 808 * Blink all three LINK LEDs on simultaneously, then all off, 809 * then restore to automatic hardware control. This is used 810 * in laboratory testing to trigger a logic analyser or scope. 811 */ 812 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 813 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 814 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 815 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 816 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 817 } 818 819 #endif /* BGE_DEBUGGING */ 820 821 /* 822 * NIC on-chip memory access routines 823 * 824 * Only 32K of NIC memory is visible at a time, controlled by the 825 * Memory Window Base Address Register (in PCI config space). Once 826 * this is set, the 32K region of NIC-local memory that it refers 827 * to can be directly addressed in the upper 32K of the 64K of PCI 828 * memory space used for the device. 829 */ 830 831 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 832 #pragma inline(bge_nic_setwin) 833 834 static void 835 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 836 { 837 chip_id_t *cidp; 838 839 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 840 (void *)bgep, base)); 841 842 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 843 844 /* 845 * Don't do repeated zero data writes, 846 * if the device is BCM5714C/15C. 847 */ 848 cidp = &bgep->chipid; 849 if ((cidp->device == DEVICE_ID_5714C) || 850 (cidp->device == DEVICE_ID_5715C)) { 851 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 852 return; 853 /* Adjust lastWriteZeroData */ 854 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 855 B_TRUE : B_FALSE); 856 } 857 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 858 } 859 860 861 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 862 #pragma inline(bge_nic_get32) 863 864 static uint32_t 865 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 866 { 867 uint32_t data; 868 869 #ifdef BGE_IPMI_ASF 870 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 871 /* workaround for word swap error */ 872 if (addr & 4) 873 addr = addr - 4; 874 else 875 addr = addr + 4; 876 } 877 #endif 878 879 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 880 addr &= MWBAR_GRANULE_MASK; 881 addr += NIC_MEM_WINDOW_OFFSET; 882 883 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 884 885 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 886 (void *)bgep, addr, data)); 887 888 return (data); 889 } 890 891 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 892 #pragma inline(bge_nic_put32) 893 894 void 895 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 896 { 897 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 898 (void *)bgep, addr, data)); 899 900 #ifdef BGE_IPMI_ASF 901 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 902 /* workaround for word swap error */ 903 if (addr & 4) 904 addr = addr - 4; 905 else 906 addr = addr + 4; 907 } 908 #endif 909 910 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 911 addr &= MWBAR_GRANULE_MASK; 912 addr += NIC_MEM_WINDOW_OFFSET; 913 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 914 BGE_PCICHK(bgep); 915 } 916 917 918 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 919 #pragma inline(bge_nic_get64) 920 921 static uint64_t 922 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 923 { 924 uint64_t data; 925 926 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 927 addr &= MWBAR_GRANULE_MASK; 928 addr += NIC_MEM_WINDOW_OFFSET; 929 930 #ifdef __amd64 931 if (bge_get_em64t_type()) { 932 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 933 data <<= 32; 934 data |= ddi_get32(bgep->io_handle, 935 PIO_ADDR(bgep, addr + 4)); 936 } else { 937 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 938 } 939 #else 940 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 941 #endif 942 943 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 944 (void *)bgep, addr, data)); 945 946 return (data); 947 } 948 949 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 950 #pragma inline(bge_nic_put64) 951 952 static void 953 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 954 { 955 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 956 (void *)bgep, addr, data)); 957 958 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 959 addr &= MWBAR_GRANULE_MASK; 960 addr += NIC_MEM_WINDOW_OFFSET; 961 962 #ifdef __amd64 963 if (bge_get_em64t_type()) { 964 ddi_put32(bgep->io_handle, 965 PIO_ADDR(bgep, addr), (uint32_t)data); 966 BGE_PCICHK(bgep); 967 ddi_put32(bgep->io_handle, 968 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 969 } else { 970 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 971 } 972 #else 973 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 974 #endif 975 976 BGE_PCICHK(bgep); 977 } 978 979 /* 980 * The DDI doesn't provide get/put functions for 128 bit data 981 * so we put RCBs out as two 64-bit chunks instead. 982 */ 983 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 984 #pragma inline(bge_nic_putrcb) 985 986 static void 987 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 988 { 989 uint64_t *p; 990 991 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 992 (void *)bgep, addr, rcbp->host_ring_addr, 993 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 994 995 ASSERT((addr % sizeof (*rcbp)) == 0); 996 997 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 998 addr &= MWBAR_GRANULE_MASK; 999 addr += NIC_MEM_WINDOW_OFFSET; 1000 1001 p = (void *)rcbp; 1002 #ifdef __amd64 1003 if (bge_get_em64t_type()) { 1004 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1005 (uint32_t)(*p)); 1006 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1007 (uint32_t)(*p >> 32)); 1008 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1009 (uint32_t)(*(p + 1))); 1010 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1011 (uint32_t)(*p >> 32)); 1012 1013 } else { 1014 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1015 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1016 } 1017 #else 1018 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1019 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1020 #endif 1021 1022 BGE_PCICHK(bgep); 1023 } 1024 1025 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1026 #pragma inline(bge_nic_zero) 1027 1028 static void 1029 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1030 { 1031 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1032 (void *)bgep, addr, nbytes)); 1033 1034 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1035 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1036 1037 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1038 addr &= MWBAR_GRANULE_MASK; 1039 addr += NIC_MEM_WINDOW_OFFSET; 1040 1041 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1042 nbytes, 1, DDI_DATA_SZ08_ACC); 1043 BGE_PCICHK(bgep); 1044 } 1045 1046 /* 1047 * MII (PHY) register get/set access routines 1048 * 1049 * These use the chip's MII auto-access method, controlled by the 1050 * MII Communication register at 0x044c, so the CPU doesn't have 1051 * to fiddle with the individual bits. 1052 */ 1053 1054 #undef BGE_DBG 1055 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1056 1057 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1058 uint16_t data, uint32_t cmd); 1059 #pragma no_inline(bge_mii_access) 1060 1061 static uint16_t 1062 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1063 { 1064 uint32_t timeout; 1065 uint32_t regval1; 1066 uint32_t regval2; 1067 1068 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1069 (void *)bgep, regno, data, cmd)); 1070 1071 ASSERT(mutex_owned(bgep->genlock)); 1072 1073 /* 1074 * Assemble the command ... 1075 */ 1076 cmd |= data << MI_COMMS_DATA_SHIFT; 1077 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1078 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1079 cmd |= MI_COMMS_START; 1080 1081 /* 1082 * Wait for any command already in progress ... 1083 * 1084 * Note: this *shouldn't* ever find that there is a command 1085 * in progress, because we already hold the <genlock> mutex. 1086 * Nonetheless, we have sometimes seen the MI_COMMS_START 1087 * bit set here -- it seems that the chip can initiate MII 1088 * accesses internally, even with polling OFF. 1089 */ 1090 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1091 for (timeout = 100; ; ) { 1092 if ((regval2 & MI_COMMS_START) == 0) { 1093 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1094 break; 1095 } 1096 if (--timeout == 0) 1097 break; 1098 drv_usecwait(10); 1099 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1100 } 1101 1102 if (timeout == 0) 1103 return ((uint16_t)~0u); 1104 1105 if (timeout != 100) 1106 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1107 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1108 cmd, 10*(100-timeout), regval1, regval2)); 1109 1110 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1111 for (timeout = 1000; ; ) { 1112 if ((regval1 & MI_COMMS_START) == 0) 1113 break; 1114 if (--timeout == 0) 1115 break; 1116 drv_usecwait(10); 1117 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1118 } 1119 1120 /* 1121 * Drop out early if the READ FAILED bit is set -- this chip 1122 * could be a 5703/4S, with a SerDes instead of a PHY! 1123 */ 1124 if (regval2 & MI_COMMS_READ_FAILED) 1125 return ((uint16_t)~0u); 1126 1127 if (timeout == 0) 1128 return ((uint16_t)~0u); 1129 1130 /* 1131 * The PRM says to wait 5us after seeing the START bit clear 1132 * and then re-read the register to get the final value of the 1133 * data field, in order to avoid a race condition where the 1134 * START bit is clear but the data field isn't yet valid. 1135 * 1136 * Note: we don't actually seem to be encounter this race; 1137 * except when the START bit is seen set again (see below), 1138 * the data field doesn't change during this 5us interval. 1139 */ 1140 drv_usecwait(5); 1141 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1142 1143 /* 1144 * Unfortunately, when following the PRMs instructions above, 1145 * we have occasionally seen the START bit set again(!) in the 1146 * value read after the 5us delay. This seems to be due to the 1147 * chip autonomously starting another MII access internally. 1148 * In such cases, the command/data/etc fields relate to the 1149 * internal command, rather than the one that we thought had 1150 * just finished. So in this case, we fall back to returning 1151 * the data from the original read that showed START clear. 1152 */ 1153 if (regval2 & MI_COMMS_START) { 1154 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1155 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1156 cmd, regval1, regval2)); 1157 regval2 = regval1; 1158 } 1159 1160 if (regval2 & MI_COMMS_START) 1161 return ((uint16_t)~0u); 1162 1163 if (regval2 & MI_COMMS_READ_FAILED) 1164 return ((uint16_t)~0u); 1165 1166 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1167 } 1168 1169 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1170 #pragma no_inline(bge_mii_get16) 1171 1172 uint16_t 1173 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1174 { 1175 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1176 (void *)bgep, regno)); 1177 1178 ASSERT(mutex_owned(bgep->genlock)); 1179 1180 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1181 } 1182 1183 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1184 #pragma no_inline(bge_mii_put16) 1185 1186 void 1187 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1188 { 1189 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1190 (void *)bgep, regno, data)); 1191 1192 ASSERT(mutex_owned(bgep->genlock)); 1193 1194 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1195 } 1196 1197 #undef BGE_DBG 1198 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1199 1200 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1201 1202 /* 1203 * Basic SEEPROM get/set access routine 1204 * 1205 * This uses the chip's SEEPROM auto-access method, controlled by the 1206 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1207 * doesn't have to fiddle with the individual bits. 1208 * 1209 * The caller should hold <genlock> and *also* have already acquired 1210 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1211 * 1212 * Return value: 1213 * 0 on success, 1214 * ENODATA on access timeout (maybe retryable: device may just be busy) 1215 * EPROTO on other h/w or s/w errors. 1216 * 1217 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1218 * from a (successful) SEEPROM_ACCESS_READ. 1219 */ 1220 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1221 uint32_t *dp); 1222 #pragma no_inline(bge_seeprom_access) 1223 1224 static int 1225 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1226 { 1227 uint32_t tries; 1228 uint32_t regval; 1229 1230 ASSERT(mutex_owned(bgep->genlock)); 1231 1232 /* 1233 * On the newer chips that support both SEEPROM & Flash, we need 1234 * to specifically enable SEEPROM access (Flash is the default). 1235 * On older chips, we don't; SEEPROM is the only NVtype supported, 1236 * and the NVM control registers don't exist ... 1237 */ 1238 switch (bgep->chipid.nvtype) { 1239 case BGE_NVTYPE_NONE: 1240 case BGE_NVTYPE_UNKNOWN: 1241 _NOTE(NOTREACHED) 1242 case BGE_NVTYPE_SEEPROM: 1243 break; 1244 1245 case BGE_NVTYPE_LEGACY_SEEPROM: 1246 case BGE_NVTYPE_UNBUFFERED_FLASH: 1247 case BGE_NVTYPE_BUFFERED_FLASH: 1248 default: 1249 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1250 NVM_CFG1_LEGACY_SEEPROM_MODE); 1251 break; 1252 } 1253 1254 /* 1255 * Check there's no command in progress. 1256 * 1257 * Note: this *shouldn't* ever find that there is a command 1258 * in progress, because we already hold the <genlock> mutex. 1259 * Also, to ensure we don't have a conflict with the chip's 1260 * internal firmware or a process accessing the same (shared) 1261 * SEEPROM through the other port of a 5704, we've already 1262 * been through the "software arbitration" protocol. 1263 * So this is just a final consistency check: we shouldn't 1264 * see EITHER the START bit (command started but not complete) 1265 * OR the COMPLETE bit (command completed but not cleared). 1266 */ 1267 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1268 if (regval & SEEPROM_ACCESS_START) 1269 return (EPROTO); 1270 if (regval & SEEPROM_ACCESS_COMPLETE) 1271 return (EPROTO); 1272 1273 /* 1274 * Assemble the command ... 1275 */ 1276 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1277 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1278 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1279 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1280 cmd |= SEEPROM_ACCESS_START; 1281 cmd |= SEEPROM_ACCESS_COMPLETE; 1282 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1283 1284 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1285 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1286 1287 /* 1288 * By observation, a successful access takes ~20us on a 5703/4, 1289 * but apparently much longer (up to 1000us) on the obsolescent 1290 * BCM5700/BCM5701. We want to be sure we don't get any false 1291 * timeouts here; but OTOH, we don't want a bogus access to lock 1292 * out interrupts for longer than necessary. So we'll allow up 1293 * to 1000us ... 1294 */ 1295 for (tries = 0; tries < 1000; ++tries) { 1296 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1297 if (regval & SEEPROM_ACCESS_COMPLETE) 1298 break; 1299 drv_usecwait(1); 1300 } 1301 1302 if (regval & SEEPROM_ACCESS_COMPLETE) { 1303 /* 1304 * All OK; read the SEEPROM data register, then write back 1305 * the value read from the address register in order to 1306 * clear the <complete> bit and leave the SEEPROM access 1307 * state machine idle, ready for the next access ... 1308 */ 1309 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1310 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1311 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1312 return (0); 1313 } 1314 1315 /* 1316 * Hmm ... what happened here? 1317 * 1318 * Most likely, the user addressed a non-existent SEEPROM. Or 1319 * maybe the SEEPROM was busy internally (e.g. processing a write) 1320 * and didn't respond to being addressed. Either way, it's left 1321 * the SEEPROM access state machine wedged. So we'll reset it 1322 * before we leave, so it's ready for next time ... 1323 */ 1324 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1325 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1326 return (ENODATA); 1327 } 1328 1329 /* 1330 * Basic Flash get/set access routine 1331 * 1332 * These use the chip's Flash auto-access method, controlled by the 1333 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1334 * fiddle with the individual bits. 1335 * 1336 * The caller should hold <genlock> and *also* have already acquired 1337 * the right to access the Flash, via bge_nvmem_acquire() above. 1338 * 1339 * Return value: 1340 * 0 on success, 1341 * ENODATA on access timeout (maybe retryable: device may just be busy) 1342 * ENODEV if the NVmem device is missing or otherwise unusable 1343 * 1344 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1345 * from a (successful) NVM_FLASH_CMD_RD. 1346 */ 1347 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1348 uint32_t *dp); 1349 #pragma no_inline(bge_flash_access) 1350 1351 static int 1352 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1353 { 1354 uint32_t tries; 1355 uint32_t regval; 1356 1357 ASSERT(mutex_owned(bgep->genlock)); 1358 1359 /* 1360 * On the newer chips that support both SEEPROM & Flash, we need 1361 * to specifically disable SEEPROM access while accessing Flash. 1362 * The older chips don't support Flash, and the NVM registers don't 1363 * exist, so we shouldn't be here at all! 1364 */ 1365 switch (bgep->chipid.nvtype) { 1366 case BGE_NVTYPE_NONE: 1367 case BGE_NVTYPE_UNKNOWN: 1368 _NOTE(NOTREACHED) 1369 case BGE_NVTYPE_SEEPROM: 1370 return (ENODEV); 1371 1372 case BGE_NVTYPE_LEGACY_SEEPROM: 1373 case BGE_NVTYPE_UNBUFFERED_FLASH: 1374 case BGE_NVTYPE_BUFFERED_FLASH: 1375 default: 1376 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1377 NVM_CFG1_LEGACY_SEEPROM_MODE); 1378 break; 1379 } 1380 1381 /* 1382 * Assemble the command ... 1383 */ 1384 addr &= NVM_FLASH_ADDR_MASK; 1385 cmd |= NVM_FLASH_CMD_DOIT; 1386 cmd |= NVM_FLASH_CMD_FIRST; 1387 cmd |= NVM_FLASH_CMD_LAST; 1388 cmd |= NVM_FLASH_CMD_DONE; 1389 1390 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1391 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1392 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1393 1394 /* 1395 * Allow up to 1000ms ... 1396 */ 1397 for (tries = 0; tries < 1000; ++tries) { 1398 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1399 if (regval & NVM_FLASH_CMD_DONE) 1400 break; 1401 drv_usecwait(1); 1402 } 1403 1404 if (regval & NVM_FLASH_CMD_DONE) { 1405 /* 1406 * All OK; read the data from the Flash read register 1407 */ 1408 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1409 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1410 return (0); 1411 } 1412 1413 /* 1414 * Hmm ... what happened here? 1415 * 1416 * Most likely, the user addressed a non-existent Flash. Or 1417 * maybe the Flash was busy internally (e.g. processing a write) 1418 * and didn't respond to being addressed. Either way, there's 1419 * nothing we can here ... 1420 */ 1421 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1422 return (ENODATA); 1423 } 1424 1425 /* 1426 * The next two functions regulate access to the NVram (if fitted). 1427 * 1428 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1429 * (SPI) interface, but they can be accessed through either port. These 1430 * are managed by different instance of this driver and have no software 1431 * state in common. 1432 * 1433 * In addition (and even on a single core chip) the chip's internal 1434 * firmware can access the SEEPROM/Flash, most notably after a RESET 1435 * when it may download code to run internally. 1436 * 1437 * So we need to arbitrate between these various software agents. For 1438 * this purpose, the chip provides the Software Arbitration Register, 1439 * which implements hardware(!) arbitration. 1440 * 1441 * This functionality didn't exist on older (5700/5701) chips, so there's 1442 * nothing we can do by way of arbitration on those; also, if there's no 1443 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1444 * nothing to do. 1445 * 1446 * The internal firmware appears to use Request 0, which is the highest 1447 * priority. So we'd like to use Request 2, leaving one higher and one 1448 * lower for any future developments ... but apparently this doesn't 1449 * always work. So for now, the code uses Request 1 ;-( 1450 */ 1451 1452 #define NVM_READ_REQ NVM_READ_REQ1 1453 #define NVM_RESET_REQ NVM_RESET_REQ1 1454 #define NVM_SET_REQ NVM_SET_REQ1 1455 1456 static void bge_nvmem_relinquish(bge_t *bgep); 1457 #pragma no_inline(bge_nvmem_relinquish) 1458 1459 static void 1460 bge_nvmem_relinquish(bge_t *bgep) 1461 { 1462 ASSERT(mutex_owned(bgep->genlock)); 1463 1464 switch (bgep->chipid.nvtype) { 1465 case BGE_NVTYPE_NONE: 1466 case BGE_NVTYPE_UNKNOWN: 1467 _NOTE(NOTREACHED) 1468 return; 1469 1470 case BGE_NVTYPE_SEEPROM: 1471 /* 1472 * No arbitration performed, no release needed 1473 */ 1474 return; 1475 1476 case BGE_NVTYPE_LEGACY_SEEPROM: 1477 case BGE_NVTYPE_UNBUFFERED_FLASH: 1478 case BGE_NVTYPE_BUFFERED_FLASH: 1479 default: 1480 break; 1481 } 1482 1483 /* 1484 * Our own request should be present (whether or not granted) ... 1485 */ 1486 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1487 1488 /* 1489 * ... this will make it go away. 1490 */ 1491 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1492 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1493 } 1494 1495 /* 1496 * Arbitrate for access to the NVmem, if necessary 1497 * 1498 * Return value: 1499 * 0 on success 1500 * EAGAIN if the device is in use (retryable) 1501 * ENODEV if the NVmem device is missing or otherwise unusable 1502 */ 1503 static int bge_nvmem_acquire(bge_t *bgep); 1504 #pragma no_inline(bge_nvmem_acquire) 1505 1506 static int 1507 bge_nvmem_acquire(bge_t *bgep) 1508 { 1509 uint32_t regval; 1510 uint32_t tries; 1511 1512 ASSERT(mutex_owned(bgep->genlock)); 1513 1514 switch (bgep->chipid.nvtype) { 1515 case BGE_NVTYPE_NONE: 1516 case BGE_NVTYPE_UNKNOWN: 1517 /* 1518 * Access denied: no (recognisable) device fitted 1519 */ 1520 return (ENODEV); 1521 1522 case BGE_NVTYPE_SEEPROM: 1523 /* 1524 * Access granted: no arbitration needed (or possible) 1525 */ 1526 return (0); 1527 1528 case BGE_NVTYPE_LEGACY_SEEPROM: 1529 case BGE_NVTYPE_UNBUFFERED_FLASH: 1530 case BGE_NVTYPE_BUFFERED_FLASH: 1531 default: 1532 /* 1533 * Access conditional: conduct arbitration protocol 1534 */ 1535 break; 1536 } 1537 1538 /* 1539 * We're holding the per-port mutex <genlock>, so no-one other 1540 * thread can be attempting to access the NVmem through *this* 1541 * port. But it could be in use by the *other* port (of a 5704), 1542 * or by the chip's internal firmware, so we have to go through 1543 * the full (hardware) arbitration protocol ... 1544 * 1545 * Note that *because* we're holding <genlock>, the interrupt handler 1546 * won't be able to progress. So we're only willing to spin for a 1547 * fairly short time. Specifically: 1548 * 1549 * We *must* wait long enough for the hardware to resolve all 1550 * requests and determine the winner. Fortunately, this is 1551 * "almost instantaneous", even as observed by GHz CPUs. 1552 * 1553 * A successful access by another Solaris thread (via either 1554 * port) typically takes ~20us. So waiting a bit longer than 1555 * that will give a good chance of success, if the other user 1556 * *is* another thread on the other port. 1557 * 1558 * However, the internal firmware can hold on to the NVmem 1559 * for *much* longer: at least 10 milliseconds just after a 1560 * RESET, and maybe even longer if the NVmem actually contains 1561 * code to download and run on the internal CPUs. 1562 * 1563 * So, we'll allow 50us; if that's not enough then it's up to the 1564 * caller to retry later (hence the choice of return code EAGAIN). 1565 */ 1566 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1567 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1568 1569 for (tries = 0; tries < 50; ++tries) { 1570 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1571 if (regval & NVM_WON_REQ1) 1572 break; 1573 drv_usecwait(1); 1574 } 1575 1576 if (regval & NVM_WON_REQ1) { 1577 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1578 return (0); 1579 } 1580 1581 /* 1582 * Somebody else must be accessing the NVmem, so abandon our 1583 * attempt take control of it. The caller can try again later ... 1584 */ 1585 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1586 bge_nvmem_relinquish(bgep); 1587 return (EAGAIN); 1588 } 1589 1590 /* 1591 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1592 * write protect line in such a way that the NVmem is protected when 1593 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1594 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1595 * 1596 * Note: there's only one set of GPIO pins on a 5704, even though they 1597 * can be accessed through either port. So the chip has to resolve what 1598 * happens if the two ports program a single pin differently ... the rule 1599 * it uses is that if the ports disagree about the *direction* of a pin, 1600 * "output" wins over "input", but if they disagree about its *value* as 1601 * an output, then the pin is TRISTATED instead! In such a case, no-one 1602 * wins, and the external signal does whatever the external circuitry 1603 * defines as the default -- which we've assumed is the PROTECTED state. 1604 * So, we always change GPIO1 back to being an *input* whenever we're not 1605 * specifically using it to unprotect the NVmem. This allows either port 1606 * to update the NVmem, although obviously only one at a time! 1607 * 1608 * The caller should hold <genlock> and *also* have already acquired the 1609 * right to access the NVmem, via bge_nvmem_acquire() above. 1610 */ 1611 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1612 #pragma inline(bge_nvmem_protect) 1613 1614 static void 1615 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1616 { 1617 uint32_t regval; 1618 1619 ASSERT(mutex_owned(bgep->genlock)); 1620 1621 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1622 if (protect) { 1623 regval |= MLCR_MISC_PINS_OUTPUT_1; 1624 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1625 } else { 1626 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1627 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1628 } 1629 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1630 } 1631 1632 /* 1633 * Now put it all together ... 1634 * 1635 * Try to acquire control of the NVmem; if successful, then: 1636 * unprotect it (if we want to write to it) 1637 * perform the requested access 1638 * reprotect it (after a write) 1639 * relinquish control 1640 * 1641 * Return value: 1642 * 0 on success, 1643 * EAGAIN if the device is in use (retryable) 1644 * ENODATA on access timeout (maybe retryable: device may just be busy) 1645 * ENODEV if the NVmem device is missing or otherwise unusable 1646 * EPROTO on other h/w or s/w errors. 1647 */ 1648 static int 1649 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1650 { 1651 int err; 1652 1653 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1654 switch (cmd) { 1655 case BGE_SEE_READ: 1656 err = bge_seeprom_access(bgep, 1657 SEEPROM_ACCESS_READ, addr, dp); 1658 break; 1659 1660 case BGE_SEE_WRITE: 1661 bge_nvmem_protect(bgep, B_FALSE); 1662 err = bge_seeprom_access(bgep, 1663 SEEPROM_ACCESS_WRITE, addr, dp); 1664 bge_nvmem_protect(bgep, B_TRUE); 1665 break; 1666 1667 case BGE_FLASH_READ: 1668 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1669 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1670 bge_reg_set32(bgep, NVM_ACCESS_REG, 1671 NVM_ACCESS_ENABLE); 1672 } 1673 err = bge_flash_access(bgep, 1674 NVM_FLASH_CMD_RD, addr, dp); 1675 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1676 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1677 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1678 NVM_ACCESS_ENABLE); 1679 } 1680 break; 1681 1682 case BGE_FLASH_WRITE: 1683 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1684 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1685 bge_reg_set32(bgep, NVM_ACCESS_REG, 1686 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1687 } 1688 bge_nvmem_protect(bgep, B_FALSE); 1689 err = bge_flash_access(bgep, 1690 NVM_FLASH_CMD_WR, addr, dp); 1691 bge_nvmem_protect(bgep, B_TRUE); 1692 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1693 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1694 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1695 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1696 } 1697 1698 break; 1699 1700 default: 1701 _NOTE(NOTREACHED) 1702 break; 1703 } 1704 bge_nvmem_relinquish(bgep); 1705 } 1706 1707 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1708 return (err); 1709 } 1710 1711 /* 1712 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1713 */ 1714 static uint64_t bge_get_nvmac(bge_t *bgep); 1715 #pragma no_inline(bge_get_nvmac) 1716 1717 static uint64_t 1718 bge_get_nvmac(bge_t *bgep) 1719 { 1720 uint32_t mac_high; 1721 uint32_t mac_low; 1722 uint32_t addr; 1723 uint32_t cmd; 1724 uint64_t mac; 1725 1726 BGE_TRACE(("bge_get_nvmac($%p)", 1727 (void *)bgep)); 1728 1729 switch (bgep->chipid.nvtype) { 1730 case BGE_NVTYPE_NONE: 1731 case BGE_NVTYPE_UNKNOWN: 1732 default: 1733 return (0ULL); 1734 1735 case BGE_NVTYPE_SEEPROM: 1736 case BGE_NVTYPE_LEGACY_SEEPROM: 1737 cmd = BGE_SEE_READ; 1738 break; 1739 1740 case BGE_NVTYPE_UNBUFFERED_FLASH: 1741 case BGE_NVTYPE_BUFFERED_FLASH: 1742 cmd = BGE_FLASH_READ; 1743 break; 1744 } 1745 1746 addr = NVMEM_DATA_MAC_ADDRESS; 1747 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1748 return (0ULL); 1749 addr += 4; 1750 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1751 return (0ULL); 1752 1753 /* 1754 * The Broadcom chip is natively BIG-endian, so that's how the 1755 * MAC address is represented in NVmem. We may need to swap it 1756 * around on a little-endian host ... 1757 */ 1758 #ifdef _BIG_ENDIAN 1759 mac = mac_high; 1760 mac = mac << 32; 1761 mac |= mac_low; 1762 #else 1763 mac = BGE_BSWAP_32(mac_high); 1764 mac = mac << 32; 1765 mac |= BGE_BSWAP_32(mac_low); 1766 #endif /* _BIG_ENDIAN */ 1767 1768 return (mac); 1769 } 1770 1771 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1772 1773 /* 1774 * Dummy version for when we're not supporting NVmem access 1775 */ 1776 static uint64_t bge_get_nvmac(bge_t *bgep); 1777 #pragma inline(bge_get_nvmac) 1778 1779 static uint64_t 1780 bge_get_nvmac(bge_t *bgep) 1781 { 1782 _NOTE(ARGUNUSED(bgep)) 1783 return (0ULL); 1784 } 1785 1786 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1787 1788 /* 1789 * Determine the type of NVmem that is (or may be) attached to this chip, 1790 */ 1791 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1792 #pragma no_inline(bge_nvmem_id) 1793 1794 static enum bge_nvmem_type 1795 bge_nvmem_id(bge_t *bgep) 1796 { 1797 enum bge_nvmem_type nvtype; 1798 uint32_t config1; 1799 1800 BGE_TRACE(("bge_nvmem_id($%p)", 1801 (void *)bgep)); 1802 1803 switch (bgep->chipid.device) { 1804 default: 1805 /* 1806 * We shouldn't get here; it means we don't recognise 1807 * the chip, which means we don't know how to determine 1808 * what sort of NVmem (if any) it has. So we'll say 1809 * NONE, to disable the NVmem access code ... 1810 */ 1811 nvtype = BGE_NVTYPE_NONE; 1812 break; 1813 1814 case DEVICE_ID_5700: 1815 case DEVICE_ID_5700x: 1816 case DEVICE_ID_5701: 1817 /* 1818 * These devices support *only* SEEPROMs 1819 */ 1820 nvtype = BGE_NVTYPE_SEEPROM; 1821 break; 1822 1823 case DEVICE_ID_5702: 1824 case DEVICE_ID_5702fe: 1825 case DEVICE_ID_5703C: 1826 case DEVICE_ID_5703S: 1827 case DEVICE_ID_5704C: 1828 case DEVICE_ID_5704S: 1829 case DEVICE_ID_5704: 1830 case DEVICE_ID_5705M: 1831 case DEVICE_ID_5705C: 1832 case DEVICE_ID_5705_2: 1833 case DEVICE_ID_5706: 1834 case DEVICE_ID_5782: 1835 case DEVICE_ID_5788: 1836 case DEVICE_ID_5789: 1837 case DEVICE_ID_5751: 1838 case DEVICE_ID_5751M: 1839 case DEVICE_ID_5752: 1840 case DEVICE_ID_5752M: 1841 case DEVICE_ID_5754: 1842 case DEVICE_ID_5721: 1843 case DEVICE_ID_5714C: 1844 case DEVICE_ID_5714S: 1845 case DEVICE_ID_5715C: 1846 case DEVICE_ID_5715S: 1847 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1848 if (config1 & NVM_CFG1_FLASH_MODE) 1849 if (config1 & NVM_CFG1_BUFFERED_MODE) 1850 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1851 else 1852 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1853 else 1854 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1855 break; 1856 } 1857 1858 return (nvtype); 1859 } 1860 1861 #undef BGE_DBG 1862 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1863 1864 static void 1865 bge_init_recv_rule(bge_t *bgep) 1866 { 1867 bge_recv_rule_t *rulep; 1868 uint32_t i; 1869 1870 /* 1871 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING 1872 * 1. to direct UDP traffic, set: 1873 * rulep->control = RULE_PROTO_CONTROL; 1874 * rulep->mask_value = RULE_UDP_MASK_VALUE; 1875 * 2. to direct ICMP traffic, set: 1876 * rulep->control = RULE_PROTO_CONTROL; 1877 * rulep->mask_value = RULE_ICMP_MASK_VALUE; 1878 * 3. to direct traffic by source ip, set: 1879 * rulep->control = RULE_SIP_CONTROL; 1880 * rulep->mask_value = RULE_SIP_MASK_VALUE; 1881 */ 1882 rulep = bgep->recv_rules; 1883 rulep->control = RULE_PROTO_CONTROL; 1884 rulep->mask_value = RULE_TCP_MASK_VALUE; 1885 1886 /* 1887 * set receive rule registers 1888 */ 1889 rulep = bgep->recv_rules; 1890 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1891 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1892 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1893 } 1894 } 1895 1896 /* 1897 * Using the values captured by bge_chip_cfg_init(), and additional probes 1898 * as required, characterise the chip fully: determine the label by which 1899 * to refer to this chip, the correct settings for various registers, and 1900 * of course whether the device and/or subsystem are supported! 1901 */ 1902 int bge_chip_id_init(bge_t *bgep); 1903 #pragma no_inline(bge_chip_id_init) 1904 1905 int 1906 bge_chip_id_init(bge_t *bgep) 1907 { 1908 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1909 boolean_t sys_ok; 1910 boolean_t dev_ok; 1911 chip_id_t *cidp; 1912 uint32_t subid; 1913 char *devname; 1914 char *sysname; 1915 int *ids; 1916 int err; 1917 uint_t i; 1918 1919 ASSERT(bgep->bge_chip_state == BGE_CHIP_INITIAL); 1920 1921 sys_ok = dev_ok = B_FALSE; 1922 cidp = &bgep->chipid; 1923 1924 /* 1925 * Check the PCI device ID to determine the generic chip type and 1926 * select parameters that depend on this. 1927 * 1928 * Note: because the SPARC platforms in general don't fit the 1929 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1930 * as zero - which is why we use <asic_rev> rather than <revision> 1931 * below ... 1932 * 1933 * Note: in general we can't distinguish between the Copper/SerDes 1934 * versions by ID alone, as some Copper devices (e.g. some but not 1935 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1936 * treat them the same here, and the MII code works out the media 1937 * type later on ... 1938 */ 1939 cidp->mbuf_base = bge_mbuf_pool_base; 1940 cidp->mbuf_length = bge_mbuf_pool_len; 1941 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1942 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1943 cidp->pci_type = BGE_PCI_X; 1944 cidp->statistic_type = BGE_STAT_BLK; 1945 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1946 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1947 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1948 1949 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1950 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1951 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1952 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1953 1954 cidp->msi_enabled = B_FALSE; 1955 1956 switch (cidp->device) { 1957 case DEVICE_ID_5700: 1958 case DEVICE_ID_5700x: 1959 cidp->chip_label = 5700; 1960 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1961 break; 1962 1963 case DEVICE_ID_5701: 1964 cidp->chip_label = 5701; 1965 dev_ok = B_TRUE; 1966 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1967 break; 1968 1969 case DEVICE_ID_5702: 1970 case DEVICE_ID_5702fe: 1971 cidp->chip_label = 5702; 1972 dev_ok = B_TRUE; 1973 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1974 cidp->pci_type = BGE_PCI; 1975 break; 1976 1977 case DEVICE_ID_5703C: 1978 case DEVICE_ID_5703S: 1979 case DEVICE_ID_5703: 1980 /* 1981 * Revision A0 of the 5703/5793 had various errata 1982 * that we can't or don't work around, so it's not 1983 * supported, but all later versions are 1984 */ 1985 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 1986 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 1987 dev_ok = B_TRUE; 1988 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1989 break; 1990 1991 case DEVICE_ID_5704C: 1992 case DEVICE_ID_5704S: 1993 case DEVICE_ID_5704: 1994 /* 1995 * Revision A0 of the 5704/5794 had various errata 1996 * but we have workarounds, so it *is* supported. 1997 */ 1998 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 1999 cidp->mbuf_base = bge_mbuf_pool_base_5704; 2000 cidp->mbuf_length = bge_mbuf_pool_len_5704; 2001 dev_ok = B_TRUE; 2002 if (cidp->asic_rev < MHCR_CHIP_REV_5704_B0) 2003 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2004 break; 2005 2006 case DEVICE_ID_5705C: 2007 case DEVICE_ID_5705M: 2008 case DEVICE_ID_5705MA3: 2009 case DEVICE_ID_5705F: 2010 case DEVICE_ID_5705_2: 2011 case DEVICE_ID_5754: 2012 if (cidp->device == DEVICE_ID_5754) { 2013 cidp->chip_label = 5754; 2014 cidp->pci_type = BGE_PCI_E; 2015 } else { 2016 cidp->chip_label = 5705; 2017 cidp->pci_type = BGE_PCI; 2018 } 2019 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2020 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2021 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2022 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2023 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2024 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2025 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2026 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2027 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2028 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2029 cidp->statistic_type = BGE_STAT_REG; 2030 dev_ok = B_TRUE; 2031 break; 2032 2033 case DEVICE_ID_5706: 2034 cidp->chip_label = 5706; 2035 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2036 break; 2037 2038 case DEVICE_ID_5782: 2039 /* 2040 * Apart from the label, we treat this as a 5705(?) 2041 */ 2042 cidp->chip_label = 5782; 2043 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2044 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2045 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2046 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2047 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2048 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2049 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2050 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2051 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2052 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2053 cidp->statistic_type = BGE_STAT_REG; 2054 dev_ok = B_TRUE; 2055 break; 2056 2057 case DEVICE_ID_5788: 2058 /* 2059 * Apart from the label, we treat this as a 5705(?) 2060 */ 2061 cidp->chip_label = 5788; 2062 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2063 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2064 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2065 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2066 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2067 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2068 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2069 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2070 cidp->statistic_type = BGE_STAT_REG; 2071 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2072 dev_ok = B_TRUE; 2073 break; 2074 2075 case DEVICE_ID_5714C: 2076 if (cidp->revision >= REVISION_ID_5714_A2) 2077 cidp->msi_enabled = bge_enable_msi; 2078 /* FALLTHRU */ 2079 case DEVICE_ID_5714S: 2080 cidp->chip_label = 5714; 2081 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2082 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2083 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2084 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2085 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2086 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2087 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2088 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2089 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2090 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2091 cidp->pci_type = BGE_PCI_E; 2092 cidp->statistic_type = BGE_STAT_REG; 2093 dev_ok = B_TRUE; 2094 break; 2095 2096 case DEVICE_ID_5715C: 2097 case DEVICE_ID_5715S: 2098 cidp->chip_label = 5715; 2099 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2100 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2101 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2102 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2103 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2104 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2105 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2106 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2107 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2108 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2109 cidp->pci_type = BGE_PCI_E; 2110 cidp->statistic_type = BGE_STAT_REG; 2111 if (cidp->revision >= REVISION_ID_5715_A2) 2112 cidp->msi_enabled = bge_enable_msi; 2113 dev_ok = B_TRUE; 2114 break; 2115 2116 case DEVICE_ID_5721: 2117 cidp->chip_label = 5721; 2118 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2119 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2120 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2121 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2122 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2123 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2124 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2125 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2126 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2127 cidp->pci_type = BGE_PCI_E; 2128 cidp->statistic_type = BGE_STAT_REG; 2129 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2130 dev_ok = B_TRUE; 2131 break; 2132 2133 case DEVICE_ID_5751: 2134 case DEVICE_ID_5751M: 2135 cidp->chip_label = 5751; 2136 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2137 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2138 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2139 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2140 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2141 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2142 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2143 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2144 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2145 cidp->pci_type = BGE_PCI_E; 2146 cidp->statistic_type = BGE_STAT_REG; 2147 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2148 dev_ok = B_TRUE; 2149 break; 2150 2151 case DEVICE_ID_5752: 2152 case DEVICE_ID_5752M: 2153 cidp->chip_label = 5752; 2154 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2155 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2156 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2157 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2158 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2159 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2160 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2161 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2162 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2163 cidp->pci_type = BGE_PCI_E; 2164 cidp->statistic_type = BGE_STAT_REG; 2165 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2166 dev_ok = B_TRUE; 2167 break; 2168 2169 case DEVICE_ID_5789: 2170 cidp->chip_label = 5789; 2171 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2172 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2173 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2174 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2175 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2176 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2177 cidp->pci_type = BGE_PCI_E; 2178 cidp->statistic_type = BGE_STAT_REG; 2179 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2180 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2181 cidp->msi_enabled = B_TRUE; 2182 dev_ok = B_TRUE; 2183 break; 2184 2185 } 2186 2187 /* 2188 * Setup the default jumbo parameter. 2189 */ 2190 cidp->ethmax_size = ETHERMAX; 2191 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2192 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2193 2194 /* 2195 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2196 * setup below jumbo specific parameters. 2197 * 2198 * For BCM5714/5715, there is only one standard receive ring. So the 2199 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2200 * feature is enabled. 2201 */ 2202 if (bge_jumbo_enable && 2203 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2204 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2205 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2206 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2207 cidp->mbuf_lo_water_rdma = 2208 RDMA_MBUF_LOWAT_5714_JUMBO; 2209 cidp->mbuf_lo_water_rmac = 2210 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2211 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2212 cidp->jumbo_slots = 0; 2213 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2214 } else { 2215 cidp->mbuf_lo_water_rdma = 2216 RDMA_MBUF_LOWAT_JUMBO; 2217 cidp->mbuf_lo_water_rmac = 2218 MAC_RX_MBUF_LOWAT_JUMBO; 2219 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2220 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2221 } 2222 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2223 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2224 cidp->ethmax_size = cidp->default_mtu + 2225 sizeof (struct ether_header); 2226 } 2227 2228 /* 2229 * Identify the NV memory type: SEEPROM or Flash? 2230 */ 2231 cidp->nvtype = bge_nvmem_id(bgep); 2232 2233 /* 2234 * Now, we want to check whether this device is part of a 2235 * supported subsystem (e.g., on the motherboard of a Sun 2236 * branded platform). 2237 * 2238 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2239 */ 2240 if (cidp->subven == VENDOR_ID_SUN) 2241 sys_ok = B_TRUE; 2242 2243 /* 2244 * Rule 2: If it's on the list on known subsystems, then it's OK. 2245 * Note: 0x14e41647 should *not* appear in the list, but the code 2246 * doesn't enforce that. 2247 */ 2248 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2249 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2250 if (err == DDI_PROP_SUCCESS) { 2251 /* 2252 * Got the list; scan for a matching subsystem vendor/device 2253 */ 2254 subid = (cidp->subven << 16) | cidp->subdev; 2255 while (i--) 2256 if (ids[i] == subid) 2257 sys_ok = B_TRUE; 2258 ddi_prop_free(ids); 2259 } 2260 2261 /* 2262 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2263 * 2264 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2265 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2266 * we have to check specially for the exact device paths to the 2267 * motherboard devices on those platforms ;-( 2268 * 2269 * Note: we can't just use the "supported-subsystems" mechanism 2270 * above, because the entry would have to be 0x14e41647 -- which 2271 * would then accept *any* plugin card that *didn't* contain a 2272 * (valid) SEEPROM ;-( 2273 */ 2274 sysname = ddi_node_name(ddi_root_node()); 2275 devname = ddi_pathname(bgep->devinfo, buf); 2276 ASSERT(strlen(devname) > 0); 2277 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2278 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2279 sys_ok = B_TRUE; 2280 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2281 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2282 sys_ok = B_TRUE; 2283 2284 /* 2285 * Now check what we've discovered: is this truly a supported 2286 * chip on (the motherboard of) a supported platform? 2287 * 2288 * Possible problems here: 2289 * 1) it's a completely unheard-of chip (e.g. 5761) 2290 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2291 * 3) it's a chip we would support if it were on the motherboard 2292 * of a Sun platform, but this one isn't ;-( 2293 */ 2294 if (cidp->chip_label == 0) 2295 bge_problem(bgep, 2296 "Device 'pci%04x,%04x' not recognized (%d?)", 2297 cidp->vendor, cidp->device, cidp->device); 2298 else if (!dev_ok) 2299 bge_problem(bgep, 2300 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2301 cidp->vendor, cidp->device, cidp->chip_label, 2302 cidp->revision); 2303 #if BGE_DEBUGGING 2304 else if (!sys_ok) 2305 bge_problem(bgep, 2306 "%d-based subsystem 'pci%04x,%04x' not validated", 2307 cidp->chip_label, cidp->subven, cidp->subdev); 2308 #endif 2309 else 2310 cidp->flags |= CHIP_FLAG_SUPPORTED; 2311 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2312 return (EIO); 2313 return (0); 2314 } 2315 2316 void 2317 bge_chip_msi_trig(bge_t *bgep) 2318 { 2319 uint32_t regval; 2320 2321 regval = bgep->param_msi_cnt<<4; 2322 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2323 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2324 } 2325 2326 /* 2327 * Various registers that control the chip's internal engines (state 2328 * machines) have a <reset> and <enable> bits (fortunately, in the 2329 * same place in each such register :-). 2330 * 2331 * To reset the state machine, the <reset> bit must be written with 1; 2332 * it will then read back as 1 while the reset is in progress, but 2333 * self-clear to 0 when the reset completes. 2334 * 2335 * To enable a state machine, one must set the <enable> bit, which 2336 * will continue to read back as 0 until the state machine is running. 2337 * 2338 * To disable a state machine, the <enable> bit must be cleared, but 2339 * it will continue to read back as 1 until the state machine actually 2340 * stops. 2341 * 2342 * This routine implements polling for completion of a reset, enable 2343 * or disable operation, returning B_TRUE on success (bit reached the 2344 * required state) or B_FALSE on timeout (200*100us == 20ms). 2345 */ 2346 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2347 uint32_t mask, uint32_t val); 2348 #pragma no_inline(bge_chip_poll_engine) 2349 2350 static boolean_t 2351 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2352 uint32_t mask, uint32_t val) 2353 { 2354 uint32_t regval; 2355 uint32_t n; 2356 2357 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2358 (void *)bgep, regno, mask, val)); 2359 2360 for (n = 200; n; --n) { 2361 regval = bge_reg_get32(bgep, regno); 2362 if ((regval & mask) == val) 2363 return (B_TRUE); 2364 drv_usecwait(100); 2365 } 2366 2367 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2368 return (B_FALSE); 2369 } 2370 2371 /* 2372 * Various registers that control the chip's internal engines (state 2373 * machines) have a <reset> bit (fortunately, in the same place in 2374 * each such register :-). To reset the state machine, this bit must 2375 * be written with 1; it will then read back as 1 while the reset is 2376 * in progress, but self-clear to 0 when the reset completes. 2377 * 2378 * This code sets the bit, then polls for it to read back as zero. 2379 * The return value is B_TRUE on success (reset bit cleared itself), 2380 * or B_FALSE if the state machine didn't recover :( 2381 * 2382 * NOTE: the Core reset is similar to other resets, except that we 2383 * can't poll for completion, since the Core reset disables memory 2384 * access! So we just have to assume that it will all complete in 2385 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2386 */ 2387 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2388 #pragma no_inline(bge_chip_reset_engine) 2389 2390 static boolean_t 2391 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2392 { 2393 uint32_t regval; 2394 uint32_t val32; 2395 2396 regval = bge_reg_get32(bgep, regno); 2397 2398 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2399 (void *)bgep, regno)); 2400 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2401 regno, regval)); 2402 2403 regval |= STATE_MACHINE_RESET_BIT; 2404 2405 switch (regno) { 2406 case MISC_CONFIG_REG: 2407 /* 2408 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2409 * resetting PCIE block and bringing PCIE link down, bit 29 2410 * in the register needs to be set first, and then set it again 2411 * while the reset bit is written. 2412 * See:P500 of 57xx-PG102-RDS.pdf. 2413 */ 2414 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2415 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2416 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2417 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2418 if (bgep->chipid.pci_type == BGE_PCI_E) { 2419 if (bgep->chipid.asic_rev == 2420 MHCR_CHIP_REV_5751_A0 || 2421 bgep->chipid.asic_rev == 2422 MHCR_CHIP_REV_5721_A0) { 2423 val32 = bge_reg_get32(bgep, 2424 PHY_TEST_CTRL_REG); 2425 if (val32 == (PHY_PCIE_SCRAM_MODE | 2426 PHY_PCIE_LTASS_MODE)) 2427 bge_reg_put32(bgep, 2428 PHY_TEST_CTRL_REG, 2429 PHY_PCIE_SCRAM_MODE); 2430 val32 = pci_config_get32 2431 (bgep->cfg_handle, 2432 PCI_CONF_BGE_CLKCTL); 2433 val32 |= CLKCTL_PCIE_A0_FIX; 2434 pci_config_put32(bgep->cfg_handle, 2435 PCI_CONF_BGE_CLKCTL, val32); 2436 } 2437 bge_reg_set32(bgep, regno, 2438 MISC_CONFIG_GRC_RESET_DISABLE); 2439 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2440 } 2441 } 2442 2443 /* 2444 * Special case - causes Core reset 2445 * 2446 * On SPARC v9 we want to ensure that we don't start 2447 * timing until the I/O access has actually reached 2448 * the chip, otherwise we might make the next access 2449 * too early. And we can't just force the write out 2450 * by following it with a read (even to config space) 2451 * because that would cause the fault we're trying 2452 * to avoid. Hence the need for membar_sync() here. 2453 */ 2454 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2455 #ifdef __sparcv9 2456 membar_sync(); 2457 #endif /* __sparcv9 */ 2458 /* 2459 * On some platforms,system need about 300us for 2460 * link setup. 2461 */ 2462 drv_usecwait(300); 2463 2464 if (bgep->chipid.pci_type == BGE_PCI_E) { 2465 /* PCI-E device need more reset time */ 2466 drv_usecwait(120000); 2467 2468 /* Set PCIE max payload size and clear error status. */ 2469 if ((bgep->chipid.chip_label == 5721) || 2470 (bgep->chipid.chip_label == 5751) || 2471 (bgep->chipid.chip_label == 5752) || 2472 (bgep->chipid.chip_label == 5789)) { 2473 pci_config_put16(bgep->cfg_handle, 2474 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2475 pci_config_put16(bgep->cfg_handle, 2476 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2477 } 2478 } 2479 2480 BGE_PCICHK(bgep); 2481 return (B_TRUE); 2482 2483 default: 2484 bge_reg_put32(bgep, regno, regval); 2485 return (bge_chip_poll_engine(bgep, regno, 2486 STATE_MACHINE_RESET_BIT, 0)); 2487 } 2488 } 2489 2490 /* 2491 * Various registers that control the chip's internal engines (state 2492 * machines) have an <enable> bit (fortunately, in the same place in 2493 * each such register :-). To stop the state machine, this bit must 2494 * be written with 0, then polled to see when the state machine has 2495 * actually stopped. 2496 * 2497 * The return value is B_TRUE on success (enable bit cleared), or 2498 * B_FALSE if the state machine didn't stop :( 2499 */ 2500 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2501 uint32_t morebits); 2502 #pragma no_inline(bge_chip_disable_engine) 2503 2504 static boolean_t 2505 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2506 { 2507 uint32_t regval; 2508 2509 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2510 (void *)bgep, regno, morebits)); 2511 2512 switch (regno) { 2513 case FTQ_RESET_REG: 2514 /* 2515 * Not quite like the others; it doesn't 2516 * have an <enable> bit, but instead we 2517 * have to set and then clear all the bits 2518 */ 2519 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2520 drv_usecwait(100); 2521 bge_reg_put32(bgep, regno, 0); 2522 return (B_TRUE); 2523 2524 default: 2525 regval = bge_reg_get32(bgep, regno); 2526 regval &= ~STATE_MACHINE_ENABLE_BIT; 2527 regval &= ~morebits; 2528 bge_reg_put32(bgep, regno, regval); 2529 return (bge_chip_poll_engine(bgep, regno, 2530 STATE_MACHINE_ENABLE_BIT, 0)); 2531 } 2532 } 2533 2534 /* 2535 * Various registers that control the chip's internal engines (state 2536 * machines) have an <enable> bit (fortunately, in the same place in 2537 * each such register :-). To start the state machine, this bit must 2538 * be written with 1, then polled to see when the state machine has 2539 * actually started. 2540 * 2541 * The return value is B_TRUE on success (enable bit set), or 2542 * B_FALSE if the state machine didn't start :( 2543 */ 2544 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2545 uint32_t morebits); 2546 #pragma no_inline(bge_chip_enable_engine) 2547 2548 static boolean_t 2549 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2550 { 2551 uint32_t regval; 2552 2553 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2554 (void *)bgep, regno, morebits)); 2555 2556 switch (regno) { 2557 case FTQ_RESET_REG: 2558 /* 2559 * Not quite like the others; it doesn't 2560 * have an <enable> bit, but instead we 2561 * have to set and then clear all the bits 2562 */ 2563 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2564 drv_usecwait(100); 2565 bge_reg_put32(bgep, regno, 0); 2566 return (B_TRUE); 2567 2568 default: 2569 regval = bge_reg_get32(bgep, regno); 2570 regval |= STATE_MACHINE_ENABLE_BIT; 2571 regval |= morebits; 2572 bge_reg_put32(bgep, regno, regval); 2573 return (bge_chip_poll_engine(bgep, regno, 2574 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2575 } 2576 } 2577 2578 /* 2579 * Reprogram the Ethernet, Transmit, and Receive MAC 2580 * modes to match the param_* variables 2581 */ 2582 static void bge_sync_mac_modes(bge_t *bgep); 2583 #pragma no_inline(bge_sync_mac_modes) 2584 2585 static void 2586 bge_sync_mac_modes(bge_t *bgep) 2587 { 2588 uint32_t macmode; 2589 uint32_t regval; 2590 2591 ASSERT(mutex_owned(bgep->genlock)); 2592 2593 /* 2594 * Reprogram the Ethernet MAC mode ... 2595 */ 2596 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2597 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2598 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2599 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2600 else 2601 macmode |= ETHERNET_MODE_LINK_POLARITY; 2602 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2603 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2604 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2605 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2606 else if (bgep->param_link_speed == 10 || bgep->param_link_speed == 100) 2607 macmode |= ETHERNET_MODE_PORTMODE_MII; 2608 else 2609 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2610 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2611 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2612 else 2613 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2614 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2615 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2616 else 2617 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2618 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2619 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2620 (void *)bgep, regval, macmode)); 2621 2622 /* 2623 * ... the Transmit MAC mode ... 2624 */ 2625 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2626 if (bgep->param_link_tx_pause) 2627 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2628 else 2629 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2630 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2631 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2632 (void *)bgep, regval, macmode)); 2633 2634 /* 2635 * ... and the Receive MAC mode 2636 */ 2637 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2638 if (bgep->param_link_rx_pause) 2639 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2640 else 2641 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2642 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2643 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2644 (void *)bgep, regval, macmode)); 2645 } 2646 2647 /* 2648 * bge_chip_sync() -- program the chip with the unicast MAC address, 2649 * the multicast hash table, the required level of promiscuity, and 2650 * the current loopback mode ... 2651 */ 2652 #ifdef BGE_IPMI_ASF 2653 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2654 #else 2655 int bge_chip_sync(bge_t *bgep); 2656 #endif 2657 #pragma no_inline(bge_chip_sync) 2658 2659 int 2660 #ifdef BGE_IPMI_ASF 2661 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2662 #else 2663 bge_chip_sync(bge_t *bgep) 2664 #endif 2665 { 2666 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2667 boolean_t promisc; 2668 uint64_t macaddr; 2669 uint32_t fill; 2670 int i, j; 2671 int retval = DDI_SUCCESS; 2672 2673 BGE_TRACE(("bge_chip_sync($%p)", 2674 (void *)bgep)); 2675 2676 ASSERT(mutex_owned(bgep->genlock)); 2677 2678 promisc = B_FALSE; 2679 fill = ~(uint32_t)0; 2680 2681 if (bgep->promisc) 2682 promisc = B_TRUE; 2683 else 2684 fill = (uint32_t)0; 2685 2686 /* 2687 * If the TX/RX MAC engines are already running, we should stop 2688 * them (and reset the RX engine) before changing the parameters. 2689 * If they're not running, this will have no effect ... 2690 * 2691 * NOTE: this is currently disabled by default because stopping 2692 * and restarting the Tx engine may cause an outgoing packet in 2693 * transit to be truncated. Also, stopping and restarting the 2694 * Rx engine seems to not work correctly on the 5705. Testing 2695 * has not (yet!) revealed any problems with NOT stopping and 2696 * restarting these engines (and Broadcom say their drivers don't 2697 * do this), but if it is found to cause problems, this variable 2698 * can be patched to re-enable the old behaviour ... 2699 */ 2700 if (bge_stop_start_on_sync) { 2701 #ifdef BGE_IPMI_ASF 2702 if (!bgep->asf_enabled) { 2703 if (!bge_chip_disable_engine(bgep, 2704 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2705 retval = DDI_FAILURE; 2706 } else { 2707 if (!bge_chip_disable_engine(bgep, 2708 RECEIVE_MAC_MODE_REG, 0)) 2709 retval = DDI_FAILURE; 2710 } 2711 #else 2712 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2713 RECEIVE_MODE_KEEP_VLAN_TAG)) 2714 retval = DDI_FAILURE; 2715 #endif 2716 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2717 retval = DDI_FAILURE; 2718 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2719 retval = DDI_FAILURE; 2720 } 2721 2722 /* 2723 * Reprogram the hashed multicast address table ... 2724 */ 2725 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2726 bge_reg_put32(bgep, MAC_HASH_REG(i), 2727 bgep->mcast_hash[i] | fill); 2728 2729 #ifdef BGE_IPMI_ASF 2730 if (!bgep->asf_enabled || !asf_keeplive) { 2731 #endif 2732 /* 2733 * Transform the MAC address(es) from host to chip format, then 2734 * reprogram the transmit random backoff seed and the unicast 2735 * MAC address(es) ... 2736 */ 2737 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2738 for (i = 0, fill = 0, macaddr = 0ull; 2739 i < ETHERADDRL; ++i) { 2740 macaddr <<= 8; 2741 macaddr |= bgep->curr_addr[j].addr[i]; 2742 fill += bgep->curr_addr[j].addr[i]; 2743 } 2744 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2745 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2746 } 2747 2748 BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx", 2749 (void *)bgep, macaddr)); 2750 #ifdef BGE_IPMI_ASF 2751 } 2752 #endif 2753 2754 /* 2755 * Set or clear the PROMISCUOUS mode bit 2756 */ 2757 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2758 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2759 2760 /* 2761 * Sync the rest of the MAC modes too ... 2762 */ 2763 bge_sync_mac_modes(bgep); 2764 2765 /* 2766 * Restart RX/TX MAC engines if required ... 2767 */ 2768 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2769 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2770 retval = DDI_FAILURE; 2771 #ifdef BGE_IPMI_ASF 2772 if (!bgep->asf_enabled) { 2773 if (!bge_chip_enable_engine(bgep, 2774 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2775 retval = DDI_FAILURE; 2776 } else { 2777 if (!bge_chip_enable_engine(bgep, 2778 RECEIVE_MAC_MODE_REG, 0)) 2779 retval = DDI_FAILURE; 2780 } 2781 #else 2782 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2783 RECEIVE_MODE_KEEP_VLAN_TAG)) 2784 retval = DDI_FAILURE; 2785 #endif 2786 } 2787 return (retval); 2788 } 2789 2790 /* 2791 * This array defines the sequence of state machine control registers 2792 * in which the <enable> bit must be cleared to bring the chip to a 2793 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2794 */ 2795 static bge_regno_t shutdown_engine_regs[] = { 2796 RECEIVE_MAC_MODE_REG, 2797 RCV_BD_INITIATOR_MODE_REG, 2798 RCV_LIST_PLACEMENT_MODE_REG, 2799 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 2800 RCV_DATA_BD_INITIATOR_MODE_REG, 2801 RCV_DATA_COMPLETION_MODE_REG, 2802 RCV_BD_COMPLETION_MODE_REG, 2803 2804 SEND_BD_SELECTOR_MODE_REG, 2805 SEND_BD_INITIATOR_MODE_REG, 2806 SEND_DATA_INITIATOR_MODE_REG, 2807 READ_DMA_MODE_REG, 2808 SEND_DATA_COMPLETION_MODE_REG, 2809 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 2810 SEND_BD_COMPLETION_MODE_REG, 2811 TRANSMIT_MAC_MODE_REG, 2812 2813 HOST_COALESCE_MODE_REG, 2814 WRITE_DMA_MODE_REG, 2815 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 2816 FTQ_RESET_REG, /* special - see code */ 2817 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 2818 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 2819 BGE_REGNO_NONE /* terminator */ 2820 }; 2821 2822 /* 2823 * bge_chip_stop() -- stop all chip processing 2824 * 2825 * If the <fault> parameter is B_TRUE, we're stopping the chip because 2826 * we've detected a problem internally; otherwise, this is a normal 2827 * (clean) stop (at user request i.e. the last STREAM has been closed). 2828 */ 2829 void bge_chip_stop(bge_t *bgep, boolean_t fault); 2830 #pragma no_inline(bge_chip_stop) 2831 2832 void 2833 bge_chip_stop(bge_t *bgep, boolean_t fault) 2834 { 2835 bge_regno_t regno; 2836 bge_regno_t *rbp; 2837 boolean_t ok; 2838 2839 BGE_TRACE(("bge_chip_stop($%p)", 2840 (void *)bgep)); 2841 2842 ASSERT(mutex_owned(bgep->genlock)); 2843 2844 rbp = shutdown_engine_regs; 2845 /* 2846 * When driver try to shutdown the BCM5705/5788/5721/5751/ 2847 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 2848 * -ory arbiter should not be disabled. 2849 */ 2850 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 2851 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 2852 ok &= bge_chip_disable_engine(bgep, regno, 0); 2853 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 2854 (regno != DMA_COMPLETION_MODE_REG) && 2855 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 2856 (regno != BUFFER_MANAGER_MODE_REG) && 2857 (regno != MEMORY_ARBITER_MODE_REG)) 2858 ok &= bge_chip_disable_engine(bgep, 2859 regno, 0); 2860 } 2861 2862 if (!ok && !fault) 2863 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 2864 2865 /* 2866 * Finally, disable (all) MAC events & clear the MAC status 2867 */ 2868 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 2869 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 2870 2871 /* 2872 * if we're stopping the chip because of a detected fault then do 2873 * appropriate actions 2874 */ 2875 if (fault) { 2876 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 2877 bgep->bge_chip_state = BGE_CHIP_FAULT; 2878 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2879 if (bgep->bge_dma_error) { 2880 /* 2881 * need to free buffers in case the fault was 2882 * due to a memory error in a buffer - got to 2883 * do a fair bit of tidying first 2884 */ 2885 if (bgep->progress & PROGRESS_KSTATS) { 2886 bge_fini_kstats(bgep); 2887 bgep->progress &= ~PROGRESS_KSTATS; 2888 } 2889 if (bgep->progress & PROGRESS_INTR) { 2890 bge_intr_disable(bgep); 2891 rw_enter(bgep->errlock, RW_WRITER); 2892 bge_fini_rings(bgep); 2893 rw_exit(bgep->errlock); 2894 bgep->progress &= ~PROGRESS_INTR; 2895 } 2896 if (bgep->progress & PROGRESS_BUFS) { 2897 bge_free_bufs(bgep); 2898 bgep->progress &= ~PROGRESS_BUFS; 2899 } 2900 bgep->bge_dma_error = B_FALSE; 2901 } 2902 } 2903 } else 2904 bgep->bge_chip_state = BGE_CHIP_STOPPED; 2905 } 2906 2907 /* 2908 * Poll for completion of chip's ROM firmware; also, at least on the 2909 * first time through, find and return the hardware MAC address, if any. 2910 */ 2911 static uint64_t bge_poll_firmware(bge_t *bgep); 2912 #pragma no_inline(bge_poll_firmware) 2913 2914 static uint64_t 2915 bge_poll_firmware(bge_t *bgep) 2916 { 2917 uint64_t magic; 2918 uint64_t mac; 2919 uint32_t gen; 2920 uint32_t i; 2921 2922 /* 2923 * Step 19: poll for firmware completion (GENCOMM port set 2924 * to the ones complement of T3_MAGIC_NUMBER). 2925 * 2926 * While we're at it, we also read the MAC address register; 2927 * at some stage the firmware will load this with the 2928 * factory-set value. 2929 * 2930 * When both the magic number and the MAC address are set, 2931 * we're done; but we impose a time limit of one second 2932 * (1000*1000us) in case the firmware fails in some fashion 2933 * or the SEEPROM that provides that MAC address isn't fitted. 2934 * 2935 * After the first time through (chip state != INITIAL), we 2936 * don't need the MAC address to be set (we've already got it 2937 * or not, from the first time), so we don't wait for it, but 2938 * we still have to wait for the T3_MAGIC_NUMBER. 2939 * 2940 * Note: the magic number is only a 32-bit quantity, but the NIC 2941 * memory is 64-bit (and big-endian) internally. Addressing the 2942 * GENCOMM word as "the upper half of a 64-bit quantity" makes 2943 * it work correctly on both big- and little-endian hosts. 2944 */ 2945 for (i = 0; i < 1000; ++i) { 2946 drv_usecwait(1000); 2947 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 2948 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 2949 #ifdef BGE_IPMI_ASF 2950 if (!bgep->asf_enabled) { 2951 #endif 2952 if (gen != ~T3_MAGIC_NUMBER) 2953 continue; 2954 #ifdef BGE_IPMI_ASF 2955 } 2956 #endif 2957 if (mac != 0ULL) 2958 break; 2959 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 2960 break; 2961 } 2962 2963 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 2964 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 2965 (void *)bgep, gen, i)); 2966 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 2967 mac, magic)); 2968 2969 return (mac); 2970 } 2971 2972 /* 2973 * Maximum times of trying to get the NVRAM access lock 2974 * by calling bge_nvmem_acquire() 2975 */ 2976 #define MAX_TRY_NVMEM_ACQUIRE 10000 2977 2978 #ifdef BGE_IPMI_ASF 2979 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 2980 #else 2981 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 2982 #endif 2983 #pragma no_inline(bge_chip_reset) 2984 2985 int 2986 #ifdef BGE_IPMI_ASF 2987 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 2988 #else 2989 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 2990 #endif 2991 { 2992 chip_id_t chipid; 2993 uint64_t mac; 2994 uint64_t magic; 2995 uint32_t modeflags; 2996 uint32_t mhcr; 2997 uint32_t sx0; 2998 uint32_t i, tries; 2999 #ifdef BGE_IPMI_ASF 3000 uint32_t mailbox; 3001 #endif 3002 int retval = DDI_SUCCESS; 3003 3004 BGE_TRACE(("bge_chip_reset($%p, %d)", 3005 (void *)bgep, enable_dma)); 3006 3007 ASSERT(mutex_owned(bgep->genlock)); 3008 3009 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3010 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3011 3012 /* 3013 * Do we need to stop the chip cleanly before resetting? 3014 */ 3015 switch (bgep->bge_chip_state) { 3016 default: 3017 _NOTE(NOTREACHED) 3018 return (DDI_FAILURE); 3019 3020 case BGE_CHIP_INITIAL: 3021 case BGE_CHIP_STOPPED: 3022 case BGE_CHIP_RESET: 3023 break; 3024 3025 case BGE_CHIP_RUNNING: 3026 case BGE_CHIP_ERROR: 3027 case BGE_CHIP_FAULT: 3028 bge_chip_stop(bgep, B_FALSE); 3029 break; 3030 } 3031 3032 #ifdef BGE_IPMI_ASF 3033 if (bgep->asf_enabled) { 3034 if (asf_mode == ASF_MODE_INIT) { 3035 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3036 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3037 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3038 } 3039 } 3040 #endif 3041 /* 3042 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3043 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3044 * 3045 * Before reset Core clock,it is 3046 * also required to initialize the Memory Arbiter as specified in step9 3047 * and Misc Host Control Register as specified in step-13 3048 * Step 4-5: reset Core clock & wait for completion 3049 * Steps 6-8: are done by bge_chip_cfg_init() 3050 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3051 */ 3052 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3053 retval = DDI_FAILURE; 3054 3055 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3056 MHCR_ENABLE_TAGGED_STATUS_MODE | 3057 MHCR_MASK_INTERRUPT_MODE | 3058 MHCR_MASK_PCI_INT_OUTPUT | 3059 MHCR_CLEAR_INTERRUPT_INTA; 3060 #ifdef _BIG_ENDIAN 3061 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3062 #endif /* _BIG_ENDIAN */ 3063 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3064 #ifdef BGE_IPMI_ASF 3065 if (bgep->asf_enabled) 3066 bgep->asf_wordswapped = B_FALSE; 3067 #endif 3068 /* 3069 * NVRAM Corruption Workaround 3070 */ 3071 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3072 if (bge_nvmem_acquire(bgep) != EAGAIN) 3073 break; 3074 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3075 BGE_DEBUG(("%s: fail to acquire nvram lock", 3076 bgep->ifname)); 3077 3078 #ifdef BGE_IPMI_ASF 3079 if (!bgep->asf_enabled) { 3080 #endif 3081 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3082 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3083 #ifdef BGE_IPMI_ASF 3084 } 3085 #endif 3086 3087 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3088 retval = DDI_FAILURE; 3089 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3090 3091 /* 3092 * Step 8a: This may belong elsewhere, but BCM5721 needs 3093 * a bit set to avoid a fifo overflow/underflow bug. 3094 */ 3095 if ((bgep->chipid.chip_label == 5721) || 3096 (bgep->chipid.chip_label == 5751) || 3097 (bgep->chipid.chip_label == 5752) || 3098 (bgep->chipid.chip_label == 5789)) 3099 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3100 3101 3102 /* 3103 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3104 * not be changed. 3105 */ 3106 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3107 retval = DDI_FAILURE; 3108 3109 /* 3110 * Steps 10-11: configure PIO endianness options and 3111 * enable indirect register access -- already done 3112 * Steps 12-13: enable writing to the PCI state & clock 3113 * control registers -- not required; we aren't going to 3114 * use those features. 3115 * Steps 14-15: Configure DMA endianness options. See 3116 * the comments on the setting of the MHCR above. 3117 */ 3118 #ifdef _BIG_ENDIAN 3119 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3120 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3121 #else 3122 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3123 #endif /* _BIG_ENDIAN */ 3124 #ifdef BGE_IPMI_ASF 3125 if (bgep->asf_enabled) 3126 modeflags |= MODE_HOST_STACK_UP; 3127 #endif 3128 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3129 3130 #ifdef BGE_IPMI_ASF 3131 if (bgep->asf_enabled) { 3132 if (asf_mode != ASF_MODE_NONE) { 3133 /* Wait for NVRAM init */ 3134 i = 0; 3135 drv_usecwait(5000); 3136 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3137 while ((mailbox != (uint32_t) 3138 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3139 (i < 10000)) { 3140 drv_usecwait(100); 3141 mailbox = bge_nic_get32(bgep, 3142 BGE_FIRMWARE_MAILBOX); 3143 i++; 3144 } 3145 if (!bgep->asf_newhandshake) { 3146 if ((asf_mode == ASF_MODE_INIT) || 3147 (asf_mode == ASF_MODE_POST_INIT)) { 3148 3149 bge_asf_post_reset_old_mode(bgep, 3150 BGE_INIT_RESET); 3151 } else { 3152 bge_asf_post_reset_old_mode(bgep, 3153 BGE_SHUTDOWN_RESET); 3154 } 3155 } 3156 } 3157 } 3158 #endif 3159 /* 3160 * Steps 16-17: poll for firmware completion 3161 */ 3162 mac = bge_poll_firmware(bgep); 3163 3164 /* 3165 * Step 18: enable external memory -- doesn't apply. 3166 * 3167 * However we take the opportunity to set the MLCR anyway, as 3168 * this register also controls the SEEPROM auto-access method 3169 * which we may want to use later ... 3170 * 3171 * The proper value here depends on the way the chip is wired 3172 * into the circuit board, as this register *also* controls which 3173 * of the "Miscellaneous I/O" pins are driven as outputs and the 3174 * values driven onto those pins! 3175 * 3176 * See also step 74 in the PRM ... 3177 */ 3178 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3179 bgep->chipid.bge_mlcr_default); 3180 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3181 3182 /* 3183 * Step 20: clear the Ethernet MAC mode register 3184 */ 3185 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3186 3187 /* 3188 * Step 21: restore cache-line-size, latency timer, and 3189 * subsystem ID registers to their original values (not 3190 * those read into the local structure <chipid>, 'cos 3191 * that was after they were cleared by the RESET). 3192 * 3193 * Note: the Subsystem Vendor/Device ID registers are not 3194 * directly writable in config space, so we use the shadow 3195 * copy in "Page Zero" of register space to restore them 3196 * both in one go ... 3197 */ 3198 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3199 bgep->chipid.clsize); 3200 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3201 bgep->chipid.latency); 3202 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3203 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3204 3205 /* 3206 * The SEND INDEX registers should be reset to zero by the 3207 * global chip reset; if they're not, there'll be trouble 3208 * later on. 3209 */ 3210 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3211 if (sx0 != 0) { 3212 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3213 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3214 retval = DDI_FAILURE; 3215 } 3216 3217 /* Enable MSI code */ 3218 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3219 bge_reg_set32(bgep, MSI_MODE_REG, 3220 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3221 3222 /* 3223 * On the first time through, save the factory-set MAC address 3224 * (if any). If bge_poll_firmware() above didn't return one 3225 * (from a chip register) consider looking in the attached NV 3226 * memory device, if any. Once we have it, we save it in both 3227 * register-image (64-bit) and byte-array forms. All-zero and 3228 * all-one addresses are not valid, and we refuse to stash those. 3229 */ 3230 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3231 if (mac == 0ULL) 3232 mac = bge_get_nvmac(bgep); 3233 if (mac != 0ULL && mac != ~0ULL) { 3234 bgep->chipid.hw_mac_addr = mac; 3235 for (i = ETHERADDRL; i-- != 0; ) { 3236 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3237 mac >>= 8; 3238 } 3239 bgep->chipid.vendor_addr.set = B_TRUE; 3240 } 3241 } 3242 3243 #ifdef BGE_IPMI_ASF 3244 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3245 if (asf_mode != ASF_MODE_NONE) { 3246 if ((asf_mode == ASF_MODE_INIT) || 3247 (asf_mode == ASF_MODE_POST_INIT)) { 3248 3249 bge_asf_post_reset_new_mode(bgep, 3250 BGE_INIT_RESET); 3251 } else { 3252 bge_asf_post_reset_new_mode(bgep, 3253 BGE_SHUTDOWN_RESET); 3254 } 3255 } 3256 } 3257 #endif 3258 3259 /* 3260 * Record the new state 3261 */ 3262 bgep->chip_resets += 1; 3263 bgep->bge_chip_state = BGE_CHIP_RESET; 3264 return (retval); 3265 } 3266 3267 /* 3268 * bge_chip_start() -- start the chip transmitting and/or receiving, 3269 * including enabling interrupts 3270 */ 3271 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3272 #pragma no_inline(bge_chip_start) 3273 3274 int 3275 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3276 { 3277 uint32_t coalmode; 3278 uint32_t ledctl; 3279 uint32_t mtu; 3280 uint32_t maxring; 3281 uint32_t stats_mask; 3282 uint64_t ring; 3283 int retval = DDI_SUCCESS; 3284 3285 BGE_TRACE(("bge_chip_start($%p)", 3286 (void *)bgep)); 3287 3288 ASSERT(mutex_owned(bgep->genlock)); 3289 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3290 3291 /* 3292 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3293 * The document specifies 95 separate steps to fully 3294 * initialise the chip!!!! 3295 * 3296 * The reset code above has already got us as far as step 3297 * 21, so we continue with ... 3298 * 3299 * Step 22: clear the MAC statistics block 3300 * (0x0300-0x0aff in NIC-local memory) 3301 */ 3302 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3303 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3304 NIC_MEM_STATISTICS_SIZE); 3305 3306 /* 3307 * Step 23: clear the status block (in host memory) 3308 */ 3309 DMA_ZERO(bgep->status_block); 3310 3311 /* 3312 * Step 24: set DMA read/write control register 3313 */ 3314 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3315 bgep->chipid.bge_dma_rwctrl); 3316 3317 /* 3318 * Step 25: Configure DMA endianness -- already done (16/17) 3319 * Step 26: Configure Host-Based Send Rings 3320 * Step 27: Indicate Host Stack Up 3321 */ 3322 bge_reg_set32(bgep, MODE_CONTROL_REG, 3323 MODE_HOST_SEND_BDS | 3324 MODE_HOST_STACK_UP); 3325 3326 /* 3327 * Step 28: Configure checksum options: 3328 * Solaris supports the hardware default checksum options. 3329 * 3330 * Workaround for Incorrect pseudo-header checksum calculation. 3331 */ 3332 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3333 bge_reg_set32(bgep, MODE_CONTROL_REG, 3334 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3335 3336 /* 3337 * Step 29: configure Timer Prescaler. The value is always the 3338 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3339 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3340 * for the whole chip! 3341 */ 3342 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3343 3344 /* 3345 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3346 * 3347 * If the mbuf_length is specified as 0, we just leave these at 3348 * their hardware defaults, rather than explicitly setting them. 3349 * As the Broadcom HRM,driver better not change the parameters 3350 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3351 */ 3352 if ((bgep->chipid.mbuf_length != 0) && 3353 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3354 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3355 bgep->chipid.mbuf_base); 3356 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3357 bgep->chipid.mbuf_length); 3358 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3359 DMAD_POOL_BASE_DEFAULT); 3360 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3361 DMAD_POOL_LENGTH_DEFAULT); 3362 } 3363 3364 /* 3365 * Step 32: configure MAC memory pool watermarks 3366 */ 3367 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3368 bgep->chipid.mbuf_lo_water_rdma); 3369 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3370 bgep->chipid.mbuf_lo_water_rmac); 3371 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3372 bgep->chipid.mbuf_hi_water); 3373 3374 /* 3375 * Step 33: configure DMA resource watermarks 3376 */ 3377 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3378 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3379 bge_dmad_lo_water); 3380 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3381 bge_dmad_hi_water); 3382 } 3383 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3384 3385 /* 3386 * Steps 34-36: enable buffer manager & internal h/w queues 3387 */ 3388 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3389 STATE_MACHINE_ATTN_ENABLE_BIT)) 3390 retval = DDI_FAILURE; 3391 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3392 retval = DDI_FAILURE; 3393 3394 /* 3395 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3396 */ 3397 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3398 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3399 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3400 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3401 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3402 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3403 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3404 } 3405 3406 /* 3407 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3408 */ 3409 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3410 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3411 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3412 bge_replenish_jumbo); 3413 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3414 bge_replenish_mini); 3415 } 3416 3417 /* 3418 * Steps 41-43: clear Send Ring Producer Indices and initialise 3419 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3420 */ 3421 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3422 maxring = BGE_SEND_RINGS_MAX; 3423 else 3424 maxring = BGE_SEND_RINGS_MAX_5705; 3425 for (ring = 0; ring < maxring; ++ring) { 3426 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3427 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3428 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3429 &bgep->send[ring].hw_rcb); 3430 } 3431 3432 /* 3433 * Steps 44-45: initialise Receive Return Rings 3434 * (0x0200-0x02ff in NIC-local memory) 3435 */ 3436 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3437 maxring = BGE_RECV_RINGS_MAX; 3438 else 3439 maxring = BGE_RECV_RINGS_MAX_5705; 3440 for (ring = 0; ring < maxring; ++ring) 3441 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3442 &bgep->recv[ring].hw_rcb); 3443 3444 /* 3445 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3446 */ 3447 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3448 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3449 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3450 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3451 } 3452 /* 3453 * Step 47: configure the MAC unicast address 3454 * Step 48: configure the random backoff seed 3455 * Step 96: set up multicast filters 3456 */ 3457 #ifdef BGE_IPMI_ASF 3458 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3459 #else 3460 if (bge_chip_sync(bgep) == DDI_FAILURE) 3461 #endif 3462 retval = DDI_FAILURE; 3463 3464 /* 3465 * Step 49: configure the MTU 3466 */ 3467 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3468 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3469 3470 /* 3471 * Step 50: configure the IPG et al 3472 */ 3473 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3474 3475 /* 3476 * Step 51: configure the default Rx Return Ring 3477 */ 3478 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3479 3480 /* 3481 * Steps 52-54: configure Receive List Placement, 3482 * and enable Receive List Placement Statistics 3483 */ 3484 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3485 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3486 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3487 case MHCR_CHIP_ASIC_REV_5700: 3488 case MHCR_CHIP_ASIC_REV_5701: 3489 case MHCR_CHIP_ASIC_REV_5703: 3490 case MHCR_CHIP_ASIC_REV_5704: 3491 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3492 break; 3493 case MHCR_CHIP_ASIC_REV_5705: 3494 break; 3495 default: 3496 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3497 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3498 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3499 break; 3500 } 3501 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3502 3503 if (bgep->chipid.rx_rings > 1) 3504 bge_init_recv_rule(bgep); 3505 3506 /* 3507 * Steps 55-56: enable Send Data Initiator Statistics 3508 */ 3509 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3510 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3511 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3512 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3513 } else { 3514 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3515 SEND_INIT_STATS_ENABLE); 3516 } 3517 /* 3518 * Steps 57-58: stop (?) the Host Coalescing Engine 3519 */ 3520 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3521 retval = DDI_FAILURE; 3522 3523 /* 3524 * Steps 59-62: initialise Host Coalescing parameters 3525 */ 3526 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3527 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3528 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3529 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3530 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3531 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3532 bge_tx_count_intr); 3533 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3534 bge_tx_ticks_intr); 3535 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3536 bge_rx_count_intr); 3537 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3538 bge_rx_ticks_intr); 3539 } 3540 3541 /* 3542 * Steps 63-64: initialise status block & statistics 3543 * host memory addresses 3544 * The statistic block does not exist in some chipsets 3545 * Step 65: initialise Statistics Coalescing Tick Counter 3546 */ 3547 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3548 bgep->status_block.cookie.dmac_laddress); 3549 3550 /* 3551 * Steps 66-67: initialise status block & statistics 3552 * NIC-local memory addresses 3553 */ 3554 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3555 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3556 bgep->statistics.cookie.dmac_laddress); 3557 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3558 STATISTICS_TICKS_DEFAULT); 3559 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3560 NIC_MEM_STATUS_BLOCK); 3561 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3562 NIC_MEM_STATISTICS); 3563 } 3564 3565 /* 3566 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3567 * Completion Engine, the Receive List Placement Engine, and the 3568 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3569 * and BCM5715. 3570 */ 3571 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3572 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3573 coalmode = COALESCE_64_BYTE_STATUS; 3574 else 3575 coalmode = 0; 3576 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3577 retval = DDI_FAILURE; 3578 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3579 STATE_MACHINE_ATTN_ENABLE_BIT)) 3580 retval = DDI_FAILURE; 3581 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3582 retval = DDI_FAILURE; 3583 3584 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3585 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3586 STATE_MACHINE_ATTN_ENABLE_BIT)) 3587 retval = DDI_FAILURE; 3588 3589 /* 3590 * Step 72: Enable MAC DMA engines 3591 * Step 73: Clear & enable MAC statistics 3592 */ 3593 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3594 ETHERNET_MODE_ENABLE_FHDE | 3595 ETHERNET_MODE_ENABLE_RDE | 3596 ETHERNET_MODE_ENABLE_TDE); 3597 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3598 ETHERNET_MODE_ENABLE_TX_STATS | 3599 ETHERNET_MODE_ENABLE_RX_STATS | 3600 ETHERNET_MODE_CLEAR_TX_STATS | 3601 ETHERNET_MODE_CLEAR_RX_STATS); 3602 3603 /* 3604 * Step 74: configure the MLCR (Miscellaneous Local Control 3605 * Register); not required, as we set up the MLCR in step 10 3606 * (part of the reset code) above. 3607 * 3608 * Step 75: clear Interrupt Mailbox 0 3609 */ 3610 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3611 3612 /* 3613 * Steps 76-87: Gentlemen, start your engines ... 3614 * 3615 * Enable the DMA Completion Engine, the Write DMA Engine, 3616 * the Read DMA Engine, Receive Data Completion Engine, 3617 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3618 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3619 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3620 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3621 * 3622 * Beware exhaust fumes? 3623 */ 3624 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3625 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3626 retval = DDI_FAILURE; 3627 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3628 (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3629 retval = DDI_FAILURE; 3630 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3631 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3632 retval = DDI_FAILURE; 3633 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3634 STATE_MACHINE_ATTN_ENABLE_BIT)) 3635 retval = DDI_FAILURE; 3636 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3637 if (!bge_chip_enable_engine(bgep, 3638 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3639 retval = DDI_FAILURE; 3640 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3641 retval = DDI_FAILURE; 3642 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3643 STATE_MACHINE_ATTN_ENABLE_BIT)) 3644 retval = DDI_FAILURE; 3645 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3646 RCV_BD_DISABLED_RING_ATTN)) 3647 retval = DDI_FAILURE; 3648 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3649 RCV_DATA_BD_ILL_RING_ATTN)) 3650 retval = DDI_FAILURE; 3651 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3652 retval = DDI_FAILURE; 3653 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3654 STATE_MACHINE_ATTN_ENABLE_BIT)) 3655 retval = DDI_FAILURE; 3656 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3657 STATE_MACHINE_ATTN_ENABLE_BIT)) 3658 retval = DDI_FAILURE; 3659 3660 /* 3661 * Step 88: download firmware -- doesn't apply 3662 * Steps 89-90: enable Transmit & Receive MAC Engines 3663 */ 3664 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3665 retval = DDI_FAILURE; 3666 #ifdef BGE_IPMI_ASF 3667 if (!bgep->asf_enabled) { 3668 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3669 RECEIVE_MODE_KEEP_VLAN_TAG)) 3670 retval = DDI_FAILURE; 3671 } else { 3672 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3673 retval = DDI_FAILURE; 3674 } 3675 #else 3676 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3677 RECEIVE_MODE_KEEP_VLAN_TAG)) 3678 retval = DDI_FAILURE; 3679 #endif 3680 3681 /* 3682 * Step 91: disable auto-polling of PHY status 3683 */ 3684 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3685 3686 /* 3687 * Step 92: configure D0 power state (not required) 3688 * Step 93: initialise LED control register () 3689 */ 3690 ledctl = LED_CONTROL_DEFAULT; 3691 switch (bgep->chipid.device) { 3692 case DEVICE_ID_5700: 3693 case DEVICE_ID_5700x: 3694 case DEVICE_ID_5701: 3695 /* 3696 * Switch to 5700 (MAC) mode on these older chips 3697 */ 3698 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 3699 ledctl |= LED_CONTROL_LED_MODE_5700; 3700 break; 3701 3702 default: 3703 break; 3704 } 3705 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 3706 3707 /* 3708 * Step 94: activate link 3709 */ 3710 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3711 3712 /* 3713 * Step 95: set up physical layer (PHY/SerDes) 3714 * restart autoneg (if required) 3715 */ 3716 if (reset_phys) 3717 if (bge_phys_update(bgep) == DDI_FAILURE) 3718 retval = DDI_FAILURE; 3719 3720 /* 3721 * Extra step (DSG): hand over all the Receive Buffers to the chip 3722 */ 3723 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 3724 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 3725 bgep->buff[ring].rf_next); 3726 3727 /* 3728 * MSI bits:The least significant MSI 16-bit word. 3729 * ISR will be triggered different. 3730 */ 3731 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3732 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 3733 3734 /* 3735 * Extra step (DSG): select which interrupts are enabled 3736 * 3737 * Program the Ethernet MAC engine to signal attention on 3738 * Link Change events, then enable interrupts on MAC, DMA, 3739 * and FLOW attention signals. 3740 */ 3741 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 3742 ETHERNET_EVENT_LINK_INT | 3743 ETHERNET_STATUS_PCS_ERROR_INT); 3744 #ifdef BGE_IPMI_ASF 3745 if (bgep->asf_enabled) { 3746 bge_reg_set32(bgep, MODE_CONTROL_REG, 3747 MODE_INT_ON_FLOW_ATTN | 3748 MODE_INT_ON_DMA_ATTN | 3749 MODE_HOST_STACK_UP| 3750 MODE_INT_ON_MAC_ATTN); 3751 } else { 3752 #endif 3753 bge_reg_set32(bgep, MODE_CONTROL_REG, 3754 MODE_INT_ON_FLOW_ATTN | 3755 MODE_INT_ON_DMA_ATTN | 3756 MODE_INT_ON_MAC_ATTN); 3757 #ifdef BGE_IPMI_ASF 3758 } 3759 #endif 3760 3761 /* 3762 * Step 97: enable PCI interrupts!!! 3763 */ 3764 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3765 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3766 MHCR_MASK_PCI_INT_OUTPUT); 3767 3768 /* 3769 * All done! 3770 */ 3771 bgep->bge_chip_state = BGE_CHIP_RUNNING; 3772 return (retval); 3773 } 3774 3775 3776 /* 3777 * ========== Hardware interrupt handler ========== 3778 */ 3779 3780 #undef BGE_DBG 3781 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 3782 3783 /* 3784 * Sync the status block, then atomically clear the specified bits in 3785 * the <flags-and-tag> field of the status block. 3786 * the <flags> word of the status block, returning the value of the 3787 * <tag> and the <flags> before the bits were cleared. 3788 */ 3789 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 3790 #pragma inline(bge_status_sync) 3791 3792 static int 3793 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 3794 { 3795 bge_status_t *bsp; 3796 int retval; 3797 3798 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 3799 (void *)bgep, bits)); 3800 3801 ASSERT(bgep->bge_guard == BGE_GUARD); 3802 3803 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 3804 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 3805 if (retval != DDI_FM_OK) 3806 return (retval); 3807 3808 bsp = DMA_VPTR(bgep->status_block); 3809 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 3810 3811 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 3812 (void *)bgep, bits, *flags)); 3813 3814 return (retval); 3815 } 3816 3817 static void bge_wake_factotum(bge_t *bgep); 3818 #pragma inline(bge_wake_factotum) 3819 3820 static void 3821 bge_wake_factotum(bge_t *bgep) 3822 { 3823 mutex_enter(bgep->softintrlock); 3824 if (bgep->factotum_flag == 0) { 3825 bgep->factotum_flag = 1; 3826 ddi_trigger_softintr(bgep->factotum_id); 3827 } 3828 mutex_exit(bgep->softintrlock); 3829 } 3830 3831 /* 3832 * bge_intr() -- handle chip interrupts 3833 */ 3834 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 3835 #pragma no_inline(bge_intr) 3836 3837 uint_t 3838 bge_intr(caddr_t arg1, caddr_t arg2) 3839 { 3840 bge_t *bgep = (bge_t *)arg1; /* private device info */ 3841 bge_status_t *bsp; 3842 uint64_t flags; 3843 uint32_t regval; 3844 uint_t result; 3845 int retval; 3846 3847 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 3848 3849 /* 3850 * GLD v2 checks that s/w setup is complete before passing 3851 * interrupts to this routine, thus eliminating the old 3852 * (and well-known) race condition around ddi_add_intr() 3853 */ 3854 ASSERT(bgep->progress & PROGRESS_HWINT); 3855 3856 result = DDI_INTR_UNCLAIMED; 3857 mutex_enter(bgep->genlock); 3858 3859 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 3860 /* 3861 * Check whether chip's says it's asserting #INTA; 3862 * if not, don't process or claim the interrupt. 3863 * 3864 * Note that the PCI signal is active low, so the 3865 * bit is *zero* when the interrupt is asserted. 3866 */ 3867 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 3868 if (regval & MLCR_INTA_STATE) { 3869 if (bge_check_acc_handle(bgep, bgep->io_handle) 3870 != DDI_FM_OK) 3871 goto chip_stop; 3872 mutex_exit(bgep->genlock); 3873 return (result); 3874 } 3875 3876 /* 3877 * Block further PCI interrupts ... 3878 */ 3879 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 3880 MHCR_MASK_PCI_INT_OUTPUT); 3881 3882 } else { 3883 /* 3884 * Check MSI status 3885 */ 3886 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 3887 if (regval & MSI_ERROR_ATTENTION) { 3888 BGE_REPORT((bgep, "msi error attention," 3889 " status=0x%x", regval)); 3890 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 3891 } 3892 } 3893 3894 result = DDI_INTR_CLAIMED; 3895 3896 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 3897 3898 /* 3899 * Sync the status block and grab the flags-n-tag from it. 3900 * We count the number of interrupts where there doesn't 3901 * seem to have been a DMA update of the status block; if 3902 * it *has* been updated, the counter will be cleared in 3903 * the while() loop below ... 3904 */ 3905 bgep->missed_dmas += 1; 3906 bsp = DMA_VPTR(bgep->status_block); 3907 for (;;) { 3908 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 3909 /* 3910 * bge_chip_stop() may have freed dma area etc 3911 * while we were in this interrupt handler - 3912 * better not call bge_status_sync() 3913 */ 3914 (void) bge_check_acc_handle(bgep, 3915 bgep->io_handle); 3916 mutex_exit(bgep->genlock); 3917 return (DDI_INTR_CLAIMED); 3918 } 3919 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 3920 &flags); 3921 if (retval != DDI_FM_OK) { 3922 bgep->bge_dma_error = B_TRUE; 3923 goto chip_stop; 3924 } 3925 3926 if (!(flags & STATUS_FLAG_UPDATED)) 3927 break; 3928 3929 /* 3930 * Tell the chip that we're processing the interrupt 3931 */ 3932 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 3933 INTERRUPT_MBOX_DISABLE(flags)); 3934 if (bge_check_acc_handle(bgep, bgep->io_handle) != 3935 DDI_FM_OK) 3936 goto chip_stop; 3937 3938 /* 3939 * Drop the mutex while we: 3940 * Receive any newly-arrived packets 3941 * Recycle any newly-finished send buffers 3942 */ 3943 bgep->bge_intr_running = B_TRUE; 3944 mutex_exit(bgep->genlock); 3945 bge_receive(bgep, bsp); 3946 bge_recycle(bgep, bsp); 3947 mutex_enter(bgep->genlock); 3948 bgep->bge_intr_running = B_FALSE; 3949 3950 /* 3951 * Tell the chip we've finished processing, and 3952 * give it the tag that we got from the status 3953 * block earlier, so that it knows just how far 3954 * we've gone. If it's got more for us to do, 3955 * it will now update the status block and try 3956 * to assert an interrupt (but we've got the 3957 * #INTA blocked at present). If we see the 3958 * update, we'll loop around to do some more. 3959 * Eventually we'll get out of here ... 3960 */ 3961 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 3962 INTERRUPT_MBOX_ENABLE(flags)); 3963 bgep->missed_dmas = 0; 3964 } 3965 3966 /* 3967 * Check for exceptional conditions that we need to handle 3968 * 3969 * Link status changed 3970 * Status block not updated 3971 */ 3972 if (flags & STATUS_FLAG_LINK_CHANGED) 3973 bge_wake_factotum(bgep); 3974 3975 if (bgep->missed_dmas) { 3976 /* 3977 * Probably due to the internal status tag not 3978 * being reset. Force a status block update now; 3979 * this should ensure that we get an update and 3980 * a new interrupt. After that, we should be in 3981 * sync again ... 3982 */ 3983 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 3984 "not updated?", flags)); 3985 bgep->missed_updates++; 3986 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 3987 COALESCE_NOW); 3988 3989 if (bgep->missed_dmas >= bge_dma_miss_limit) { 3990 /* 3991 * If this happens multiple times in a row, 3992 * it means DMA is just not working. Maybe 3993 * the chip's failed, or maybe there's a 3994 * problem on the PCI bus or in the host-PCI 3995 * bridge (Tomatillo). 3996 * 3997 * At all events, we want to stop further 3998 * interrupts and let the recovery code take 3999 * over to see whether anything can be done 4000 * about it ... 4001 */ 4002 bge_fm_ereport(bgep, 4003 DDI_FM_DEVICE_BADINT_LIMIT); 4004 goto chip_stop; 4005 } 4006 } 4007 4008 /* 4009 * Reenable assertion of #INTA, unless there's a DMA fault 4010 */ 4011 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4012 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4013 MHCR_MASK_PCI_INT_OUTPUT); 4014 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4015 DDI_FM_OK) 4016 goto chip_stop; 4017 } 4018 4019 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4020 goto chip_stop; 4021 4022 mutex_exit(bgep->genlock); 4023 return (result); 4024 4025 chip_stop: 4026 #ifdef BGE_IPMI_ASF 4027 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4028 /* 4029 * We must stop ASF heart beat before 4030 * bge_chip_stop(), otherwise some 4031 * computers (ex. IBM HS20 blade 4032 * server) may crash. 4033 */ 4034 bge_asf_update_status(bgep); 4035 bge_asf_stop_timer(bgep); 4036 bgep->asf_status = ASF_STAT_STOP; 4037 4038 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4039 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4040 } 4041 #endif 4042 bge_chip_stop(bgep, B_TRUE); 4043 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4044 mutex_exit(bgep->genlock); 4045 return (result); 4046 } 4047 4048 /* 4049 * ========== Factotum, implemented as a softint handler ========== 4050 */ 4051 4052 #undef BGE_DBG 4053 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4054 4055 static void bge_factotum_error_handler(bge_t *bgep); 4056 #pragma no_inline(bge_factotum_error_handler) 4057 4058 static void 4059 bge_factotum_error_handler(bge_t *bgep) 4060 { 4061 uint32_t flow; 4062 uint32_t rdma; 4063 uint32_t wdma; 4064 uint32_t tmac; 4065 uint32_t rmac; 4066 uint32_t rxrs; 4067 uint32_t txrs = 0; 4068 4069 ASSERT(mutex_owned(bgep->genlock)); 4070 4071 /* 4072 * Read all the registers that show the possible 4073 * reasons for the ERROR bit to be asserted 4074 */ 4075 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4076 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4077 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4078 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4079 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4080 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4081 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4082 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4083 4084 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4085 (void *)bgep, flow, rdma, wdma)); 4086 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4087 (void *)bgep, tmac, rmac, rxrs, txrs)); 4088 4089 /* 4090 * For now, just clear all the errors ... 4091 */ 4092 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4093 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4094 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4095 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4096 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4097 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4098 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4099 } 4100 4101 /* 4102 * Handler for hardware link state change. 4103 * 4104 * When this routine is called, the hardware link state has changed 4105 * and the new state is reflected in the param_* variables. Here 4106 * we must update the softstate, reprogram the MAC to match, and 4107 * record the change in the log and/or on the console. 4108 */ 4109 static void bge_factotum_link_handler(bge_t *bgep); 4110 #pragma no_inline(bge_factotum_link_handler) 4111 4112 static void 4113 bge_factotum_link_handler(bge_t *bgep) 4114 { 4115 void (*logfn)(bge_t *bgep, const char *fmt, ...); 4116 const char *msg; 4117 hrtime_t deltat; 4118 4119 ASSERT(mutex_owned(bgep->genlock)); 4120 4121 /* 4122 * Update the s/w link_state 4123 */ 4124 if (bgep->param_link_up) 4125 bgep->link_state = LINK_STATE_UP; 4126 else 4127 bgep->link_state = LINK_STATE_DOWN; 4128 4129 /* 4130 * Reprogram the MAC modes to match 4131 */ 4132 bge_sync_mac_modes(bgep); 4133 4134 /* 4135 * Finally, we have to decide whether to write a message 4136 * on the console or only in the log. If the PHY has 4137 * been reprogrammed (at user request) "recently", then 4138 * the message only goes in the log. Otherwise it's an 4139 * "unexpected" event, and it goes on the console as well. 4140 */ 4141 deltat = bgep->phys_event_time - bgep->phys_write_time; 4142 if (deltat > BGE_LINK_SETTLE_TIME) 4143 msg = ""; 4144 else if (bgep->param_link_up) 4145 msg = bgep->link_up_msg; 4146 else 4147 msg = bgep->link_down_msg; 4148 4149 logfn = (msg == NULL || *msg == '\0') ? bge_notice : bge_log; 4150 (*logfn)(bgep, "link %s%s", bgep->link_mode_msg, msg); 4151 } 4152 4153 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4154 #pragma no_inline(bge_factotum_link_check) 4155 4156 static boolean_t 4157 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4158 { 4159 boolean_t check; 4160 uint64_t flags; 4161 uint32_t tmac_status; 4162 4163 ASSERT(mutex_owned(bgep->genlock)); 4164 4165 /* 4166 * Get & clear the writable status bits in the Tx status register 4167 * (some bits are write-1-to-clear, others are just readonly). 4168 */ 4169 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4170 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4171 4172 /* 4173 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4174 */ 4175 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4176 STATUS_FLAG_LINK_CHANGED, &flags); 4177 if (*dma_state != DDI_FM_OK) 4178 return (B_FALSE); 4179 4180 /* 4181 * Clear any errors flagged in the status block ... 4182 */ 4183 if (flags & STATUS_FLAG_ERROR) 4184 bge_factotum_error_handler(bgep); 4185 4186 /* 4187 * We need to check the link status if: 4188 * the status block says there's been a link change 4189 * or there's any discrepancy between the various 4190 * flags indicating the link state (link_state, 4191 * param_link_up, and the LINK STATE bit in the 4192 * Transmit MAC status register). 4193 */ 4194 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4195 switch (bgep->link_state) { 4196 case LINK_STATE_UP: 4197 check |= (bgep->param_link_up == B_FALSE); 4198 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4199 break; 4200 4201 case LINK_STATE_DOWN: 4202 check |= (bgep->param_link_up != B_FALSE); 4203 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4204 break; 4205 4206 default: 4207 check = B_TRUE; 4208 break; 4209 } 4210 4211 /* 4212 * If <check> is false, we're sure the link hasn't changed. 4213 * If true, however, it's not yet definitive; we have to call 4214 * bge_phys_check() to determine whether the link has settled 4215 * into a new state yet ... and if it has, then call the link 4216 * state change handler.But when the chip is 5700 in Dell 6650 4217 * ,even if check is false, the link may have changed.So we 4218 * have to call bge_phys_check() to determine the link state. 4219 */ 4220 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4221 check = bge_phys_check(bgep); 4222 if (check) 4223 bge_factotum_link_handler(bgep); 4224 } 4225 4226 return (check); 4227 } 4228 4229 /* 4230 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4231 */ 4232 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4233 #pragma no_inline(bge_factotum_stall_check) 4234 4235 static boolean_t 4236 bge_factotum_stall_check(bge_t *bgep) 4237 { 4238 uint32_t dogval; 4239 4240 ASSERT(mutex_owned(bgep->genlock)); 4241 4242 /* 4243 * Specific check for Tx stall ... 4244 * 4245 * The 'watchdog' counter is incremented whenever a packet 4246 * is queued, reset to 1 when some (but not all) buffers 4247 * are reclaimed, reset to 0 (disabled) when all buffers 4248 * are reclaimed, and shifted left here. If it exceeds the 4249 * threshold value, the chip is assumed to have stalled and 4250 * is put into the ERROR state. The factotum will then reset 4251 * it on the next pass. 4252 * 4253 * All of which should ensure that we don't get into a state 4254 * where packets are left pending indefinitely! 4255 */ 4256 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4257 if (dogval < bge_watchdog_count) 4258 return (B_FALSE); 4259 4260 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4261 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4262 return (B_TRUE); 4263 } 4264 4265 /* 4266 * The factotum is woken up when there's something to do that we'd rather 4267 * not do from inside a hardware interrupt handler or high-level cyclic. 4268 * Its two main tasks are: 4269 * reset & restart the chip after an error 4270 * check the link status whenever necessary 4271 */ 4272 uint_t bge_chip_factotum(caddr_t arg); 4273 #pragma no_inline(bge_chip_factotum) 4274 4275 uint_t 4276 bge_chip_factotum(caddr_t arg) 4277 { 4278 bge_t *bgep; 4279 uint_t result; 4280 boolean_t error; 4281 boolean_t linkchg; 4282 int dma_state; 4283 4284 bgep = (bge_t *)arg; 4285 4286 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4287 4288 mutex_enter(bgep->softintrlock); 4289 if (bgep->factotum_flag == 0) { 4290 mutex_exit(bgep->softintrlock); 4291 return (DDI_INTR_UNCLAIMED); 4292 } 4293 bgep->factotum_flag = 0; 4294 mutex_exit(bgep->softintrlock); 4295 4296 result = DDI_INTR_CLAIMED; 4297 error = B_FALSE; 4298 linkchg = B_FALSE; 4299 4300 mutex_enter(bgep->genlock); 4301 switch (bgep->bge_chip_state) { 4302 default: 4303 break; 4304 4305 case BGE_CHIP_RUNNING: 4306 linkchg = bge_factotum_link_check(bgep, &dma_state); 4307 error = bge_factotum_stall_check(bgep); 4308 if (dma_state != DDI_FM_OK) { 4309 bgep->bge_dma_error = B_TRUE; 4310 error = B_TRUE; 4311 } 4312 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4313 error = B_TRUE; 4314 if (error) 4315 bgep->bge_chip_state = BGE_CHIP_ERROR; 4316 break; 4317 4318 case BGE_CHIP_ERROR: 4319 error = B_TRUE; 4320 break; 4321 4322 case BGE_CHIP_FAULT: 4323 /* 4324 * Fault detected, time to reset ... 4325 */ 4326 if (bge_autorecover) { 4327 if (!(bgep->progress & PROGRESS_BUFS)) { 4328 /* 4329 * if we can't allocate the ring buffers, 4330 * try later 4331 */ 4332 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4333 mutex_exit(bgep->genlock); 4334 return (result); 4335 } 4336 bgep->progress |= PROGRESS_BUFS; 4337 } 4338 if (!(bgep->progress & PROGRESS_INTR)) { 4339 bge_init_rings(bgep); 4340 bge_intr_enable(bgep); 4341 bgep->progress |= PROGRESS_INTR; 4342 } 4343 if (!(bgep->progress & PROGRESS_KSTATS)) { 4344 bge_init_kstats(bgep, 4345 ddi_get_instance(bgep->devinfo)); 4346 bgep->progress |= PROGRESS_KSTATS; 4347 } 4348 4349 BGE_REPORT((bgep, "automatic recovery activated")); 4350 4351 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4352 bgep->bge_chip_state = BGE_CHIP_ERROR; 4353 error = B_TRUE; 4354 } 4355 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4356 DDI_FM_OK) { 4357 bgep->bge_chip_state = BGE_CHIP_ERROR; 4358 error = B_TRUE; 4359 } 4360 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4361 DDI_FM_OK) { 4362 bgep->bge_chip_state = BGE_CHIP_ERROR; 4363 error = B_TRUE; 4364 } 4365 if (error == B_FALSE) { 4366 #ifdef BGE_IPMI_ASF 4367 if (bgep->asf_enabled && 4368 bgep->asf_status != ASF_STAT_RUN) { 4369 bgep->asf_timeout_id = timeout( 4370 bge_asf_heartbeat, (void *)bgep, 4371 drv_usectohz( 4372 BGE_ASF_HEARTBEAT_INTERVAL)); 4373 bgep->asf_status = ASF_STAT_RUN; 4374 } 4375 #endif 4376 ddi_fm_service_impact(bgep->devinfo, 4377 DDI_SERVICE_RESTORED); 4378 } 4379 } 4380 break; 4381 } 4382 4383 4384 /* 4385 * If an error is detected, stop the chip now, marking it as 4386 * faulty, so that it will be reset next time through ... 4387 * 4388 * Note that if intr_running is set, then bge_intr() has dropped 4389 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4390 * this point so have to wait until the next time the factotum runs. 4391 */ 4392 if (error && !bgep->bge_intr_running) { 4393 #ifdef BGE_IPMI_ASF 4394 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4395 /* 4396 * We must stop ASF heart beat before bge_chip_stop(), 4397 * otherwise some computers (ex. IBM HS20 blade server) 4398 * may crash. 4399 */ 4400 bge_asf_update_status(bgep); 4401 bge_asf_stop_timer(bgep); 4402 bgep->asf_status = ASF_STAT_STOP; 4403 4404 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4405 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4406 } 4407 #endif 4408 bge_chip_stop(bgep, B_TRUE); 4409 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4410 } 4411 mutex_exit(bgep->genlock); 4412 4413 /* 4414 * If the link state changed, tell the world about it. 4415 * Note: can't do this while still holding the mutex. 4416 */ 4417 if (linkchg) 4418 mac_link_update(bgep->mh, bgep->link_state); 4419 4420 return (result); 4421 } 4422 4423 /* 4424 * High-level cyclic handler 4425 * 4426 * This routine schedules a (low-level) softint callback to the 4427 * factotum, and prods the chip to update the status block (which 4428 * will cause a hardware interrupt when complete). 4429 */ 4430 void bge_chip_cyclic(void *arg); 4431 #pragma no_inline(bge_chip_cyclic) 4432 4433 void 4434 bge_chip_cyclic(void *arg) 4435 { 4436 bge_t *bgep; 4437 4438 bgep = arg; 4439 4440 switch (bgep->bge_chip_state) { 4441 default: 4442 return; 4443 4444 case BGE_CHIP_RUNNING: 4445 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4446 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4447 ddi_fm_service_impact(bgep->devinfo, 4448 DDI_SERVICE_UNAFFECTED); 4449 break; 4450 4451 case BGE_CHIP_FAULT: 4452 case BGE_CHIP_ERROR: 4453 break; 4454 } 4455 4456 bge_wake_factotum(bgep); 4457 } 4458 4459 4460 /* 4461 * ========== Ioctl subfunctions ========== 4462 */ 4463 4464 #undef BGE_DBG 4465 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4466 4467 #if BGE_DEBUGGING || BGE_DO_PPIO 4468 4469 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4470 #pragma no_inline(bge_chip_peek_cfg) 4471 4472 static void 4473 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4474 { 4475 uint64_t regval; 4476 uint64_t regno; 4477 4478 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4479 (void *)bgep, (void *)ppd)); 4480 4481 regno = ppd->pp_acc_offset; 4482 4483 switch (ppd->pp_acc_size) { 4484 case 1: 4485 regval = pci_config_get8(bgep->cfg_handle, regno); 4486 break; 4487 4488 case 2: 4489 regval = pci_config_get16(bgep->cfg_handle, regno); 4490 break; 4491 4492 case 4: 4493 regval = pci_config_get32(bgep->cfg_handle, regno); 4494 break; 4495 4496 case 8: 4497 regval = pci_config_get64(bgep->cfg_handle, regno); 4498 break; 4499 } 4500 4501 ppd->pp_acc_data = regval; 4502 } 4503 4504 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4505 #pragma no_inline(bge_chip_poke_cfg) 4506 4507 static void 4508 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4509 { 4510 uint64_t regval; 4511 uint64_t regno; 4512 4513 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4514 (void *)bgep, (void *)ppd)); 4515 4516 regno = ppd->pp_acc_offset; 4517 regval = ppd->pp_acc_data; 4518 4519 switch (ppd->pp_acc_size) { 4520 case 1: 4521 pci_config_put8(bgep->cfg_handle, regno, regval); 4522 break; 4523 4524 case 2: 4525 pci_config_put16(bgep->cfg_handle, regno, regval); 4526 break; 4527 4528 case 4: 4529 pci_config_put32(bgep->cfg_handle, regno, regval); 4530 break; 4531 4532 case 8: 4533 pci_config_put64(bgep->cfg_handle, regno, regval); 4534 break; 4535 } 4536 } 4537 4538 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4539 #pragma no_inline(bge_chip_peek_reg) 4540 4541 static void 4542 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4543 { 4544 uint64_t regval; 4545 void *regaddr; 4546 4547 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4548 (void *)bgep, (void *)ppd)); 4549 4550 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4551 4552 switch (ppd->pp_acc_size) { 4553 case 1: 4554 regval = ddi_get8(bgep->io_handle, regaddr); 4555 break; 4556 4557 case 2: 4558 regval = ddi_get16(bgep->io_handle, regaddr); 4559 break; 4560 4561 case 4: 4562 regval = ddi_get32(bgep->io_handle, regaddr); 4563 break; 4564 4565 case 8: 4566 regval = ddi_get64(bgep->io_handle, regaddr); 4567 break; 4568 } 4569 4570 ppd->pp_acc_data = regval; 4571 } 4572 4573 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4574 #pragma no_inline(bge_chip_peek_reg) 4575 4576 static void 4577 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4578 { 4579 uint64_t regval; 4580 void *regaddr; 4581 4582 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4583 (void *)bgep, (void *)ppd)); 4584 4585 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4586 regval = ppd->pp_acc_data; 4587 4588 switch (ppd->pp_acc_size) { 4589 case 1: 4590 ddi_put8(bgep->io_handle, regaddr, regval); 4591 break; 4592 4593 case 2: 4594 ddi_put16(bgep->io_handle, regaddr, regval); 4595 break; 4596 4597 case 4: 4598 ddi_put32(bgep->io_handle, regaddr, regval); 4599 break; 4600 4601 case 8: 4602 ddi_put64(bgep->io_handle, regaddr, regval); 4603 break; 4604 } 4605 BGE_PCICHK(bgep); 4606 } 4607 4608 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4609 #pragma no_inline(bge_chip_peek_nic) 4610 4611 static void 4612 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4613 { 4614 uint64_t regoff; 4615 uint64_t regval; 4616 void *regaddr; 4617 4618 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4619 (void *)bgep, (void *)ppd)); 4620 4621 regoff = ppd->pp_acc_offset; 4622 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4623 regoff &= MWBAR_GRANULE_MASK; 4624 regoff += NIC_MEM_WINDOW_OFFSET; 4625 regaddr = PIO_ADDR(bgep, regoff); 4626 4627 switch (ppd->pp_acc_size) { 4628 case 1: 4629 regval = ddi_get8(bgep->io_handle, regaddr); 4630 break; 4631 4632 case 2: 4633 regval = ddi_get16(bgep->io_handle, regaddr); 4634 break; 4635 4636 case 4: 4637 regval = ddi_get32(bgep->io_handle, regaddr); 4638 break; 4639 4640 case 8: 4641 regval = ddi_get64(bgep->io_handle, regaddr); 4642 break; 4643 } 4644 4645 ppd->pp_acc_data = regval; 4646 } 4647 4648 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4649 #pragma no_inline(bge_chip_poke_nic) 4650 4651 static void 4652 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4653 { 4654 uint64_t regoff; 4655 uint64_t regval; 4656 void *regaddr; 4657 4658 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4659 (void *)bgep, (void *)ppd)); 4660 4661 regoff = ppd->pp_acc_offset; 4662 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4663 regoff &= MWBAR_GRANULE_MASK; 4664 regoff += NIC_MEM_WINDOW_OFFSET; 4665 regaddr = PIO_ADDR(bgep, regoff); 4666 regval = ppd->pp_acc_data; 4667 4668 switch (ppd->pp_acc_size) { 4669 case 1: 4670 ddi_put8(bgep->io_handle, regaddr, regval); 4671 break; 4672 4673 case 2: 4674 ddi_put16(bgep->io_handle, regaddr, regval); 4675 break; 4676 4677 case 4: 4678 ddi_put32(bgep->io_handle, regaddr, regval); 4679 break; 4680 4681 case 8: 4682 ddi_put64(bgep->io_handle, regaddr, regval); 4683 break; 4684 } 4685 BGE_PCICHK(bgep); 4686 } 4687 4688 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4689 #pragma no_inline(bge_chip_peek_mii) 4690 4691 static void 4692 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4693 { 4694 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 4695 (void *)bgep, (void *)ppd)); 4696 4697 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 4698 } 4699 4700 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4701 #pragma no_inline(bge_chip_poke_mii) 4702 4703 static void 4704 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4705 { 4706 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 4707 (void *)bgep, (void *)ppd)); 4708 4709 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 4710 } 4711 4712 #if BGE_SEE_IO32 4713 4714 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4715 #pragma no_inline(bge_chip_peek_seeprom) 4716 4717 static void 4718 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4719 { 4720 uint32_t data; 4721 int err; 4722 4723 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 4724 (void *)bgep, (void *)ppd)); 4725 4726 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 4727 ppd->pp_acc_data = err ? ~0ull : data; 4728 } 4729 4730 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4731 #pragma no_inline(bge_chip_poke_seeprom) 4732 4733 static void 4734 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4735 { 4736 uint32_t data; 4737 4738 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 4739 (void *)bgep, (void *)ppd)); 4740 4741 data = ppd->pp_acc_data; 4742 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 4743 } 4744 #endif /* BGE_SEE_IO32 */ 4745 4746 #if BGE_FLASH_IO32 4747 4748 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4749 #pragma no_inline(bge_chip_peek_flash) 4750 4751 static void 4752 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4753 { 4754 uint32_t data; 4755 int err; 4756 4757 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 4758 (void *)bgep, (void *)ppd)); 4759 4760 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 4761 ppd->pp_acc_data = err ? ~0ull : data; 4762 } 4763 4764 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4765 #pragma no_inline(bge_chip_poke_flash) 4766 4767 static void 4768 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4769 { 4770 uint32_t data; 4771 4772 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 4773 (void *)bgep, (void *)ppd)); 4774 4775 data = ppd->pp_acc_data; 4776 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 4777 ppd->pp_acc_offset, &data); 4778 } 4779 #endif /* BGE_FLASH_IO32 */ 4780 4781 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4782 #pragma no_inline(bge_chip_peek_mem) 4783 4784 static void 4785 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4786 { 4787 uint64_t regval; 4788 void *vaddr; 4789 4790 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 4791 (void *)bgep, (void *)ppd)); 4792 4793 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4794 4795 switch (ppd->pp_acc_size) { 4796 case 1: 4797 regval = *(uint8_t *)vaddr; 4798 break; 4799 4800 case 2: 4801 regval = *(uint16_t *)vaddr; 4802 break; 4803 4804 case 4: 4805 regval = *(uint32_t *)vaddr; 4806 break; 4807 4808 case 8: 4809 regval = *(uint64_t *)vaddr; 4810 break; 4811 } 4812 4813 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 4814 (void *)bgep, (void *)ppd, regval, vaddr)); 4815 4816 ppd->pp_acc_data = regval; 4817 } 4818 4819 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4820 #pragma no_inline(bge_chip_poke_mem) 4821 4822 static void 4823 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4824 { 4825 uint64_t regval; 4826 void *vaddr; 4827 4828 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 4829 (void *)bgep, (void *)ppd)); 4830 4831 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4832 regval = ppd->pp_acc_data; 4833 4834 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 4835 (void *)bgep, (void *)ppd, regval, vaddr)); 4836 4837 switch (ppd->pp_acc_size) { 4838 case 1: 4839 *(uint8_t *)vaddr = (uint8_t)regval; 4840 break; 4841 4842 case 2: 4843 *(uint16_t *)vaddr = (uint16_t)regval; 4844 break; 4845 4846 case 4: 4847 *(uint32_t *)vaddr = (uint32_t)regval; 4848 break; 4849 4850 case 8: 4851 *(uint64_t *)vaddr = (uint64_t)regval; 4852 break; 4853 } 4854 } 4855 4856 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4857 struct iocblk *iocp); 4858 #pragma no_inline(bge_pp_ioctl) 4859 4860 static enum ioc_reply 4861 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4862 { 4863 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 4864 bge_peekpoke_t *ppd; 4865 dma_area_t *areap; 4866 uint64_t sizemask; 4867 uint64_t mem_va; 4868 uint64_t maxoff; 4869 boolean_t peek; 4870 4871 switch (cmd) { 4872 default: 4873 /* NOTREACHED */ 4874 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 4875 return (IOC_INVAL); 4876 4877 case BGE_PEEK: 4878 peek = B_TRUE; 4879 break; 4880 4881 case BGE_POKE: 4882 peek = B_FALSE; 4883 break; 4884 } 4885 4886 /* 4887 * Validate format of ioctl 4888 */ 4889 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 4890 return (IOC_INVAL); 4891 if (mp->b_cont == NULL) 4892 return (IOC_INVAL); 4893 ppd = (bge_peekpoke_t *)mp->b_cont->b_rptr; 4894 4895 /* 4896 * Validate request parameters 4897 */ 4898 switch (ppd->pp_acc_space) { 4899 default: 4900 return (IOC_INVAL); 4901 4902 case BGE_PP_SPACE_CFG: 4903 /* 4904 * Config space 4905 */ 4906 sizemask = 8|4|2|1; 4907 mem_va = 0; 4908 maxoff = PCI_CONF_HDR_SIZE; 4909 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 4910 break; 4911 4912 case BGE_PP_SPACE_REG: 4913 /* 4914 * Memory-mapped I/O space 4915 */ 4916 sizemask = 8|4|2|1; 4917 mem_va = 0; 4918 maxoff = RIAAR_REGISTER_MAX; 4919 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 4920 break; 4921 4922 case BGE_PP_SPACE_NIC: 4923 /* 4924 * NIC on-chip memory 4925 */ 4926 sizemask = 8|4|2|1; 4927 mem_va = 0; 4928 maxoff = MWBAR_ONCHIP_MAX; 4929 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 4930 break; 4931 4932 case BGE_PP_SPACE_MII: 4933 /* 4934 * PHY's MII registers 4935 * NB: all PHY registers are two bytes, but the 4936 * addresses increment in ones (word addressing). 4937 * So we scale the address here, then undo the 4938 * transformation inside the peek/poke functions. 4939 */ 4940 ppd->pp_acc_offset *= 2; 4941 sizemask = 2; 4942 mem_va = 0; 4943 maxoff = (MII_MAXREG+1)*2; 4944 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 4945 break; 4946 4947 #if BGE_SEE_IO32 4948 case BGE_PP_SPACE_SEEPROM: 4949 /* 4950 * Attached SEEPROM(s), if any. 4951 * NB: we use the high-order bits of the 'address' as 4952 * a device select to accommodate multiple SEEPROMS, 4953 * If each one is the maximum size (64kbytes), this 4954 * makes them appear contiguous. Otherwise, there may 4955 * be holes in the mapping. ENxS doesn't have any 4956 * SEEPROMs anyway ... 4957 */ 4958 sizemask = 4; 4959 mem_va = 0; 4960 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 4961 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 4962 break; 4963 #endif /* BGE_SEE_IO32 */ 4964 4965 #if BGE_FLASH_IO32 4966 case BGE_PP_SPACE_FLASH: 4967 /* 4968 * Attached Flash device (if any); a maximum of one device 4969 * is currently supported. But it can be up to 1MB (unlike 4970 * the 64k limit on SEEPROMs) so why would you need more ;-) 4971 */ 4972 sizemask = 4; 4973 mem_va = 0; 4974 maxoff = NVM_FLASH_ADDR_MASK; 4975 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 4976 break; 4977 #endif /* BGE_FLASH_IO32 */ 4978 4979 case BGE_PP_SPACE_BGE: 4980 /* 4981 * BGE data structure! 4982 */ 4983 sizemask = 8|4|2|1; 4984 mem_va = (uintptr_t)bgep; 4985 maxoff = sizeof (*bgep); 4986 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 4987 break; 4988 4989 case BGE_PP_SPACE_STATUS: 4990 case BGE_PP_SPACE_STATISTICS: 4991 case BGE_PP_SPACE_TXDESC: 4992 case BGE_PP_SPACE_TXBUFF: 4993 case BGE_PP_SPACE_RXDESC: 4994 case BGE_PP_SPACE_RXBUFF: 4995 /* 4996 * Various DMA_AREAs 4997 */ 4998 switch (ppd->pp_acc_space) { 4999 case BGE_PP_SPACE_TXDESC: 5000 areap = &bgep->tx_desc; 5001 break; 5002 case BGE_PP_SPACE_TXBUFF: 5003 areap = &bgep->tx_buff[0]; 5004 break; 5005 case BGE_PP_SPACE_RXDESC: 5006 areap = &bgep->rx_desc[0]; 5007 break; 5008 case BGE_PP_SPACE_RXBUFF: 5009 areap = &bgep->rx_buff[0]; 5010 break; 5011 case BGE_PP_SPACE_STATUS: 5012 areap = &bgep->status_block; 5013 break; 5014 case BGE_PP_SPACE_STATISTICS: 5015 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5016 areap = &bgep->statistics; 5017 break; 5018 } 5019 5020 sizemask = 8|4|2|1; 5021 mem_va = (uintptr_t)areap->mem_va; 5022 maxoff = areap->alength; 5023 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5024 break; 5025 } 5026 5027 switch (ppd->pp_acc_size) { 5028 default: 5029 return (IOC_INVAL); 5030 5031 case 8: 5032 case 4: 5033 case 2: 5034 case 1: 5035 if ((ppd->pp_acc_size & sizemask) == 0) 5036 return (IOC_INVAL); 5037 break; 5038 } 5039 5040 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5041 return (IOC_INVAL); 5042 5043 if (ppd->pp_acc_offset >= maxoff) 5044 return (IOC_INVAL); 5045 5046 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5047 return (IOC_INVAL); 5048 5049 /* 5050 * All OK - go do it! 5051 */ 5052 ppd->pp_acc_offset += mem_va; 5053 (*ppfn)(bgep, ppd); 5054 return (peek ? IOC_REPLY : IOC_ACK); 5055 } 5056 5057 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5058 struct iocblk *iocp); 5059 #pragma no_inline(bge_diag_ioctl) 5060 5061 static enum ioc_reply 5062 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5063 { 5064 ASSERT(mutex_owned(bgep->genlock)); 5065 5066 switch (cmd) { 5067 default: 5068 /* NOTREACHED */ 5069 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5070 return (IOC_INVAL); 5071 5072 case BGE_DIAG: 5073 /* 5074 * Currently a no-op 5075 */ 5076 return (IOC_ACK); 5077 5078 case BGE_PEEK: 5079 case BGE_POKE: 5080 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5081 5082 case BGE_PHY_RESET: 5083 return (IOC_RESTART_ACK); 5084 5085 case BGE_SOFT_RESET: 5086 case BGE_HARD_RESET: 5087 /* 5088 * Reset and reinitialise the 570x hardware 5089 */ 5090 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5091 return (IOC_ACK); 5092 } 5093 5094 /* NOTREACHED */ 5095 } 5096 5097 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5098 5099 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5100 struct iocblk *iocp); 5101 #pragma no_inline(bge_mii_ioctl) 5102 5103 static enum ioc_reply 5104 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5105 { 5106 struct bge_mii_rw *miirwp; 5107 5108 /* 5109 * Validate format of ioctl 5110 */ 5111 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5112 return (IOC_INVAL); 5113 if (mp->b_cont == NULL) 5114 return (IOC_INVAL); 5115 miirwp = (struct bge_mii_rw *)mp->b_cont->b_rptr; 5116 5117 /* 5118 * Validate request parameters ... 5119 */ 5120 if (miirwp->mii_reg > MII_MAXREG) 5121 return (IOC_INVAL); 5122 5123 switch (cmd) { 5124 default: 5125 /* NOTREACHED */ 5126 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5127 return (IOC_INVAL); 5128 5129 case BGE_MII_READ: 5130 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5131 return (IOC_REPLY); 5132 5133 case BGE_MII_WRITE: 5134 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5135 return (IOC_ACK); 5136 } 5137 5138 /* NOTREACHED */ 5139 } 5140 5141 #if BGE_SEE_IO32 5142 5143 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5144 struct iocblk *iocp); 5145 #pragma no_inline(bge_see_ioctl) 5146 5147 static enum ioc_reply 5148 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5149 { 5150 struct bge_see_rw *seerwp; 5151 5152 /* 5153 * Validate format of ioctl 5154 */ 5155 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5156 return (IOC_INVAL); 5157 if (mp->b_cont == NULL) 5158 return (IOC_INVAL); 5159 seerwp = (struct bge_see_rw *)mp->b_cont->b_rptr; 5160 5161 /* 5162 * Validate request parameters ... 5163 */ 5164 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5165 return (IOC_INVAL); 5166 5167 switch (cmd) { 5168 default: 5169 /* NOTREACHED */ 5170 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5171 return (IOC_INVAL); 5172 5173 case BGE_SEE_READ: 5174 case BGE_SEE_WRITE: 5175 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5176 seerwp->see_addr, &seerwp->see_data); 5177 return (IOC_REPLY); 5178 } 5179 5180 /* NOTREACHED */ 5181 } 5182 5183 #endif /* BGE_SEE_IO32 */ 5184 5185 #if BGE_FLASH_IO32 5186 5187 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5188 struct iocblk *iocp); 5189 #pragma no_inline(bge_flash_ioctl) 5190 5191 static enum ioc_reply 5192 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5193 { 5194 struct bge_flash_rw *flashrwp; 5195 5196 /* 5197 * Validate format of ioctl 5198 */ 5199 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5200 return (IOC_INVAL); 5201 if (mp->b_cont == NULL) 5202 return (IOC_INVAL); 5203 flashrwp = (struct bge_flash_rw *)mp->b_cont->b_rptr; 5204 5205 /* 5206 * Validate request parameters ... 5207 */ 5208 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5209 return (IOC_INVAL); 5210 5211 switch (cmd) { 5212 default: 5213 /* NOTREACHED */ 5214 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5215 return (IOC_INVAL); 5216 5217 case BGE_FLASH_READ: 5218 case BGE_FLASH_WRITE: 5219 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5220 flashrwp->flash_addr, &flashrwp->flash_data); 5221 return (IOC_REPLY); 5222 } 5223 5224 /* NOTREACHED */ 5225 } 5226 5227 #endif /* BGE_FLASH_IO32 */ 5228 5229 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5230 struct iocblk *iocp); 5231 #pragma no_inline(bge_chip_ioctl) 5232 5233 enum ioc_reply 5234 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5235 { 5236 int cmd; 5237 5238 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5239 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5240 5241 ASSERT(mutex_owned(bgep->genlock)); 5242 5243 cmd = iocp->ioc_cmd; 5244 switch (cmd) { 5245 default: 5246 /* NOTREACHED */ 5247 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5248 return (IOC_INVAL); 5249 5250 case BGE_DIAG: 5251 case BGE_PEEK: 5252 case BGE_POKE: 5253 case BGE_PHY_RESET: 5254 case BGE_SOFT_RESET: 5255 case BGE_HARD_RESET: 5256 #if BGE_DEBUGGING || BGE_DO_PPIO 5257 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5258 #else 5259 return (IOC_INVAL); 5260 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5261 5262 case BGE_MII_READ: 5263 case BGE_MII_WRITE: 5264 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5265 5266 #if BGE_SEE_IO32 5267 case BGE_SEE_READ: 5268 case BGE_SEE_WRITE: 5269 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5270 #endif /* BGE_SEE_IO32 */ 5271 5272 #if BGE_FLASH_IO32 5273 case BGE_FLASH_READ: 5274 case BGE_FLASH_WRITE: 5275 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5276 #endif /* BGE_FLASH_IO32 */ 5277 } 5278 5279 /* NOTREACHED */ 5280 } 5281 5282 void 5283 bge_chip_blank(void *arg, time_t ticks, uint_t count) 5284 { 5285 bge_t *bgep = arg; 5286 5287 mutex_enter(bgep->genlock); 5288 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5289 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5290 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5291 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5292 mutex_exit(bgep->genlock); 5293 } 5294 5295 #ifdef BGE_IPMI_ASF 5296 5297 uint32_t 5298 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5299 { 5300 uint32_t data; 5301 5302 if (!bgep->asf_wordswapped) { 5303 /* a workaround word swap error */ 5304 if (addr & 4) 5305 addr = addr - 4; 5306 else 5307 addr = addr + 4; 5308 } 5309 5310 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5311 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5312 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5313 5314 return (data); 5315 } 5316 5317 5318 void 5319 bge_asf_update_status(bge_t *bgep) 5320 { 5321 uint32_t event; 5322 5323 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5324 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5325 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5326 5327 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5328 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5329 } 5330 5331 5332 /* 5333 * The driver is supposed to notify ASF that the OS is still running 5334 * every three seconds, otherwise the management server may attempt 5335 * to reboot the machine. If it hasn't actually failed, this is 5336 * not a desirable result. However, this isn't running as a real-time 5337 * thread, and even if it were, it might not be able to generate the 5338 * heartbeat in a timely manner due to system load. As it isn't a 5339 * significant strain on the machine, we will set the interval to half 5340 * of the required value. 5341 */ 5342 void 5343 bge_asf_heartbeat(void *arg) 5344 { 5345 bge_t *bgep = (bge_t *)arg; 5346 5347 mutex_enter(bgep->genlock); 5348 bge_asf_update_status((bge_t *)bgep); 5349 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5350 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5351 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5352 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5353 mutex_exit(bgep->genlock); 5354 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5355 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5356 } 5357 5358 5359 void 5360 bge_asf_stop_timer(bge_t *bgep) 5361 { 5362 timeout_id_t tmp_id = 0; 5363 5364 while ((bgep->asf_timeout_id != 0) && 5365 (tmp_id != bgep->asf_timeout_id)) { 5366 tmp_id = bgep->asf_timeout_id; 5367 (void) untimeout(tmp_id); 5368 } 5369 bgep->asf_timeout_id = 0; 5370 } 5371 5372 5373 5374 /* 5375 * This function should be placed at the earliest position of bge_attach(). 5376 */ 5377 void 5378 bge_asf_get_config(bge_t *bgep) 5379 { 5380 uint32_t nicsig; 5381 uint32_t niccfg; 5382 5383 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5384 if (nicsig == BGE_NIC_DATA_SIG) { 5385 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5386 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5387 /* 5388 * Here, we don't consider BAXTER, because BGE haven't 5389 * supported BAXTER (that is 5752). Also, as I know, 5390 * BAXTER doesn't support ASF feature. 5391 */ 5392 bgep->asf_enabled = B_TRUE; 5393 else 5394 bgep->asf_enabled = B_FALSE; 5395 } else 5396 bgep->asf_enabled = B_FALSE; 5397 } 5398 5399 5400 void 5401 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5402 { 5403 uint32_t tries; 5404 uint32_t event; 5405 5406 ASSERT(bgep->asf_enabled); 5407 5408 /* Issues "pause firmware" command and wait for ACK */ 5409 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5410 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5411 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5412 5413 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5414 tries = 0; 5415 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5416 drv_usecwait(1); 5417 tries ++; 5418 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5419 } 5420 5421 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5422 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5423 5424 if (bgep->asf_newhandshake) { 5425 switch (mode) { 5426 case BGE_INIT_RESET: 5427 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5428 BGE_DRV_STATE_START); 5429 break; 5430 case BGE_SHUTDOWN_RESET: 5431 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5432 BGE_DRV_STATE_UNLOAD); 5433 break; 5434 case BGE_SUSPEND_RESET: 5435 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5436 BGE_DRV_STATE_SUSPEND); 5437 break; 5438 default: 5439 break; 5440 } 5441 } 5442 } 5443 5444 5445 void 5446 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5447 { 5448 switch (mode) { 5449 case BGE_INIT_RESET: 5450 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5451 BGE_DRV_STATE_START); 5452 break; 5453 case BGE_SHUTDOWN_RESET: 5454 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5455 BGE_DRV_STATE_UNLOAD); 5456 break; 5457 case BGE_SUSPEND_RESET: 5458 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5459 BGE_DRV_STATE_SUSPEND); 5460 break; 5461 default: 5462 break; 5463 } 5464 } 5465 5466 5467 void 5468 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5469 { 5470 switch (mode) { 5471 case BGE_INIT_RESET: 5472 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5473 BGE_DRV_STATE_START_DONE); 5474 break; 5475 case BGE_SHUTDOWN_RESET: 5476 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5477 BGE_DRV_STATE_UNLOAD_DONE); 5478 break; 5479 default: 5480 break; 5481 } 5482 } 5483 5484 #endif /* BGE_IPMI_ASF */ 5485