1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #ifndef _IDXD_REGISTERS_H_ 4 #define _IDXD_REGISTERS_H_ 5 6 #ifdef __KERNEL__ 7 #include <uapi/linux/idxd.h> 8 #else 9 #include <linux/idxd.h> 10 #endif 11 12 /* PCI Config */ 13 #define PCI_DEVICE_ID_INTEL_DSA_GNRD 0x11fb 14 #define PCI_DEVICE_ID_INTEL_DSA_DMR 0x1212 15 #define PCI_DEVICE_ID_INTEL_IAA_DMR 0x1216 16 #define PCI_DEVICE_ID_INTEL_IAA_PTL 0xb02d 17 18 #define DEVICE_VERSION_1 0x100 19 #define DEVICE_VERSION_2 0x200 20 21 #define IDXD_MMIO_BAR 0 22 #define IDXD_WQ_BAR 2 23 #define IDXD_PORTAL_SIZE PAGE_SIZE 24 25 /* MMIO Device BAR0 Registers */ 26 #define IDXD_VER_OFFSET 0x00 27 #define IDXD_VER_MAJOR_MASK 0xf0 28 #define IDXD_VER_MINOR_MASK 0x0f 29 #define GET_IDXD_VER_MAJOR(x) (((x) & IDXD_VER_MAJOR_MASK) >> 4) 30 #define GET_IDXD_VER_MINOR(x) ((x) & IDXD_VER_MINOR_MASK) 31 32 union gen_cap_reg { 33 struct { 34 u64 block_on_fault:1; 35 u64 overlap_copy:1; 36 u64 cache_control_mem:1; 37 u64 cache_control_cache:1; 38 u64 cmd_cap:1; 39 u64 rsvd:3; 40 u64 dest_readback:1; 41 u64 drain_readback:1; 42 u64 rsvd2:3; 43 u64 evl_support:2; 44 u64 batch_continuation:1; 45 u64 max_xfer_shift:5; 46 u64 max_batch_shift:4; 47 u64 max_ims_mult:6; 48 u64 config_en:1; 49 u64 rsvd3:32; 50 }; 51 u64 bits; 52 }; 53 #define IDXD_GENCAP_OFFSET 0x10 54 55 union wq_cap_reg { 56 struct { 57 u64 total_wq_size:16; 58 u64 num_wqs:8; 59 u64 wqcfg_size:4; 60 u64 rsvd:20; 61 u64 shared_mode:1; 62 u64 dedicated_mode:1; 63 u64 wq_ats_support:1; 64 u64 priority:1; 65 u64 occupancy:1; 66 u64 occupancy_int:1; 67 u64 op_config:1; 68 u64 wq_prs_support:1; 69 u64 rsvd4:8; 70 }; 71 u64 bits; 72 }; 73 #define IDXD_WQCAP_OFFSET 0x20 74 #define IDXD_WQCFG_MIN 5 75 76 union group_cap_reg { 77 struct { 78 u64 num_groups:8; 79 u64 total_rdbufs:8; /* formerly total_tokens */ 80 u64 rdbuf_ctrl:1; /* formerly token_en */ 81 u64 rdbuf_limit:1; /* formerly token_limit */ 82 u64 progress_limit:1; /* descriptor and batch descriptor */ 83 u64 rsvd:45; 84 }; 85 u64 bits; 86 }; 87 #define IDXD_GRPCAP_OFFSET 0x30 88 89 union engine_cap_reg { 90 struct { 91 u64 num_engines:8; 92 u64 rsvd:56; 93 }; 94 u64 bits; 95 }; 96 97 #define IDXD_ENGCAP_OFFSET 0x38 98 99 #define IDXD_OPCAP_NOOP 0x0001 100 #define IDXD_OPCAP_BATCH 0x0002 101 #define IDXD_OPCAP_MEMMOVE 0x0008 102 struct opcap { 103 u64 bits[4]; 104 }; 105 106 #define IDXD_MAX_OPCAP_BITS 256U 107 108 #define IDXD_OPCAP_OFFSET 0x40 109 110 #define IDXD_TABLE_OFFSET 0x60 111 union offsets_reg { 112 struct { 113 u64 grpcfg:16; 114 u64 wqcfg:16; 115 u64 msix_perm:16; 116 u64 ims:16; 117 u64 perfmon:16; 118 u64 rsvd:48; 119 }; 120 u64 bits[2]; 121 }; 122 123 #define IDXD_TABLE_MULT 0x100 124 125 #define IDXD_GENCFG_OFFSET 0x80 126 union gencfg_reg { 127 struct { 128 u32 rdbuf_limit:8; 129 u32 rsvd:4; 130 u32 user_int_en:1; 131 u32 evl_en:1; 132 u32 rsvd2:18; 133 }; 134 u32 bits; 135 }; 136 137 #define IDXD_GENCTRL_OFFSET 0x88 138 union genctrl_reg { 139 struct { 140 u32 softerr_int_en:1; 141 u32 halt_int_en:1; 142 u32 evl_int_en:1; 143 u32 rsvd:29; 144 }; 145 u32 bits; 146 }; 147 148 #define IDXD_GENSTATS_OFFSET 0x90 149 union gensts_reg { 150 struct { 151 u32 state:2; 152 u32 reset_type:2; 153 u32 rsvd:28; 154 }; 155 u32 bits; 156 }; 157 158 enum idxd_device_status_state { 159 IDXD_DEVICE_STATE_DISABLED = 0, 160 IDXD_DEVICE_STATE_ENABLED, 161 IDXD_DEVICE_STATE_DRAIN, 162 IDXD_DEVICE_STATE_HALT, 163 }; 164 165 enum idxd_device_reset_type { 166 IDXD_DEVICE_RESET_SOFTWARE = 0, 167 IDXD_DEVICE_RESET_FLR, 168 IDXD_DEVICE_RESET_WARM, 169 IDXD_DEVICE_RESET_COLD, 170 }; 171 172 #define IDXD_INTCAUSE_OFFSET 0x98 173 #define IDXD_INTC_ERR 0x01 174 #define IDXD_INTC_CMD 0x02 175 #define IDXD_INTC_OCCUPY 0x04 176 #define IDXD_INTC_PERFMON_OVFL 0x08 177 #define IDXD_INTC_HALT_STATE 0x10 178 #define IDXD_INTC_EVL 0x20 179 #define IDXD_INTC_INT_HANDLE_REVOKED 0x80000000 180 181 #define IDXD_CMD_OFFSET 0xa0 182 union idxd_command_reg { 183 struct { 184 u32 operand:20; 185 u32 cmd:5; 186 u32 rsvd:6; 187 u32 int_req:1; 188 }; 189 u32 bits; 190 }; 191 192 enum idxd_cmd { 193 IDXD_CMD_ENABLE_DEVICE = 1, 194 IDXD_CMD_DISABLE_DEVICE, 195 IDXD_CMD_DRAIN_ALL, 196 IDXD_CMD_ABORT_ALL, 197 IDXD_CMD_RESET_DEVICE, 198 IDXD_CMD_ENABLE_WQ, 199 IDXD_CMD_DISABLE_WQ, 200 IDXD_CMD_DRAIN_WQ, 201 IDXD_CMD_ABORT_WQ, 202 IDXD_CMD_RESET_WQ, 203 IDXD_CMD_DRAIN_PASID, 204 IDXD_CMD_ABORT_PASID, 205 IDXD_CMD_REQUEST_INT_HANDLE, 206 IDXD_CMD_RELEASE_INT_HANDLE, 207 }; 208 209 #define CMD_INT_HANDLE_IMS 0x10000 210 211 #define IDXD_CMDSTS_OFFSET 0xa8 212 union cmdsts_reg { 213 struct { 214 u8 err; 215 u16 result; 216 u8 rsvd:7; 217 u8 active:1; 218 }; 219 u32 bits; 220 }; 221 #define IDXD_CMDSTS_ACTIVE 0x80000000 222 #define IDXD_CMDSTS_ERR_MASK 0xff 223 #define IDXD_CMDSTS_RES_SHIFT 8 224 225 enum idxd_cmdsts_err { 226 IDXD_CMDSTS_SUCCESS = 0, 227 IDXD_CMDSTS_INVAL_CMD, 228 IDXD_CMDSTS_INVAL_WQIDX, 229 IDXD_CMDSTS_HW_ERR, 230 /* enable device errors */ 231 IDXD_CMDSTS_ERR_DEV_ENABLED = 0x10, 232 IDXD_CMDSTS_ERR_CONFIG, 233 IDXD_CMDSTS_ERR_BUSMASTER_EN, 234 IDXD_CMDSTS_ERR_PASID_INVAL, 235 IDXD_CMDSTS_ERR_WQ_SIZE_ERANGE, 236 IDXD_CMDSTS_ERR_GRP_CONFIG, 237 IDXD_CMDSTS_ERR_GRP_CONFIG2, 238 IDXD_CMDSTS_ERR_GRP_CONFIG3, 239 IDXD_CMDSTS_ERR_GRP_CONFIG4, 240 /* enable wq errors */ 241 IDXD_CMDSTS_ERR_DEV_NOTEN = 0x20, 242 IDXD_CMDSTS_ERR_WQ_ENABLED, 243 IDXD_CMDSTS_ERR_WQ_SIZE, 244 IDXD_CMDSTS_ERR_WQ_PRIOR, 245 IDXD_CMDSTS_ERR_WQ_MODE, 246 IDXD_CMDSTS_ERR_BOF_EN, 247 IDXD_CMDSTS_ERR_PASID_EN, 248 IDXD_CMDSTS_ERR_MAX_BATCH_SIZE, 249 IDXD_CMDSTS_ERR_MAX_XFER_SIZE, 250 /* disable device errors */ 251 IDXD_CMDSTS_ERR_DIS_DEV_EN = 0x31, 252 /* disable WQ, drain WQ, abort WQ, reset WQ */ 253 IDXD_CMDSTS_ERR_DEV_NOT_EN, 254 /* request interrupt handle */ 255 IDXD_CMDSTS_ERR_INVAL_INT_IDX = 0x41, 256 IDXD_CMDSTS_ERR_NO_HANDLE, 257 }; 258 259 #define IDXD_CMDCAP_OFFSET 0xb0 260 261 #define IDXD_SWERR_OFFSET 0xc0 262 #define IDXD_SWERR_VALID 0x00000001 263 #define IDXD_SWERR_OVERFLOW 0x00000002 264 #define IDXD_SWERR_ACK (IDXD_SWERR_VALID | IDXD_SWERR_OVERFLOW) 265 union sw_err_reg { 266 struct { 267 u64 valid:1; 268 u64 overflow:1; 269 u64 desc_valid:1; 270 u64 wq_idx_valid:1; 271 u64 batch:1; 272 u64 fault_rw:1; 273 u64 priv:1; 274 u64 rsvd:1; 275 u64 error:8; 276 u64 wq_idx:8; 277 u64 rsvd2:8; 278 u64 operation:8; 279 u64 pasid:20; 280 u64 rsvd3:4; 281 282 u64 batch_idx:16; 283 u64 rsvd4:16; 284 u64 invalid_flags:32; 285 286 u64 fault_addr; 287 288 u64 rsvd5; 289 }; 290 u64 bits[4]; 291 }; 292 293 union iaa_cap_reg { 294 struct { 295 u64 dec_aecs_format_ver:1; 296 u64 drop_init_bits:1; 297 u64 chaining:1; 298 u64 force_array_output_mod:1; 299 u64 load_part_aecs:1; 300 u64 comp_early_abort:1; 301 u64 nested_comp:1; 302 u64 diction_comp:1; 303 u64 header_gen:1; 304 u64 crypto_gcm:1; 305 u64 crypto_cfb:1; 306 u64 crypto_xts:1; 307 u64 rsvd:52; 308 }; 309 u64 bits; 310 }; 311 312 #define IDXD_IAACAP_OFFSET 0x180 313 314 #define IDXD_EVLCFG_OFFSET 0xe0 315 union evlcfg_reg { 316 struct { 317 u64 pasid_en:1; 318 u64 priv:1; 319 u64 rsvd:10; 320 u64 base_addr:52; 321 322 u64 size:16; 323 u64 pasid:20; 324 u64 rsvd2:28; 325 }; 326 u64 bits[2]; 327 }; 328 329 #define IDXD_EVL_SIZE_MIN 0x0040 330 #define IDXD_EVL_SIZE_MAX 0xffff 331 332 union msix_perm { 333 struct { 334 u32 rsvd:2; 335 u32 ignore:1; 336 u32 pasid_en:1; 337 u32 rsvd2:8; 338 u32 pasid:20; 339 }; 340 u32 bits; 341 }; 342 343 union group_flags { 344 struct { 345 u64 tc_a:3; 346 u64 tc_b:3; 347 u64 rsvd:1; 348 u64 use_rdbuf_limit:1; 349 u64 rdbufs_reserved:8; 350 u64 rsvd2:4; 351 u64 rdbufs_allowed:8; 352 u64 rsvd3:4; 353 u64 desc_progress_limit:2; 354 u64 rsvd4:2; 355 u64 batch_progress_limit:2; 356 u64 rsvd5:26; 357 }; 358 u64 bits; 359 }; 360 361 struct grpcfg { 362 u64 wqs[4]; 363 u64 engines; 364 union group_flags flags; 365 }; 366 367 union wqcfg { 368 struct { 369 /* bytes 0-3 */ 370 u16 wq_size; 371 u16 rsvd; 372 373 /* bytes 4-7 */ 374 u16 wq_thresh; 375 u16 rsvd1; 376 377 /* bytes 8-11 */ 378 u32 mode:1; /* shared or dedicated */ 379 u32 bof:1; /* block on fault */ 380 u32 wq_ats_disable:1; 381 u32 wq_prs_disable:1; 382 u32 priority:4; 383 u32 pasid:20; 384 u32 pasid_en:1; 385 u32 priv:1; 386 u32 rsvd3:2; 387 388 /* bytes 12-15 */ 389 u32 max_xfer_shift:5; 390 u32 max_batch_shift:4; 391 u32 rsvd4:23; 392 393 /* bytes 16-19 */ 394 u16 occupancy_inth; 395 u16 occupancy_table_sel:1; 396 u16 rsvd5:15; 397 398 /* bytes 20-23 */ 399 u16 occupancy_limit; 400 u16 occupancy_int_en:1; 401 u16 rsvd6:15; 402 403 /* bytes 24-27 */ 404 u16 occupancy; 405 u16 occupancy_int:1; 406 u16 rsvd7:12; 407 u16 mode_support:1; 408 u16 wq_state:2; 409 410 /* bytes 28-31 */ 411 u32 rsvd8; 412 413 /* bytes 32-63 */ 414 u64 op_config[4]; 415 }; 416 u32 bits[16]; 417 }; 418 419 #define WQCFG_PASID_IDX 2 420 #define WQCFG_PRIVL_IDX 2 421 #define WQCFG_OCCUP_IDX 6 422 423 #define WQCFG_OCCUP_MASK 0xffff 424 425 /* 426 * This macro calculates the offset into the WQCFG register 427 * idxd - struct idxd * 428 * n - wq id 429 * ofs - the index of the 32b dword for the config register 430 * 431 * The WQCFG register block is divided into groups per each wq. The n index 432 * allows us to move to the register group that's for that particular wq. 433 * Each register is 32bits. The ofs gives us the number of register to access. 434 */ 435 #define WQCFG_OFFSET(_idxd_dev, n, ofs) \ 436 ({\ 437 typeof(_idxd_dev) __idxd_dev = (_idxd_dev); \ 438 (__idxd_dev)->wqcfg_offset + (n) * (__idxd_dev)->wqcfg_size + sizeof(u32) * (ofs); \ 439 }) 440 441 #define WQCFG_STRIDES(_idxd_dev) ((_idxd_dev)->wqcfg_size / sizeof(u32)) 442 443 #define GRPCFG_SIZE 64 444 #define GRPWQCFG_STRIDES 4 445 446 /* 447 * This macro calculates the offset into the GRPCFG register 448 * idxd - struct idxd * 449 * n - group id 450 * ofs - the index of the 64b qword for the config register 451 * 452 * The GRPCFG register block is divided into three sub-registers, which 453 * are GRPWQCFG, GRPENGCFG and GRPFLGCFG. The n index allows us to move 454 * to the register block that contains the three sub-registers. 455 * Each register block is 64bits. And the ofs gives us the offset 456 * within the GRPWQCFG register to access. 457 */ 458 #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\ 459 (n) * GRPCFG_SIZE + sizeof(u64) * (ofs)) 460 #define GRPENGCFG_OFFSET(idxd_dev, n) ((idxd_dev)->grpcfg_offset + (n) * GRPCFG_SIZE + 32) 461 #define GRPFLGCFG_OFFSET(idxd_dev, n) ((idxd_dev)->grpcfg_offset + (n) * GRPCFG_SIZE + 40) 462 463 /* Following is performance monitor registers */ 464 #define IDXD_PERFCAP_OFFSET 0x0 465 union idxd_perfcap { 466 struct { 467 u64 num_perf_counter:6; 468 u64 rsvd1:2; 469 u64 counter_width:8; 470 u64 num_event_category:4; 471 u64 global_event_category:16; 472 u64 filter:8; 473 u64 rsvd2:8; 474 u64 cap_per_counter:1; 475 u64 writeable_counter:1; 476 u64 counter_freeze:1; 477 u64 overflow_interrupt:1; 478 u64 rsvd3:8; 479 }; 480 u64 bits; 481 }; 482 483 #define IDXD_EVNTCAP_OFFSET 0x80 484 union idxd_evntcap { 485 struct { 486 u64 events:28; 487 u64 rsvd:36; 488 }; 489 u64 bits; 490 }; 491 492 struct idxd_event { 493 union { 494 struct { 495 u32 event_category:4; 496 u32 events:28; 497 }; 498 u32 val; 499 }; 500 }; 501 502 #define IDXD_CNTRCAP_OFFSET 0x800 503 struct idxd_cntrcap { 504 union { 505 struct { 506 u32 counter_width:8; 507 u32 rsvd:20; 508 u32 num_events:4; 509 }; 510 u32 val; 511 }; 512 struct idxd_event events[]; 513 }; 514 515 #define IDXD_PERFRST_OFFSET 0x10 516 union idxd_perfrst { 517 struct { 518 u32 perfrst_config:1; 519 u32 perfrst_counter:1; 520 u32 rsvd:30; 521 }; 522 u32 val; 523 }; 524 525 #define IDXD_OVFSTATUS_OFFSET 0x30 526 #define IDXD_PERFFRZ_OFFSET 0x20 527 #define IDXD_CNTRCFG_OFFSET 0x100 528 union idxd_cntrcfg { 529 struct { 530 u64 enable:1; 531 u64 interrupt_ovf:1; 532 u64 global_freeze_ovf:1; 533 u64 rsvd1:5; 534 u64 event_category:4; 535 u64 rsvd2:20; 536 u64 events:28; 537 u64 rsvd3:4; 538 }; 539 u64 val; 540 }; 541 542 #define IDXD_FLTCFG_OFFSET 0x300 543 544 #define IDXD_CNTRDATA_OFFSET 0x200 545 union idxd_cntrdata { 546 struct { 547 u64 event_count_value; 548 }; 549 u64 val; 550 }; 551 552 union event_cfg { 553 struct { 554 u64 event_cat:4; 555 u64 event_enc:28; 556 }; 557 u64 val; 558 }; 559 560 union filter_cfg { 561 struct { 562 u64 wq:32; 563 u64 tc:8; 564 u64 pg_sz:4; 565 u64 xfer_sz:8; 566 u64 eng:8; 567 }; 568 u64 val; 569 }; 570 571 #define IDXD_EVLSTATUS_OFFSET 0xf0 572 573 union evl_status_reg { 574 struct { 575 u32 head:16; 576 u32 rsvd:16; 577 u32 tail:16; 578 u32 rsvd2:14; 579 u32 int_pending:1; 580 u32 rsvd3:1; 581 }; 582 struct { 583 u32 bits_lower32; 584 u32 bits_upper32; 585 }; 586 u64 bits; 587 }; 588 589 #define IDXD_MAX_BATCH_IDENT 256 590 591 struct __evl_entry { 592 u64 rsvd:2; 593 u64 desc_valid:1; 594 u64 wq_idx_valid:1; 595 u64 batch:1; 596 u64 fault_rw:1; 597 u64 priv:1; 598 u64 err_info_valid:1; 599 u64 error:8; 600 u64 wq_idx:8; 601 u64 batch_id:8; 602 u64 operation:8; 603 u64 pasid:20; 604 u64 rsvd2:4; 605 606 u16 batch_idx; 607 u16 rsvd3; 608 union { 609 /* Invalid Flags 0x11 */ 610 u32 invalid_flags; 611 /* Invalid Int Handle 0x19 */ 612 /* Page fault 0x1a */ 613 /* Page fault 0x06, 0x1f, only operand_id */ 614 /* Page fault before drain or in batch, 0x26, 0x27 */ 615 struct { 616 u16 int_handle; 617 u16 rci:1; 618 u16 ims:1; 619 u16 rcr:1; 620 u16 first_err_in_batch:1; 621 u16 rsvd4_2:9; 622 u16 operand_id:3; 623 }; 624 }; 625 u64 fault_addr; 626 u64 rsvd5; 627 }; 628 629 struct dsa_evl_entry { 630 struct __evl_entry e; 631 struct dsa_completion_record cr; 632 }; 633 634 struct iax_evl_entry { 635 struct __evl_entry e; 636 u64 rsvd[4]; 637 struct iax_completion_record cr; 638 }; 639 640 #endif 641