1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Cache Allocation Technology (CAT) test 4 * 5 * Copyright (C) 2018 Intel Corporation 6 * 7 * Authors: 8 * Sai Praneeth Prakhya <sai.praneeth.prakhya@intel.com>, 9 * Fenghua Yu <fenghua.yu@intel.com> 10 */ 11 #include "resctrl.h" 12 #include <unistd.h> 13 14 #define RESULT_FILE_NAME "result_cat" 15 #define NUM_OF_RUNS 5 16 17 static int show_results_info(__u64 sum_llc_val, int no_of_bits, 18 unsigned long cache_span, 19 unsigned long num_of_runs, bool platform, 20 __s64 *prev_avg_llc_val) 21 { 22 __u64 avg_llc_val = 0; 23 int ret = 0; 24 25 avg_llc_val = sum_llc_val / num_of_runs; 26 if (*prev_avg_llc_val) { 27 ret = platform && (avg_llc_val < *prev_avg_llc_val); 28 29 ksft_print_msg("%s Check cache miss rate increased\n", 30 ret ? "Fail:" : "Pass:"); 31 } 32 *prev_avg_llc_val = avg_llc_val; 33 34 show_cache_info(no_of_bits, avg_llc_val, cache_span, true); 35 36 return ret; 37 } 38 39 /* Remove the highest bits from CBM */ 40 static unsigned long next_mask(unsigned long current_mask) 41 { 42 return current_mask & (current_mask >> 2); 43 } 44 45 static int check_results(struct resctrl_val_param *param, const char *cache_type, 46 unsigned long cache_total_size, unsigned long full_cache_mask, 47 unsigned long current_mask) 48 { 49 char *token_array[8], temp[512]; 50 __u64 sum_llc_perf_miss = 0; 51 __s64 prev_avg_llc_val = 0; 52 unsigned long alloc_size; 53 int runs = 0; 54 int fail = 0; 55 int ret; 56 FILE *fp; 57 58 ksft_print_msg("Checking for pass/fail\n"); 59 fp = fopen(param->filename, "r"); 60 if (!fp) { 61 ksft_perror("Cannot open file"); 62 63 return -1; 64 } 65 66 while (fgets(temp, sizeof(temp), fp)) { 67 char *token = strtok(temp, ":\t"); 68 int fields = 0; 69 int bits; 70 71 while (token) { 72 token_array[fields++] = token; 73 token = strtok(NULL, ":\t"); 74 } 75 76 sum_llc_perf_miss += strtoull(token_array[3], NULL, 0); 77 runs++; 78 79 if (runs < NUM_OF_RUNS) 80 continue; 81 82 if (!current_mask) { 83 ksft_print_msg("Unexpected empty cache mask\n"); 84 break; 85 } 86 87 alloc_size = cache_portion_size(cache_total_size, current_mask, full_cache_mask); 88 89 bits = count_bits(current_mask); 90 91 ret = show_results_info(sum_llc_perf_miss, bits, 92 alloc_size / 64, 93 runs, get_vendor() == ARCH_INTEL, 94 &prev_avg_llc_val); 95 if (ret) 96 fail = 1; 97 98 runs = 0; 99 sum_llc_perf_miss = 0; 100 current_mask = next_mask(current_mask); 101 } 102 103 fclose(fp); 104 105 return fail; 106 } 107 108 static void cat_test_cleanup(void) 109 { 110 remove(RESULT_FILE_NAME); 111 } 112 113 /* 114 * cat_test - Execute CAT benchmark and measure cache misses 115 * @test: Test information structure 116 * @uparams: User supplied parameters 117 * @param: Parameters passed to cat_test() 118 * @span: Buffer size for the benchmark 119 * @current_mask Start mask for the first iteration 120 * 121 * Run CAT selftest by varying the allocated cache portion and comparing the 122 * impact on cache misses (the result analysis is done in check_results() 123 * and show_results_info(), not in this function). 124 * 125 * One bit is removed from the CAT allocation bit mask (in current_mask) for 126 * each subsequent test which keeps reducing the size of the allocated cache 127 * portion. A single test flushes the buffer, reads it to warm up the cache, 128 * and reads the buffer again. The cache misses are measured during the last 129 * read pass. 130 * 131 * Return: 0 when the test was run, < 0 on error. 132 */ 133 static int cat_test(const struct resctrl_test *test, 134 const struct user_params *uparams, 135 struct resctrl_val_param *param, 136 size_t span, unsigned long current_mask) 137 { 138 struct perf_event_read pe_read; 139 struct perf_event_attr pea; 140 cpu_set_t old_affinity; 141 unsigned char *buf; 142 char schemata[64]; 143 int ret, i, pe_fd; 144 pid_t bm_pid; 145 146 if (strcmp(param->filename, "") == 0) 147 sprintf(param->filename, "stdio"); 148 149 bm_pid = getpid(); 150 151 /* Taskset benchmark to specified cpu */ 152 ret = taskset_benchmark(bm_pid, uparams->cpu, &old_affinity); 153 if (ret) 154 return ret; 155 156 /* Write benchmark to specified con_mon grp, mon_grp in resctrl FS*/ 157 ret = write_bm_pid_to_resctrl(bm_pid, param->ctrlgrp, param->mongrp); 158 if (ret) 159 goto reset_affinity; 160 161 perf_event_attr_initialize(&pea, PERF_COUNT_HW_CACHE_MISSES); 162 perf_event_initialize_read_format(&pe_read); 163 pe_fd = perf_open(&pea, bm_pid, uparams->cpu); 164 if (pe_fd < 0) { 165 ret = -1; 166 goto reset_affinity; 167 } 168 169 buf = alloc_buffer(span, 1); 170 if (!buf) { 171 ret = -1; 172 goto pe_close; 173 } 174 175 while (current_mask) { 176 snprintf(schemata, sizeof(schemata), "%lx", param->mask & ~current_mask); 177 ret = write_schemata("", schemata, uparams->cpu, test->resource); 178 if (ret) 179 goto free_buf; 180 snprintf(schemata, sizeof(schemata), "%lx", current_mask); 181 ret = write_schemata(param->ctrlgrp, schemata, uparams->cpu, test->resource); 182 if (ret) 183 goto free_buf; 184 185 for (i = 0; i < NUM_OF_RUNS; i++) { 186 mem_flush(buf, span); 187 fill_cache_read(buf, span, true); 188 189 ret = perf_event_reset_enable(pe_fd); 190 if (ret) 191 goto free_buf; 192 193 fill_cache_read(buf, span, true); 194 195 ret = perf_event_measure(pe_fd, &pe_read, param->filename, bm_pid); 196 if (ret) 197 goto free_buf; 198 } 199 current_mask = next_mask(current_mask); 200 } 201 202 free_buf: 203 free(buf); 204 pe_close: 205 close(pe_fd); 206 reset_affinity: 207 taskset_restore(bm_pid, &old_affinity); 208 209 return ret; 210 } 211 212 static int cat_run_test(const struct resctrl_test *test, const struct user_params *uparams) 213 { 214 unsigned long long_mask, start_mask, full_cache_mask; 215 unsigned long cache_total_size = 0; 216 int n = uparams->bits; 217 unsigned int start; 218 int count_of_bits; 219 size_t span; 220 int ret; 221 222 ret = get_full_cbm(test->resource, &full_cache_mask); 223 if (ret) 224 return ret; 225 /* Get the largest contiguous exclusive portion of the cache */ 226 ret = get_mask_no_shareable(test->resource, &long_mask); 227 if (ret) 228 return ret; 229 230 /* Get L3/L2 cache size */ 231 ret = get_cache_size(uparams->cpu, test->resource, &cache_total_size); 232 if (ret) 233 return ret; 234 ksft_print_msg("Cache size :%lu\n", cache_total_size); 235 236 count_of_bits = count_contiguous_bits(long_mask, &start); 237 238 if (!n) 239 n = count_of_bits / 2; 240 241 if (n > count_of_bits - 1) { 242 ksft_print_msg("Invalid input value for no_of_bits n!\n"); 243 ksft_print_msg("Please enter value in range 1 to %d\n", 244 count_of_bits - 1); 245 return -1; 246 } 247 start_mask = create_bit_mask(start, n); 248 249 struct resctrl_val_param param = { 250 .ctrlgrp = "c1", 251 .filename = RESULT_FILE_NAME, 252 .num_of_runs = 0, 253 }; 254 param.mask = long_mask; 255 span = cache_portion_size(cache_total_size, start_mask, full_cache_mask); 256 257 remove(param.filename); 258 259 ret = cat_test(test, uparams, ¶m, span, start_mask); 260 if (ret) 261 return ret; 262 263 ret = check_results(¶m, test->resource, 264 cache_total_size, full_cache_mask, start_mask); 265 return ret; 266 } 267 268 static bool arch_supports_noncont_cat(const struct resctrl_test *test) 269 { 270 unsigned int vendor_id = get_vendor(); 271 272 /* AMD and Hygon always support non-contiguous CBM. */ 273 if (vendor_id == ARCH_AMD || vendor_id == ARCH_HYGON) 274 return true; 275 276 #if defined(__i386__) || defined(__x86_64__) /* arch */ 277 unsigned int eax, ebx, ecx, edx; 278 /* Intel support for non-contiguous CBM needs to be discovered. */ 279 if (!strcmp(test->resource, "L3")) 280 __cpuid_count(0x10, 1, eax, ebx, ecx, edx); 281 else if (!strcmp(test->resource, "L2")) 282 __cpuid_count(0x10, 2, eax, ebx, ecx, edx); 283 else 284 return false; 285 286 return ((ecx >> 3) & 1); 287 #endif /* end arch */ 288 289 return false; 290 } 291 292 static int noncont_cat_run_test(const struct resctrl_test *test, 293 const struct user_params *uparams) 294 { 295 unsigned long full_cache_mask, cont_mask, noncont_mask; 296 unsigned int sparse_masks; 297 int bit_center, ret; 298 char schemata[64]; 299 300 /* Check to compare sparse_masks content to CPUID output. */ 301 ret = resource_info_unsigned_get(test->resource, "sparse_masks", &sparse_masks); 302 if (ret) 303 return ret; 304 305 if (arch_supports_noncont_cat(test) != sparse_masks) { 306 ksft_print_msg("Hardware and kernel differ on non-contiguous CBM support!\n"); 307 return 1; 308 } 309 310 /* Write checks initialization. */ 311 ret = get_full_cbm(test->resource, &full_cache_mask); 312 if (ret < 0) 313 return ret; 314 bit_center = count_bits(full_cache_mask) / 2; 315 316 /* 317 * The bit_center needs to be at least 3 to properly calculate the CBM 318 * hole in the noncont_mask. If it's smaller return an error since the 319 * cache mask is too short and that shouldn't happen. 320 */ 321 if (bit_center < 3) 322 return -EINVAL; 323 cont_mask = full_cache_mask >> bit_center; 324 325 /* Contiguous mask write check. */ 326 snprintf(schemata, sizeof(schemata), "%lx", cont_mask); 327 ret = write_schemata("", schemata, uparams->cpu, test->resource); 328 if (ret) { 329 ksft_print_msg("Write of contiguous CBM failed\n"); 330 return 1; 331 } 332 333 /* 334 * Non-contiguous mask write check. CBM has a 0xf hole approximately in the middle. 335 * Output is compared with support information to catch any edge case errors. 336 */ 337 noncont_mask = ~(0xfUL << (bit_center - 2)) & full_cache_mask; 338 snprintf(schemata, sizeof(schemata), "%lx", noncont_mask); 339 ret = write_schemata("", schemata, uparams->cpu, test->resource); 340 if (ret && sparse_masks) 341 ksft_print_msg("Non-contiguous CBMs supported but write of non-contiguous CBM failed\n"); 342 else if (ret && !sparse_masks) 343 ksft_print_msg("Non-contiguous CBMs not supported and write of non-contiguous CBM failed as expected\n"); 344 else if (!ret && !sparse_masks) 345 ksft_print_msg("Non-contiguous CBMs not supported but write of non-contiguous CBM succeeded\n"); 346 347 return !ret == !sparse_masks; 348 } 349 350 static bool noncont_cat_feature_check(const struct resctrl_test *test) 351 { 352 if (!resctrl_resource_exists(test->resource)) 353 return false; 354 355 return resource_info_file_exists(test->resource, "sparse_masks"); 356 } 357 358 struct resctrl_test l3_cat_test = { 359 .name = "L3_CAT", 360 .group = "CAT", 361 .resource = "L3", 362 .feature_check = test_resource_feature_check, 363 .run_test = cat_run_test, 364 .cleanup = cat_test_cleanup, 365 }; 366 367 struct resctrl_test l3_noncont_cat_test = { 368 .name = "L3_NONCONT_CAT", 369 .group = "CAT", 370 .resource = "L3", 371 .feature_check = noncont_cat_feature_check, 372 .run_test = noncont_cat_run_test, 373 }; 374 375 struct resctrl_test l2_noncont_cat_test = { 376 .name = "L2_NONCONT_CAT", 377 .group = "CAT", 378 .resource = "L2", 379 .feature_check = noncont_cat_feature_check, 380 .run_test = noncont_cat_run_test, 381 }; 382