xref: /linux/tools/testing/selftests/powerpc/tm/tm-resched-dscr.c (revision b319ee8445961c5f7b2fd199c0ef99c418ee2d4a)
1 /* Test context switching to see if the DSCR SPR is correctly preserved
2  * when within a transaction.
3  *
4  * Note: We assume that the DSCR has been left at the default value (0)
5  * for all CPUs.
6  *
7  * Method:
8  *
9  * Set a value into the DSCR.
10  *
11  * Start a transaction, and suspend it (*).
12  *
13  * Hard loop checking to see if the transaction has become doomed.
14  *
15  * Now that we *may* have been preempted, record the DSCR and TEXASR SPRS.
16  *
17  * If the abort was because of a context switch, check the DSCR value.
18  * Otherwise, try again.
19  *
20  * (*) If the transaction is not suspended we can't see the problem because
21  * the transaction abort handler will restore the DSCR to it's checkpointed
22  * value before we regain control.
23  */
24 
25 #include <inttypes.h>
26 #include <stdio.h>
27 #include <stdlib.h>
28 #include <assert.h>
29 #include <asm/tm.h>
30 
31 #include "utils.h"
32 #include "tm.h"
33 
34 #define TBEGIN          ".long 0x7C00051D ;"
35 #define TEND            ".long 0x7C00055D ;"
36 #define TCHECK          ".long 0x7C00059C ;"
37 #define TSUSPEND        ".long 0x7C0005DD ;"
38 #define TRESUME         ".long 0x7C2005DD ;"
39 #define SPRN_TEXASR     0x82
40 #define SPRN_DSCR       0x03
41 
42 int test_body(void)
43 {
44 	uint64_t rv, dscr1 = 1, dscr2, texasr;
45 
46 	SKIP_IF(!have_htm());
47 
48 	printf("Check DSCR TM context switch: ");
49 	fflush(stdout);
50 	for (;;) {
51 		rv = 1;
52 		asm __volatile__ (
53 			/* set a known value into the DSCR */
54 			"ld      3, %[dscr1];"
55 			"mtspr   %[sprn_dscr], 3;"
56 
57 			/* start and suspend a transaction */
58 			TBEGIN
59 			"beq     1f;"
60 			TSUSPEND
61 
62 			/* hard loop until the transaction becomes doomed */
63 			"2: ;"
64 			TCHECK
65 			"bc      4, 0, 2b;"
66 
67 			/* record DSCR and TEXASR */
68 			"mfspr   3, %[sprn_dscr];"
69 			"std     3, %[dscr2];"
70 			"mfspr   3, %[sprn_texasr];"
71 			"std     3, %[texasr];"
72 
73 			TRESUME
74 			TEND
75 			"li      %[rv], 0;"
76 			"1: ;"
77 			: [rv]"=r"(rv), [dscr2]"=m"(dscr2), [texasr]"=m"(texasr)
78 			: [dscr1]"m"(dscr1)
79 			, [sprn_dscr]"i"(SPRN_DSCR), [sprn_texasr]"i"(SPRN_TEXASR)
80 			: "memory", "r3"
81 		);
82 		assert(rv); /* make sure the transaction aborted */
83 		if ((texasr >> 56) != TM_CAUSE_RESCHED) {
84 			putchar('.');
85 			fflush(stdout);
86 			continue;
87 		}
88 		if (dscr2 != dscr1) {
89 			printf(" FAIL\n");
90 			return 1;
91 		} else {
92 			printf(" OK\n");
93 			return 0;
94 		}
95 	}
96 }
97 
98 int main(void)
99 {
100 	return test_harness(test_body, "tm_resched_dscr");
101 }
102