xref: /linux/tools/testing/selftests/powerpc/tm/tm-resched-dscr.c (revision 1ebfc603d046f1dda6507d11803f9b4046cee712)
1 /* Test context switching to see if the DSCR SPR is correctly preserved
2  * when within a transaction.
3  *
4  * Note: We assume that the DSCR has been left at the default value (0)
5  * for all CPUs.
6  *
7  * Method:
8  *
9  * Set a value into the DSCR.
10  *
11  * Start a transaction, and suspend it (*).
12  *
13  * Hard loop checking to see if the transaction has become doomed.
14  *
15  * Now that we *may* have been preempted, record the DSCR and TEXASR SPRS.
16  *
17  * If the abort was because of a context switch, check the DSCR value.
18  * Otherwise, try again.
19  *
20  * (*) If the transaction is not suspended we can't see the problem because
21  * the transaction abort handler will restore the DSCR to it's checkpointed
22  * value before we regain control.
23  */
24 
25 #include <inttypes.h>
26 #include <stdio.h>
27 #include <stdlib.h>
28 #include <assert.h>
29 #include <asm/tm.h>
30 
31 #include "utils.h"
32 #include "tm.h"
33 #include "../pmu/lib.h"
34 
35 #define SPRN_DSCR       0x03
36 
37 int test_body(void)
38 {
39 	uint64_t rv, dscr1 = 1, dscr2, texasr;
40 
41 	SKIP_IF(!have_htm());
42 
43 	printf("Check DSCR TM context switch: ");
44 	fflush(stdout);
45 	for (;;) {
46 		asm __volatile__ (
47 			/* set a known value into the DSCR */
48 			"ld      3, %[dscr1];"
49 			"mtspr   %[sprn_dscr], 3;"
50 
51 			"li      %[rv], 1;"
52 			/* start and suspend a transaction */
53 			"tbegin.;"
54 			"beq     1f;"
55 			"tsuspend.;"
56 
57 			/* hard loop until the transaction becomes doomed */
58 			"2: ;"
59 			"tcheck 0;"
60 			"bc      4, 0, 2b;"
61 
62 			/* record DSCR and TEXASR */
63 			"mfspr   3, %[sprn_dscr];"
64 			"std     3, %[dscr2];"
65 			"mfspr   3, %[sprn_texasr];"
66 			"std     3, %[texasr];"
67 
68 			"tresume.;"
69 			"tend.;"
70 			"li      %[rv], 0;"
71 			"1: ;"
72 			: [rv]"=r"(rv), [dscr2]"=m"(dscr2), [texasr]"=m"(texasr)
73 			: [dscr1]"m"(dscr1)
74 			, [sprn_dscr]"i"(SPRN_DSCR), [sprn_texasr]"i"(SPRN_TEXASR)
75 			: "memory", "r3"
76 		);
77 		assert(rv); /* make sure the transaction aborted */
78 		if ((texasr >> 56) != TM_CAUSE_RESCHED) {
79 			continue;
80 		}
81 		if (dscr2 != dscr1) {
82 			printf(" FAIL\n");
83 			return 1;
84 		} else {
85 			printf(" OK\n");
86 			return 0;
87 		}
88 	}
89 }
90 
91 static int tm_resched_dscr(void)
92 {
93 	return eat_cpu(test_body);
94 }
95 
96 int main(int argc, const char *argv[])
97 {
98 	return test_harness(tm_resched_dscr, "tm_resched_dscr");
99 }
100