1*2874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 215ec3997SSimon Guo /* 315ec3997SSimon Guo * Copyright 2016, Cyril Bur, IBM Corp. 415ec3997SSimon Guo */ 515ec3997SSimon Guo 615ec3997SSimon Guo #ifndef _SELFTESTS_POWERPC_GPR_ASM_H 715ec3997SSimon Guo #define _SELFTESTS_POWERPC_GPR_ASM_H 815ec3997SSimon Guo 915ec3997SSimon Guo #include "basic_asm.h" 1015ec3997SSimon Guo 1115ec3997SSimon Guo #define __PUSH_NVREGS(top_pos); \ 1215ec3997SSimon Guo std r31,(top_pos)(%r1); \ 1315ec3997SSimon Guo std r30,(top_pos - 8)(%r1); \ 1415ec3997SSimon Guo std r29,(top_pos - 16)(%r1); \ 1515ec3997SSimon Guo std r28,(top_pos - 24)(%r1); \ 1615ec3997SSimon Guo std r27,(top_pos - 32)(%r1); \ 1715ec3997SSimon Guo std r26,(top_pos - 40)(%r1); \ 1815ec3997SSimon Guo std r25,(top_pos - 48)(%r1); \ 1915ec3997SSimon Guo std r24,(top_pos - 56)(%r1); \ 2015ec3997SSimon Guo std r23,(top_pos - 64)(%r1); \ 2115ec3997SSimon Guo std r22,(top_pos - 72)(%r1); \ 2215ec3997SSimon Guo std r21,(top_pos - 80)(%r1); \ 2315ec3997SSimon Guo std r20,(top_pos - 88)(%r1); \ 2415ec3997SSimon Guo std r19,(top_pos - 96)(%r1); \ 2515ec3997SSimon Guo std r18,(top_pos - 104)(%r1); \ 2615ec3997SSimon Guo std r17,(top_pos - 112)(%r1); \ 2715ec3997SSimon Guo std r16,(top_pos - 120)(%r1); \ 2815ec3997SSimon Guo std r15,(top_pos - 128)(%r1); \ 2915ec3997SSimon Guo std r14,(top_pos - 136)(%r1) 3015ec3997SSimon Guo 3115ec3997SSimon Guo #define __POP_NVREGS(top_pos); \ 3215ec3997SSimon Guo ld r31,(top_pos)(%r1); \ 3315ec3997SSimon Guo ld r30,(top_pos - 8)(%r1); \ 3415ec3997SSimon Guo ld r29,(top_pos - 16)(%r1); \ 3515ec3997SSimon Guo ld r28,(top_pos - 24)(%r1); \ 3615ec3997SSimon Guo ld r27,(top_pos - 32)(%r1); \ 3715ec3997SSimon Guo ld r26,(top_pos - 40)(%r1); \ 3815ec3997SSimon Guo ld r25,(top_pos - 48)(%r1); \ 3915ec3997SSimon Guo ld r24,(top_pos - 56)(%r1); \ 4015ec3997SSimon Guo ld r23,(top_pos - 64)(%r1); \ 4115ec3997SSimon Guo ld r22,(top_pos - 72)(%r1); \ 4215ec3997SSimon Guo ld r21,(top_pos - 80)(%r1); \ 4315ec3997SSimon Guo ld r20,(top_pos - 88)(%r1); \ 4415ec3997SSimon Guo ld r19,(top_pos - 96)(%r1); \ 4515ec3997SSimon Guo ld r18,(top_pos - 104)(%r1); \ 4615ec3997SSimon Guo ld r17,(top_pos - 112)(%r1); \ 4715ec3997SSimon Guo ld r16,(top_pos - 120)(%r1); \ 4815ec3997SSimon Guo ld r15,(top_pos - 128)(%r1); \ 4915ec3997SSimon Guo ld r14,(top_pos - 136)(%r1) 5015ec3997SSimon Guo 5115ec3997SSimon Guo #define PUSH_NVREGS(stack_size) \ 5215ec3997SSimon Guo __PUSH_NVREGS(stack_size + STACK_FRAME_MIN_SIZE) 5315ec3997SSimon Guo 5415ec3997SSimon Guo /* 18 NV FPU REGS */ 5515ec3997SSimon Guo #define PUSH_NVREGS_BELOW_FPU(stack_size) \ 5615ec3997SSimon Guo __PUSH_NVREGS(stack_size + STACK_FRAME_MIN_SIZE - (18 * 8)) 5715ec3997SSimon Guo 5815ec3997SSimon Guo #define POP_NVREGS(stack_size) \ 5915ec3997SSimon Guo __POP_NVREGS(stack_size + STACK_FRAME_MIN_SIZE) 6015ec3997SSimon Guo 6115ec3997SSimon Guo /* 18 NV FPU REGS */ 6215ec3997SSimon Guo #define POP_NVREGS_BELOW_FPU(stack_size) \ 6315ec3997SSimon Guo __POP_NVREGS(stack_size + STACK_FRAME_MIN_SIZE - (18 * 8)) 6415ec3997SSimon Guo 6515ec3997SSimon Guo /* 6615ec3997SSimon Guo * Careful calling this, it will 'clobber' NVGPRs (by design) 6715ec3997SSimon Guo * Don't call this from C 6815ec3997SSimon Guo */ 6915ec3997SSimon Guo FUNC_START(load_gpr) 7015ec3997SSimon Guo ld r14,0(r3) 7115ec3997SSimon Guo ld r15,8(r3) 7215ec3997SSimon Guo ld r16,16(r3) 7315ec3997SSimon Guo ld r17,24(r3) 7415ec3997SSimon Guo ld r18,32(r3) 7515ec3997SSimon Guo ld r19,40(r3) 7615ec3997SSimon Guo ld r20,48(r3) 7715ec3997SSimon Guo ld r21,56(r3) 7815ec3997SSimon Guo ld r22,64(r3) 7915ec3997SSimon Guo ld r23,72(r3) 8015ec3997SSimon Guo ld r24,80(r3) 8115ec3997SSimon Guo ld r25,88(r3) 8215ec3997SSimon Guo ld r26,96(r3) 8315ec3997SSimon Guo ld r27,104(r3) 8415ec3997SSimon Guo ld r28,112(r3) 8515ec3997SSimon Guo ld r29,120(r3) 8615ec3997SSimon Guo ld r30,128(r3) 8715ec3997SSimon Guo ld r31,136(r3) 8815ec3997SSimon Guo blr 8915ec3997SSimon Guo FUNC_END(load_gpr) 9015ec3997SSimon Guo 9115ec3997SSimon Guo 9215ec3997SSimon Guo #endif /* _SELFTESTS_POWERPC_GPR_ASM_H */ 93