1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef _PKEYS_X86_H 4 #define _PKEYS_X86_H 5 6 #ifdef __i386__ 7 8 #define REG_IP_IDX REG_EIP 9 #define si_pkey_offset 0x14 10 11 #else 12 13 #define REG_IP_IDX REG_RIP 14 #define si_pkey_offset 0x20 15 16 #endif 17 18 #define MCONTEXT_IP(mc) mc.gregs[REG_IP_IDX] 19 #define MCONTEXT_TRAPNO(mc) mc.gregs[REG_TRAPNO] 20 #define MCONTEXT_FPREGS 21 22 #ifndef PKEY_DISABLE_ACCESS 23 # define PKEY_DISABLE_ACCESS 0x1 24 #endif 25 26 #ifndef PKEY_DISABLE_WRITE 27 # define PKEY_DISABLE_WRITE 0x2 28 #endif 29 30 #define NR_PKEYS 16 31 #define NR_RESERVED_PKEYS 2 /* pkey-0 and exec-only-pkey */ 32 #define PKEY_BITS_PER_PKEY 2 33 #define HPAGE_SIZE (1UL<<21) 34 #define PAGE_SIZE 4096 35 #define MB (1<<20) 36 37 static inline void __page_o_noops(void) 38 { 39 /* 8-bytes of instruction * 512 bytes = 1 page */ 40 asm(".rept 512 ; nopl 0x7eeeeeee(%eax) ; .endr"); 41 } 42 43 static inline u64 __read_pkey_reg(void) 44 { 45 unsigned int eax, edx; 46 unsigned int ecx = 0; 47 unsigned pkey_reg; 48 49 asm volatile(".byte 0x0f,0x01,0xee\n\t" 50 : "=a" (eax), "=d" (edx) 51 : "c" (ecx)); 52 pkey_reg = eax; 53 return pkey_reg; 54 } 55 56 static inline void __write_pkey_reg(u64 pkey_reg) 57 { 58 unsigned int eax = pkey_reg; 59 unsigned int ecx = 0; 60 unsigned int edx = 0; 61 62 dprintf4("%s() changing %016llx to %016llx\n", __func__, 63 __read_pkey_reg(), pkey_reg); 64 asm volatile(".byte 0x0f,0x01,0xef\n\t" 65 : : "a" (eax), "c" (ecx), "d" (edx)); 66 assert(pkey_reg == __read_pkey_reg()); 67 } 68 69 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx) */ 70 #define X86_FEATURE_PKU (1<<3) /* Protection Keys for Userspace */ 71 #define X86_FEATURE_OSPKE (1<<4) /* OS Protection Keys Enable */ 72 73 static inline int cpu_has_pkeys(void) 74 { 75 unsigned int eax; 76 unsigned int ebx; 77 unsigned int ecx; 78 unsigned int edx; 79 80 __cpuid_count(0x7, 0x0, eax, ebx, ecx, edx); 81 82 if (!(ecx & X86_FEATURE_PKU)) { 83 dprintf2("cpu does not have PKU\n"); 84 return 0; 85 } 86 if (!(ecx & X86_FEATURE_OSPKE)) { 87 dprintf2("cpu does not have OSPKE\n"); 88 return 0; 89 } 90 return 1; 91 } 92 93 static inline int cpu_max_xsave_size(void) 94 { 95 unsigned long XSTATE_CPUID = 0xd; 96 unsigned int eax; 97 unsigned int ebx; 98 unsigned int ecx; 99 unsigned int edx; 100 101 __cpuid_count(XSTATE_CPUID, 0, eax, ebx, ecx, edx); 102 return ecx; 103 } 104 105 static inline u32 pkey_bit_position(int pkey) 106 { 107 return pkey * PKEY_BITS_PER_PKEY; 108 } 109 110 #define XSTATE_PKEY_BIT (9) 111 #define XSTATE_PKEY 0x200 112 #define XSTATE_BV_OFFSET 512 113 114 int pkey_reg_xstate_offset(void) 115 { 116 unsigned int eax; 117 unsigned int ebx; 118 unsigned int ecx; 119 unsigned int edx; 120 int xstate_offset; 121 int xstate_size = 0; 122 unsigned long XSTATE_CPUID = 0xd; 123 int leaf; 124 125 /* assume that XSTATE_PKEY is set in XCR0 */ 126 leaf = XSTATE_PKEY_BIT; 127 { 128 __cpuid_count(XSTATE_CPUID, leaf, eax, ebx, ecx, edx); 129 130 if (leaf == XSTATE_PKEY_BIT) { 131 xstate_offset = ebx; 132 xstate_size = eax; 133 } 134 } 135 136 if (xstate_size == 0) { 137 printf("could not find size/offset of PKEY in xsave state\n"); 138 return 0; 139 } 140 141 return xstate_offset; 142 } 143 144 static inline int get_arch_reserved_keys(void) 145 { 146 return NR_RESERVED_PKEYS; 147 } 148 149 void expect_fault_on_read_execonly_key(void *p1, int pkey) 150 { 151 int ptr_contents; 152 153 ptr_contents = read_ptr(p1); 154 dprintf2("ptr (%p) contents@%d: %x\n", p1, __LINE__, ptr_contents); 155 expected_pkey_fault(pkey); 156 } 157 158 void *malloc_pkey_with_mprotect_subpage(long size, int prot, u16 pkey) 159 { 160 return PTR_ERR_ENOTSUP; 161 } 162 163 #endif /* _PKEYS_X86_H */ 164