1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <fcntl.h> 3 #include <stdio.h> 4 #include <stdlib.h> 5 #include <string.h> 6 #include <sys/ioctl.h> 7 8 #include "apic.h" 9 #include "kvm_util.h" 10 #include "processor.h" 11 #include "test_util.h" 12 13 struct xapic_vcpu { 14 struct kvm_vcpu *vcpu; 15 bool is_x2apic; 16 }; 17 18 static void xapic_guest_code(void) 19 { 20 asm volatile("cli"); 21 22 xapic_enable(); 23 24 while (1) { 25 uint64_t val = (u64)xapic_read_reg(APIC_IRR) | 26 (u64)xapic_read_reg(APIC_IRR + 0x10) << 32; 27 28 xapic_write_reg(APIC_ICR2, val >> 32); 29 xapic_write_reg(APIC_ICR, val); 30 GUEST_SYNC(val); 31 } 32 } 33 34 static void x2apic_guest_code(void) 35 { 36 asm volatile("cli"); 37 38 x2apic_enable(); 39 40 do { 41 uint64_t val = x2apic_read_reg(APIC_IRR) | 42 x2apic_read_reg(APIC_IRR + 0x10) << 32; 43 44 x2apic_write_reg(APIC_ICR, val); 45 GUEST_SYNC(val); 46 } while (1); 47 } 48 49 static void ____test_icr(struct xapic_vcpu *x, uint64_t val) 50 { 51 struct kvm_vcpu *vcpu = x->vcpu; 52 struct kvm_lapic_state xapic; 53 struct ucall uc; 54 uint64_t icr; 55 56 /* 57 * Tell the guest what ICR value to write. Use the IRR to pass info, 58 * all bits are valid and should not be modified by KVM (ignoring the 59 * fact that vectors 0-15 are technically illegal). 60 */ 61 vcpu_ioctl(vcpu, KVM_GET_LAPIC, &xapic); 62 *((u32 *)&xapic.regs[APIC_IRR]) = val; 63 *((u32 *)&xapic.regs[APIC_IRR + 0x10]) = val >> 32; 64 vcpu_ioctl(vcpu, KVM_SET_LAPIC, &xapic); 65 66 vcpu_run(vcpu); 67 TEST_ASSERT_EQ(get_ucall(vcpu, &uc), UCALL_SYNC); 68 TEST_ASSERT_EQ(uc.args[1], val); 69 70 vcpu_ioctl(vcpu, KVM_GET_LAPIC, &xapic); 71 icr = (u64)(*((u32 *)&xapic.regs[APIC_ICR])) | 72 (u64)(*((u32 *)&xapic.regs[APIC_ICR2])) << 32; 73 if (!x->is_x2apic) { 74 val &= (-1u | (0xffull << (32 + 24))); 75 TEST_ASSERT_EQ(icr, val & ~APIC_ICR_BUSY); 76 } else { 77 TEST_ASSERT_EQ(icr & ~APIC_ICR_BUSY, val & ~APIC_ICR_BUSY); 78 } 79 } 80 81 #define X2APIC_RSVED_BITS_MASK (GENMASK_ULL(31,20) | \ 82 GENMASK_ULL(17,16) | \ 83 GENMASK_ULL(13,13)) 84 85 static void __test_icr(struct xapic_vcpu *x, uint64_t val) 86 { 87 if (x->is_x2apic) { 88 /* Hardware writing vICR register requires reserved bits 31:20, 89 * 17:16 and 13 kept as zero to avoid #GP exception. Data value 90 * written to vICR should mask out those bits above. 91 */ 92 val &= ~X2APIC_RSVED_BITS_MASK; 93 } 94 ____test_icr(x, val | APIC_ICR_BUSY); 95 ____test_icr(x, val & ~(u64)APIC_ICR_BUSY); 96 } 97 98 static void test_icr(struct xapic_vcpu *x) 99 { 100 struct kvm_vcpu *vcpu = x->vcpu; 101 uint64_t icr, i, j; 102 103 icr = APIC_DEST_SELF | APIC_INT_ASSERT | APIC_DM_FIXED; 104 for (i = 0; i <= 0xff; i++) 105 __test_icr(x, icr | i); 106 107 icr = APIC_INT_ASSERT | APIC_DM_FIXED; 108 for (i = 0; i <= 0xff; i++) 109 __test_icr(x, icr | i); 110 111 /* 112 * Send all flavors of IPIs to non-existent vCPUs. TODO: use number of 113 * vCPUs, not vcpu.id + 1. Arbitrarily use vector 0xff. 114 */ 115 icr = APIC_INT_ASSERT | 0xff; 116 for (i = 0; i < 0xff; i++) { 117 if (i == vcpu->id) 118 continue; 119 for (j = 0; j < 8; j++) 120 __test_icr(x, i << (32 + 24) | icr | (j << 8)); 121 } 122 123 /* And again with a shorthand destination for all types of IPIs. */ 124 icr = APIC_DEST_ALLBUT | APIC_INT_ASSERT; 125 for (i = 0; i < 8; i++) 126 __test_icr(x, icr | (i << 8)); 127 128 /* And a few garbage value, just make sure it's an IRQ (blocked). */ 129 __test_icr(x, 0xa5a5a5a5a5a5a5a5 & ~APIC_DM_FIXED_MASK); 130 __test_icr(x, 0x5a5a5a5a5a5a5a5a & ~APIC_DM_FIXED_MASK); 131 __test_icr(x, -1ull & ~APIC_DM_FIXED_MASK); 132 } 133 134 static void __test_apic_id(struct kvm_vcpu *vcpu, uint64_t apic_base) 135 { 136 uint32_t apic_id, expected; 137 struct kvm_lapic_state xapic; 138 139 vcpu_set_msr(vcpu, MSR_IA32_APICBASE, apic_base); 140 141 vcpu_ioctl(vcpu, KVM_GET_LAPIC, &xapic); 142 143 expected = apic_base & X2APIC_ENABLE ? vcpu->id : vcpu->id << 24; 144 apic_id = *((u32 *)&xapic.regs[APIC_ID]); 145 146 TEST_ASSERT(apic_id == expected, 147 "APIC_ID not set back to %s format; wanted = %x, got = %x", 148 (apic_base & X2APIC_ENABLE) ? "x2APIC" : "xAPIC", 149 expected, apic_id); 150 } 151 152 /* 153 * Verify that KVM switches the APIC_ID between xAPIC and x2APIC when userspace 154 * stuffs MSR_IA32_APICBASE. Setting the APIC_ID when x2APIC is enabled and 155 * when the APIC transitions for DISABLED to ENABLED is architectural behavior 156 * (on Intel), whereas the x2APIC => xAPIC transition behavior is KVM ABI since 157 * attempted to transition from x2APIC to xAPIC without disabling the APIC is 158 * architecturally disallowed. 159 */ 160 static void test_apic_id(void) 161 { 162 const uint32_t NR_VCPUS = 3; 163 struct kvm_vcpu *vcpus[NR_VCPUS]; 164 uint64_t apic_base; 165 struct kvm_vm *vm; 166 int i; 167 168 vm = vm_create_with_vcpus(NR_VCPUS, NULL, vcpus); 169 vm_enable_cap(vm, KVM_CAP_X2APIC_API, KVM_X2APIC_API_USE_32BIT_IDS); 170 171 for (i = 0; i < NR_VCPUS; i++) { 172 apic_base = vcpu_get_msr(vcpus[i], MSR_IA32_APICBASE); 173 174 TEST_ASSERT(apic_base & MSR_IA32_APICBASE_ENABLE, 175 "APIC not in ENABLED state at vCPU RESET"); 176 TEST_ASSERT(!(apic_base & X2APIC_ENABLE), 177 "APIC not in xAPIC mode at vCPU RESET"); 178 179 __test_apic_id(vcpus[i], apic_base); 180 __test_apic_id(vcpus[i], apic_base | X2APIC_ENABLE); 181 __test_apic_id(vcpus[i], apic_base); 182 } 183 184 kvm_vm_free(vm); 185 } 186 187 static void test_x2apic_id(void) 188 { 189 struct kvm_lapic_state lapic = {}; 190 struct kvm_vcpu *vcpu; 191 struct kvm_vm *vm; 192 int i; 193 194 vm = vm_create_with_one_vcpu(&vcpu, NULL); 195 vcpu_set_msr(vcpu, MSR_IA32_APICBASE, MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 196 197 /* 198 * Try stuffing a modified x2APIC ID, KVM should ignore the value and 199 * always return the vCPU's default/readonly x2APIC ID. 200 */ 201 for (i = 0; i <= 0xff; i++) { 202 *(u32 *)(lapic.regs + APIC_ID) = i << 24; 203 *(u32 *)(lapic.regs + APIC_SPIV) = APIC_SPIV_APIC_ENABLED; 204 vcpu_ioctl(vcpu, KVM_SET_LAPIC, &lapic); 205 206 vcpu_ioctl(vcpu, KVM_GET_LAPIC, &lapic); 207 TEST_ASSERT(*((u32 *)&lapic.regs[APIC_ID]) == vcpu->id << 24, 208 "x2APIC ID should be fully readonly"); 209 } 210 211 kvm_vm_free(vm); 212 } 213 214 int main(int argc, char *argv[]) 215 { 216 struct xapic_vcpu x = { 217 .vcpu = NULL, 218 .is_x2apic = true, 219 }; 220 struct kvm_vm *vm; 221 222 vm = vm_create_with_one_vcpu(&x.vcpu, x2apic_guest_code); 223 test_icr(&x); 224 kvm_vm_free(vm); 225 226 /* 227 * Use a second VM for the xAPIC test so that x2APIC can be hidden from 228 * the guest in order to test AVIC. KVM disallows changing CPUID after 229 * KVM_RUN and AVIC is disabled if _any_ vCPU is allowed to use x2APIC. 230 */ 231 vm = vm_create_with_one_vcpu(&x.vcpu, xapic_guest_code); 232 x.is_x2apic = false; 233 234 vcpu_clear_cpuid_feature(x.vcpu, X86_FEATURE_X2APIC); 235 236 virt_pg_map(vm, APIC_DEFAULT_GPA, APIC_DEFAULT_GPA); 237 test_icr(&x); 238 kvm_vm_free(vm); 239 240 test_apic_id(); 241 test_x2apic_id(); 242 } 243