1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2021, Red Hat, Inc. 4 * 5 * Tests for Hyper-V features enablement 6 */ 7 #include <asm/kvm_para.h> 8 #include <linux/kvm_para.h> 9 #include <stdint.h> 10 11 #include "test_util.h" 12 #include "kvm_util.h" 13 #include "processor.h" 14 #include "hyperv.h" 15 16 /* 17 * HYPERV_CPUID_ENLIGHTMENT_INFO.EBX is not a 'feature' CPUID leaf 18 * but to activate the feature it is sufficient to set it to a non-zero 19 * value. Use BIT(0) for that. 20 */ 21 #define HV_PV_SPINLOCKS_TEST \ 22 KVM_X86_CPU_FEATURE(HYPERV_CPUID_ENLIGHTMENT_INFO, 0, EBX, 0) 23 24 struct msr_data { 25 u32 idx; 26 bool fault_expected; 27 bool write; 28 u64 write_val; 29 bool reset_expected; 30 }; 31 32 struct hcall_data { 33 u64 control; 34 u64 expect; 35 bool ud_expected; 36 }; 37 38 static bool is_write_only_msr(u32 msr) 39 { 40 return msr == HV_X64_MSR_EOI; 41 } 42 43 static void guest_msr(struct msr_data *msr) 44 { 45 u8 vector = 0; 46 u64 msr_val = 0; 47 48 GUEST_ASSERT(msr->idx); 49 50 if (msr->write) 51 vector = wrmsr_safe(msr->idx, msr->write_val); 52 53 if (!vector && (!msr->write || !is_write_only_msr(msr->idx))) 54 vector = rdmsr_safe(msr->idx, &msr_val); 55 56 if (msr->fault_expected) 57 __GUEST_ASSERT(vector == GP_VECTOR, 58 "Expected #GP on %sMSR(0x%x), got %s", 59 msr->write ? "WR" : "RD", msr->idx, ex_str(vector)); 60 else 61 __GUEST_ASSERT(!vector, 62 "Expected success on %sMSR(0x%x), got %s", 63 msr->write ? "WR" : "RD", msr->idx, ex_str(vector)); 64 65 if (vector || is_write_only_msr(msr->idx)) 66 goto done; 67 68 if (msr->write) 69 __GUEST_ASSERT(!vector, 70 "WRMSR(0x%x) to '0x%lx', RDMSR read '0x%lx'", 71 msr->idx, msr->write_val, msr_val); 72 73 /* Invariant TSC bit appears when TSC invariant control MSR is written to */ 74 if (msr->idx == HV_X64_MSR_TSC_INVARIANT_CONTROL) { 75 if (!this_cpu_has(HV_ACCESS_TSC_INVARIANT)) 76 GUEST_ASSERT(this_cpu_has(X86_FEATURE_INVTSC)); 77 else 78 GUEST_ASSERT(this_cpu_has(X86_FEATURE_INVTSC) == 79 !!(msr_val & HV_INVARIANT_TSC_EXPOSED)); 80 } 81 82 done: 83 GUEST_DONE(); 84 } 85 86 static void guest_hcall(gpa_t pgs_gpa, struct hcall_data *hcall) 87 { 88 u64 res, input, output; 89 u8 vector; 90 91 GUEST_ASSERT_NE(hcall->control, 0); 92 93 wrmsr(HV_X64_MSR_GUEST_OS_ID, HYPERV_LINUX_OS_ID); 94 wrmsr(HV_X64_MSR_HYPERCALL, pgs_gpa); 95 96 if (!(hcall->control & HV_HYPERCALL_FAST_BIT)) { 97 input = pgs_gpa; 98 output = pgs_gpa + PAGE_SIZE; 99 } else { 100 input = output = 0; 101 } 102 103 vector = __hyperv_hypercall(hcall->control, input, output, &res); 104 if (hcall->ud_expected) { 105 __GUEST_ASSERT(vector == UD_VECTOR, 106 "Expected #UD for control '%lu', got %s", 107 hcall->control, ex_str(vector)); 108 } else { 109 __GUEST_ASSERT(!vector, 110 "Expected no exception for control '%lu', got %s", 111 hcall->control, ex_str(vector)); 112 GUEST_ASSERT_EQ(res, hcall->expect); 113 } 114 115 GUEST_DONE(); 116 } 117 118 static void vcpu_reset_hv_cpuid(struct kvm_vcpu *vcpu) 119 { 120 /* 121 * Enable all supported Hyper-V features, then clear the leafs holding 122 * the features that will be tested one by one. 123 */ 124 vcpu_set_hv_cpuid(vcpu); 125 126 vcpu_clear_cpuid_entry(vcpu, HYPERV_CPUID_FEATURES); 127 vcpu_clear_cpuid_entry(vcpu, HYPERV_CPUID_ENLIGHTMENT_INFO); 128 vcpu_clear_cpuid_entry(vcpu, HYPERV_CPUID_SYNDBG_PLATFORM_CAPABILITIES); 129 } 130 131 static void guest_test_msrs_access(void) 132 { 133 struct kvm_cpuid2 *prev_cpuid = NULL; 134 struct kvm_vcpu *vcpu; 135 struct kvm_vm *vm; 136 struct ucall uc; 137 int stage = 0; 138 gva_t msr_gva; 139 struct msr_data *msr; 140 bool has_invtsc = kvm_cpu_has(X86_FEATURE_INVTSC); 141 142 while (true) { 143 vm = vm_create_with_one_vcpu(&vcpu, guest_msr); 144 145 msr_gva = vm_alloc_page(vm); 146 memset(addr_gva2hva(vm, msr_gva), 0x0, getpagesize()); 147 msr = addr_gva2hva(vm, msr_gva); 148 149 vcpu_args_set(vcpu, 1, msr_gva); 150 vcpu_enable_cap(vcpu, KVM_CAP_HYPERV_ENFORCE_CPUID, 1); 151 152 if (!prev_cpuid) { 153 vcpu_reset_hv_cpuid(vcpu); 154 155 prev_cpuid = allocate_kvm_cpuid2(vcpu->cpuid->nent); 156 } else { 157 vcpu_init_cpuid(vcpu, prev_cpuid); 158 } 159 160 /* TODO: Make this entire test easier to maintain. */ 161 if (stage >= 21) 162 vcpu_enable_cap(vcpu, KVM_CAP_HYPERV_SYNIC2, 0); 163 164 switch (stage) { 165 case 0: 166 /* 167 * Only available when Hyper-V identification is set 168 */ 169 msr->idx = HV_X64_MSR_GUEST_OS_ID; 170 msr->write = false; 171 msr->fault_expected = true; 172 break; 173 case 1: 174 msr->idx = HV_X64_MSR_HYPERCALL; 175 msr->write = false; 176 msr->fault_expected = true; 177 break; 178 case 2: 179 vcpu_set_cpuid_feature(vcpu, HV_MSR_HYPERCALL_AVAILABLE); 180 /* 181 * HV_X64_MSR_GUEST_OS_ID has to be written first to make 182 * HV_X64_MSR_HYPERCALL available. 183 */ 184 msr->idx = HV_X64_MSR_GUEST_OS_ID; 185 msr->write = true; 186 msr->write_val = HYPERV_LINUX_OS_ID; 187 msr->fault_expected = false; 188 break; 189 case 3: 190 msr->idx = HV_X64_MSR_GUEST_OS_ID; 191 msr->write = false; 192 msr->fault_expected = false; 193 break; 194 case 4: 195 msr->idx = HV_X64_MSR_HYPERCALL; 196 msr->write = false; 197 msr->fault_expected = false; 198 break; 199 200 case 5: 201 msr->idx = HV_X64_MSR_VP_RUNTIME; 202 msr->write = false; 203 msr->fault_expected = true; 204 break; 205 case 6: 206 vcpu_set_cpuid_feature(vcpu, HV_MSR_VP_RUNTIME_AVAILABLE); 207 msr->idx = HV_X64_MSR_VP_RUNTIME; 208 msr->write = false; 209 msr->fault_expected = false; 210 break; 211 case 7: 212 /* Read only */ 213 msr->idx = HV_X64_MSR_VP_RUNTIME; 214 msr->write = true; 215 msr->write_val = 1; 216 msr->fault_expected = true; 217 break; 218 219 case 8: 220 msr->idx = HV_X64_MSR_TIME_REF_COUNT; 221 msr->write = false; 222 msr->fault_expected = true; 223 break; 224 case 9: 225 vcpu_set_cpuid_feature(vcpu, HV_MSR_TIME_REF_COUNT_AVAILABLE); 226 msr->idx = HV_X64_MSR_TIME_REF_COUNT; 227 msr->write = false; 228 msr->fault_expected = false; 229 break; 230 case 10: 231 /* Read only */ 232 msr->idx = HV_X64_MSR_TIME_REF_COUNT; 233 msr->write = true; 234 msr->write_val = 1; 235 msr->fault_expected = true; 236 break; 237 238 case 11: 239 msr->idx = HV_X64_MSR_VP_INDEX; 240 msr->write = false; 241 msr->fault_expected = true; 242 break; 243 case 12: 244 vcpu_set_cpuid_feature(vcpu, HV_MSR_VP_INDEX_AVAILABLE); 245 msr->idx = HV_X64_MSR_VP_INDEX; 246 msr->write = false; 247 msr->fault_expected = false; 248 break; 249 case 13: 250 /* Read only */ 251 msr->idx = HV_X64_MSR_VP_INDEX; 252 msr->write = true; 253 msr->write_val = 1; 254 msr->fault_expected = true; 255 break; 256 257 case 14: 258 msr->idx = HV_X64_MSR_RESET; 259 msr->write = false; 260 msr->fault_expected = true; 261 break; 262 case 15: 263 vcpu_set_cpuid_feature(vcpu, HV_MSR_RESET_AVAILABLE); 264 msr->idx = HV_X64_MSR_RESET; 265 msr->write = false; 266 msr->fault_expected = false; 267 break; 268 case 16: 269 msr->idx = HV_X64_MSR_RESET; 270 msr->write = true; 271 msr->write_val = 1; 272 msr->fault_expected = false; 273 msr->reset_expected = true; 274 break; 275 276 case 17: 277 msr->idx = HV_X64_MSR_REFERENCE_TSC; 278 msr->write = false; 279 msr->fault_expected = true; 280 break; 281 case 18: 282 vcpu_set_cpuid_feature(vcpu, HV_MSR_REFERENCE_TSC_AVAILABLE); 283 msr->idx = HV_X64_MSR_REFERENCE_TSC; 284 msr->write = false; 285 msr->fault_expected = false; 286 break; 287 case 19: 288 msr->idx = HV_X64_MSR_REFERENCE_TSC; 289 msr->write = true; 290 msr->write_val = 0; 291 msr->fault_expected = false; 292 break; 293 294 case 20: 295 msr->idx = HV_X64_MSR_EOM; 296 msr->write = false; 297 msr->fault_expected = true; 298 break; 299 case 21: 300 /* 301 * Remains unavailable even with KVM_CAP_HYPERV_SYNIC2 302 * capability enabled and guest visible CPUID bit unset. 303 */ 304 msr->idx = HV_X64_MSR_EOM; 305 msr->write = false; 306 msr->fault_expected = true; 307 break; 308 case 22: 309 vcpu_set_cpuid_feature(vcpu, HV_MSR_SYNIC_AVAILABLE); 310 msr->idx = HV_X64_MSR_EOM; 311 msr->write = false; 312 msr->fault_expected = false; 313 break; 314 case 23: 315 msr->idx = HV_X64_MSR_EOM; 316 msr->write = true; 317 msr->write_val = 0; 318 msr->fault_expected = false; 319 break; 320 321 case 24: 322 msr->idx = HV_X64_MSR_STIMER0_CONFIG; 323 msr->write = false; 324 msr->fault_expected = true; 325 break; 326 case 25: 327 vcpu_set_cpuid_feature(vcpu, HV_MSR_SYNTIMER_AVAILABLE); 328 msr->idx = HV_X64_MSR_STIMER0_CONFIG; 329 msr->write = false; 330 msr->fault_expected = false; 331 break; 332 case 26: 333 msr->idx = HV_X64_MSR_STIMER0_CONFIG; 334 msr->write = true; 335 msr->write_val = 0; 336 msr->fault_expected = false; 337 break; 338 case 27: 339 /* Direct mode test */ 340 msr->idx = HV_X64_MSR_STIMER0_CONFIG; 341 msr->write = true; 342 msr->write_val = 1 << 12; 343 msr->fault_expected = true; 344 break; 345 case 28: 346 vcpu_set_cpuid_feature(vcpu, HV_STIMER_DIRECT_MODE_AVAILABLE); 347 msr->idx = HV_X64_MSR_STIMER0_CONFIG; 348 msr->write = true; 349 msr->write_val = 1 << 12; 350 msr->fault_expected = false; 351 break; 352 353 case 29: 354 msr->idx = HV_X64_MSR_EOI; 355 msr->write = false; 356 msr->fault_expected = true; 357 break; 358 case 30: 359 vcpu_set_cpuid_feature(vcpu, HV_MSR_APIC_ACCESS_AVAILABLE); 360 msr->idx = HV_X64_MSR_EOI; 361 msr->write = true; 362 msr->write_val = 1; 363 msr->fault_expected = false; 364 break; 365 366 case 31: 367 msr->idx = HV_X64_MSR_TSC_FREQUENCY; 368 msr->write = false; 369 msr->fault_expected = true; 370 break; 371 case 32: 372 vcpu_set_cpuid_feature(vcpu, HV_ACCESS_FREQUENCY_MSRS); 373 msr->idx = HV_X64_MSR_TSC_FREQUENCY; 374 msr->write = false; 375 msr->fault_expected = false; 376 break; 377 case 33: 378 /* Read only */ 379 msr->idx = HV_X64_MSR_TSC_FREQUENCY; 380 msr->write = true; 381 msr->write_val = 1; 382 msr->fault_expected = true; 383 break; 384 385 case 34: 386 msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL; 387 msr->write = false; 388 msr->fault_expected = true; 389 break; 390 case 35: 391 vcpu_set_cpuid_feature(vcpu, HV_ACCESS_REENLIGHTENMENT); 392 msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL; 393 msr->write = false; 394 msr->fault_expected = false; 395 break; 396 case 36: 397 msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL; 398 msr->write = true; 399 msr->write_val = 1; 400 msr->fault_expected = false; 401 break; 402 case 37: 403 /* Can only write '0' */ 404 msr->idx = HV_X64_MSR_TSC_EMULATION_STATUS; 405 msr->write = true; 406 msr->write_val = 1; 407 msr->fault_expected = true; 408 break; 409 410 case 38: 411 msr->idx = HV_X64_MSR_CRASH_P0; 412 msr->write = false; 413 msr->fault_expected = true; 414 break; 415 case 39: 416 vcpu_set_cpuid_feature(vcpu, HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE); 417 msr->idx = HV_X64_MSR_CRASH_P0; 418 msr->write = false; 419 msr->fault_expected = false; 420 break; 421 case 40: 422 msr->idx = HV_X64_MSR_CRASH_P0; 423 msr->write = true; 424 msr->write_val = 1; 425 msr->fault_expected = false; 426 break; 427 428 case 41: 429 msr->idx = HV_X64_MSR_SYNDBG_STATUS; 430 msr->write = false; 431 msr->fault_expected = true; 432 break; 433 case 42: 434 vcpu_set_cpuid_feature(vcpu, HV_FEATURE_DEBUG_MSRS_AVAILABLE); 435 vcpu_set_cpuid_feature(vcpu, HV_X64_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING); 436 msr->idx = HV_X64_MSR_SYNDBG_STATUS; 437 msr->write = false; 438 msr->fault_expected = false; 439 break; 440 case 43: 441 msr->idx = HV_X64_MSR_SYNDBG_STATUS; 442 msr->write = true; 443 msr->write_val = 0; 444 msr->fault_expected = false; 445 break; 446 447 case 44: 448 /* MSR is not available when CPUID feature bit is unset */ 449 if (!has_invtsc) 450 goto next_stage; 451 msr->idx = HV_X64_MSR_TSC_INVARIANT_CONTROL; 452 msr->write = false; 453 msr->fault_expected = true; 454 break; 455 case 45: 456 /* MSR is available when CPUID feature bit is set */ 457 if (!has_invtsc) 458 goto next_stage; 459 vcpu_set_cpuid_feature(vcpu, HV_ACCESS_TSC_INVARIANT); 460 msr->idx = HV_X64_MSR_TSC_INVARIANT_CONTROL; 461 msr->write = false; 462 msr->fault_expected = false; 463 break; 464 case 46: 465 /* Writing bits other than 0 is forbidden */ 466 if (!has_invtsc) 467 goto next_stage; 468 msr->idx = HV_X64_MSR_TSC_INVARIANT_CONTROL; 469 msr->write = true; 470 msr->write_val = 0xdeadbeef; 471 msr->fault_expected = true; 472 break; 473 case 47: 474 /* Setting bit 0 enables the feature */ 475 if (!has_invtsc) 476 goto next_stage; 477 msr->idx = HV_X64_MSR_TSC_INVARIANT_CONTROL; 478 msr->write = true; 479 msr->write_val = 1; 480 msr->fault_expected = false; 481 break; 482 483 default: 484 kvm_vm_free(vm); 485 return; 486 } 487 488 vcpu_set_cpuid(vcpu); 489 490 memcpy(prev_cpuid, vcpu->cpuid, kvm_cpuid2_size(vcpu->cpuid->nent)); 491 492 pr_debug("Stage %d: testing msr: 0x%x for %s\n", stage, 493 msr->idx, msr->write ? "write" : "read"); 494 495 vcpu_run(vcpu); 496 497 if (msr->reset_expected) { 498 TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_SYSTEM_EVENT); 499 TEST_ASSERT(vcpu->run->system_event.type == KVM_SYSTEM_EVENT_RESET, 500 "Expected reset system event, got type %u", 501 vcpu->run->system_event.type); 502 goto next_stage; 503 } 504 505 TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_IO); 506 507 switch (get_ucall(vcpu, &uc)) { 508 case UCALL_ABORT: 509 REPORT_GUEST_ASSERT(uc); 510 return; 511 case UCALL_DONE: 512 break; 513 default: 514 TEST_FAIL("Unhandled ucall: %ld", uc.cmd); 515 return; 516 } 517 518 next_stage: 519 stage++; 520 kvm_vm_free(vm); 521 } 522 } 523 524 static void guest_test_hcalls_access(void) 525 { 526 struct kvm_cpuid2 *prev_cpuid = NULL; 527 struct kvm_vcpu *vcpu; 528 struct kvm_vm *vm; 529 struct ucall uc; 530 int stage = 0; 531 gva_t hcall_page, hcall_params; 532 struct hcall_data *hcall; 533 534 while (true) { 535 vm = vm_create_with_one_vcpu(&vcpu, guest_hcall); 536 537 /* Hypercall input/output */ 538 hcall_page = vm_alloc_pages(vm, 2); 539 memset(addr_gva2hva(vm, hcall_page), 0x0, 2 * getpagesize()); 540 541 hcall_params = vm_alloc_page(vm); 542 memset(addr_gva2hva(vm, hcall_params), 0x0, getpagesize()); 543 hcall = addr_gva2hva(vm, hcall_params); 544 545 vcpu_args_set(vcpu, 2, addr_gva2gpa(vm, hcall_page), hcall_params); 546 vcpu_enable_cap(vcpu, KVM_CAP_HYPERV_ENFORCE_CPUID, 1); 547 548 if (!prev_cpuid) { 549 vcpu_reset_hv_cpuid(vcpu); 550 551 prev_cpuid = allocate_kvm_cpuid2(vcpu->cpuid->nent); 552 } else { 553 vcpu_init_cpuid(vcpu, prev_cpuid); 554 } 555 556 switch (stage) { 557 case 0: 558 vcpu_set_cpuid_feature(vcpu, HV_MSR_HYPERCALL_AVAILABLE); 559 hcall->control = 0xbeef; 560 hcall->expect = HV_STATUS_INVALID_HYPERCALL_CODE; 561 break; 562 563 case 1: 564 hcall->control = HVCALL_POST_MESSAGE; 565 hcall->expect = HV_STATUS_ACCESS_DENIED; 566 break; 567 case 2: 568 vcpu_set_cpuid_feature(vcpu, HV_POST_MESSAGES); 569 hcall->control = HVCALL_POST_MESSAGE; 570 hcall->expect = HV_STATUS_INVALID_HYPERCALL_INPUT; 571 break; 572 573 case 3: 574 hcall->control = HVCALL_SIGNAL_EVENT; 575 hcall->expect = HV_STATUS_ACCESS_DENIED; 576 break; 577 case 4: 578 vcpu_set_cpuid_feature(vcpu, HV_SIGNAL_EVENTS); 579 hcall->control = HVCALL_SIGNAL_EVENT; 580 hcall->expect = HV_STATUS_INVALID_HYPERCALL_INPUT; 581 break; 582 583 case 5: 584 hcall->control = HVCALL_RESET_DEBUG_SESSION; 585 hcall->expect = HV_STATUS_INVALID_HYPERCALL_CODE; 586 break; 587 case 6: 588 vcpu_set_cpuid_feature(vcpu, HV_X64_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING); 589 hcall->control = HVCALL_RESET_DEBUG_SESSION; 590 hcall->expect = HV_STATUS_ACCESS_DENIED; 591 break; 592 case 7: 593 vcpu_set_cpuid_feature(vcpu, HV_DEBUGGING); 594 hcall->control = HVCALL_RESET_DEBUG_SESSION; 595 hcall->expect = HV_STATUS_OPERATION_DENIED; 596 break; 597 598 case 8: 599 hcall->control = HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE; 600 hcall->expect = HV_STATUS_ACCESS_DENIED; 601 break; 602 case 9: 603 vcpu_set_cpuid_feature(vcpu, HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED); 604 hcall->control = HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE; 605 hcall->expect = HV_STATUS_SUCCESS; 606 break; 607 case 10: 608 hcall->control = HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX; 609 hcall->expect = HV_STATUS_ACCESS_DENIED; 610 break; 611 case 11: 612 vcpu_set_cpuid_feature(vcpu, HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED); 613 hcall->control = HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX; 614 hcall->expect = HV_STATUS_SUCCESS; 615 break; 616 617 case 12: 618 hcall->control = HVCALL_SEND_IPI; 619 hcall->expect = HV_STATUS_ACCESS_DENIED; 620 break; 621 case 13: 622 vcpu_set_cpuid_feature(vcpu, HV_X64_CLUSTER_IPI_RECOMMENDED); 623 hcall->control = HVCALL_SEND_IPI; 624 hcall->expect = HV_STATUS_INVALID_HYPERCALL_INPUT; 625 break; 626 case 14: 627 /* Nothing in 'sparse banks' -> success */ 628 hcall->control = HVCALL_SEND_IPI_EX; 629 hcall->expect = HV_STATUS_SUCCESS; 630 break; 631 632 case 15: 633 hcall->control = HVCALL_NOTIFY_LONG_SPIN_WAIT; 634 hcall->expect = HV_STATUS_ACCESS_DENIED; 635 break; 636 case 16: 637 vcpu_set_cpuid_feature(vcpu, HV_PV_SPINLOCKS_TEST); 638 hcall->control = HVCALL_NOTIFY_LONG_SPIN_WAIT; 639 hcall->expect = HV_STATUS_SUCCESS; 640 break; 641 case 17: 642 /* XMM fast hypercall */ 643 hcall->control = HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE | HV_HYPERCALL_FAST_BIT; 644 hcall->ud_expected = true; 645 break; 646 case 18: 647 vcpu_set_cpuid_feature(vcpu, HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE); 648 hcall->control = HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE | HV_HYPERCALL_FAST_BIT; 649 hcall->ud_expected = false; 650 hcall->expect = HV_STATUS_SUCCESS; 651 break; 652 case 19: 653 hcall->control = HV_EXT_CALL_QUERY_CAPABILITIES; 654 hcall->expect = HV_STATUS_ACCESS_DENIED; 655 break; 656 case 20: 657 vcpu_set_cpuid_feature(vcpu, HV_ENABLE_EXTENDED_HYPERCALLS); 658 hcall->control = HV_EXT_CALL_QUERY_CAPABILITIES | HV_HYPERCALL_FAST_BIT; 659 hcall->expect = HV_STATUS_INVALID_PARAMETER; 660 break; 661 case 21: 662 kvm_vm_free(vm); 663 return; 664 } 665 666 vcpu_set_cpuid(vcpu); 667 668 memcpy(prev_cpuid, vcpu->cpuid, kvm_cpuid2_size(vcpu->cpuid->nent)); 669 670 pr_debug("Stage %d: testing hcall: 0x%lx\n", stage, hcall->control); 671 672 vcpu_run(vcpu); 673 TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_IO); 674 675 switch (get_ucall(vcpu, &uc)) { 676 case UCALL_ABORT: 677 REPORT_GUEST_ASSERT(uc); 678 return; 679 case UCALL_DONE: 680 break; 681 default: 682 TEST_FAIL("Unhandled ucall: %ld", uc.cmd); 683 return; 684 } 685 686 stage++; 687 kvm_vm_free(vm); 688 } 689 } 690 691 int main(void) 692 { 693 TEST_REQUIRE(kvm_has_cap(KVM_CAP_HYPERV_ENFORCE_CPUID)); 694 695 pr_info("Testing access to Hyper-V specific MSRs\n"); 696 guest_test_msrs_access(); 697 698 pr_info("Testing access to Hyper-V hypercalls\n"); 699 guest_test_hcalls_access(); 700 } 701