1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2018, Google LLC. 4 */ 5 6 #include <asm/msr-index.h> 7 8 #include "test_util.h" 9 #include "kvm_util.h" 10 #include "processor.h" 11 #include "vmx.h" 12 13 #define PAGE_SHIFT_4K 12 14 15 #define KVM_EPT_PAGE_TABLE_MIN_PADDR 0x1c0000 16 17 bool enable_evmcs; 18 19 struct hv_enlightened_vmcs *current_evmcs; 20 struct hv_vp_assist_page *current_vp_assist; 21 22 struct eptPageTableEntry { 23 uint64_t readable:1; 24 uint64_t writable:1; 25 uint64_t executable:1; 26 uint64_t memory_type:3; 27 uint64_t ignore_pat:1; 28 uint64_t page_size:1; 29 uint64_t accessed:1; 30 uint64_t dirty:1; 31 uint64_t ignored_11_10:2; 32 uint64_t address:40; 33 uint64_t ignored_62_52:11; 34 uint64_t suppress_ve:1; 35 }; 36 37 struct eptPageTablePointer { 38 uint64_t memory_type:3; 39 uint64_t page_walk_length:3; 40 uint64_t ad_enabled:1; 41 uint64_t reserved_11_07:5; 42 uint64_t address:40; 43 uint64_t reserved_63_52:12; 44 }; 45 int vcpu_enable_evmcs(struct kvm_vcpu *vcpu) 46 { 47 uint16_t evmcs_ver; 48 49 vcpu_enable_cap(vcpu, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 50 (unsigned long)&evmcs_ver); 51 52 /* KVM should return supported EVMCS version range */ 53 TEST_ASSERT(((evmcs_ver >> 8) >= (evmcs_ver & 0xff)) && 54 (evmcs_ver & 0xff) > 0, 55 "Incorrect EVMCS version range: %x:%x", 56 evmcs_ver & 0xff, evmcs_ver >> 8); 57 58 return evmcs_ver; 59 } 60 61 /* Allocate memory regions for nested VMX tests. 62 * 63 * Input Args: 64 * vm - The VM to allocate guest-virtual addresses in. 65 * 66 * Output Args: 67 * p_vmx_gva - The guest virtual address for the struct vmx_pages. 68 * 69 * Return: 70 * Pointer to structure with the addresses of the VMX areas. 71 */ 72 struct vmx_pages * 73 vcpu_alloc_vmx(struct kvm_vm *vm, vm_vaddr_t *p_vmx_gva) 74 { 75 vm_vaddr_t vmx_gva = vm_vaddr_alloc_page(vm); 76 struct vmx_pages *vmx = addr_gva2hva(vm, vmx_gva); 77 78 /* Setup of a region of guest memory for the vmxon region. */ 79 vmx->vmxon = (void *)vm_vaddr_alloc_page(vm); 80 vmx->vmxon_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmxon); 81 vmx->vmxon_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmxon); 82 83 /* Setup of a region of guest memory for a vmcs. */ 84 vmx->vmcs = (void *)vm_vaddr_alloc_page(vm); 85 vmx->vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmcs); 86 vmx->vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmcs); 87 88 /* Setup of a region of guest memory for the MSR bitmap. */ 89 vmx->msr = (void *)vm_vaddr_alloc_page(vm); 90 vmx->msr_hva = addr_gva2hva(vm, (uintptr_t)vmx->msr); 91 vmx->msr_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->msr); 92 memset(vmx->msr_hva, 0, getpagesize()); 93 94 /* Setup of a region of guest memory for the shadow VMCS. */ 95 vmx->shadow_vmcs = (void *)vm_vaddr_alloc_page(vm); 96 vmx->shadow_vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->shadow_vmcs); 97 vmx->shadow_vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->shadow_vmcs); 98 99 /* Setup of a region of guest memory for the VMREAD and VMWRITE bitmaps. */ 100 vmx->vmread = (void *)vm_vaddr_alloc_page(vm); 101 vmx->vmread_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmread); 102 vmx->vmread_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmread); 103 memset(vmx->vmread_hva, 0, getpagesize()); 104 105 vmx->vmwrite = (void *)vm_vaddr_alloc_page(vm); 106 vmx->vmwrite_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmwrite); 107 vmx->vmwrite_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmwrite); 108 memset(vmx->vmwrite_hva, 0, getpagesize()); 109 110 *p_vmx_gva = vmx_gva; 111 return vmx; 112 } 113 114 bool prepare_for_vmx_operation(struct vmx_pages *vmx) 115 { 116 uint64_t feature_control; 117 uint64_t required; 118 unsigned long cr0; 119 unsigned long cr4; 120 121 /* 122 * Ensure bits in CR0 and CR4 are valid in VMX operation: 123 * - Bit X is 1 in _FIXED0: bit X is fixed to 1 in CRx. 124 * - Bit X is 0 in _FIXED1: bit X is fixed to 0 in CRx. 125 */ 126 __asm__ __volatile__("mov %%cr0, %0" : "=r"(cr0) : : "memory"); 127 cr0 &= rdmsr(MSR_IA32_VMX_CR0_FIXED1); 128 cr0 |= rdmsr(MSR_IA32_VMX_CR0_FIXED0); 129 __asm__ __volatile__("mov %0, %%cr0" : : "r"(cr0) : "memory"); 130 131 __asm__ __volatile__("mov %%cr4, %0" : "=r"(cr4) : : "memory"); 132 cr4 &= rdmsr(MSR_IA32_VMX_CR4_FIXED1); 133 cr4 |= rdmsr(MSR_IA32_VMX_CR4_FIXED0); 134 /* Enable VMX operation */ 135 cr4 |= X86_CR4_VMXE; 136 __asm__ __volatile__("mov %0, %%cr4" : : "r"(cr4) : "memory"); 137 138 /* 139 * Configure IA32_FEATURE_CONTROL MSR to allow VMXON: 140 * Bit 0: Lock bit. If clear, VMXON causes a #GP. 141 * Bit 2: Enables VMXON outside of SMX operation. If clear, VMXON 142 * outside of SMX causes a #GP. 143 */ 144 required = FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; 145 required |= FEAT_CTL_LOCKED; 146 feature_control = rdmsr(MSR_IA32_FEAT_CTL); 147 if ((feature_control & required) != required) 148 wrmsr(MSR_IA32_FEAT_CTL, feature_control | required); 149 150 /* Enter VMX root operation. */ 151 *(uint32_t *)(vmx->vmxon) = vmcs_revision(); 152 if (vmxon(vmx->vmxon_gpa)) 153 return false; 154 155 return true; 156 } 157 158 bool load_vmcs(struct vmx_pages *vmx) 159 { 160 /* Load a VMCS. */ 161 *(uint32_t *)(vmx->vmcs) = vmcs_revision(); 162 if (vmclear(vmx->vmcs_gpa)) 163 return false; 164 165 if (vmptrld(vmx->vmcs_gpa)) 166 return false; 167 168 /* Setup shadow VMCS, do not load it yet. */ 169 *(uint32_t *)(vmx->shadow_vmcs) = vmcs_revision() | 0x80000000ul; 170 if (vmclear(vmx->shadow_vmcs_gpa)) 171 return false; 172 173 return true; 174 } 175 176 static bool ept_vpid_cap_supported(uint64_t mask) 177 { 178 return rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & mask; 179 } 180 181 bool ept_1g_pages_supported(void) 182 { 183 return ept_vpid_cap_supported(VMX_EPT_VPID_CAP_1G_PAGES); 184 } 185 186 /* 187 * Initialize the control fields to the most basic settings possible. 188 */ 189 static inline void init_vmcs_control_fields(struct vmx_pages *vmx) 190 { 191 uint32_t sec_exec_ctl = 0; 192 193 vmwrite(VIRTUAL_PROCESSOR_ID, 0); 194 vmwrite(POSTED_INTR_NV, 0); 195 196 vmwrite(PIN_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PINBASED_CTLS)); 197 198 if (vmx->eptp_gpa) { 199 uint64_t ept_paddr; 200 struct eptPageTablePointer eptp = { 201 .memory_type = X86_MEMTYPE_WB, 202 .page_walk_length = 3, /* + 1 */ 203 .ad_enabled = ept_vpid_cap_supported(VMX_EPT_VPID_CAP_AD_BITS), 204 .address = vmx->eptp_gpa >> PAGE_SHIFT_4K, 205 }; 206 207 memcpy(&ept_paddr, &eptp, sizeof(ept_paddr)); 208 vmwrite(EPT_POINTER, ept_paddr); 209 sec_exec_ctl |= SECONDARY_EXEC_ENABLE_EPT; 210 } 211 212 if (!vmwrite(SECONDARY_VM_EXEC_CONTROL, sec_exec_ctl)) 213 vmwrite(CPU_BASED_VM_EXEC_CONTROL, 214 rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS) | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS); 215 else { 216 vmwrite(CPU_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS)); 217 GUEST_ASSERT(!sec_exec_ctl); 218 } 219 220 vmwrite(EXCEPTION_BITMAP, 0); 221 vmwrite(PAGE_FAULT_ERROR_CODE_MASK, 0); 222 vmwrite(PAGE_FAULT_ERROR_CODE_MATCH, -1); /* Never match */ 223 vmwrite(CR3_TARGET_COUNT, 0); 224 vmwrite(VM_EXIT_CONTROLS, rdmsr(MSR_IA32_VMX_EXIT_CTLS) | 225 VM_EXIT_HOST_ADDR_SPACE_SIZE); /* 64-bit host */ 226 vmwrite(VM_EXIT_MSR_STORE_COUNT, 0); 227 vmwrite(VM_EXIT_MSR_LOAD_COUNT, 0); 228 vmwrite(VM_ENTRY_CONTROLS, rdmsr(MSR_IA32_VMX_ENTRY_CTLS) | 229 VM_ENTRY_IA32E_MODE); /* 64-bit guest */ 230 vmwrite(VM_ENTRY_MSR_LOAD_COUNT, 0); 231 vmwrite(VM_ENTRY_INTR_INFO_FIELD, 0); 232 vmwrite(TPR_THRESHOLD, 0); 233 234 vmwrite(CR0_GUEST_HOST_MASK, 0); 235 vmwrite(CR4_GUEST_HOST_MASK, 0); 236 vmwrite(CR0_READ_SHADOW, get_cr0()); 237 vmwrite(CR4_READ_SHADOW, get_cr4()); 238 239 vmwrite(MSR_BITMAP, vmx->msr_gpa); 240 vmwrite(VMREAD_BITMAP, vmx->vmread_gpa); 241 vmwrite(VMWRITE_BITMAP, vmx->vmwrite_gpa); 242 } 243 244 /* 245 * Initialize the host state fields based on the current host state, with 246 * the exception of HOST_RSP and HOST_RIP, which should be set by vmlaunch 247 * or vmresume. 248 */ 249 static inline void init_vmcs_host_state(void) 250 { 251 uint32_t exit_controls = vmreadz(VM_EXIT_CONTROLS); 252 253 vmwrite(HOST_ES_SELECTOR, get_es()); 254 vmwrite(HOST_CS_SELECTOR, get_cs()); 255 vmwrite(HOST_SS_SELECTOR, get_ss()); 256 vmwrite(HOST_DS_SELECTOR, get_ds()); 257 vmwrite(HOST_FS_SELECTOR, get_fs()); 258 vmwrite(HOST_GS_SELECTOR, get_gs()); 259 vmwrite(HOST_TR_SELECTOR, get_tr()); 260 261 if (exit_controls & VM_EXIT_LOAD_IA32_PAT) 262 vmwrite(HOST_IA32_PAT, rdmsr(MSR_IA32_CR_PAT)); 263 if (exit_controls & VM_EXIT_LOAD_IA32_EFER) 264 vmwrite(HOST_IA32_EFER, rdmsr(MSR_EFER)); 265 if (exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 266 vmwrite(HOST_IA32_PERF_GLOBAL_CTRL, 267 rdmsr(MSR_CORE_PERF_GLOBAL_CTRL)); 268 269 vmwrite(HOST_IA32_SYSENTER_CS, rdmsr(MSR_IA32_SYSENTER_CS)); 270 271 vmwrite(HOST_CR0, get_cr0()); 272 vmwrite(HOST_CR3, get_cr3()); 273 vmwrite(HOST_CR4, get_cr4()); 274 vmwrite(HOST_FS_BASE, rdmsr(MSR_FS_BASE)); 275 vmwrite(HOST_GS_BASE, rdmsr(MSR_GS_BASE)); 276 vmwrite(HOST_TR_BASE, 277 get_desc64_base((struct desc64 *)(get_gdt().address + get_tr()))); 278 vmwrite(HOST_GDTR_BASE, get_gdt().address); 279 vmwrite(HOST_IDTR_BASE, get_idt().address); 280 vmwrite(HOST_IA32_SYSENTER_ESP, rdmsr(MSR_IA32_SYSENTER_ESP)); 281 vmwrite(HOST_IA32_SYSENTER_EIP, rdmsr(MSR_IA32_SYSENTER_EIP)); 282 } 283 284 /* 285 * Initialize the guest state fields essentially as a clone of 286 * the host state fields. Some host state fields have fixed 287 * values, and we set the corresponding guest state fields accordingly. 288 */ 289 static inline void init_vmcs_guest_state(void *rip, void *rsp) 290 { 291 vmwrite(GUEST_ES_SELECTOR, vmreadz(HOST_ES_SELECTOR)); 292 vmwrite(GUEST_CS_SELECTOR, vmreadz(HOST_CS_SELECTOR)); 293 vmwrite(GUEST_SS_SELECTOR, vmreadz(HOST_SS_SELECTOR)); 294 vmwrite(GUEST_DS_SELECTOR, vmreadz(HOST_DS_SELECTOR)); 295 vmwrite(GUEST_FS_SELECTOR, vmreadz(HOST_FS_SELECTOR)); 296 vmwrite(GUEST_GS_SELECTOR, vmreadz(HOST_GS_SELECTOR)); 297 vmwrite(GUEST_LDTR_SELECTOR, 0); 298 vmwrite(GUEST_TR_SELECTOR, vmreadz(HOST_TR_SELECTOR)); 299 vmwrite(GUEST_INTR_STATUS, 0); 300 vmwrite(GUEST_PML_INDEX, 0); 301 302 vmwrite(VMCS_LINK_POINTER, -1ll); 303 vmwrite(GUEST_IA32_DEBUGCTL, 0); 304 vmwrite(GUEST_IA32_PAT, vmreadz(HOST_IA32_PAT)); 305 vmwrite(GUEST_IA32_EFER, vmreadz(HOST_IA32_EFER)); 306 vmwrite(GUEST_IA32_PERF_GLOBAL_CTRL, 307 vmreadz(HOST_IA32_PERF_GLOBAL_CTRL)); 308 309 vmwrite(GUEST_ES_LIMIT, -1); 310 vmwrite(GUEST_CS_LIMIT, -1); 311 vmwrite(GUEST_SS_LIMIT, -1); 312 vmwrite(GUEST_DS_LIMIT, -1); 313 vmwrite(GUEST_FS_LIMIT, -1); 314 vmwrite(GUEST_GS_LIMIT, -1); 315 vmwrite(GUEST_LDTR_LIMIT, -1); 316 vmwrite(GUEST_TR_LIMIT, 0x67); 317 vmwrite(GUEST_GDTR_LIMIT, 0xffff); 318 vmwrite(GUEST_IDTR_LIMIT, 0xffff); 319 vmwrite(GUEST_ES_AR_BYTES, 320 vmreadz(GUEST_ES_SELECTOR) == 0 ? 0x10000 : 0xc093); 321 vmwrite(GUEST_CS_AR_BYTES, 0xa09b); 322 vmwrite(GUEST_SS_AR_BYTES, 0xc093); 323 vmwrite(GUEST_DS_AR_BYTES, 324 vmreadz(GUEST_DS_SELECTOR) == 0 ? 0x10000 : 0xc093); 325 vmwrite(GUEST_FS_AR_BYTES, 326 vmreadz(GUEST_FS_SELECTOR) == 0 ? 0x10000 : 0xc093); 327 vmwrite(GUEST_GS_AR_BYTES, 328 vmreadz(GUEST_GS_SELECTOR) == 0 ? 0x10000 : 0xc093); 329 vmwrite(GUEST_LDTR_AR_BYTES, 0x10000); 330 vmwrite(GUEST_TR_AR_BYTES, 0x8b); 331 vmwrite(GUEST_INTERRUPTIBILITY_INFO, 0); 332 vmwrite(GUEST_ACTIVITY_STATE, 0); 333 vmwrite(GUEST_SYSENTER_CS, vmreadz(HOST_IA32_SYSENTER_CS)); 334 vmwrite(VMX_PREEMPTION_TIMER_VALUE, 0); 335 336 vmwrite(GUEST_CR0, vmreadz(HOST_CR0)); 337 vmwrite(GUEST_CR3, vmreadz(HOST_CR3)); 338 vmwrite(GUEST_CR4, vmreadz(HOST_CR4)); 339 vmwrite(GUEST_ES_BASE, 0); 340 vmwrite(GUEST_CS_BASE, 0); 341 vmwrite(GUEST_SS_BASE, 0); 342 vmwrite(GUEST_DS_BASE, 0); 343 vmwrite(GUEST_FS_BASE, vmreadz(HOST_FS_BASE)); 344 vmwrite(GUEST_GS_BASE, vmreadz(HOST_GS_BASE)); 345 vmwrite(GUEST_LDTR_BASE, 0); 346 vmwrite(GUEST_TR_BASE, vmreadz(HOST_TR_BASE)); 347 vmwrite(GUEST_GDTR_BASE, vmreadz(HOST_GDTR_BASE)); 348 vmwrite(GUEST_IDTR_BASE, vmreadz(HOST_IDTR_BASE)); 349 vmwrite(GUEST_DR7, 0x400); 350 vmwrite(GUEST_RSP, (uint64_t)rsp); 351 vmwrite(GUEST_RIP, (uint64_t)rip); 352 vmwrite(GUEST_RFLAGS, 2); 353 vmwrite(GUEST_PENDING_DBG_EXCEPTIONS, 0); 354 vmwrite(GUEST_SYSENTER_ESP, vmreadz(HOST_IA32_SYSENTER_ESP)); 355 vmwrite(GUEST_SYSENTER_EIP, vmreadz(HOST_IA32_SYSENTER_EIP)); 356 } 357 358 void prepare_vmcs(struct vmx_pages *vmx, void *guest_rip, void *guest_rsp) 359 { 360 init_vmcs_control_fields(vmx); 361 init_vmcs_host_state(); 362 init_vmcs_guest_state(guest_rip, guest_rsp); 363 } 364 365 static void nested_create_pte(struct kvm_vm *vm, 366 struct eptPageTableEntry *pte, 367 uint64_t nested_paddr, 368 uint64_t paddr, 369 int current_level, 370 int target_level) 371 { 372 if (!pte->readable) { 373 pte->writable = true; 374 pte->readable = true; 375 pte->executable = true; 376 pte->page_size = (current_level == target_level); 377 if (pte->page_size) 378 pte->address = paddr >> vm->page_shift; 379 else 380 pte->address = vm_alloc_page_table(vm) >> vm->page_shift; 381 } else { 382 /* 383 * Entry already present. Assert that the caller doesn't want 384 * a hugepage at this level, and that there isn't a hugepage at 385 * this level. 386 */ 387 TEST_ASSERT(current_level != target_level, 388 "Cannot create hugepage at level: %u, nested_paddr: 0x%lx", 389 current_level, nested_paddr); 390 TEST_ASSERT(!pte->page_size, 391 "Cannot create page table at level: %u, nested_paddr: 0x%lx", 392 current_level, nested_paddr); 393 } 394 } 395 396 397 void __nested_pg_map(struct vmx_pages *vmx, struct kvm_vm *vm, 398 uint64_t nested_paddr, uint64_t paddr, int target_level) 399 { 400 const uint64_t page_size = PG_LEVEL_SIZE(target_level); 401 struct eptPageTableEntry *pt = vmx->eptp_hva, *pte; 402 uint16_t index; 403 404 TEST_ASSERT(vm->mode == VM_MODE_PXXV48_4K, "Attempt to use " 405 "unknown or unsupported guest mode, mode: 0x%x", vm->mode); 406 407 TEST_ASSERT((nested_paddr >> 48) == 0, 408 "Nested physical address 0x%lx requires 5-level paging", 409 nested_paddr); 410 TEST_ASSERT((nested_paddr % page_size) == 0, 411 "Nested physical address not on page boundary,\n" 412 " nested_paddr: 0x%lx page_size: 0x%lx", 413 nested_paddr, page_size); 414 TEST_ASSERT((nested_paddr >> vm->page_shift) <= vm->max_gfn, 415 "Physical address beyond beyond maximum supported,\n" 416 " nested_paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", 417 paddr, vm->max_gfn, vm->page_size); 418 TEST_ASSERT((paddr % page_size) == 0, 419 "Physical address not on page boundary,\n" 420 " paddr: 0x%lx page_size: 0x%lx", 421 paddr, page_size); 422 TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn, 423 "Physical address beyond beyond maximum supported,\n" 424 " paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", 425 paddr, vm->max_gfn, vm->page_size); 426 427 for (int level = PG_LEVEL_512G; level >= PG_LEVEL_4K; level--) { 428 index = (nested_paddr >> PG_LEVEL_SHIFT(level)) & 0x1ffu; 429 pte = &pt[index]; 430 431 nested_create_pte(vm, pte, nested_paddr, paddr, level, target_level); 432 433 if (pte->page_size) 434 break; 435 436 pt = addr_gpa2hva(vm, pte->address * vm->page_size); 437 } 438 439 /* 440 * For now mark these as accessed and dirty because the only 441 * testcase we have needs that. Can be reconsidered later. 442 */ 443 pte->accessed = true; 444 pte->dirty = true; 445 446 } 447 448 void nested_pg_map(struct vmx_pages *vmx, struct kvm_vm *vm, 449 uint64_t nested_paddr, uint64_t paddr) 450 { 451 __nested_pg_map(vmx, vm, nested_paddr, paddr, PG_LEVEL_4K); 452 } 453 454 /* 455 * Map a range of EPT guest physical addresses to the VM's physical address 456 * 457 * Input Args: 458 * vm - Virtual Machine 459 * nested_paddr - Nested guest physical address to map 460 * paddr - VM Physical Address 461 * size - The size of the range to map 462 * level - The level at which to map the range 463 * 464 * Output Args: None 465 * 466 * Return: None 467 * 468 * Within the VM given by vm, creates a nested guest translation for the 469 * page range starting at nested_paddr to the page range starting at paddr. 470 */ 471 void __nested_map(struct vmx_pages *vmx, struct kvm_vm *vm, 472 uint64_t nested_paddr, uint64_t paddr, uint64_t size, 473 int level) 474 { 475 size_t page_size = PG_LEVEL_SIZE(level); 476 size_t npages = size / page_size; 477 478 TEST_ASSERT(nested_paddr + size > nested_paddr, "Vaddr overflow"); 479 TEST_ASSERT(paddr + size > paddr, "Paddr overflow"); 480 481 while (npages--) { 482 __nested_pg_map(vmx, vm, nested_paddr, paddr, level); 483 nested_paddr += page_size; 484 paddr += page_size; 485 } 486 } 487 488 void nested_map(struct vmx_pages *vmx, struct kvm_vm *vm, 489 uint64_t nested_paddr, uint64_t paddr, uint64_t size) 490 { 491 __nested_map(vmx, vm, nested_paddr, paddr, size, PG_LEVEL_4K); 492 } 493 494 /* Prepare an identity extended page table that maps all the 495 * physical pages in VM. 496 */ 497 void nested_map_memslot(struct vmx_pages *vmx, struct kvm_vm *vm, 498 uint32_t memslot) 499 { 500 sparsebit_idx_t i, last; 501 struct userspace_mem_region *region = 502 memslot2region(vm, memslot); 503 504 i = (region->region.guest_phys_addr >> vm->page_shift) - 1; 505 last = i + (region->region.memory_size >> vm->page_shift); 506 for (;;) { 507 i = sparsebit_next_clear(region->unused_phy_pages, i); 508 if (i > last) 509 break; 510 511 nested_map(vmx, vm, 512 (uint64_t)i << vm->page_shift, 513 (uint64_t)i << vm->page_shift, 514 1 << vm->page_shift); 515 } 516 } 517 518 /* Identity map a region with 1GiB Pages. */ 519 void nested_identity_map_1g(struct vmx_pages *vmx, struct kvm_vm *vm, 520 uint64_t addr, uint64_t size) 521 { 522 __nested_map(vmx, vm, addr, addr, size, PG_LEVEL_1G); 523 } 524 525 bool kvm_cpu_has_ept(void) 526 { 527 uint64_t ctrl; 528 529 ctrl = kvm_get_feature_msr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS) >> 32; 530 if (!(ctrl & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) 531 return false; 532 533 ctrl = kvm_get_feature_msr(MSR_IA32_VMX_PROCBASED_CTLS2) >> 32; 534 return ctrl & SECONDARY_EXEC_ENABLE_EPT; 535 } 536 537 void prepare_eptp(struct vmx_pages *vmx, struct kvm_vm *vm, 538 uint32_t eptp_memslot) 539 { 540 TEST_ASSERT(kvm_cpu_has_ept(), "KVM doesn't support nested EPT"); 541 542 vmx->eptp = (void *)vm_vaddr_alloc_page(vm); 543 vmx->eptp_hva = addr_gva2hva(vm, (uintptr_t)vmx->eptp); 544 vmx->eptp_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->eptp); 545 } 546 547 void prepare_virtualize_apic_accesses(struct vmx_pages *vmx, struct kvm_vm *vm) 548 { 549 vmx->apic_access = (void *)vm_vaddr_alloc_page(vm); 550 vmx->apic_access_hva = addr_gva2hva(vm, (uintptr_t)vmx->apic_access); 551 vmx->apic_access_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->apic_access); 552 } 553