1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2018, Google LLC. 4 */ 5 6 #include "linux/bitmap.h" 7 #include "test_util.h" 8 #include "kvm_util.h" 9 #include "processor.h" 10 #include "sev.h" 11 12 #ifndef NUM_INTERRUPTS 13 #define NUM_INTERRUPTS 256 14 #endif 15 16 #define KERNEL_CS 0x8 17 #define KERNEL_DS 0x10 18 #define KERNEL_TSS 0x18 19 20 vm_vaddr_t exception_handlers; 21 bool host_cpu_is_amd; 22 bool host_cpu_is_intel; 23 bool is_forced_emulation_enabled; 24 uint64_t guest_tsc_khz; 25 26 static void regs_dump(FILE *stream, struct kvm_regs *regs, uint8_t indent) 27 { 28 fprintf(stream, "%*srax: 0x%.16llx rbx: 0x%.16llx " 29 "rcx: 0x%.16llx rdx: 0x%.16llx\n", 30 indent, "", 31 regs->rax, regs->rbx, regs->rcx, regs->rdx); 32 fprintf(stream, "%*srsi: 0x%.16llx rdi: 0x%.16llx " 33 "rsp: 0x%.16llx rbp: 0x%.16llx\n", 34 indent, "", 35 regs->rsi, regs->rdi, regs->rsp, regs->rbp); 36 fprintf(stream, "%*sr8: 0x%.16llx r9: 0x%.16llx " 37 "r10: 0x%.16llx r11: 0x%.16llx\n", 38 indent, "", 39 regs->r8, regs->r9, regs->r10, regs->r11); 40 fprintf(stream, "%*sr12: 0x%.16llx r13: 0x%.16llx " 41 "r14: 0x%.16llx r15: 0x%.16llx\n", 42 indent, "", 43 regs->r12, regs->r13, regs->r14, regs->r15); 44 fprintf(stream, "%*srip: 0x%.16llx rfl: 0x%.16llx\n", 45 indent, "", 46 regs->rip, regs->rflags); 47 } 48 49 static void segment_dump(FILE *stream, struct kvm_segment *segment, 50 uint8_t indent) 51 { 52 fprintf(stream, "%*sbase: 0x%.16llx limit: 0x%.8x " 53 "selector: 0x%.4x type: 0x%.2x\n", 54 indent, "", segment->base, segment->limit, 55 segment->selector, segment->type); 56 fprintf(stream, "%*spresent: 0x%.2x dpl: 0x%.2x " 57 "db: 0x%.2x s: 0x%.2x l: 0x%.2x\n", 58 indent, "", segment->present, segment->dpl, 59 segment->db, segment->s, segment->l); 60 fprintf(stream, "%*sg: 0x%.2x avl: 0x%.2x " 61 "unusable: 0x%.2x padding: 0x%.2x\n", 62 indent, "", segment->g, segment->avl, 63 segment->unusable, segment->padding); 64 } 65 66 static void dtable_dump(FILE *stream, struct kvm_dtable *dtable, 67 uint8_t indent) 68 { 69 fprintf(stream, "%*sbase: 0x%.16llx limit: 0x%.4x " 70 "padding: 0x%.4x 0x%.4x 0x%.4x\n", 71 indent, "", dtable->base, dtable->limit, 72 dtable->padding[0], dtable->padding[1], dtable->padding[2]); 73 } 74 75 static void sregs_dump(FILE *stream, struct kvm_sregs *sregs, uint8_t indent) 76 { 77 unsigned int i; 78 79 fprintf(stream, "%*scs:\n", indent, ""); 80 segment_dump(stream, &sregs->cs, indent + 2); 81 fprintf(stream, "%*sds:\n", indent, ""); 82 segment_dump(stream, &sregs->ds, indent + 2); 83 fprintf(stream, "%*ses:\n", indent, ""); 84 segment_dump(stream, &sregs->es, indent + 2); 85 fprintf(stream, "%*sfs:\n", indent, ""); 86 segment_dump(stream, &sregs->fs, indent + 2); 87 fprintf(stream, "%*sgs:\n", indent, ""); 88 segment_dump(stream, &sregs->gs, indent + 2); 89 fprintf(stream, "%*sss:\n", indent, ""); 90 segment_dump(stream, &sregs->ss, indent + 2); 91 fprintf(stream, "%*str:\n", indent, ""); 92 segment_dump(stream, &sregs->tr, indent + 2); 93 fprintf(stream, "%*sldt:\n", indent, ""); 94 segment_dump(stream, &sregs->ldt, indent + 2); 95 96 fprintf(stream, "%*sgdt:\n", indent, ""); 97 dtable_dump(stream, &sregs->gdt, indent + 2); 98 fprintf(stream, "%*sidt:\n", indent, ""); 99 dtable_dump(stream, &sregs->idt, indent + 2); 100 101 fprintf(stream, "%*scr0: 0x%.16llx cr2: 0x%.16llx " 102 "cr3: 0x%.16llx cr4: 0x%.16llx\n", 103 indent, "", 104 sregs->cr0, sregs->cr2, sregs->cr3, sregs->cr4); 105 fprintf(stream, "%*scr8: 0x%.16llx efer: 0x%.16llx " 106 "apic_base: 0x%.16llx\n", 107 indent, "", 108 sregs->cr8, sregs->efer, sregs->apic_base); 109 110 fprintf(stream, "%*sinterrupt_bitmap:\n", indent, ""); 111 for (i = 0; i < (KVM_NR_INTERRUPTS + 63) / 64; i++) { 112 fprintf(stream, "%*s%.16llx\n", indent + 2, "", 113 sregs->interrupt_bitmap[i]); 114 } 115 } 116 117 bool kvm_is_tdp_enabled(void) 118 { 119 if (host_cpu_is_intel) 120 return get_kvm_intel_param_bool("ept"); 121 else 122 return get_kvm_amd_param_bool("npt"); 123 } 124 125 void virt_arch_pgd_alloc(struct kvm_vm *vm) 126 { 127 TEST_ASSERT(vm->mode == VM_MODE_PXXV48_4K, "Attempt to use " 128 "unknown or unsupported guest mode, mode: 0x%x", vm->mode); 129 130 /* If needed, create page map l4 table. */ 131 if (!vm->pgd_created) { 132 vm->pgd = vm_alloc_page_table(vm); 133 vm->pgd_created = true; 134 } 135 } 136 137 static void *virt_get_pte(struct kvm_vm *vm, uint64_t *parent_pte, 138 uint64_t vaddr, int level) 139 { 140 uint64_t pt_gpa = PTE_GET_PA(*parent_pte); 141 uint64_t *page_table = addr_gpa2hva(vm, pt_gpa); 142 int index = (vaddr >> PG_LEVEL_SHIFT(level)) & 0x1ffu; 143 144 TEST_ASSERT((*parent_pte & PTE_PRESENT_MASK) || parent_pte == &vm->pgd, 145 "Parent PTE (level %d) not PRESENT for gva: 0x%08lx", 146 level + 1, vaddr); 147 148 return &page_table[index]; 149 } 150 151 static uint64_t *virt_create_upper_pte(struct kvm_vm *vm, 152 uint64_t *parent_pte, 153 uint64_t vaddr, 154 uint64_t paddr, 155 int current_level, 156 int target_level) 157 { 158 uint64_t *pte = virt_get_pte(vm, parent_pte, vaddr, current_level); 159 160 paddr = vm_untag_gpa(vm, paddr); 161 162 if (!(*pte & PTE_PRESENT_MASK)) { 163 *pte = PTE_PRESENT_MASK | PTE_WRITABLE_MASK; 164 if (current_level == target_level) 165 *pte |= PTE_LARGE_MASK | (paddr & PHYSICAL_PAGE_MASK); 166 else 167 *pte |= vm_alloc_page_table(vm) & PHYSICAL_PAGE_MASK; 168 } else { 169 /* 170 * Entry already present. Assert that the caller doesn't want 171 * a hugepage at this level, and that there isn't a hugepage at 172 * this level. 173 */ 174 TEST_ASSERT(current_level != target_level, 175 "Cannot create hugepage at level: %u, vaddr: 0x%lx", 176 current_level, vaddr); 177 TEST_ASSERT(!(*pte & PTE_LARGE_MASK), 178 "Cannot create page table at level: %u, vaddr: 0x%lx", 179 current_level, vaddr); 180 } 181 return pte; 182 } 183 184 void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, int level) 185 { 186 const uint64_t pg_size = PG_LEVEL_SIZE(level); 187 uint64_t *pml4e, *pdpe, *pde; 188 uint64_t *pte; 189 190 TEST_ASSERT(vm->mode == VM_MODE_PXXV48_4K, 191 "Unknown or unsupported guest mode, mode: 0x%x", vm->mode); 192 193 TEST_ASSERT((vaddr % pg_size) == 0, 194 "Virtual address not aligned,\n" 195 "vaddr: 0x%lx page size: 0x%lx", vaddr, pg_size); 196 TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, (vaddr >> vm->page_shift)), 197 "Invalid virtual address, vaddr: 0x%lx", vaddr); 198 TEST_ASSERT((paddr % pg_size) == 0, 199 "Physical address not aligned,\n" 200 " paddr: 0x%lx page size: 0x%lx", paddr, pg_size); 201 TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn, 202 "Physical address beyond maximum supported,\n" 203 " paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", 204 paddr, vm->max_gfn, vm->page_size); 205 TEST_ASSERT(vm_untag_gpa(vm, paddr) == paddr, 206 "Unexpected bits in paddr: %lx", paddr); 207 208 /* 209 * Allocate upper level page tables, if not already present. Return 210 * early if a hugepage was created. 211 */ 212 pml4e = virt_create_upper_pte(vm, &vm->pgd, vaddr, paddr, PG_LEVEL_512G, level); 213 if (*pml4e & PTE_LARGE_MASK) 214 return; 215 216 pdpe = virt_create_upper_pte(vm, pml4e, vaddr, paddr, PG_LEVEL_1G, level); 217 if (*pdpe & PTE_LARGE_MASK) 218 return; 219 220 pde = virt_create_upper_pte(vm, pdpe, vaddr, paddr, PG_LEVEL_2M, level); 221 if (*pde & PTE_LARGE_MASK) 222 return; 223 224 /* Fill in page table entry. */ 225 pte = virt_get_pte(vm, pde, vaddr, PG_LEVEL_4K); 226 TEST_ASSERT(!(*pte & PTE_PRESENT_MASK), 227 "PTE already present for 4k page at vaddr: 0x%lx", vaddr); 228 *pte = PTE_PRESENT_MASK | PTE_WRITABLE_MASK | (paddr & PHYSICAL_PAGE_MASK); 229 230 /* 231 * Neither SEV nor TDX supports shared page tables, so only the final 232 * leaf PTE needs manually set the C/S-bit. 233 */ 234 if (vm_is_gpa_protected(vm, paddr)) 235 *pte |= vm->arch.c_bit; 236 else 237 *pte |= vm->arch.s_bit; 238 } 239 240 void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr) 241 { 242 __virt_pg_map(vm, vaddr, paddr, PG_LEVEL_4K); 243 } 244 245 void virt_map_level(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, 246 uint64_t nr_bytes, int level) 247 { 248 uint64_t pg_size = PG_LEVEL_SIZE(level); 249 uint64_t nr_pages = nr_bytes / pg_size; 250 int i; 251 252 TEST_ASSERT(nr_bytes % pg_size == 0, 253 "Region size not aligned: nr_bytes: 0x%lx, page size: 0x%lx", 254 nr_bytes, pg_size); 255 256 for (i = 0; i < nr_pages; i++) { 257 __virt_pg_map(vm, vaddr, paddr, level); 258 259 vaddr += pg_size; 260 paddr += pg_size; 261 } 262 } 263 264 static bool vm_is_target_pte(uint64_t *pte, int *level, int current_level) 265 { 266 if (*pte & PTE_LARGE_MASK) { 267 TEST_ASSERT(*level == PG_LEVEL_NONE || 268 *level == current_level, 269 "Unexpected hugepage at level %d", current_level); 270 *level = current_level; 271 } 272 273 return *level == current_level; 274 } 275 276 uint64_t *__vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr, 277 int *level) 278 { 279 uint64_t *pml4e, *pdpe, *pde; 280 281 TEST_ASSERT(!vm->arch.is_pt_protected, 282 "Walking page tables of protected guests is impossible"); 283 284 TEST_ASSERT(*level >= PG_LEVEL_NONE && *level < PG_LEVEL_NUM, 285 "Invalid PG_LEVEL_* '%d'", *level); 286 287 TEST_ASSERT(vm->mode == VM_MODE_PXXV48_4K, "Attempt to use " 288 "unknown or unsupported guest mode, mode: 0x%x", vm->mode); 289 TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, 290 (vaddr >> vm->page_shift)), 291 "Invalid virtual address, vaddr: 0x%lx", 292 vaddr); 293 /* 294 * Based on the mode check above there are 48 bits in the vaddr, so 295 * shift 16 to sign extend the last bit (bit-47), 296 */ 297 TEST_ASSERT(vaddr == (((int64_t)vaddr << 16) >> 16), 298 "Canonical check failed. The virtual address is invalid."); 299 300 pml4e = virt_get_pte(vm, &vm->pgd, vaddr, PG_LEVEL_512G); 301 if (vm_is_target_pte(pml4e, level, PG_LEVEL_512G)) 302 return pml4e; 303 304 pdpe = virt_get_pte(vm, pml4e, vaddr, PG_LEVEL_1G); 305 if (vm_is_target_pte(pdpe, level, PG_LEVEL_1G)) 306 return pdpe; 307 308 pde = virt_get_pte(vm, pdpe, vaddr, PG_LEVEL_2M); 309 if (vm_is_target_pte(pde, level, PG_LEVEL_2M)) 310 return pde; 311 312 return virt_get_pte(vm, pde, vaddr, PG_LEVEL_4K); 313 } 314 315 uint64_t *vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr) 316 { 317 int level = PG_LEVEL_4K; 318 319 return __vm_get_page_table_entry(vm, vaddr, &level); 320 } 321 322 void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent) 323 { 324 uint64_t *pml4e, *pml4e_start; 325 uint64_t *pdpe, *pdpe_start; 326 uint64_t *pde, *pde_start; 327 uint64_t *pte, *pte_start; 328 329 if (!vm->pgd_created) 330 return; 331 332 fprintf(stream, "%*s " 333 " no\n", indent, ""); 334 fprintf(stream, "%*s index hvaddr gpaddr " 335 "addr w exec dirty\n", 336 indent, ""); 337 pml4e_start = (uint64_t *) addr_gpa2hva(vm, vm->pgd); 338 for (uint16_t n1 = 0; n1 <= 0x1ffu; n1++) { 339 pml4e = &pml4e_start[n1]; 340 if (!(*pml4e & PTE_PRESENT_MASK)) 341 continue; 342 fprintf(stream, "%*spml4e 0x%-3zx %p 0x%-12lx 0x%-10llx %u " 343 " %u\n", 344 indent, "", 345 pml4e - pml4e_start, pml4e, 346 addr_hva2gpa(vm, pml4e), PTE_GET_PFN(*pml4e), 347 !!(*pml4e & PTE_WRITABLE_MASK), !!(*pml4e & PTE_NX_MASK)); 348 349 pdpe_start = addr_gpa2hva(vm, *pml4e & PHYSICAL_PAGE_MASK); 350 for (uint16_t n2 = 0; n2 <= 0x1ffu; n2++) { 351 pdpe = &pdpe_start[n2]; 352 if (!(*pdpe & PTE_PRESENT_MASK)) 353 continue; 354 fprintf(stream, "%*spdpe 0x%-3zx %p 0x%-12lx 0x%-10llx " 355 "%u %u\n", 356 indent, "", 357 pdpe - pdpe_start, pdpe, 358 addr_hva2gpa(vm, pdpe), 359 PTE_GET_PFN(*pdpe), !!(*pdpe & PTE_WRITABLE_MASK), 360 !!(*pdpe & PTE_NX_MASK)); 361 362 pde_start = addr_gpa2hva(vm, *pdpe & PHYSICAL_PAGE_MASK); 363 for (uint16_t n3 = 0; n3 <= 0x1ffu; n3++) { 364 pde = &pde_start[n3]; 365 if (!(*pde & PTE_PRESENT_MASK)) 366 continue; 367 fprintf(stream, "%*spde 0x%-3zx %p " 368 "0x%-12lx 0x%-10llx %u %u\n", 369 indent, "", pde - pde_start, pde, 370 addr_hva2gpa(vm, pde), 371 PTE_GET_PFN(*pde), !!(*pde & PTE_WRITABLE_MASK), 372 !!(*pde & PTE_NX_MASK)); 373 374 pte_start = addr_gpa2hva(vm, *pde & PHYSICAL_PAGE_MASK); 375 for (uint16_t n4 = 0; n4 <= 0x1ffu; n4++) { 376 pte = &pte_start[n4]; 377 if (!(*pte & PTE_PRESENT_MASK)) 378 continue; 379 fprintf(stream, "%*spte 0x%-3zx %p " 380 "0x%-12lx 0x%-10llx %u %u " 381 " %u 0x%-10lx\n", 382 indent, "", 383 pte - pte_start, pte, 384 addr_hva2gpa(vm, pte), 385 PTE_GET_PFN(*pte), 386 !!(*pte & PTE_WRITABLE_MASK), 387 !!(*pte & PTE_NX_MASK), 388 !!(*pte & PTE_DIRTY_MASK), 389 ((uint64_t) n1 << 27) 390 | ((uint64_t) n2 << 18) 391 | ((uint64_t) n3 << 9) 392 | ((uint64_t) n4)); 393 } 394 } 395 } 396 } 397 } 398 399 /* 400 * Set Unusable Segment 401 * 402 * Input Args: None 403 * 404 * Output Args: 405 * segp - Pointer to segment register 406 * 407 * Return: None 408 * 409 * Sets the segment register pointed to by @segp to an unusable state. 410 */ 411 static void kvm_seg_set_unusable(struct kvm_segment *segp) 412 { 413 memset(segp, 0, sizeof(*segp)); 414 segp->unusable = true; 415 } 416 417 static void kvm_seg_fill_gdt_64bit(struct kvm_vm *vm, struct kvm_segment *segp) 418 { 419 void *gdt = addr_gva2hva(vm, vm->arch.gdt); 420 struct desc64 *desc = gdt + (segp->selector >> 3) * 8; 421 422 desc->limit0 = segp->limit & 0xFFFF; 423 desc->base0 = segp->base & 0xFFFF; 424 desc->base1 = segp->base >> 16; 425 desc->type = segp->type; 426 desc->s = segp->s; 427 desc->dpl = segp->dpl; 428 desc->p = segp->present; 429 desc->limit1 = segp->limit >> 16; 430 desc->avl = segp->avl; 431 desc->l = segp->l; 432 desc->db = segp->db; 433 desc->g = segp->g; 434 desc->base2 = segp->base >> 24; 435 if (!segp->s) 436 desc->base3 = segp->base >> 32; 437 } 438 439 static void kvm_seg_set_kernel_code_64bit(struct kvm_segment *segp) 440 { 441 memset(segp, 0, sizeof(*segp)); 442 segp->selector = KERNEL_CS; 443 segp->limit = 0xFFFFFFFFu; 444 segp->s = 0x1; /* kTypeCodeData */ 445 segp->type = 0x08 | 0x01 | 0x02; /* kFlagCode | kFlagCodeAccessed 446 * | kFlagCodeReadable 447 */ 448 segp->g = true; 449 segp->l = true; 450 segp->present = 1; 451 } 452 453 static void kvm_seg_set_kernel_data_64bit(struct kvm_segment *segp) 454 { 455 memset(segp, 0, sizeof(*segp)); 456 segp->selector = KERNEL_DS; 457 segp->limit = 0xFFFFFFFFu; 458 segp->s = 0x1; /* kTypeCodeData */ 459 segp->type = 0x00 | 0x01 | 0x02; /* kFlagData | kFlagDataAccessed 460 * | kFlagDataWritable 461 */ 462 segp->g = true; 463 segp->present = true; 464 } 465 466 vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva) 467 { 468 int level = PG_LEVEL_NONE; 469 uint64_t *pte = __vm_get_page_table_entry(vm, gva, &level); 470 471 TEST_ASSERT(*pte & PTE_PRESENT_MASK, 472 "Leaf PTE not PRESENT for gva: 0x%08lx", gva); 473 474 /* 475 * No need for a hugepage mask on the PTE, x86-64 requires the "unused" 476 * address bits to be zero. 477 */ 478 return vm_untag_gpa(vm, PTE_GET_PA(*pte)) | (gva & ~HUGEPAGE_MASK(level)); 479 } 480 481 static void kvm_seg_set_tss_64bit(vm_vaddr_t base, struct kvm_segment *segp) 482 { 483 memset(segp, 0, sizeof(*segp)); 484 segp->base = base; 485 segp->limit = 0x67; 486 segp->selector = KERNEL_TSS; 487 segp->type = 0xb; 488 segp->present = 1; 489 } 490 491 static void vcpu_init_sregs(struct kvm_vm *vm, struct kvm_vcpu *vcpu) 492 { 493 struct kvm_sregs sregs; 494 495 TEST_ASSERT_EQ(vm->mode, VM_MODE_PXXV48_4K); 496 497 /* Set mode specific system register values. */ 498 vcpu_sregs_get(vcpu, &sregs); 499 500 sregs.idt.base = vm->arch.idt; 501 sregs.idt.limit = NUM_INTERRUPTS * sizeof(struct idt_entry) - 1; 502 sregs.gdt.base = vm->arch.gdt; 503 sregs.gdt.limit = getpagesize() - 1; 504 505 sregs.cr0 = X86_CR0_PE | X86_CR0_NE | X86_CR0_PG; 506 sregs.cr4 |= X86_CR4_PAE | X86_CR4_OSFXSR; 507 if (kvm_cpu_has(X86_FEATURE_XSAVE)) 508 sregs.cr4 |= X86_CR4_OSXSAVE; 509 sregs.efer |= (EFER_LME | EFER_LMA | EFER_NX); 510 511 kvm_seg_set_unusable(&sregs.ldt); 512 kvm_seg_set_kernel_code_64bit(&sregs.cs); 513 kvm_seg_set_kernel_data_64bit(&sregs.ds); 514 kvm_seg_set_kernel_data_64bit(&sregs.es); 515 kvm_seg_set_kernel_data_64bit(&sregs.gs); 516 kvm_seg_set_tss_64bit(vm->arch.tss, &sregs.tr); 517 518 sregs.cr3 = vm->pgd; 519 vcpu_sregs_set(vcpu, &sregs); 520 } 521 522 static void vcpu_init_xcrs(struct kvm_vm *vm, struct kvm_vcpu *vcpu) 523 { 524 struct kvm_xcrs xcrs = { 525 .nr_xcrs = 1, 526 .xcrs[0].xcr = 0, 527 .xcrs[0].value = kvm_cpu_supported_xcr0(), 528 }; 529 530 if (!kvm_cpu_has(X86_FEATURE_XSAVE)) 531 return; 532 533 vcpu_xcrs_set(vcpu, &xcrs); 534 } 535 536 static void set_idt_entry(struct kvm_vm *vm, int vector, unsigned long addr, 537 int dpl, unsigned short selector) 538 { 539 struct idt_entry *base = 540 (struct idt_entry *)addr_gva2hva(vm, vm->arch.idt); 541 struct idt_entry *e = &base[vector]; 542 543 memset(e, 0, sizeof(*e)); 544 e->offset0 = addr; 545 e->selector = selector; 546 e->ist = 0; 547 e->type = 14; 548 e->dpl = dpl; 549 e->p = 1; 550 e->offset1 = addr >> 16; 551 e->offset2 = addr >> 32; 552 } 553 554 static bool kvm_fixup_exception(struct ex_regs *regs) 555 { 556 if (regs->r9 != KVM_EXCEPTION_MAGIC || regs->rip != regs->r10) 557 return false; 558 559 if (regs->vector == DE_VECTOR) 560 return false; 561 562 regs->rip = regs->r11; 563 regs->r9 = regs->vector; 564 regs->r10 = regs->error_code; 565 return true; 566 } 567 568 void route_exception(struct ex_regs *regs) 569 { 570 typedef void(*handler)(struct ex_regs *); 571 handler *handlers = (handler *)exception_handlers; 572 573 if (handlers && handlers[regs->vector]) { 574 handlers[regs->vector](regs); 575 return; 576 } 577 578 if (kvm_fixup_exception(regs)) 579 return; 580 581 GUEST_FAIL("Unhandled exception '0x%lx' at guest RIP '0x%lx'", 582 regs->vector, regs->rip); 583 } 584 585 static void vm_init_descriptor_tables(struct kvm_vm *vm) 586 { 587 extern void *idt_handlers; 588 struct kvm_segment seg; 589 int i; 590 591 vm->arch.gdt = __vm_vaddr_alloc_page(vm, MEM_REGION_DATA); 592 vm->arch.idt = __vm_vaddr_alloc_page(vm, MEM_REGION_DATA); 593 vm->handlers = __vm_vaddr_alloc_page(vm, MEM_REGION_DATA); 594 vm->arch.tss = __vm_vaddr_alloc_page(vm, MEM_REGION_DATA); 595 596 /* Handlers have the same address in both address spaces.*/ 597 for (i = 0; i < NUM_INTERRUPTS; i++) 598 set_idt_entry(vm, i, (unsigned long)(&idt_handlers)[i], 0, KERNEL_CS); 599 600 *(vm_vaddr_t *)addr_gva2hva(vm, (vm_vaddr_t)(&exception_handlers)) = vm->handlers; 601 602 kvm_seg_set_kernel_code_64bit(&seg); 603 kvm_seg_fill_gdt_64bit(vm, &seg); 604 605 kvm_seg_set_kernel_data_64bit(&seg); 606 kvm_seg_fill_gdt_64bit(vm, &seg); 607 608 kvm_seg_set_tss_64bit(vm->arch.tss, &seg); 609 kvm_seg_fill_gdt_64bit(vm, &seg); 610 } 611 612 void vm_install_exception_handler(struct kvm_vm *vm, int vector, 613 void (*handler)(struct ex_regs *)) 614 { 615 vm_vaddr_t *handlers = (vm_vaddr_t *)addr_gva2hva(vm, vm->handlers); 616 617 handlers[vector] = (vm_vaddr_t)handler; 618 } 619 620 void assert_on_unhandled_exception(struct kvm_vcpu *vcpu) 621 { 622 struct ucall uc; 623 624 if (get_ucall(vcpu, &uc) == UCALL_ABORT) 625 REPORT_GUEST_ASSERT(uc); 626 } 627 628 void kvm_arch_vm_post_create(struct kvm_vm *vm) 629 { 630 int r; 631 632 TEST_ASSERT(kvm_has_cap(KVM_CAP_GET_TSC_KHZ), 633 "Require KVM_GET_TSC_KHZ to provide udelay() to guest."); 634 635 vm_create_irqchip(vm); 636 vm_init_descriptor_tables(vm); 637 638 sync_global_to_guest(vm, host_cpu_is_intel); 639 sync_global_to_guest(vm, host_cpu_is_amd); 640 sync_global_to_guest(vm, is_forced_emulation_enabled); 641 642 if (vm->type == KVM_X86_SEV_VM || vm->type == KVM_X86_SEV_ES_VM) { 643 struct kvm_sev_init init = { 0 }; 644 645 vm_sev_ioctl(vm, KVM_SEV_INIT2, &init); 646 } 647 648 r = __vm_ioctl(vm, KVM_GET_TSC_KHZ, NULL); 649 TEST_ASSERT(r > 0, "KVM_GET_TSC_KHZ did not provide a valid TSC frequency."); 650 guest_tsc_khz = r; 651 sync_global_to_guest(vm, guest_tsc_khz); 652 } 653 654 void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code) 655 { 656 struct kvm_regs regs; 657 658 vcpu_regs_get(vcpu, ®s); 659 regs.rip = (unsigned long) guest_code; 660 vcpu_regs_set(vcpu, ®s); 661 } 662 663 struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id) 664 { 665 struct kvm_mp_state mp_state; 666 struct kvm_regs regs; 667 vm_vaddr_t stack_vaddr; 668 struct kvm_vcpu *vcpu; 669 670 stack_vaddr = __vm_vaddr_alloc(vm, DEFAULT_STACK_PGS * getpagesize(), 671 DEFAULT_GUEST_STACK_VADDR_MIN, 672 MEM_REGION_DATA); 673 674 stack_vaddr += DEFAULT_STACK_PGS * getpagesize(); 675 676 /* 677 * Align stack to match calling sequence requirements in section "The 678 * Stack Frame" of the System V ABI AMD64 Architecture Processor 679 * Supplement, which requires the value (%rsp + 8) to be a multiple of 680 * 16 when control is transferred to the function entry point. 681 * 682 * If this code is ever used to launch a vCPU with 32-bit entry point it 683 * may need to subtract 4 bytes instead of 8 bytes. 684 */ 685 TEST_ASSERT(IS_ALIGNED(stack_vaddr, PAGE_SIZE), 686 "__vm_vaddr_alloc() did not provide a page-aligned address"); 687 stack_vaddr -= 8; 688 689 vcpu = __vm_vcpu_add(vm, vcpu_id); 690 vcpu_init_cpuid(vcpu, kvm_get_supported_cpuid()); 691 vcpu_init_sregs(vm, vcpu); 692 vcpu_init_xcrs(vm, vcpu); 693 694 /* Setup guest general purpose registers */ 695 vcpu_regs_get(vcpu, ®s); 696 regs.rflags = regs.rflags | 0x2; 697 regs.rsp = stack_vaddr; 698 vcpu_regs_set(vcpu, ®s); 699 700 /* Setup the MP state */ 701 mp_state.mp_state = 0; 702 vcpu_mp_state_set(vcpu, &mp_state); 703 704 /* 705 * Refresh CPUID after setting SREGS and XCR0, so that KVM's "runtime" 706 * updates to guest CPUID, e.g. for OSXSAVE and XSAVE state size, are 707 * reflected into selftests' vCPU CPUID cache, i.e. so that the cache 708 * is consistent with vCPU state. 709 */ 710 vcpu_get_cpuid(vcpu); 711 return vcpu; 712 } 713 714 struct kvm_vcpu *vm_arch_vcpu_recreate(struct kvm_vm *vm, uint32_t vcpu_id) 715 { 716 struct kvm_vcpu *vcpu = __vm_vcpu_add(vm, vcpu_id); 717 718 vcpu_init_cpuid(vcpu, kvm_get_supported_cpuid()); 719 720 return vcpu; 721 } 722 723 void vcpu_arch_free(struct kvm_vcpu *vcpu) 724 { 725 if (vcpu->cpuid) 726 free(vcpu->cpuid); 727 } 728 729 /* Do not use kvm_supported_cpuid directly except for validity checks. */ 730 static void *kvm_supported_cpuid; 731 732 const struct kvm_cpuid2 *kvm_get_supported_cpuid(void) 733 { 734 int kvm_fd; 735 736 if (kvm_supported_cpuid) 737 return kvm_supported_cpuid; 738 739 kvm_supported_cpuid = allocate_kvm_cpuid2(MAX_NR_CPUID_ENTRIES); 740 kvm_fd = open_kvm_dev_path_or_exit(); 741 742 kvm_ioctl(kvm_fd, KVM_GET_SUPPORTED_CPUID, 743 (struct kvm_cpuid2 *)kvm_supported_cpuid); 744 745 close(kvm_fd); 746 return kvm_supported_cpuid; 747 } 748 749 static uint32_t __kvm_cpu_has(const struct kvm_cpuid2 *cpuid, 750 uint32_t function, uint32_t index, 751 uint8_t reg, uint8_t lo, uint8_t hi) 752 { 753 const struct kvm_cpuid_entry2 *entry; 754 int i; 755 756 for (i = 0; i < cpuid->nent; i++) { 757 entry = &cpuid->entries[i]; 758 759 /* 760 * The output registers in kvm_cpuid_entry2 are in alphabetical 761 * order, but kvm_x86_cpu_feature matches that mess, so yay 762 * pointer shenanigans! 763 */ 764 if (entry->function == function && entry->index == index) 765 return ((&entry->eax)[reg] & GENMASK(hi, lo)) >> lo; 766 } 767 768 return 0; 769 } 770 771 bool kvm_cpuid_has(const struct kvm_cpuid2 *cpuid, 772 struct kvm_x86_cpu_feature feature) 773 { 774 return __kvm_cpu_has(cpuid, feature.function, feature.index, 775 feature.reg, feature.bit, feature.bit); 776 } 777 778 uint32_t kvm_cpuid_property(const struct kvm_cpuid2 *cpuid, 779 struct kvm_x86_cpu_property property) 780 { 781 return __kvm_cpu_has(cpuid, property.function, property.index, 782 property.reg, property.lo_bit, property.hi_bit); 783 } 784 785 uint64_t kvm_get_feature_msr(uint64_t msr_index) 786 { 787 struct { 788 struct kvm_msrs header; 789 struct kvm_msr_entry entry; 790 } buffer = {}; 791 int r, kvm_fd; 792 793 buffer.header.nmsrs = 1; 794 buffer.entry.index = msr_index; 795 kvm_fd = open_kvm_dev_path_or_exit(); 796 797 r = __kvm_ioctl(kvm_fd, KVM_GET_MSRS, &buffer.header); 798 TEST_ASSERT(r == 1, KVM_IOCTL_ERROR(KVM_GET_MSRS, r)); 799 800 close(kvm_fd); 801 return buffer.entry.data; 802 } 803 804 void __vm_xsave_require_permission(uint64_t xfeature, const char *name) 805 { 806 int kvm_fd; 807 u64 bitmask; 808 long rc; 809 struct kvm_device_attr attr = { 810 .group = 0, 811 .attr = KVM_X86_XCOMP_GUEST_SUPP, 812 .addr = (unsigned long) &bitmask, 813 }; 814 815 TEST_ASSERT(!kvm_supported_cpuid, 816 "kvm_get_supported_cpuid() cannot be used before ARCH_REQ_XCOMP_GUEST_PERM"); 817 818 TEST_ASSERT(is_power_of_2(xfeature), 819 "Dynamic XFeatures must be enabled one at a time"); 820 821 kvm_fd = open_kvm_dev_path_or_exit(); 822 rc = __kvm_ioctl(kvm_fd, KVM_GET_DEVICE_ATTR, &attr); 823 close(kvm_fd); 824 825 if (rc == -1 && (errno == ENXIO || errno == EINVAL)) 826 __TEST_REQUIRE(0, "KVM_X86_XCOMP_GUEST_SUPP not supported"); 827 828 TEST_ASSERT(rc == 0, "KVM_GET_DEVICE_ATTR(0, KVM_X86_XCOMP_GUEST_SUPP) error: %ld", rc); 829 830 __TEST_REQUIRE(bitmask & xfeature, 831 "Required XSAVE feature '%s' not supported", name); 832 833 TEST_REQUIRE(!syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_GUEST_PERM, ilog2(xfeature))); 834 835 rc = syscall(SYS_arch_prctl, ARCH_GET_XCOMP_GUEST_PERM, &bitmask); 836 TEST_ASSERT(rc == 0, "prctl(ARCH_GET_XCOMP_GUEST_PERM) error: %ld", rc); 837 TEST_ASSERT(bitmask & xfeature, 838 "'%s' (0x%lx) not permitted after prctl(ARCH_REQ_XCOMP_GUEST_PERM) permitted=0x%lx", 839 name, xfeature, bitmask); 840 } 841 842 void vcpu_init_cpuid(struct kvm_vcpu *vcpu, const struct kvm_cpuid2 *cpuid) 843 { 844 TEST_ASSERT(cpuid != vcpu->cpuid, "@cpuid can't be the vCPU's CPUID"); 845 846 /* Allow overriding the default CPUID. */ 847 if (vcpu->cpuid && vcpu->cpuid->nent < cpuid->nent) { 848 free(vcpu->cpuid); 849 vcpu->cpuid = NULL; 850 } 851 852 if (!vcpu->cpuid) 853 vcpu->cpuid = allocate_kvm_cpuid2(cpuid->nent); 854 855 memcpy(vcpu->cpuid, cpuid, kvm_cpuid2_size(cpuid->nent)); 856 vcpu_set_cpuid(vcpu); 857 } 858 859 void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu, 860 struct kvm_x86_cpu_property property, 861 uint32_t value) 862 { 863 struct kvm_cpuid_entry2 *entry; 864 865 entry = __vcpu_get_cpuid_entry(vcpu, property.function, property.index); 866 867 (&entry->eax)[property.reg] &= ~GENMASK(property.hi_bit, property.lo_bit); 868 (&entry->eax)[property.reg] |= value << property.lo_bit; 869 870 vcpu_set_cpuid(vcpu); 871 872 /* Sanity check that @value doesn't exceed the bounds in any way. */ 873 TEST_ASSERT_EQ(kvm_cpuid_property(vcpu->cpuid, property), value); 874 } 875 876 void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, uint32_t function) 877 { 878 struct kvm_cpuid_entry2 *entry = vcpu_get_cpuid_entry(vcpu, function); 879 880 entry->eax = 0; 881 entry->ebx = 0; 882 entry->ecx = 0; 883 entry->edx = 0; 884 vcpu_set_cpuid(vcpu); 885 } 886 887 void vcpu_set_or_clear_cpuid_feature(struct kvm_vcpu *vcpu, 888 struct kvm_x86_cpu_feature feature, 889 bool set) 890 { 891 struct kvm_cpuid_entry2 *entry; 892 u32 *reg; 893 894 entry = __vcpu_get_cpuid_entry(vcpu, feature.function, feature.index); 895 reg = (&entry->eax) + feature.reg; 896 897 if (set) 898 *reg |= BIT(feature.bit); 899 else 900 *reg &= ~BIT(feature.bit); 901 902 vcpu_set_cpuid(vcpu); 903 } 904 905 uint64_t vcpu_get_msr(struct kvm_vcpu *vcpu, uint64_t msr_index) 906 { 907 struct { 908 struct kvm_msrs header; 909 struct kvm_msr_entry entry; 910 } buffer = {}; 911 912 buffer.header.nmsrs = 1; 913 buffer.entry.index = msr_index; 914 915 vcpu_msrs_get(vcpu, &buffer.header); 916 917 return buffer.entry.data; 918 } 919 920 int _vcpu_set_msr(struct kvm_vcpu *vcpu, uint64_t msr_index, uint64_t msr_value) 921 { 922 struct { 923 struct kvm_msrs header; 924 struct kvm_msr_entry entry; 925 } buffer = {}; 926 927 memset(&buffer, 0, sizeof(buffer)); 928 buffer.header.nmsrs = 1; 929 buffer.entry.index = msr_index; 930 buffer.entry.data = msr_value; 931 932 return __vcpu_ioctl(vcpu, KVM_SET_MSRS, &buffer.header); 933 } 934 935 void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...) 936 { 937 va_list ap; 938 struct kvm_regs regs; 939 940 TEST_ASSERT(num >= 1 && num <= 6, "Unsupported number of args,\n" 941 " num: %u", 942 num); 943 944 va_start(ap, num); 945 vcpu_regs_get(vcpu, ®s); 946 947 if (num >= 1) 948 regs.rdi = va_arg(ap, uint64_t); 949 950 if (num >= 2) 951 regs.rsi = va_arg(ap, uint64_t); 952 953 if (num >= 3) 954 regs.rdx = va_arg(ap, uint64_t); 955 956 if (num >= 4) 957 regs.rcx = va_arg(ap, uint64_t); 958 959 if (num >= 5) 960 regs.r8 = va_arg(ap, uint64_t); 961 962 if (num >= 6) 963 regs.r9 = va_arg(ap, uint64_t); 964 965 vcpu_regs_set(vcpu, ®s); 966 va_end(ap); 967 } 968 969 void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent) 970 { 971 struct kvm_regs regs; 972 struct kvm_sregs sregs; 973 974 fprintf(stream, "%*svCPU ID: %u\n", indent, "", vcpu->id); 975 976 fprintf(stream, "%*sregs:\n", indent + 2, ""); 977 vcpu_regs_get(vcpu, ®s); 978 regs_dump(stream, ®s, indent + 4); 979 980 fprintf(stream, "%*ssregs:\n", indent + 2, ""); 981 vcpu_sregs_get(vcpu, &sregs); 982 sregs_dump(stream, &sregs, indent + 4); 983 } 984 985 static struct kvm_msr_list *__kvm_get_msr_index_list(bool feature_msrs) 986 { 987 struct kvm_msr_list *list; 988 struct kvm_msr_list nmsrs; 989 int kvm_fd, r; 990 991 kvm_fd = open_kvm_dev_path_or_exit(); 992 993 nmsrs.nmsrs = 0; 994 if (!feature_msrs) 995 r = __kvm_ioctl(kvm_fd, KVM_GET_MSR_INDEX_LIST, &nmsrs); 996 else 997 r = __kvm_ioctl(kvm_fd, KVM_GET_MSR_FEATURE_INDEX_LIST, &nmsrs); 998 999 TEST_ASSERT(r == -1 && errno == E2BIG, 1000 "Expected -E2BIG, got rc: %i errno: %i (%s)", 1001 r, errno, strerror(errno)); 1002 1003 list = malloc(sizeof(*list) + nmsrs.nmsrs * sizeof(list->indices[0])); 1004 TEST_ASSERT(list, "-ENOMEM when allocating MSR index list"); 1005 list->nmsrs = nmsrs.nmsrs; 1006 1007 if (!feature_msrs) 1008 kvm_ioctl(kvm_fd, KVM_GET_MSR_INDEX_LIST, list); 1009 else 1010 kvm_ioctl(kvm_fd, KVM_GET_MSR_FEATURE_INDEX_LIST, list); 1011 close(kvm_fd); 1012 1013 TEST_ASSERT(list->nmsrs == nmsrs.nmsrs, 1014 "Number of MSRs in list changed, was %d, now %d", 1015 nmsrs.nmsrs, list->nmsrs); 1016 return list; 1017 } 1018 1019 const struct kvm_msr_list *kvm_get_msr_index_list(void) 1020 { 1021 static const struct kvm_msr_list *list; 1022 1023 if (!list) 1024 list = __kvm_get_msr_index_list(false); 1025 return list; 1026 } 1027 1028 1029 const struct kvm_msr_list *kvm_get_feature_msr_index_list(void) 1030 { 1031 static const struct kvm_msr_list *list; 1032 1033 if (!list) 1034 list = __kvm_get_msr_index_list(true); 1035 return list; 1036 } 1037 1038 bool kvm_msr_is_in_save_restore_list(uint32_t msr_index) 1039 { 1040 const struct kvm_msr_list *list = kvm_get_msr_index_list(); 1041 int i; 1042 1043 for (i = 0; i < list->nmsrs; ++i) { 1044 if (list->indices[i] == msr_index) 1045 return true; 1046 } 1047 1048 return false; 1049 } 1050 1051 static void vcpu_save_xsave_state(struct kvm_vcpu *vcpu, 1052 struct kvm_x86_state *state) 1053 { 1054 int size = vm_check_cap(vcpu->vm, KVM_CAP_XSAVE2); 1055 1056 if (size) { 1057 state->xsave = malloc(size); 1058 vcpu_xsave2_get(vcpu, state->xsave); 1059 } else { 1060 state->xsave = malloc(sizeof(struct kvm_xsave)); 1061 vcpu_xsave_get(vcpu, state->xsave); 1062 } 1063 } 1064 1065 struct kvm_x86_state *vcpu_save_state(struct kvm_vcpu *vcpu) 1066 { 1067 const struct kvm_msr_list *msr_list = kvm_get_msr_index_list(); 1068 struct kvm_x86_state *state; 1069 int i; 1070 1071 static int nested_size = -1; 1072 1073 if (nested_size == -1) { 1074 nested_size = kvm_check_cap(KVM_CAP_NESTED_STATE); 1075 TEST_ASSERT(nested_size <= sizeof(state->nested_), 1076 "Nested state size too big, %i > %zi", 1077 nested_size, sizeof(state->nested_)); 1078 } 1079 1080 /* 1081 * When KVM exits to userspace with KVM_EXIT_IO, KVM guarantees 1082 * guest state is consistent only after userspace re-enters the 1083 * kernel with KVM_RUN. Complete IO prior to migrating state 1084 * to a new VM. 1085 */ 1086 vcpu_run_complete_io(vcpu); 1087 1088 state = malloc(sizeof(*state) + msr_list->nmsrs * sizeof(state->msrs.entries[0])); 1089 TEST_ASSERT(state, "-ENOMEM when allocating kvm state"); 1090 1091 vcpu_events_get(vcpu, &state->events); 1092 vcpu_mp_state_get(vcpu, &state->mp_state); 1093 vcpu_regs_get(vcpu, &state->regs); 1094 vcpu_save_xsave_state(vcpu, state); 1095 1096 if (kvm_has_cap(KVM_CAP_XCRS)) 1097 vcpu_xcrs_get(vcpu, &state->xcrs); 1098 1099 vcpu_sregs_get(vcpu, &state->sregs); 1100 1101 if (nested_size) { 1102 state->nested.size = sizeof(state->nested_); 1103 1104 vcpu_nested_state_get(vcpu, &state->nested); 1105 TEST_ASSERT(state->nested.size <= nested_size, 1106 "Nested state size too big, %i (KVM_CHECK_CAP gave %i)", 1107 state->nested.size, nested_size); 1108 } else { 1109 state->nested.size = 0; 1110 } 1111 1112 state->msrs.nmsrs = msr_list->nmsrs; 1113 for (i = 0; i < msr_list->nmsrs; i++) 1114 state->msrs.entries[i].index = msr_list->indices[i]; 1115 vcpu_msrs_get(vcpu, &state->msrs); 1116 1117 vcpu_debugregs_get(vcpu, &state->debugregs); 1118 1119 return state; 1120 } 1121 1122 void vcpu_load_state(struct kvm_vcpu *vcpu, struct kvm_x86_state *state) 1123 { 1124 vcpu_sregs_set(vcpu, &state->sregs); 1125 vcpu_msrs_set(vcpu, &state->msrs); 1126 1127 if (kvm_has_cap(KVM_CAP_XCRS)) 1128 vcpu_xcrs_set(vcpu, &state->xcrs); 1129 1130 vcpu_xsave_set(vcpu, state->xsave); 1131 vcpu_events_set(vcpu, &state->events); 1132 vcpu_mp_state_set(vcpu, &state->mp_state); 1133 vcpu_debugregs_set(vcpu, &state->debugregs); 1134 vcpu_regs_set(vcpu, &state->regs); 1135 1136 if (state->nested.size) 1137 vcpu_nested_state_set(vcpu, &state->nested); 1138 } 1139 1140 void kvm_x86_state_cleanup(struct kvm_x86_state *state) 1141 { 1142 free(state->xsave); 1143 free(state); 1144 } 1145 1146 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits) 1147 { 1148 if (!kvm_cpu_has_p(X86_PROPERTY_MAX_PHY_ADDR)) { 1149 *pa_bits = kvm_cpu_has(X86_FEATURE_PAE) ? 36 : 32; 1150 *va_bits = 32; 1151 } else { 1152 *pa_bits = kvm_cpu_property(X86_PROPERTY_MAX_PHY_ADDR); 1153 *va_bits = kvm_cpu_property(X86_PROPERTY_MAX_VIRT_ADDR); 1154 } 1155 } 1156 1157 void kvm_init_vm_address_properties(struct kvm_vm *vm) 1158 { 1159 if (vm->type == KVM_X86_SEV_VM || vm->type == KVM_X86_SEV_ES_VM) { 1160 vm->arch.sev_fd = open_sev_dev_path_or_exit(); 1161 vm->arch.c_bit = BIT_ULL(this_cpu_property(X86_PROPERTY_SEV_C_BIT)); 1162 vm->gpa_tag_mask = vm->arch.c_bit; 1163 } else { 1164 vm->arch.sev_fd = -1; 1165 } 1166 } 1167 1168 const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid, 1169 uint32_t function, uint32_t index) 1170 { 1171 int i; 1172 1173 for (i = 0; i < cpuid->nent; i++) { 1174 if (cpuid->entries[i].function == function && 1175 cpuid->entries[i].index == index) 1176 return &cpuid->entries[i]; 1177 } 1178 1179 TEST_FAIL("CPUID function 0x%x index 0x%x not found ", function, index); 1180 1181 return NULL; 1182 } 1183 1184 #define X86_HYPERCALL(inputs...) \ 1185 ({ \ 1186 uint64_t r; \ 1187 \ 1188 asm volatile("test %[use_vmmcall], %[use_vmmcall]\n\t" \ 1189 "jnz 1f\n\t" \ 1190 "vmcall\n\t" \ 1191 "jmp 2f\n\t" \ 1192 "1: vmmcall\n\t" \ 1193 "2:" \ 1194 : "=a"(r) \ 1195 : [use_vmmcall] "r" (host_cpu_is_amd), inputs); \ 1196 \ 1197 r; \ 1198 }) 1199 1200 uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2, 1201 uint64_t a3) 1202 { 1203 return X86_HYPERCALL("a"(nr), "b"(a0), "c"(a1), "d"(a2), "S"(a3)); 1204 } 1205 1206 uint64_t __xen_hypercall(uint64_t nr, uint64_t a0, void *a1) 1207 { 1208 return X86_HYPERCALL("a"(nr), "D"(a0), "S"(a1)); 1209 } 1210 1211 void xen_hypercall(uint64_t nr, uint64_t a0, void *a1) 1212 { 1213 GUEST_ASSERT(!__xen_hypercall(nr, a0, a1)); 1214 } 1215 1216 unsigned long vm_compute_max_gfn(struct kvm_vm *vm) 1217 { 1218 const unsigned long num_ht_pages = 12 << (30 - vm->page_shift); /* 12 GiB */ 1219 unsigned long ht_gfn, max_gfn, max_pfn; 1220 uint8_t maxphyaddr, guest_maxphyaddr; 1221 1222 /* 1223 * Use "guest MAXPHYADDR" from KVM if it's available. Guest MAXPHYADDR 1224 * enumerates the max _mappable_ GPA, which can be less than the raw 1225 * MAXPHYADDR, e.g. if MAXPHYADDR=52, KVM is using TDP, and the CPU 1226 * doesn't support 5-level TDP. 1227 */ 1228 guest_maxphyaddr = kvm_cpu_property(X86_PROPERTY_GUEST_MAX_PHY_ADDR); 1229 guest_maxphyaddr = guest_maxphyaddr ?: vm->pa_bits; 1230 TEST_ASSERT(guest_maxphyaddr <= vm->pa_bits, 1231 "Guest MAXPHYADDR should never be greater than raw MAXPHYADDR"); 1232 1233 max_gfn = (1ULL << (guest_maxphyaddr - vm->page_shift)) - 1; 1234 1235 /* Avoid reserved HyperTransport region on AMD processors. */ 1236 if (!host_cpu_is_amd) 1237 return max_gfn; 1238 1239 /* On parts with <40 physical address bits, the area is fully hidden */ 1240 if (vm->pa_bits < 40) 1241 return max_gfn; 1242 1243 /* Before family 17h, the HyperTransport area is just below 1T. */ 1244 ht_gfn = (1 << 28) - num_ht_pages; 1245 if (this_cpu_family() < 0x17) 1246 goto done; 1247 1248 /* 1249 * Otherwise it's at the top of the physical address space, possibly 1250 * reduced due to SME by bits 11:6 of CPUID[0x8000001f].EBX. Use 1251 * the old conservative value if MAXPHYADDR is not enumerated. 1252 */ 1253 if (!this_cpu_has_p(X86_PROPERTY_MAX_PHY_ADDR)) 1254 goto done; 1255 1256 maxphyaddr = this_cpu_property(X86_PROPERTY_MAX_PHY_ADDR); 1257 max_pfn = (1ULL << (maxphyaddr - vm->page_shift)) - 1; 1258 1259 if (this_cpu_has_p(X86_PROPERTY_PHYS_ADDR_REDUCTION)) 1260 max_pfn >>= this_cpu_property(X86_PROPERTY_PHYS_ADDR_REDUCTION); 1261 1262 ht_gfn = max_pfn - num_ht_pages; 1263 done: 1264 return min(max_gfn, ht_gfn - 1); 1265 } 1266 1267 /* Returns true if kvm_intel was loaded with unrestricted_guest=1. */ 1268 bool vm_is_unrestricted_guest(struct kvm_vm *vm) 1269 { 1270 /* Ensure that a KVM vendor-specific module is loaded. */ 1271 if (vm == NULL) 1272 close(open_kvm_dev_path_or_exit()); 1273 1274 return get_kvm_intel_param_bool("unrestricted_guest"); 1275 } 1276 1277 void kvm_selftest_arch_init(void) 1278 { 1279 host_cpu_is_intel = this_cpu_is_intel(); 1280 host_cpu_is_amd = this_cpu_is_amd(); 1281 is_forced_emulation_enabled = kvm_is_forced_emulation_enabled(); 1282 } 1283 1284 bool sys_clocksource_is_based_on_tsc(void) 1285 { 1286 char *clk_name = sys_get_cur_clocksource(); 1287 bool ret = !strcmp(clk_name, "tsc\n") || 1288 !strcmp(clk_name, "hyperv_clocksource_tsc_page\n"); 1289 1290 free(clk_name); 1291 1292 return ret; 1293 } 1294