1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * RISC-V code 4 * 5 * Copyright (C) 2021 Western Digital Corporation or its affiliates. 6 */ 7 8 #include <linux/compiler.h> 9 #include <assert.h> 10 11 #include "kvm_util.h" 12 #include "processor.h" 13 #include "ucall_common.h" 14 15 #define DEFAULT_RISCV_GUEST_STACK_VADDR_MIN 0xac0000 16 17 static vm_vaddr_t exception_handlers; 18 19 bool __vcpu_has_ext(struct kvm_vcpu *vcpu, uint64_t ext) 20 { 21 unsigned long value = 0; 22 int ret; 23 24 ret = __vcpu_get_reg(vcpu, ext, &value); 25 26 return !ret && !!value; 27 } 28 29 static uint64_t pte_addr(struct kvm_vm *vm, uint64_t entry) 30 { 31 return ((entry & PGTBL_PTE_ADDR_MASK) >> PGTBL_PTE_ADDR_SHIFT) << 32 PGTBL_PAGE_SIZE_SHIFT; 33 } 34 35 static uint64_t ptrs_per_pte(struct kvm_vm *vm) 36 { 37 return PGTBL_PAGE_SIZE / sizeof(uint64_t); 38 } 39 40 static uint64_t pte_index_mask[] = { 41 PGTBL_L0_INDEX_MASK, 42 PGTBL_L1_INDEX_MASK, 43 PGTBL_L2_INDEX_MASK, 44 PGTBL_L3_INDEX_MASK, 45 }; 46 47 static uint32_t pte_index_shift[] = { 48 PGTBL_L0_INDEX_SHIFT, 49 PGTBL_L1_INDEX_SHIFT, 50 PGTBL_L2_INDEX_SHIFT, 51 PGTBL_L3_INDEX_SHIFT, 52 }; 53 54 static uint64_t pte_index(struct kvm_vm *vm, vm_vaddr_t gva, int level) 55 { 56 TEST_ASSERT(level > -1, 57 "Negative page table level (%d) not possible", level); 58 TEST_ASSERT(level < vm->mmu.pgtable_levels, 59 "Invalid page table level (%d)", level); 60 61 return (gva & pte_index_mask[level]) >> pte_index_shift[level]; 62 } 63 64 void virt_arch_pgd_alloc(struct kvm_vm *vm) 65 { 66 size_t nr_pages = vm_page_align(vm, ptrs_per_pte(vm) * 8) / vm->page_size; 67 68 if (vm->mmu.pgd_created) 69 return; 70 71 vm->mmu.pgd = vm_phy_pages_alloc(vm, nr_pages, 72 KVM_GUEST_PAGE_TABLE_MIN_PADDR, 73 vm->memslots[MEM_REGION_PT]); 74 vm->mmu.pgd_created = true; 75 } 76 77 void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr) 78 { 79 uint64_t *ptep, next_ppn; 80 int level = vm->mmu.pgtable_levels - 1; 81 82 TEST_ASSERT((vaddr % vm->page_size) == 0, 83 "Virtual address not on page boundary,\n" 84 " vaddr: 0x%lx vm->page_size: 0x%x", vaddr, vm->page_size); 85 TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, 86 (vaddr >> vm->page_shift)), 87 "Invalid virtual address, vaddr: 0x%lx", vaddr); 88 TEST_ASSERT((paddr % vm->page_size) == 0, 89 "Physical address not on page boundary,\n" 90 " paddr: 0x%lx vm->page_size: 0x%x", paddr, vm->page_size); 91 TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn, 92 "Physical address beyond maximum supported,\n" 93 " paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", 94 paddr, vm->max_gfn, vm->page_size); 95 96 ptep = addr_gpa2hva(vm, vm->mmu.pgd) + pte_index(vm, vaddr, level) * 8; 97 if (!*ptep) { 98 next_ppn = vm_alloc_page_table(vm) >> PGTBL_PAGE_SIZE_SHIFT; 99 *ptep = (next_ppn << PGTBL_PTE_ADDR_SHIFT) | 100 PGTBL_PTE_VALID_MASK; 101 } 102 level--; 103 104 while (level > -1) { 105 ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + 106 pte_index(vm, vaddr, level) * 8; 107 if (!*ptep && level > 0) { 108 next_ppn = vm_alloc_page_table(vm) >> 109 PGTBL_PAGE_SIZE_SHIFT; 110 *ptep = (next_ppn << PGTBL_PTE_ADDR_SHIFT) | 111 PGTBL_PTE_VALID_MASK; 112 } 113 level--; 114 } 115 116 paddr = paddr >> PGTBL_PAGE_SIZE_SHIFT; 117 *ptep = (paddr << PGTBL_PTE_ADDR_SHIFT) | 118 PGTBL_PTE_PERM_MASK | PGTBL_PTE_VALID_MASK; 119 } 120 121 vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva) 122 { 123 uint64_t *ptep; 124 int level = vm->mmu.pgtable_levels - 1; 125 126 if (!vm->mmu.pgd_created) 127 goto unmapped_gva; 128 129 ptep = addr_gpa2hva(vm, vm->mmu.pgd) + pte_index(vm, gva, level) * 8; 130 if (!ptep) 131 goto unmapped_gva; 132 level--; 133 134 while (level > -1) { 135 ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + 136 pte_index(vm, gva, level) * 8; 137 if (!ptep) 138 goto unmapped_gva; 139 level--; 140 } 141 142 return pte_addr(vm, *ptep) + (gva & (vm->page_size - 1)); 143 144 unmapped_gva: 145 TEST_FAIL("No mapping for vm virtual address gva: 0x%lx level: %d", 146 gva, level); 147 exit(1); 148 } 149 150 static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent, 151 uint64_t page, int level) 152 { 153 #ifdef DEBUG 154 static const char *const type[] = { "pte", "pmd", "pud", "p4d"}; 155 uint64_t pte, *ptep; 156 157 if (level < 0) 158 return; 159 160 for (pte = page; pte < page + ptrs_per_pte(vm) * 8; pte += 8) { 161 ptep = addr_gpa2hva(vm, pte); 162 if (!*ptep) 163 continue; 164 fprintf(stream, "%*s%s: %lx: %lx at %p\n", indent, "", 165 type[level], pte, *ptep, ptep); 166 pte_dump(stream, vm, indent + 1, 167 pte_addr(vm, *ptep), level - 1); 168 } 169 #endif 170 } 171 172 void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent) 173 { 174 struct kvm_mmu *mmu = &vm->mmu; 175 int level = mmu->pgtable_levels - 1; 176 uint64_t pgd, *ptep; 177 178 if (!mmu->pgd_created) 179 return; 180 181 for (pgd = mmu->pgd; pgd < mmu->pgd + ptrs_per_pte(vm) * 8; pgd += 8) { 182 ptep = addr_gpa2hva(vm, pgd); 183 if (!*ptep) 184 continue; 185 fprintf(stream, "%*spgd: %lx: %lx at %p\n", indent, "", 186 pgd, *ptep, ptep); 187 pte_dump(stream, vm, indent + 1, 188 pte_addr(vm, *ptep), level - 1); 189 } 190 } 191 192 void riscv_vcpu_mmu_setup(struct kvm_vcpu *vcpu) 193 { 194 struct kvm_vm *vm = vcpu->vm; 195 unsigned long satp; 196 197 /* 198 * The RISC-V Sv48 MMU mode supports 56-bit physical address 199 * for 48-bit virtual address with 4KB last level page size. 200 */ 201 switch (vm->mode) { 202 case VM_MODE_P52V48_4K: 203 case VM_MODE_P48V48_4K: 204 case VM_MODE_P40V48_4K: 205 break; 206 default: 207 TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode); 208 } 209 210 satp = (vm->mmu.pgd >> PGTBL_PAGE_SIZE_SHIFT) & SATP_PPN; 211 satp |= SATP_MODE_48; 212 213 vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(satp), satp); 214 } 215 216 void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent) 217 { 218 struct kvm_riscv_core core; 219 220 core.mode = vcpu_get_reg(vcpu, RISCV_CORE_REG(mode)); 221 core.regs.pc = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.pc)); 222 core.regs.ra = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.ra)); 223 core.regs.sp = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.sp)); 224 core.regs.gp = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.gp)); 225 core.regs.tp = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.tp)); 226 core.regs.t0 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t0)); 227 core.regs.t1 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t1)); 228 core.regs.t2 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t2)); 229 core.regs.s0 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s0)); 230 core.regs.s1 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s1)); 231 core.regs.a0 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a0)); 232 core.regs.a1 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a1)); 233 core.regs.a2 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a2)); 234 core.regs.a3 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a3)); 235 core.regs.a4 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a4)); 236 core.regs.a5 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a5)); 237 core.regs.a6 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a6)); 238 core.regs.a7 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a7)); 239 core.regs.s2 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s2)); 240 core.regs.s3 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s3)); 241 core.regs.s4 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s4)); 242 core.regs.s5 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s5)); 243 core.regs.s6 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s6)); 244 core.regs.s7 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s7)); 245 core.regs.s8 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s8)); 246 core.regs.s9 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s9)); 247 core.regs.s10 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s10)); 248 core.regs.s11 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s11)); 249 core.regs.t3 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t3)); 250 core.regs.t4 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t4)); 251 core.regs.t5 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t5)); 252 core.regs.t6 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t6)); 253 254 fprintf(stream, 255 " MODE: 0x%lx\n", core.mode); 256 fprintf(stream, 257 " PC: 0x%016lx RA: 0x%016lx SP: 0x%016lx GP: 0x%016lx\n", 258 core.regs.pc, core.regs.ra, core.regs.sp, core.regs.gp); 259 fprintf(stream, 260 " TP: 0x%016lx T0: 0x%016lx T1: 0x%016lx T2: 0x%016lx\n", 261 core.regs.tp, core.regs.t0, core.regs.t1, core.regs.t2); 262 fprintf(stream, 263 " S0: 0x%016lx S1: 0x%016lx A0: 0x%016lx A1: 0x%016lx\n", 264 core.regs.s0, core.regs.s1, core.regs.a0, core.regs.a1); 265 fprintf(stream, 266 " A2: 0x%016lx A3: 0x%016lx A4: 0x%016lx A5: 0x%016lx\n", 267 core.regs.a2, core.regs.a3, core.regs.a4, core.regs.a5); 268 fprintf(stream, 269 " A6: 0x%016lx A7: 0x%016lx S2: 0x%016lx S3: 0x%016lx\n", 270 core.regs.a6, core.regs.a7, core.regs.s2, core.regs.s3); 271 fprintf(stream, 272 " S4: 0x%016lx S5: 0x%016lx S6: 0x%016lx S7: 0x%016lx\n", 273 core.regs.s4, core.regs.s5, core.regs.s6, core.regs.s7); 274 fprintf(stream, 275 " S8: 0x%016lx S9: 0x%016lx S10: 0x%016lx S11: 0x%016lx\n", 276 core.regs.s8, core.regs.s9, core.regs.s10, core.regs.s11); 277 fprintf(stream, 278 " T3: 0x%016lx T4: 0x%016lx T5: 0x%016lx T6: 0x%016lx\n", 279 core.regs.t3, core.regs.t4, core.regs.t5, core.regs.t6); 280 } 281 282 static void __aligned(16) guest_unexp_trap(void) 283 { 284 sbi_ecall(KVM_RISCV_SELFTESTS_SBI_EXT, 285 KVM_RISCV_SELFTESTS_SBI_UNEXP, 286 0, 0, 0, 0, 0, 0); 287 } 288 289 void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code) 290 { 291 vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.pc), (unsigned long)guest_code); 292 } 293 294 struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id) 295 { 296 int r; 297 size_t stack_size; 298 unsigned long stack_vaddr; 299 unsigned long current_gp = 0; 300 struct kvm_mp_state mps; 301 struct kvm_vcpu *vcpu; 302 303 stack_size = vm->page_size == 4096 ? DEFAULT_STACK_PGS * vm->page_size : 304 vm->page_size; 305 stack_vaddr = __vm_vaddr_alloc(vm, stack_size, 306 DEFAULT_RISCV_GUEST_STACK_VADDR_MIN, 307 MEM_REGION_DATA); 308 309 vcpu = __vm_vcpu_add(vm, vcpu_id); 310 riscv_vcpu_mmu_setup(vcpu); 311 312 /* 313 * With SBI HSM support in KVM RISC-V, all secondary VCPUs are 314 * powered-off by default so we ensure that all secondary VCPUs 315 * are powered-on using KVM_SET_MP_STATE ioctl(). 316 */ 317 mps.mp_state = KVM_MP_STATE_RUNNABLE; 318 r = __vcpu_ioctl(vcpu, KVM_SET_MP_STATE, &mps); 319 TEST_ASSERT(!r, "IOCTL KVM_SET_MP_STATE failed (error %d)", r); 320 321 /* Setup global pointer of guest to be same as the host */ 322 asm volatile ( 323 "add %0, gp, zero" : "=r" (current_gp) : : "memory"); 324 vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.gp), current_gp); 325 326 /* Setup stack pointer and program counter of guest */ 327 vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.sp), stack_vaddr + stack_size); 328 329 /* Setup sscratch for guest_get_vcpuid() */ 330 vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(sscratch), vcpu_id); 331 332 /* Setup default exception vector of guest */ 333 vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(stvec), (unsigned long)guest_unexp_trap); 334 335 return vcpu; 336 } 337 338 void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...) 339 { 340 va_list ap; 341 uint64_t id = RISCV_CORE_REG(regs.a0); 342 int i; 343 344 TEST_ASSERT(num >= 1 && num <= 8, "Unsupported number of args,\n" 345 " num: %u", num); 346 347 va_start(ap, num); 348 349 for (i = 0; i < num; i++) { 350 switch (i) { 351 case 0: 352 id = RISCV_CORE_REG(regs.a0); 353 break; 354 case 1: 355 id = RISCV_CORE_REG(regs.a1); 356 break; 357 case 2: 358 id = RISCV_CORE_REG(regs.a2); 359 break; 360 case 3: 361 id = RISCV_CORE_REG(regs.a3); 362 break; 363 case 4: 364 id = RISCV_CORE_REG(regs.a4); 365 break; 366 case 5: 367 id = RISCV_CORE_REG(regs.a5); 368 break; 369 case 6: 370 id = RISCV_CORE_REG(regs.a6); 371 break; 372 case 7: 373 id = RISCV_CORE_REG(regs.a7); 374 break; 375 } 376 vcpu_set_reg(vcpu, id, va_arg(ap, uint64_t)); 377 } 378 379 va_end(ap); 380 } 381 382 void kvm_exit_unexpected_exception(int vector, int ec) 383 { 384 ucall(UCALL_UNHANDLED, 2, vector, ec); 385 } 386 387 void assert_on_unhandled_exception(struct kvm_vcpu *vcpu) 388 { 389 struct ucall uc; 390 391 if (get_ucall(vcpu, &uc) == UCALL_UNHANDLED) { 392 TEST_FAIL("Unexpected exception (vector:0x%lx, ec:0x%lx)", 393 uc.args[0], uc.args[1]); 394 } 395 } 396 397 struct handlers { 398 exception_handler_fn exception_handlers[NR_VECTORS][NR_EXCEPTIONS]; 399 }; 400 401 void route_exception(struct pt_regs *regs) 402 { 403 struct handlers *handlers = (struct handlers *)exception_handlers; 404 int vector = 0, ec; 405 406 ec = regs->cause & ~CAUSE_IRQ_FLAG; 407 if (ec >= NR_EXCEPTIONS) 408 goto unexpected_exception; 409 410 /* Use the same handler for all the interrupts */ 411 if (regs->cause & CAUSE_IRQ_FLAG) { 412 vector = 1; 413 ec = 0; 414 } 415 416 if (handlers && handlers->exception_handlers[vector][ec]) 417 return handlers->exception_handlers[vector][ec](regs); 418 419 unexpected_exception: 420 return kvm_exit_unexpected_exception(vector, ec); 421 } 422 423 void vcpu_init_vector_tables(struct kvm_vcpu *vcpu) 424 { 425 extern char exception_vectors; 426 427 vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(stvec), (unsigned long)&exception_vectors); 428 } 429 430 void vm_init_vector_tables(struct kvm_vm *vm) 431 { 432 vm->handlers = __vm_vaddr_alloc(vm, sizeof(struct handlers), 433 vm->page_size, MEM_REGION_DATA); 434 435 *(vm_vaddr_t *)addr_gva2hva(vm, (vm_vaddr_t)(&exception_handlers)) = vm->handlers; 436 } 437 438 void vm_install_exception_handler(struct kvm_vm *vm, int vector, exception_handler_fn handler) 439 { 440 struct handlers *handlers = addr_gva2hva(vm, vm->handlers); 441 442 assert(vector < NR_EXCEPTIONS); 443 handlers->exception_handlers[0][vector] = handler; 444 } 445 446 void vm_install_interrupt_handler(struct kvm_vm *vm, exception_handler_fn handler) 447 { 448 struct handlers *handlers = addr_gva2hva(vm, vm->handlers); 449 450 handlers->exception_handlers[1][0] = handler; 451 } 452 453 uint32_t guest_get_vcpuid(void) 454 { 455 return csr_read(CSR_SSCRATCH); 456 } 457 458 struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, 459 unsigned long arg1, unsigned long arg2, 460 unsigned long arg3, unsigned long arg4, 461 unsigned long arg5) 462 { 463 register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); 464 register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); 465 register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); 466 register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3); 467 register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4); 468 register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5); 469 register uintptr_t a6 asm ("a6") = (uintptr_t)(fid); 470 register uintptr_t a7 asm ("a7") = (uintptr_t)(ext); 471 struct sbiret ret; 472 473 asm volatile ( 474 "ecall" 475 : "+r" (a0), "+r" (a1) 476 : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7) 477 : "memory"); 478 ret.error = a0; 479 ret.value = a1; 480 481 return ret; 482 } 483 484 bool guest_sbi_probe_extension(int extid, long *out_val) 485 { 486 struct sbiret ret; 487 488 ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, extid, 489 0, 0, 0, 0, 0); 490 491 __GUEST_ASSERT(!ret.error || ret.error == SBI_ERR_NOT_SUPPORTED, 492 "ret.error=%ld, ret.value=%ld\n", ret.error, ret.value); 493 494 if (ret.error == SBI_ERR_NOT_SUPPORTED) 495 return false; 496 497 if (out_val) 498 *out_val = ret.value; 499 500 return true; 501 } 502 503 unsigned long get_host_sbi_spec_version(void) 504 { 505 struct sbiret ret; 506 507 ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0, 508 0, 0, 0, 0, 0); 509 510 GUEST_ASSERT(!ret.error); 511 512 return ret.value; 513 } 514