1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * RISC-V code 4 * 5 * Copyright (C) 2021 Western Digital Corporation or its affiliates. 6 */ 7 8 #include <linux/compiler.h> 9 #include <assert.h> 10 11 #include "guest_modes.h" 12 #include "kvm_util.h" 13 #include "processor.h" 14 #include "ucall_common.h" 15 16 #define DEFAULT_RISCV_GUEST_STACK_VADDR_MIN 0xac0000 17 18 static vm_vaddr_t exception_handlers; 19 20 bool __vcpu_has_ext(struct kvm_vcpu *vcpu, uint64_t ext) 21 { 22 unsigned long value = 0; 23 int ret; 24 25 ret = __vcpu_get_reg(vcpu, ext, &value); 26 27 return !ret && !!value; 28 } 29 30 static uint64_t pte_addr(struct kvm_vm *vm, uint64_t entry) 31 { 32 return ((entry & PGTBL_PTE_ADDR_MASK) >> PGTBL_PTE_ADDR_SHIFT) << 33 PGTBL_PAGE_SIZE_SHIFT; 34 } 35 36 static uint64_t ptrs_per_pte(struct kvm_vm *vm) 37 { 38 return PGTBL_PAGE_SIZE / sizeof(uint64_t); 39 } 40 41 static uint64_t pte_index_mask[] = { 42 PGTBL_L0_INDEX_MASK, 43 PGTBL_L1_INDEX_MASK, 44 PGTBL_L2_INDEX_MASK, 45 PGTBL_L3_INDEX_MASK, 46 }; 47 48 static uint32_t pte_index_shift[] = { 49 PGTBL_L0_INDEX_SHIFT, 50 PGTBL_L1_INDEX_SHIFT, 51 PGTBL_L2_INDEX_SHIFT, 52 PGTBL_L3_INDEX_SHIFT, 53 }; 54 55 static uint64_t pte_index(struct kvm_vm *vm, vm_vaddr_t gva, int level) 56 { 57 TEST_ASSERT(level > -1, 58 "Negative page table level (%d) not possible", level); 59 TEST_ASSERT(level < vm->mmu.pgtable_levels, 60 "Invalid page table level (%d)", level); 61 62 return (gva & pte_index_mask[level]) >> pte_index_shift[level]; 63 } 64 65 void virt_arch_pgd_alloc(struct kvm_vm *vm) 66 { 67 size_t nr_pages = vm_page_align(vm, ptrs_per_pte(vm) * 8) / vm->page_size; 68 69 if (vm->mmu.pgd_created) 70 return; 71 72 vm->mmu.pgd = vm_phy_pages_alloc(vm, nr_pages, 73 KVM_GUEST_PAGE_TABLE_MIN_PADDR, 74 vm->memslots[MEM_REGION_PT]); 75 vm->mmu.pgd_created = true; 76 } 77 78 void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr) 79 { 80 uint64_t *ptep, next_ppn; 81 int level = vm->mmu.pgtable_levels - 1; 82 83 TEST_ASSERT((vaddr % vm->page_size) == 0, 84 "Virtual address not on page boundary,\n" 85 " vaddr: 0x%lx vm->page_size: 0x%x", vaddr, vm->page_size); 86 TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, 87 (vaddr >> vm->page_shift)), 88 "Invalid virtual address, vaddr: 0x%lx", vaddr); 89 TEST_ASSERT((paddr % vm->page_size) == 0, 90 "Physical address not on page boundary,\n" 91 " paddr: 0x%lx vm->page_size: 0x%x", paddr, vm->page_size); 92 TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn, 93 "Physical address beyond maximum supported,\n" 94 " paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", 95 paddr, vm->max_gfn, vm->page_size); 96 97 ptep = addr_gpa2hva(vm, vm->mmu.pgd) + pte_index(vm, vaddr, level) * 8; 98 if (!*ptep) { 99 next_ppn = vm_alloc_page_table(vm) >> PGTBL_PAGE_SIZE_SHIFT; 100 *ptep = (next_ppn << PGTBL_PTE_ADDR_SHIFT) | 101 PGTBL_PTE_VALID_MASK; 102 } 103 level--; 104 105 while (level > -1) { 106 ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + 107 pte_index(vm, vaddr, level) * 8; 108 if (!*ptep && level > 0) { 109 next_ppn = vm_alloc_page_table(vm) >> 110 PGTBL_PAGE_SIZE_SHIFT; 111 *ptep = (next_ppn << PGTBL_PTE_ADDR_SHIFT) | 112 PGTBL_PTE_VALID_MASK; 113 } 114 level--; 115 } 116 117 paddr = paddr >> PGTBL_PAGE_SIZE_SHIFT; 118 *ptep = (paddr << PGTBL_PTE_ADDR_SHIFT) | 119 PGTBL_PTE_PERM_MASK | PGTBL_PTE_VALID_MASK; 120 } 121 122 vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva) 123 { 124 uint64_t *ptep; 125 int level = vm->mmu.pgtable_levels - 1; 126 127 if (!vm->mmu.pgd_created) 128 goto unmapped_gva; 129 130 ptep = addr_gpa2hva(vm, vm->mmu.pgd) + pte_index(vm, gva, level) * 8; 131 if (!ptep) 132 goto unmapped_gva; 133 level--; 134 135 while (level > -1) { 136 ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + 137 pte_index(vm, gva, level) * 8; 138 if (!ptep) 139 goto unmapped_gva; 140 level--; 141 } 142 143 return pte_addr(vm, *ptep) + (gva & (vm->page_size - 1)); 144 145 unmapped_gva: 146 TEST_FAIL("No mapping for vm virtual address gva: 0x%lx level: %d", 147 gva, level); 148 exit(1); 149 } 150 151 static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent, 152 uint64_t page, int level) 153 { 154 #ifdef DEBUG 155 static const char *const type[] = { "pte", "pmd", "pud", "p4d"}; 156 uint64_t pte, *ptep; 157 158 if (level < 0) 159 return; 160 161 for (pte = page; pte < page + ptrs_per_pte(vm) * 8; pte += 8) { 162 ptep = addr_gpa2hva(vm, pte); 163 if (!*ptep) 164 continue; 165 fprintf(stream, "%*s%s: %lx: %lx at %p\n", indent, "", 166 type[level], pte, *ptep, ptep); 167 pte_dump(stream, vm, indent + 1, 168 pte_addr(vm, *ptep), level - 1); 169 } 170 #endif 171 } 172 173 void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent) 174 { 175 struct kvm_mmu *mmu = &vm->mmu; 176 int level = mmu->pgtable_levels - 1; 177 uint64_t pgd, *ptep; 178 179 if (!mmu->pgd_created) 180 return; 181 182 for (pgd = mmu->pgd; pgd < mmu->pgd + ptrs_per_pte(vm) * 8; pgd += 8) { 183 ptep = addr_gpa2hva(vm, pgd); 184 if (!*ptep) 185 continue; 186 fprintf(stream, "%*spgd: %lx: %lx at %p\n", indent, "", 187 pgd, *ptep, ptep); 188 pte_dump(stream, vm, indent + 1, 189 pte_addr(vm, *ptep), level - 1); 190 } 191 } 192 193 void riscv_vcpu_mmu_setup(struct kvm_vcpu *vcpu) 194 { 195 struct kvm_vm *vm = vcpu->vm; 196 unsigned long satp; 197 unsigned long satp_mode; 198 unsigned long max_satp_mode; 199 200 /* 201 * The RISC-V Sv48 MMU mode supports 56-bit physical address 202 * for 48-bit virtual address with 4KB last level page size. 203 */ 204 switch (vm->mode) { 205 case VM_MODE_P56V57_4K: 206 case VM_MODE_P50V57_4K: 207 case VM_MODE_P41V57_4K: 208 satp_mode = SATP_MODE_57; 209 break; 210 case VM_MODE_P56V48_4K: 211 case VM_MODE_P50V48_4K: 212 case VM_MODE_P41V48_4K: 213 satp_mode = SATP_MODE_48; 214 break; 215 case VM_MODE_P56V39_4K: 216 case VM_MODE_P50V39_4K: 217 case VM_MODE_P41V39_4K: 218 satp_mode = SATP_MODE_39; 219 break; 220 default: 221 TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode); 222 } 223 224 max_satp_mode = vcpu_get_reg(vcpu, RISCV_CONFIG_REG(satp_mode)); 225 226 if ((satp_mode >> SATP_MODE_SHIFT) > max_satp_mode) 227 TEST_FAIL("Unable to set satp mode 0x%lx, max mode 0x%lx\n", 228 satp_mode >> SATP_MODE_SHIFT, max_satp_mode); 229 230 satp = (vm->mmu.pgd >> PGTBL_PAGE_SIZE_SHIFT) & SATP_PPN; 231 satp |= satp_mode; 232 233 vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(satp), satp); 234 } 235 236 void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent) 237 { 238 struct kvm_riscv_core core; 239 240 core.mode = vcpu_get_reg(vcpu, RISCV_CORE_REG(mode)); 241 core.regs.pc = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.pc)); 242 core.regs.ra = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.ra)); 243 core.regs.sp = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.sp)); 244 core.regs.gp = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.gp)); 245 core.regs.tp = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.tp)); 246 core.regs.t0 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t0)); 247 core.regs.t1 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t1)); 248 core.regs.t2 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t2)); 249 core.regs.s0 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s0)); 250 core.regs.s1 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s1)); 251 core.regs.a0 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a0)); 252 core.regs.a1 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a1)); 253 core.regs.a2 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a2)); 254 core.regs.a3 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a3)); 255 core.regs.a4 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a4)); 256 core.regs.a5 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a5)); 257 core.regs.a6 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a6)); 258 core.regs.a7 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a7)); 259 core.regs.s2 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s2)); 260 core.regs.s3 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s3)); 261 core.regs.s4 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s4)); 262 core.regs.s5 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s5)); 263 core.regs.s6 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s6)); 264 core.regs.s7 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s7)); 265 core.regs.s8 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s8)); 266 core.regs.s9 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s9)); 267 core.regs.s10 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s10)); 268 core.regs.s11 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s11)); 269 core.regs.t3 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t3)); 270 core.regs.t4 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t4)); 271 core.regs.t5 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t5)); 272 core.regs.t6 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t6)); 273 274 fprintf(stream, 275 " MODE: 0x%lx\n", core.mode); 276 fprintf(stream, 277 " PC: 0x%016lx RA: 0x%016lx SP: 0x%016lx GP: 0x%016lx\n", 278 core.regs.pc, core.regs.ra, core.regs.sp, core.regs.gp); 279 fprintf(stream, 280 " TP: 0x%016lx T0: 0x%016lx T1: 0x%016lx T2: 0x%016lx\n", 281 core.regs.tp, core.regs.t0, core.regs.t1, core.regs.t2); 282 fprintf(stream, 283 " S0: 0x%016lx S1: 0x%016lx A0: 0x%016lx A1: 0x%016lx\n", 284 core.regs.s0, core.regs.s1, core.regs.a0, core.regs.a1); 285 fprintf(stream, 286 " A2: 0x%016lx A3: 0x%016lx A4: 0x%016lx A5: 0x%016lx\n", 287 core.regs.a2, core.regs.a3, core.regs.a4, core.regs.a5); 288 fprintf(stream, 289 " A6: 0x%016lx A7: 0x%016lx S2: 0x%016lx S3: 0x%016lx\n", 290 core.regs.a6, core.regs.a7, core.regs.s2, core.regs.s3); 291 fprintf(stream, 292 " S4: 0x%016lx S5: 0x%016lx S6: 0x%016lx S7: 0x%016lx\n", 293 core.regs.s4, core.regs.s5, core.regs.s6, core.regs.s7); 294 fprintf(stream, 295 " S8: 0x%016lx S9: 0x%016lx S10: 0x%016lx S11: 0x%016lx\n", 296 core.regs.s8, core.regs.s9, core.regs.s10, core.regs.s11); 297 fprintf(stream, 298 " T3: 0x%016lx T4: 0x%016lx T5: 0x%016lx T6: 0x%016lx\n", 299 core.regs.t3, core.regs.t4, core.regs.t5, core.regs.t6); 300 } 301 302 static void __aligned(16) guest_unexp_trap(void) 303 { 304 sbi_ecall(KVM_RISCV_SELFTESTS_SBI_EXT, 305 KVM_RISCV_SELFTESTS_SBI_UNEXP, 306 0, 0, 0, 0, 0, 0); 307 } 308 309 void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code) 310 { 311 vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.pc), (unsigned long)guest_code); 312 } 313 314 struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id) 315 { 316 int r; 317 size_t stack_size; 318 unsigned long stack_vaddr; 319 unsigned long current_gp = 0; 320 struct kvm_mp_state mps; 321 struct kvm_vcpu *vcpu; 322 323 stack_size = vm->page_size == 4096 ? DEFAULT_STACK_PGS * vm->page_size : 324 vm->page_size; 325 stack_vaddr = __vm_vaddr_alloc(vm, stack_size, 326 DEFAULT_RISCV_GUEST_STACK_VADDR_MIN, 327 MEM_REGION_DATA); 328 329 vcpu = __vm_vcpu_add(vm, vcpu_id); 330 riscv_vcpu_mmu_setup(vcpu); 331 332 /* 333 * With SBI HSM support in KVM RISC-V, all secondary VCPUs are 334 * powered-off by default so we ensure that all secondary VCPUs 335 * are powered-on using KVM_SET_MP_STATE ioctl(). 336 */ 337 mps.mp_state = KVM_MP_STATE_RUNNABLE; 338 r = __vcpu_ioctl(vcpu, KVM_SET_MP_STATE, &mps); 339 TEST_ASSERT(!r, "IOCTL KVM_SET_MP_STATE failed (error %d)", r); 340 341 /* Setup global pointer of guest to be same as the host */ 342 asm volatile ( 343 "add %0, gp, zero" : "=r" (current_gp) : : "memory"); 344 vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.gp), current_gp); 345 346 /* Setup stack pointer and program counter of guest */ 347 vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.sp), stack_vaddr + stack_size); 348 349 /* Setup sscratch for guest_get_vcpuid() */ 350 vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(sscratch), vcpu_id); 351 352 /* Setup default exception vector of guest */ 353 vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(stvec), (unsigned long)guest_unexp_trap); 354 355 return vcpu; 356 } 357 358 void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...) 359 { 360 va_list ap; 361 uint64_t id = RISCV_CORE_REG(regs.a0); 362 int i; 363 364 TEST_ASSERT(num >= 1 && num <= 8, "Unsupported number of args,\n" 365 " num: %u", num); 366 367 va_start(ap, num); 368 369 for (i = 0; i < num; i++) { 370 switch (i) { 371 case 0: 372 id = RISCV_CORE_REG(regs.a0); 373 break; 374 case 1: 375 id = RISCV_CORE_REG(regs.a1); 376 break; 377 case 2: 378 id = RISCV_CORE_REG(regs.a2); 379 break; 380 case 3: 381 id = RISCV_CORE_REG(regs.a3); 382 break; 383 case 4: 384 id = RISCV_CORE_REG(regs.a4); 385 break; 386 case 5: 387 id = RISCV_CORE_REG(regs.a5); 388 break; 389 case 6: 390 id = RISCV_CORE_REG(regs.a6); 391 break; 392 case 7: 393 id = RISCV_CORE_REG(regs.a7); 394 break; 395 } 396 vcpu_set_reg(vcpu, id, va_arg(ap, uint64_t)); 397 } 398 399 va_end(ap); 400 } 401 402 void kvm_exit_unexpected_exception(int vector, int ec) 403 { 404 ucall(UCALL_UNHANDLED, 2, vector, ec); 405 } 406 407 void assert_on_unhandled_exception(struct kvm_vcpu *vcpu) 408 { 409 struct ucall uc; 410 411 if (get_ucall(vcpu, &uc) == UCALL_UNHANDLED) { 412 TEST_FAIL("Unexpected exception (vector:0x%lx, ec:0x%lx)", 413 uc.args[0], uc.args[1]); 414 } 415 } 416 417 struct handlers { 418 exception_handler_fn exception_handlers[NR_VECTORS][NR_EXCEPTIONS]; 419 }; 420 421 void route_exception(struct pt_regs *regs) 422 { 423 struct handlers *handlers = (struct handlers *)exception_handlers; 424 int vector = 0, ec; 425 426 ec = regs->cause & ~CAUSE_IRQ_FLAG; 427 if (ec >= NR_EXCEPTIONS) 428 goto unexpected_exception; 429 430 /* Use the same handler for all the interrupts */ 431 if (regs->cause & CAUSE_IRQ_FLAG) { 432 vector = 1; 433 ec = 0; 434 } 435 436 if (handlers && handlers->exception_handlers[vector][ec]) 437 return handlers->exception_handlers[vector][ec](regs); 438 439 unexpected_exception: 440 return kvm_exit_unexpected_exception(vector, ec); 441 } 442 443 void vcpu_init_vector_tables(struct kvm_vcpu *vcpu) 444 { 445 extern char exception_vectors; 446 447 vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(stvec), (unsigned long)&exception_vectors); 448 } 449 450 void vm_init_vector_tables(struct kvm_vm *vm) 451 { 452 vm->handlers = __vm_vaddr_alloc(vm, sizeof(struct handlers), 453 vm->page_size, MEM_REGION_DATA); 454 455 *(vm_vaddr_t *)addr_gva2hva(vm, (vm_vaddr_t)(&exception_handlers)) = vm->handlers; 456 } 457 458 void vm_install_exception_handler(struct kvm_vm *vm, int vector, exception_handler_fn handler) 459 { 460 struct handlers *handlers = addr_gva2hva(vm, vm->handlers); 461 462 assert(vector < NR_EXCEPTIONS); 463 handlers->exception_handlers[0][vector] = handler; 464 } 465 466 void vm_install_interrupt_handler(struct kvm_vm *vm, exception_handler_fn handler) 467 { 468 struct handlers *handlers = addr_gva2hva(vm, vm->handlers); 469 470 handlers->exception_handlers[1][0] = handler; 471 } 472 473 uint32_t guest_get_vcpuid(void) 474 { 475 return csr_read(CSR_SSCRATCH); 476 } 477 478 struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, 479 unsigned long arg1, unsigned long arg2, 480 unsigned long arg3, unsigned long arg4, 481 unsigned long arg5) 482 { 483 register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); 484 register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); 485 register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); 486 register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3); 487 register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4); 488 register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5); 489 register uintptr_t a6 asm ("a6") = (uintptr_t)(fid); 490 register uintptr_t a7 asm ("a7") = (uintptr_t)(ext); 491 struct sbiret ret; 492 493 asm volatile ( 494 "ecall" 495 : "+r" (a0), "+r" (a1) 496 : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7) 497 : "memory"); 498 ret.error = a0; 499 ret.value = a1; 500 501 return ret; 502 } 503 504 bool guest_sbi_probe_extension(int extid, long *out_val) 505 { 506 struct sbiret ret; 507 508 ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, extid, 509 0, 0, 0, 0, 0); 510 511 __GUEST_ASSERT(!ret.error || ret.error == SBI_ERR_NOT_SUPPORTED, 512 "ret.error=%ld, ret.value=%ld\n", ret.error, ret.value); 513 514 if (ret.error == SBI_ERR_NOT_SUPPORTED) 515 return false; 516 517 if (out_val) 518 *out_val = ret.value; 519 520 return true; 521 } 522 523 unsigned long get_host_sbi_spec_version(void) 524 { 525 struct sbiret ret; 526 527 ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0, 528 0, 0, 0, 0, 0); 529 530 GUEST_ASSERT(!ret.error); 531 532 return ret.value; 533 } 534 535 void kvm_selftest_arch_init(void) 536 { 537 /* 538 * riscv64 doesn't have a true default mode, so start by detecting the 539 * supported vm mode. 540 */ 541 guest_modes_append_default(); 542 } 543 544 unsigned long riscv64_get_satp_mode(void) 545 { 546 int kvm_fd, vm_fd, vcpu_fd, err; 547 uint64_t val; 548 struct kvm_one_reg reg = { 549 .id = RISCV_CONFIG_REG(satp_mode), 550 .addr = (uint64_t)&val, 551 }; 552 553 kvm_fd = open_kvm_dev_path_or_exit(); 554 vm_fd = __kvm_ioctl(kvm_fd, KVM_CREATE_VM, NULL); 555 TEST_ASSERT(vm_fd >= 0, KVM_IOCTL_ERROR(KVM_CREATE_VM, vm_fd)); 556 557 vcpu_fd = ioctl(vm_fd, KVM_CREATE_VCPU, 0); 558 TEST_ASSERT(vcpu_fd >= 0, KVM_IOCTL_ERROR(KVM_CREATE_VCPU, vcpu_fd)); 559 560 err = ioctl(vcpu_fd, KVM_GET_ONE_REG, ®); 561 TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_GET_ONE_REG, vcpu_fd)); 562 563 close(vcpu_fd); 564 close(vm_fd); 565 close(kvm_fd); 566 567 return val; 568 } 569