1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2018, Google LLC. 4 */ 5 6 #ifndef SELFTEST_KVM_PROCESSOR_H 7 #define SELFTEST_KVM_PROCESSOR_H 8 9 #include <assert.h> 10 #include <stdint.h> 11 #include <syscall.h> 12 13 #include <asm/msr-index.h> 14 #include <asm/prctl.h> 15 16 #include <linux/kvm_para.h> 17 #include <linux/stringify.h> 18 19 #include "kvm_util.h" 20 #include "ucall_common.h" 21 22 extern bool host_cpu_is_intel; 23 extern bool host_cpu_is_amd; 24 extern uint64_t guest_tsc_khz; 25 26 #ifndef MAX_NR_CPUID_ENTRIES 27 #define MAX_NR_CPUID_ENTRIES 100 28 #endif 29 30 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 31 32 /* Forced emulation prefix, used to invoke the emulator unconditionally. */ 33 #define KVM_FEP "ud2; .byte 'k', 'v', 'm';" 34 35 #define NMI_VECTOR 0x02 36 37 #define X86_EFLAGS_FIXED (1u << 1) 38 39 #define X86_CR4_VME (1ul << 0) 40 #define X86_CR4_PVI (1ul << 1) 41 #define X86_CR4_TSD (1ul << 2) 42 #define X86_CR4_DE (1ul << 3) 43 #define X86_CR4_PSE (1ul << 4) 44 #define X86_CR4_PAE (1ul << 5) 45 #define X86_CR4_MCE (1ul << 6) 46 #define X86_CR4_PGE (1ul << 7) 47 #define X86_CR4_PCE (1ul << 8) 48 #define X86_CR4_OSFXSR (1ul << 9) 49 #define X86_CR4_OSXMMEXCPT (1ul << 10) 50 #define X86_CR4_UMIP (1ul << 11) 51 #define X86_CR4_LA57 (1ul << 12) 52 #define X86_CR4_VMXE (1ul << 13) 53 #define X86_CR4_SMXE (1ul << 14) 54 #define X86_CR4_FSGSBASE (1ul << 16) 55 #define X86_CR4_PCIDE (1ul << 17) 56 #define X86_CR4_OSXSAVE (1ul << 18) 57 #define X86_CR4_SMEP (1ul << 20) 58 #define X86_CR4_SMAP (1ul << 21) 59 #define X86_CR4_PKE (1ul << 22) 60 61 struct xstate_header { 62 u64 xstate_bv; 63 u64 xcomp_bv; 64 u64 reserved[6]; 65 } __attribute__((packed)); 66 67 struct xstate { 68 u8 i387[512]; 69 struct xstate_header header; 70 u8 extended_state_area[0]; 71 } __attribute__ ((packed, aligned (64))); 72 73 #define XFEATURE_MASK_FP BIT_ULL(0) 74 #define XFEATURE_MASK_SSE BIT_ULL(1) 75 #define XFEATURE_MASK_YMM BIT_ULL(2) 76 #define XFEATURE_MASK_BNDREGS BIT_ULL(3) 77 #define XFEATURE_MASK_BNDCSR BIT_ULL(4) 78 #define XFEATURE_MASK_OPMASK BIT_ULL(5) 79 #define XFEATURE_MASK_ZMM_Hi256 BIT_ULL(6) 80 #define XFEATURE_MASK_Hi16_ZMM BIT_ULL(7) 81 #define XFEATURE_MASK_PT BIT_ULL(8) 82 #define XFEATURE_MASK_PKRU BIT_ULL(9) 83 #define XFEATURE_MASK_PASID BIT_ULL(10) 84 #define XFEATURE_MASK_CET_USER BIT_ULL(11) 85 #define XFEATURE_MASK_CET_KERNEL BIT_ULL(12) 86 #define XFEATURE_MASK_LBR BIT_ULL(15) 87 #define XFEATURE_MASK_XTILE_CFG BIT_ULL(17) 88 #define XFEATURE_MASK_XTILE_DATA BIT_ULL(18) 89 90 #define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK | \ 91 XFEATURE_MASK_ZMM_Hi256 | \ 92 XFEATURE_MASK_Hi16_ZMM) 93 #define XFEATURE_MASK_XTILE (XFEATURE_MASK_XTILE_DATA | \ 94 XFEATURE_MASK_XTILE_CFG) 95 96 /* Note, these are ordered alphabetically to match kvm_cpuid_entry2. Eww. */ 97 enum cpuid_output_regs { 98 KVM_CPUID_EAX, 99 KVM_CPUID_EBX, 100 KVM_CPUID_ECX, 101 KVM_CPUID_EDX 102 }; 103 104 /* 105 * Pack the information into a 64-bit value so that each X86_FEATURE_XXX can be 106 * passed by value with no overhead. 107 */ 108 struct kvm_x86_cpu_feature { 109 u32 function; 110 u16 index; 111 u8 reg; 112 u8 bit; 113 }; 114 #define KVM_X86_CPU_FEATURE(fn, idx, gpr, __bit) \ 115 ({ \ 116 struct kvm_x86_cpu_feature feature = { \ 117 .function = fn, \ 118 .index = idx, \ 119 .reg = KVM_CPUID_##gpr, \ 120 .bit = __bit, \ 121 }; \ 122 \ 123 kvm_static_assert((fn & 0xc0000000) == 0 || \ 124 (fn & 0xc0000000) == 0x40000000 || \ 125 (fn & 0xc0000000) == 0x80000000 || \ 126 (fn & 0xc0000000) == 0xc0000000); \ 127 kvm_static_assert(idx < BIT(sizeof(feature.index) * BITS_PER_BYTE)); \ 128 feature; \ 129 }) 130 131 /* 132 * Basic Leafs, a.k.a. Intel defined 133 */ 134 #define X86_FEATURE_MWAIT KVM_X86_CPU_FEATURE(0x1, 0, ECX, 3) 135 #define X86_FEATURE_VMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 5) 136 #define X86_FEATURE_SMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 6) 137 #define X86_FEATURE_PDCM KVM_X86_CPU_FEATURE(0x1, 0, ECX, 15) 138 #define X86_FEATURE_PCID KVM_X86_CPU_FEATURE(0x1, 0, ECX, 17) 139 #define X86_FEATURE_X2APIC KVM_X86_CPU_FEATURE(0x1, 0, ECX, 21) 140 #define X86_FEATURE_MOVBE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 22) 141 #define X86_FEATURE_TSC_DEADLINE_TIMER KVM_X86_CPU_FEATURE(0x1, 0, ECX, 24) 142 #define X86_FEATURE_XSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 26) 143 #define X86_FEATURE_OSXSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 27) 144 #define X86_FEATURE_RDRAND KVM_X86_CPU_FEATURE(0x1, 0, ECX, 30) 145 #define X86_FEATURE_HYPERVISOR KVM_X86_CPU_FEATURE(0x1, 0, ECX, 31) 146 #define X86_FEATURE_PAE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 6) 147 #define X86_FEATURE_MCE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 7) 148 #define X86_FEATURE_APIC KVM_X86_CPU_FEATURE(0x1, 0, EDX, 9) 149 #define X86_FEATURE_CLFLUSH KVM_X86_CPU_FEATURE(0x1, 0, EDX, 19) 150 #define X86_FEATURE_XMM KVM_X86_CPU_FEATURE(0x1, 0, EDX, 25) 151 #define X86_FEATURE_XMM2 KVM_X86_CPU_FEATURE(0x1, 0, EDX, 26) 152 #define X86_FEATURE_FSGSBASE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 0) 153 #define X86_FEATURE_TSC_ADJUST KVM_X86_CPU_FEATURE(0x7, 0, EBX, 1) 154 #define X86_FEATURE_SGX KVM_X86_CPU_FEATURE(0x7, 0, EBX, 2) 155 #define X86_FEATURE_HLE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 4) 156 #define X86_FEATURE_SMEP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 7) 157 #define X86_FEATURE_INVPCID KVM_X86_CPU_FEATURE(0x7, 0, EBX, 10) 158 #define X86_FEATURE_RTM KVM_X86_CPU_FEATURE(0x7, 0, EBX, 11) 159 #define X86_FEATURE_MPX KVM_X86_CPU_FEATURE(0x7, 0, EBX, 14) 160 #define X86_FEATURE_SMAP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 20) 161 #define X86_FEATURE_PCOMMIT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 22) 162 #define X86_FEATURE_CLFLUSHOPT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 23) 163 #define X86_FEATURE_CLWB KVM_X86_CPU_FEATURE(0x7, 0, EBX, 24) 164 #define X86_FEATURE_UMIP KVM_X86_CPU_FEATURE(0x7, 0, ECX, 2) 165 #define X86_FEATURE_PKU KVM_X86_CPU_FEATURE(0x7, 0, ECX, 3) 166 #define X86_FEATURE_OSPKE KVM_X86_CPU_FEATURE(0x7, 0, ECX, 4) 167 #define X86_FEATURE_LA57 KVM_X86_CPU_FEATURE(0x7, 0, ECX, 16) 168 #define X86_FEATURE_RDPID KVM_X86_CPU_FEATURE(0x7, 0, ECX, 22) 169 #define X86_FEATURE_SGX_LC KVM_X86_CPU_FEATURE(0x7, 0, ECX, 30) 170 #define X86_FEATURE_SHSTK KVM_X86_CPU_FEATURE(0x7, 0, ECX, 7) 171 #define X86_FEATURE_IBT KVM_X86_CPU_FEATURE(0x7, 0, EDX, 20) 172 #define X86_FEATURE_AMX_TILE KVM_X86_CPU_FEATURE(0x7, 0, EDX, 24) 173 #define X86_FEATURE_SPEC_CTRL KVM_X86_CPU_FEATURE(0x7, 0, EDX, 26) 174 #define X86_FEATURE_ARCH_CAPABILITIES KVM_X86_CPU_FEATURE(0x7, 0, EDX, 29) 175 #define X86_FEATURE_PKS KVM_X86_CPU_FEATURE(0x7, 0, ECX, 31) 176 #define X86_FEATURE_XTILECFG KVM_X86_CPU_FEATURE(0xD, 0, EAX, 17) 177 #define X86_FEATURE_XTILEDATA KVM_X86_CPU_FEATURE(0xD, 0, EAX, 18) 178 #define X86_FEATURE_XSAVES KVM_X86_CPU_FEATURE(0xD, 1, EAX, 3) 179 #define X86_FEATURE_XFD KVM_X86_CPU_FEATURE(0xD, 1, EAX, 4) 180 #define X86_FEATURE_XTILEDATA_XFD KVM_X86_CPU_FEATURE(0xD, 18, ECX, 2) 181 182 /* 183 * Extended Leafs, a.k.a. AMD defined 184 */ 185 #define X86_FEATURE_SVM KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 2) 186 #define X86_FEATURE_NX KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 20) 187 #define X86_FEATURE_GBPAGES KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 26) 188 #define X86_FEATURE_RDTSCP KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 27) 189 #define X86_FEATURE_LM KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 29) 190 #define X86_FEATURE_INVTSC KVM_X86_CPU_FEATURE(0x80000007, 0, EDX, 8) 191 #define X86_FEATURE_RDPRU KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 4) 192 #define X86_FEATURE_AMD_IBPB KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 12) 193 #define X86_FEATURE_NPT KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 0) 194 #define X86_FEATURE_LBRV KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 1) 195 #define X86_FEATURE_NRIPS KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 3) 196 #define X86_FEATURE_TSCRATEMSR KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 4) 197 #define X86_FEATURE_PAUSEFILTER KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 10) 198 #define X86_FEATURE_PFTHRESHOLD KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 12) 199 #define X86_FEATURE_VGIF KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 16) 200 #define X86_FEATURE_SEV KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 1) 201 #define X86_FEATURE_SEV_ES KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 3) 202 203 /* 204 * KVM defined paravirt features. 205 */ 206 #define X86_FEATURE_KVM_CLOCKSOURCE KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 0) 207 #define X86_FEATURE_KVM_NOP_IO_DELAY KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 1) 208 #define X86_FEATURE_KVM_MMU_OP KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 2) 209 #define X86_FEATURE_KVM_CLOCKSOURCE2 KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 3) 210 #define X86_FEATURE_KVM_ASYNC_PF KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 4) 211 #define X86_FEATURE_KVM_STEAL_TIME KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 5) 212 #define X86_FEATURE_KVM_PV_EOI KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 6) 213 #define X86_FEATURE_KVM_PV_UNHALT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 7) 214 /* Bit 8 apparently isn't used?!?! */ 215 #define X86_FEATURE_KVM_PV_TLB_FLUSH KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 9) 216 #define X86_FEATURE_KVM_ASYNC_PF_VMEXIT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 10) 217 #define X86_FEATURE_KVM_PV_SEND_IPI KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 11) 218 #define X86_FEATURE_KVM_POLL_CONTROL KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 12) 219 #define X86_FEATURE_KVM_PV_SCHED_YIELD KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 13) 220 #define X86_FEATURE_KVM_ASYNC_PF_INT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 14) 221 #define X86_FEATURE_KVM_MSI_EXT_DEST_ID KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 15) 222 #define X86_FEATURE_KVM_HC_MAP_GPA_RANGE KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 16) 223 #define X86_FEATURE_KVM_MIGRATION_CONTROL KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 17) 224 225 /* 226 * Same idea as X86_FEATURE_XXX, but X86_PROPERTY_XXX retrieves a multi-bit 227 * value/property as opposed to a single-bit feature. Again, pack the info 228 * into a 64-bit value to pass by value with no overhead. 229 */ 230 struct kvm_x86_cpu_property { 231 u32 function; 232 u8 index; 233 u8 reg; 234 u8 lo_bit; 235 u8 hi_bit; 236 }; 237 #define KVM_X86_CPU_PROPERTY(fn, idx, gpr, low_bit, high_bit) \ 238 ({ \ 239 struct kvm_x86_cpu_property property = { \ 240 .function = fn, \ 241 .index = idx, \ 242 .reg = KVM_CPUID_##gpr, \ 243 .lo_bit = low_bit, \ 244 .hi_bit = high_bit, \ 245 }; \ 246 \ 247 kvm_static_assert(low_bit < high_bit); \ 248 kvm_static_assert((fn & 0xc0000000) == 0 || \ 249 (fn & 0xc0000000) == 0x40000000 || \ 250 (fn & 0xc0000000) == 0x80000000 || \ 251 (fn & 0xc0000000) == 0xc0000000); \ 252 kvm_static_assert(idx < BIT(sizeof(property.index) * BITS_PER_BYTE)); \ 253 property; \ 254 }) 255 256 #define X86_PROPERTY_MAX_BASIC_LEAF KVM_X86_CPU_PROPERTY(0, 0, EAX, 0, 31) 257 #define X86_PROPERTY_PMU_VERSION KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 0, 7) 258 #define X86_PROPERTY_PMU_NR_GP_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 8, 15) 259 #define X86_PROPERTY_PMU_GP_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 16, 23) 260 #define X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 24, 31) 261 #define X86_PROPERTY_PMU_EVENTS_MASK KVM_X86_CPU_PROPERTY(0xa, 0, EBX, 0, 7) 262 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK KVM_X86_CPU_PROPERTY(0xa, 0, ECX, 0, 31) 263 #define X86_PROPERTY_PMU_NR_FIXED_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EDX, 0, 4) 264 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0, EDX, 5, 12) 265 266 #define X86_PROPERTY_SUPPORTED_XCR0_LO KVM_X86_CPU_PROPERTY(0xd, 0, EAX, 0, 31) 267 #define X86_PROPERTY_XSTATE_MAX_SIZE_XCR0 KVM_X86_CPU_PROPERTY(0xd, 0, EBX, 0, 31) 268 #define X86_PROPERTY_XSTATE_MAX_SIZE KVM_X86_CPU_PROPERTY(0xd, 0, ECX, 0, 31) 269 #define X86_PROPERTY_SUPPORTED_XCR0_HI KVM_X86_CPU_PROPERTY(0xd, 0, EDX, 0, 31) 270 271 #define X86_PROPERTY_XSTATE_TILE_SIZE KVM_X86_CPU_PROPERTY(0xd, 18, EAX, 0, 31) 272 #define X86_PROPERTY_XSTATE_TILE_OFFSET KVM_X86_CPU_PROPERTY(0xd, 18, EBX, 0, 31) 273 #define X86_PROPERTY_AMX_MAX_PALETTE_TABLES KVM_X86_CPU_PROPERTY(0x1d, 0, EAX, 0, 31) 274 #define X86_PROPERTY_AMX_TOTAL_TILE_BYTES KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 0, 15) 275 #define X86_PROPERTY_AMX_BYTES_PER_TILE KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 16, 31) 276 #define X86_PROPERTY_AMX_BYTES_PER_ROW KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 0, 15) 277 #define X86_PROPERTY_AMX_NR_TILE_REGS KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 16, 31) 278 #define X86_PROPERTY_AMX_MAX_ROWS KVM_X86_CPU_PROPERTY(0x1d, 1, ECX, 0, 15) 279 280 #define X86_PROPERTY_MAX_KVM_LEAF KVM_X86_CPU_PROPERTY(0x40000000, 0, EAX, 0, 31) 281 282 #define X86_PROPERTY_MAX_EXT_LEAF KVM_X86_CPU_PROPERTY(0x80000000, 0, EAX, 0, 31) 283 #define X86_PROPERTY_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 0, 7) 284 #define X86_PROPERTY_MAX_VIRT_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 8, 15) 285 #define X86_PROPERTY_GUEST_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 16, 23) 286 #define X86_PROPERTY_SEV_C_BIT KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 0, 5) 287 #define X86_PROPERTY_PHYS_ADDR_REDUCTION KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 6, 11) 288 289 #define X86_PROPERTY_MAX_CENTAUR_LEAF KVM_X86_CPU_PROPERTY(0xC0000000, 0, EAX, 0, 31) 290 291 /* 292 * Intel's architectural PMU events are bizarre. They have a "feature" bit 293 * that indicates the feature is _not_ supported, and a property that states 294 * the length of the bit mask of unsupported features. A feature is supported 295 * if the size of the bit mask is larger than the "unavailable" bit, and said 296 * bit is not set. Fixed counters also bizarre enumeration, but inverted from 297 * arch events for general purpose counters. Fixed counters are supported if a 298 * feature flag is set **OR** the total number of fixed counters is greater 299 * than index of the counter. 300 * 301 * Wrap the events for general purpose and fixed counters to simplify checking 302 * whether or not a given architectural event is supported. 303 */ 304 struct kvm_x86_pmu_feature { 305 struct kvm_x86_cpu_feature f; 306 }; 307 #define KVM_X86_PMU_FEATURE(__reg, __bit) \ 308 ({ \ 309 struct kvm_x86_pmu_feature feature = { \ 310 .f = KVM_X86_CPU_FEATURE(0xa, 0, __reg, __bit), \ 311 }; \ 312 \ 313 kvm_static_assert(KVM_CPUID_##__reg == KVM_CPUID_EBX || \ 314 KVM_CPUID_##__reg == KVM_CPUID_ECX); \ 315 feature; \ 316 }) 317 318 #define X86_PMU_FEATURE_CPU_CYCLES KVM_X86_PMU_FEATURE(EBX, 0) 319 #define X86_PMU_FEATURE_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 1) 320 #define X86_PMU_FEATURE_REFERENCE_CYCLES KVM_X86_PMU_FEATURE(EBX, 2) 321 #define X86_PMU_FEATURE_LLC_REFERENCES KVM_X86_PMU_FEATURE(EBX, 3) 322 #define X86_PMU_FEATURE_LLC_MISSES KVM_X86_PMU_FEATURE(EBX, 4) 323 #define X86_PMU_FEATURE_BRANCH_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 5) 324 #define X86_PMU_FEATURE_BRANCHES_MISPREDICTED KVM_X86_PMU_FEATURE(EBX, 6) 325 #define X86_PMU_FEATURE_TOPDOWN_SLOTS KVM_X86_PMU_FEATURE(EBX, 7) 326 327 #define X86_PMU_FEATURE_INSNS_RETIRED_FIXED KVM_X86_PMU_FEATURE(ECX, 0) 328 #define X86_PMU_FEATURE_CPU_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX, 1) 329 #define X86_PMU_FEATURE_REFERENCE_TSC_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX, 2) 330 #define X86_PMU_FEATURE_TOPDOWN_SLOTS_FIXED KVM_X86_PMU_FEATURE(ECX, 3) 331 332 static inline unsigned int x86_family(unsigned int eax) 333 { 334 unsigned int x86; 335 336 x86 = (eax >> 8) & 0xf; 337 338 if (x86 == 0xf) 339 x86 += (eax >> 20) & 0xff; 340 341 return x86; 342 } 343 344 static inline unsigned int x86_model(unsigned int eax) 345 { 346 return ((eax >> 12) & 0xf0) | ((eax >> 4) & 0x0f); 347 } 348 349 /* Page table bitfield declarations */ 350 #define PTE_PRESENT_MASK BIT_ULL(0) 351 #define PTE_WRITABLE_MASK BIT_ULL(1) 352 #define PTE_USER_MASK BIT_ULL(2) 353 #define PTE_ACCESSED_MASK BIT_ULL(5) 354 #define PTE_DIRTY_MASK BIT_ULL(6) 355 #define PTE_LARGE_MASK BIT_ULL(7) 356 #define PTE_GLOBAL_MASK BIT_ULL(8) 357 #define PTE_NX_MASK BIT_ULL(63) 358 359 #define PHYSICAL_PAGE_MASK GENMASK_ULL(51, 12) 360 361 #define PAGE_SHIFT 12 362 #define PAGE_SIZE (1ULL << PAGE_SHIFT) 363 #define PAGE_MASK (~(PAGE_SIZE-1) & PHYSICAL_PAGE_MASK) 364 365 #define HUGEPAGE_SHIFT(x) (PAGE_SHIFT + (((x) - 1) * 9)) 366 #define HUGEPAGE_SIZE(x) (1UL << HUGEPAGE_SHIFT(x)) 367 #define HUGEPAGE_MASK(x) (~(HUGEPAGE_SIZE(x) - 1) & PHYSICAL_PAGE_MASK) 368 369 #define PTE_GET_PA(pte) ((pte) & PHYSICAL_PAGE_MASK) 370 #define PTE_GET_PFN(pte) (PTE_GET_PA(pte) >> PAGE_SHIFT) 371 372 /* General Registers in 64-Bit Mode */ 373 struct gpr64_regs { 374 u64 rax; 375 u64 rcx; 376 u64 rdx; 377 u64 rbx; 378 u64 rsp; 379 u64 rbp; 380 u64 rsi; 381 u64 rdi; 382 u64 r8; 383 u64 r9; 384 u64 r10; 385 u64 r11; 386 u64 r12; 387 u64 r13; 388 u64 r14; 389 u64 r15; 390 }; 391 392 struct desc64 { 393 uint16_t limit0; 394 uint16_t base0; 395 unsigned base1:8, type:4, s:1, dpl:2, p:1; 396 unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8; 397 uint32_t base3; 398 uint32_t zero1; 399 } __attribute__((packed)); 400 401 struct desc_ptr { 402 uint16_t size; 403 uint64_t address; 404 } __attribute__((packed)); 405 406 struct kvm_x86_state { 407 struct kvm_xsave *xsave; 408 struct kvm_vcpu_events events; 409 struct kvm_mp_state mp_state; 410 struct kvm_regs regs; 411 struct kvm_xcrs xcrs; 412 struct kvm_sregs sregs; 413 struct kvm_debugregs debugregs; 414 union { 415 struct kvm_nested_state nested; 416 char nested_[16384]; 417 }; 418 struct kvm_msrs msrs; 419 }; 420 421 static inline uint64_t get_desc64_base(const struct desc64 *desc) 422 { 423 return ((uint64_t)desc->base3 << 32) | 424 (desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24)); 425 } 426 427 static inline uint64_t rdtsc(void) 428 { 429 uint32_t eax, edx; 430 uint64_t tsc_val; 431 /* 432 * The lfence is to wait (on Intel CPUs) until all previous 433 * instructions have been executed. If software requires RDTSC to be 434 * executed prior to execution of any subsequent instruction, it can 435 * execute LFENCE immediately after RDTSC 436 */ 437 __asm__ __volatile__("lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx)); 438 tsc_val = ((uint64_t)edx) << 32 | eax; 439 return tsc_val; 440 } 441 442 static inline uint64_t rdtscp(uint32_t *aux) 443 { 444 uint32_t eax, edx; 445 446 __asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux)); 447 return ((uint64_t)edx) << 32 | eax; 448 } 449 450 static inline uint64_t rdmsr(uint32_t msr) 451 { 452 uint32_t a, d; 453 454 __asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory"); 455 456 return a | ((uint64_t) d << 32); 457 } 458 459 static inline void wrmsr(uint32_t msr, uint64_t value) 460 { 461 uint32_t a = value; 462 uint32_t d = value >> 32; 463 464 __asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory"); 465 } 466 467 468 static inline uint16_t inw(uint16_t port) 469 { 470 uint16_t tmp; 471 472 __asm__ __volatile__("in %%dx, %%ax" 473 : /* output */ "=a" (tmp) 474 : /* input */ "d" (port)); 475 476 return tmp; 477 } 478 479 static inline uint16_t get_es(void) 480 { 481 uint16_t es; 482 483 __asm__ __volatile__("mov %%es, %[es]" 484 : /* output */ [es]"=rm"(es)); 485 return es; 486 } 487 488 static inline uint16_t get_cs(void) 489 { 490 uint16_t cs; 491 492 __asm__ __volatile__("mov %%cs, %[cs]" 493 : /* output */ [cs]"=rm"(cs)); 494 return cs; 495 } 496 497 static inline uint16_t get_ss(void) 498 { 499 uint16_t ss; 500 501 __asm__ __volatile__("mov %%ss, %[ss]" 502 : /* output */ [ss]"=rm"(ss)); 503 return ss; 504 } 505 506 static inline uint16_t get_ds(void) 507 { 508 uint16_t ds; 509 510 __asm__ __volatile__("mov %%ds, %[ds]" 511 : /* output */ [ds]"=rm"(ds)); 512 return ds; 513 } 514 515 static inline uint16_t get_fs(void) 516 { 517 uint16_t fs; 518 519 __asm__ __volatile__("mov %%fs, %[fs]" 520 : /* output */ [fs]"=rm"(fs)); 521 return fs; 522 } 523 524 static inline uint16_t get_gs(void) 525 { 526 uint16_t gs; 527 528 __asm__ __volatile__("mov %%gs, %[gs]" 529 : /* output */ [gs]"=rm"(gs)); 530 return gs; 531 } 532 533 static inline uint16_t get_tr(void) 534 { 535 uint16_t tr; 536 537 __asm__ __volatile__("str %[tr]" 538 : /* output */ [tr]"=rm"(tr)); 539 return tr; 540 } 541 542 static inline uint64_t get_cr0(void) 543 { 544 uint64_t cr0; 545 546 __asm__ __volatile__("mov %%cr0, %[cr0]" 547 : /* output */ [cr0]"=r"(cr0)); 548 return cr0; 549 } 550 551 static inline uint64_t get_cr3(void) 552 { 553 uint64_t cr3; 554 555 __asm__ __volatile__("mov %%cr3, %[cr3]" 556 : /* output */ [cr3]"=r"(cr3)); 557 return cr3; 558 } 559 560 static inline uint64_t get_cr4(void) 561 { 562 uint64_t cr4; 563 564 __asm__ __volatile__("mov %%cr4, %[cr4]" 565 : /* output */ [cr4]"=r"(cr4)); 566 return cr4; 567 } 568 569 static inline void set_cr4(uint64_t val) 570 { 571 __asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory"); 572 } 573 574 static inline void set_idt(const struct desc_ptr *idt_desc) 575 { 576 __asm__ __volatile__("lidt %0"::"m"(*idt_desc)); 577 } 578 579 static inline u64 xgetbv(u32 index) 580 { 581 u32 eax, edx; 582 583 __asm__ __volatile__("xgetbv;" 584 : "=a" (eax), "=d" (edx) 585 : "c" (index)); 586 return eax | ((u64)edx << 32); 587 } 588 589 static inline void xsetbv(u32 index, u64 value) 590 { 591 u32 eax = value; 592 u32 edx = value >> 32; 593 594 __asm__ __volatile__("xsetbv" :: "a" (eax), "d" (edx), "c" (index)); 595 } 596 597 static inline void wrpkru(u32 pkru) 598 { 599 /* Note, ECX and EDX are architecturally required to be '0'. */ 600 asm volatile(".byte 0x0f,0x01,0xef\n\t" 601 : : "a" (pkru), "c"(0), "d"(0)); 602 } 603 604 static inline struct desc_ptr get_gdt(void) 605 { 606 struct desc_ptr gdt; 607 __asm__ __volatile__("sgdt %[gdt]" 608 : /* output */ [gdt]"=m"(gdt)); 609 return gdt; 610 } 611 612 static inline struct desc_ptr get_idt(void) 613 { 614 struct desc_ptr idt; 615 __asm__ __volatile__("sidt %[idt]" 616 : /* output */ [idt]"=m"(idt)); 617 return idt; 618 } 619 620 static inline void outl(uint16_t port, uint32_t value) 621 { 622 __asm__ __volatile__("outl %%eax, %%dx" : : "d"(port), "a"(value)); 623 } 624 625 static inline void __cpuid(uint32_t function, uint32_t index, 626 uint32_t *eax, uint32_t *ebx, 627 uint32_t *ecx, uint32_t *edx) 628 { 629 *eax = function; 630 *ecx = index; 631 632 asm volatile("cpuid" 633 : "=a" (*eax), 634 "=b" (*ebx), 635 "=c" (*ecx), 636 "=d" (*edx) 637 : "0" (*eax), "2" (*ecx) 638 : "memory"); 639 } 640 641 static inline void cpuid(uint32_t function, 642 uint32_t *eax, uint32_t *ebx, 643 uint32_t *ecx, uint32_t *edx) 644 { 645 return __cpuid(function, 0, eax, ebx, ecx, edx); 646 } 647 648 static inline uint32_t this_cpu_fms(void) 649 { 650 uint32_t eax, ebx, ecx, edx; 651 652 cpuid(1, &eax, &ebx, &ecx, &edx); 653 return eax; 654 } 655 656 static inline uint32_t this_cpu_family(void) 657 { 658 return x86_family(this_cpu_fms()); 659 } 660 661 static inline uint32_t this_cpu_model(void) 662 { 663 return x86_model(this_cpu_fms()); 664 } 665 666 static inline bool this_cpu_vendor_string_is(const char *vendor) 667 { 668 const uint32_t *chunk = (const uint32_t *)vendor; 669 uint32_t eax, ebx, ecx, edx; 670 671 cpuid(0, &eax, &ebx, &ecx, &edx); 672 return (ebx == chunk[0] && edx == chunk[1] && ecx == chunk[2]); 673 } 674 675 static inline bool this_cpu_is_intel(void) 676 { 677 return this_cpu_vendor_string_is("GenuineIntel"); 678 } 679 680 /* 681 * Exclude early K5 samples with a vendor string of "AMDisbetter!" 682 */ 683 static inline bool this_cpu_is_amd(void) 684 { 685 return this_cpu_vendor_string_is("AuthenticAMD"); 686 } 687 688 static inline uint32_t __this_cpu_has(uint32_t function, uint32_t index, 689 uint8_t reg, uint8_t lo, uint8_t hi) 690 { 691 uint32_t gprs[4]; 692 693 __cpuid(function, index, 694 &gprs[KVM_CPUID_EAX], &gprs[KVM_CPUID_EBX], 695 &gprs[KVM_CPUID_ECX], &gprs[KVM_CPUID_EDX]); 696 697 return (gprs[reg] & GENMASK(hi, lo)) >> lo; 698 } 699 700 static inline bool this_cpu_has(struct kvm_x86_cpu_feature feature) 701 { 702 return __this_cpu_has(feature.function, feature.index, 703 feature.reg, feature.bit, feature.bit); 704 } 705 706 static inline uint32_t this_cpu_property(struct kvm_x86_cpu_property property) 707 { 708 return __this_cpu_has(property.function, property.index, 709 property.reg, property.lo_bit, property.hi_bit); 710 } 711 712 static __always_inline bool this_cpu_has_p(struct kvm_x86_cpu_property property) 713 { 714 uint32_t max_leaf; 715 716 switch (property.function & 0xc0000000) { 717 case 0: 718 max_leaf = this_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF); 719 break; 720 case 0x40000000: 721 max_leaf = this_cpu_property(X86_PROPERTY_MAX_KVM_LEAF); 722 break; 723 case 0x80000000: 724 max_leaf = this_cpu_property(X86_PROPERTY_MAX_EXT_LEAF); 725 break; 726 case 0xc0000000: 727 max_leaf = this_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF); 728 } 729 return max_leaf >= property.function; 730 } 731 732 static inline bool this_pmu_has(struct kvm_x86_pmu_feature feature) 733 { 734 uint32_t nr_bits; 735 736 if (feature.f.reg == KVM_CPUID_EBX) { 737 nr_bits = this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); 738 return nr_bits > feature.f.bit && !this_cpu_has(feature.f); 739 } 740 741 GUEST_ASSERT(feature.f.reg == KVM_CPUID_ECX); 742 nr_bits = this_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); 743 return nr_bits > feature.f.bit || this_cpu_has(feature.f); 744 } 745 746 static __always_inline uint64_t this_cpu_supported_xcr0(void) 747 { 748 if (!this_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) 749 return 0; 750 751 return this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | 752 ((uint64_t)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); 753 } 754 755 typedef u32 __attribute__((vector_size(16))) sse128_t; 756 #define __sse128_u union { sse128_t vec; u64 as_u64[2]; u32 as_u32[4]; } 757 #define sse128_lo(x) ({ __sse128_u t; t.vec = x; t.as_u64[0]; }) 758 #define sse128_hi(x) ({ __sse128_u t; t.vec = x; t.as_u64[1]; }) 759 760 static inline void read_sse_reg(int reg, sse128_t *data) 761 { 762 switch (reg) { 763 case 0: 764 asm("movdqa %%xmm0, %0" : "=m"(*data)); 765 break; 766 case 1: 767 asm("movdqa %%xmm1, %0" : "=m"(*data)); 768 break; 769 case 2: 770 asm("movdqa %%xmm2, %0" : "=m"(*data)); 771 break; 772 case 3: 773 asm("movdqa %%xmm3, %0" : "=m"(*data)); 774 break; 775 case 4: 776 asm("movdqa %%xmm4, %0" : "=m"(*data)); 777 break; 778 case 5: 779 asm("movdqa %%xmm5, %0" : "=m"(*data)); 780 break; 781 case 6: 782 asm("movdqa %%xmm6, %0" : "=m"(*data)); 783 break; 784 case 7: 785 asm("movdqa %%xmm7, %0" : "=m"(*data)); 786 break; 787 default: 788 BUG(); 789 } 790 } 791 792 static inline void write_sse_reg(int reg, const sse128_t *data) 793 { 794 switch (reg) { 795 case 0: 796 asm("movdqa %0, %%xmm0" : : "m"(*data)); 797 break; 798 case 1: 799 asm("movdqa %0, %%xmm1" : : "m"(*data)); 800 break; 801 case 2: 802 asm("movdqa %0, %%xmm2" : : "m"(*data)); 803 break; 804 case 3: 805 asm("movdqa %0, %%xmm3" : : "m"(*data)); 806 break; 807 case 4: 808 asm("movdqa %0, %%xmm4" : : "m"(*data)); 809 break; 810 case 5: 811 asm("movdqa %0, %%xmm5" : : "m"(*data)); 812 break; 813 case 6: 814 asm("movdqa %0, %%xmm6" : : "m"(*data)); 815 break; 816 case 7: 817 asm("movdqa %0, %%xmm7" : : "m"(*data)); 818 break; 819 default: 820 BUG(); 821 } 822 } 823 824 static inline void cpu_relax(void) 825 { 826 asm volatile("rep; nop" ::: "memory"); 827 } 828 829 static inline void udelay(unsigned long usec) 830 { 831 uint64_t start, now, cycles; 832 833 GUEST_ASSERT(guest_tsc_khz); 834 cycles = guest_tsc_khz / 1000 * usec; 835 836 /* 837 * Deliberately don't PAUSE, a.k.a. cpu_relax(), so that the delay is 838 * as accurate as possible, e.g. doesn't trigger PAUSE-Loop VM-Exits. 839 */ 840 start = rdtsc(); 841 do { 842 now = rdtsc(); 843 } while (now - start < cycles); 844 } 845 846 #define ud2() \ 847 __asm__ __volatile__( \ 848 "ud2\n" \ 849 ) 850 851 #define hlt() \ 852 __asm__ __volatile__( \ 853 "hlt\n" \ 854 ) 855 856 struct kvm_x86_state *vcpu_save_state(struct kvm_vcpu *vcpu); 857 void vcpu_load_state(struct kvm_vcpu *vcpu, struct kvm_x86_state *state); 858 void kvm_x86_state_cleanup(struct kvm_x86_state *state); 859 860 const struct kvm_msr_list *kvm_get_msr_index_list(void); 861 const struct kvm_msr_list *kvm_get_feature_msr_index_list(void); 862 bool kvm_msr_is_in_save_restore_list(uint32_t msr_index); 863 uint64_t kvm_get_feature_msr(uint64_t msr_index); 864 865 static inline void vcpu_msrs_get(struct kvm_vcpu *vcpu, 866 struct kvm_msrs *msrs) 867 { 868 int r = __vcpu_ioctl(vcpu, KVM_GET_MSRS, msrs); 869 870 TEST_ASSERT(r == msrs->nmsrs, 871 "KVM_GET_MSRS failed, r: %i (failed on MSR %x)", 872 r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index); 873 } 874 static inline void vcpu_msrs_set(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs) 875 { 876 int r = __vcpu_ioctl(vcpu, KVM_SET_MSRS, msrs); 877 878 TEST_ASSERT(r == msrs->nmsrs, 879 "KVM_SET_MSRS failed, r: %i (failed on MSR %x)", 880 r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index); 881 } 882 static inline void vcpu_debugregs_get(struct kvm_vcpu *vcpu, 883 struct kvm_debugregs *debugregs) 884 { 885 vcpu_ioctl(vcpu, KVM_GET_DEBUGREGS, debugregs); 886 } 887 static inline void vcpu_debugregs_set(struct kvm_vcpu *vcpu, 888 struct kvm_debugregs *debugregs) 889 { 890 vcpu_ioctl(vcpu, KVM_SET_DEBUGREGS, debugregs); 891 } 892 static inline void vcpu_xsave_get(struct kvm_vcpu *vcpu, 893 struct kvm_xsave *xsave) 894 { 895 vcpu_ioctl(vcpu, KVM_GET_XSAVE, xsave); 896 } 897 static inline void vcpu_xsave2_get(struct kvm_vcpu *vcpu, 898 struct kvm_xsave *xsave) 899 { 900 vcpu_ioctl(vcpu, KVM_GET_XSAVE2, xsave); 901 } 902 static inline void vcpu_xsave_set(struct kvm_vcpu *vcpu, 903 struct kvm_xsave *xsave) 904 { 905 vcpu_ioctl(vcpu, KVM_SET_XSAVE, xsave); 906 } 907 static inline void vcpu_xcrs_get(struct kvm_vcpu *vcpu, 908 struct kvm_xcrs *xcrs) 909 { 910 vcpu_ioctl(vcpu, KVM_GET_XCRS, xcrs); 911 } 912 static inline void vcpu_xcrs_set(struct kvm_vcpu *vcpu, struct kvm_xcrs *xcrs) 913 { 914 vcpu_ioctl(vcpu, KVM_SET_XCRS, xcrs); 915 } 916 917 const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid, 918 uint32_t function, uint32_t index); 919 const struct kvm_cpuid2 *kvm_get_supported_cpuid(void); 920 921 static inline uint32_t kvm_cpu_fms(void) 922 { 923 return get_cpuid_entry(kvm_get_supported_cpuid(), 0x1, 0)->eax; 924 } 925 926 static inline uint32_t kvm_cpu_family(void) 927 { 928 return x86_family(kvm_cpu_fms()); 929 } 930 931 static inline uint32_t kvm_cpu_model(void) 932 { 933 return x86_model(kvm_cpu_fms()); 934 } 935 936 bool kvm_cpuid_has(const struct kvm_cpuid2 *cpuid, 937 struct kvm_x86_cpu_feature feature); 938 939 static inline bool kvm_cpu_has(struct kvm_x86_cpu_feature feature) 940 { 941 return kvm_cpuid_has(kvm_get_supported_cpuid(), feature); 942 } 943 944 uint32_t kvm_cpuid_property(const struct kvm_cpuid2 *cpuid, 945 struct kvm_x86_cpu_property property); 946 947 static inline uint32_t kvm_cpu_property(struct kvm_x86_cpu_property property) 948 { 949 return kvm_cpuid_property(kvm_get_supported_cpuid(), property); 950 } 951 952 static __always_inline bool kvm_cpu_has_p(struct kvm_x86_cpu_property property) 953 { 954 uint32_t max_leaf; 955 956 switch (property.function & 0xc0000000) { 957 case 0: 958 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF); 959 break; 960 case 0x40000000: 961 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_KVM_LEAF); 962 break; 963 case 0x80000000: 964 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_EXT_LEAF); 965 break; 966 case 0xc0000000: 967 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF); 968 } 969 return max_leaf >= property.function; 970 } 971 972 static inline bool kvm_pmu_has(struct kvm_x86_pmu_feature feature) 973 { 974 uint32_t nr_bits; 975 976 if (feature.f.reg == KVM_CPUID_EBX) { 977 nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); 978 return nr_bits > feature.f.bit && !kvm_cpu_has(feature.f); 979 } 980 981 TEST_ASSERT_EQ(feature.f.reg, KVM_CPUID_ECX); 982 nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); 983 return nr_bits > feature.f.bit || kvm_cpu_has(feature.f); 984 } 985 986 static __always_inline uint64_t kvm_cpu_supported_xcr0(void) 987 { 988 if (!kvm_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) 989 return 0; 990 991 return kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | 992 ((uint64_t)kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); 993 } 994 995 static inline size_t kvm_cpuid2_size(int nr_entries) 996 { 997 return sizeof(struct kvm_cpuid2) + 998 sizeof(struct kvm_cpuid_entry2) * nr_entries; 999 } 1000 1001 /* 1002 * Allocate a "struct kvm_cpuid2* instance, with the 0-length arrary of 1003 * entries sized to hold @nr_entries. The caller is responsible for freeing 1004 * the struct. 1005 */ 1006 static inline struct kvm_cpuid2 *allocate_kvm_cpuid2(int nr_entries) 1007 { 1008 struct kvm_cpuid2 *cpuid; 1009 1010 cpuid = malloc(kvm_cpuid2_size(nr_entries)); 1011 TEST_ASSERT(cpuid, "-ENOMEM when allocating kvm_cpuid2"); 1012 1013 cpuid->nent = nr_entries; 1014 1015 return cpuid; 1016 } 1017 1018 void vcpu_init_cpuid(struct kvm_vcpu *vcpu, const struct kvm_cpuid2 *cpuid); 1019 1020 static inline void vcpu_get_cpuid(struct kvm_vcpu *vcpu) 1021 { 1022 vcpu_ioctl(vcpu, KVM_GET_CPUID2, vcpu->cpuid); 1023 } 1024 1025 static inline struct kvm_cpuid_entry2 *__vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu, 1026 uint32_t function, 1027 uint32_t index) 1028 { 1029 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first (or equivalent)"); 1030 1031 vcpu_get_cpuid(vcpu); 1032 1033 return (struct kvm_cpuid_entry2 *)get_cpuid_entry(vcpu->cpuid, 1034 function, index); 1035 } 1036 1037 static inline struct kvm_cpuid_entry2 *vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu, 1038 uint32_t function) 1039 { 1040 return __vcpu_get_cpuid_entry(vcpu, function, 0); 1041 } 1042 1043 static inline int __vcpu_set_cpuid(struct kvm_vcpu *vcpu) 1044 { 1045 int r; 1046 1047 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first"); 1048 r = __vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid); 1049 if (r) 1050 return r; 1051 1052 /* On success, refresh the cache to pick up adjustments made by KVM. */ 1053 vcpu_get_cpuid(vcpu); 1054 return 0; 1055 } 1056 1057 static inline void vcpu_set_cpuid(struct kvm_vcpu *vcpu) 1058 { 1059 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first"); 1060 vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid); 1061 1062 /* Refresh the cache to pick up adjustments made by KVM. */ 1063 vcpu_get_cpuid(vcpu); 1064 } 1065 1066 void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu, 1067 struct kvm_x86_cpu_property property, 1068 uint32_t value); 1069 void vcpu_set_cpuid_maxphyaddr(struct kvm_vcpu *vcpu, uint8_t maxphyaddr); 1070 1071 void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, uint32_t function); 1072 1073 static inline bool vcpu_cpuid_has(struct kvm_vcpu *vcpu, 1074 struct kvm_x86_cpu_feature feature) 1075 { 1076 struct kvm_cpuid_entry2 *entry; 1077 1078 entry = __vcpu_get_cpuid_entry(vcpu, feature.function, feature.index); 1079 return *((&entry->eax) + feature.reg) & BIT(feature.bit); 1080 } 1081 1082 void vcpu_set_or_clear_cpuid_feature(struct kvm_vcpu *vcpu, 1083 struct kvm_x86_cpu_feature feature, 1084 bool set); 1085 1086 static inline void vcpu_set_cpuid_feature(struct kvm_vcpu *vcpu, 1087 struct kvm_x86_cpu_feature feature) 1088 { 1089 vcpu_set_or_clear_cpuid_feature(vcpu, feature, true); 1090 1091 } 1092 1093 static inline void vcpu_clear_cpuid_feature(struct kvm_vcpu *vcpu, 1094 struct kvm_x86_cpu_feature feature) 1095 { 1096 vcpu_set_or_clear_cpuid_feature(vcpu, feature, false); 1097 } 1098 1099 uint64_t vcpu_get_msr(struct kvm_vcpu *vcpu, uint64_t msr_index); 1100 int _vcpu_set_msr(struct kvm_vcpu *vcpu, uint64_t msr_index, uint64_t msr_value); 1101 1102 /* 1103 * Assert on an MSR access(es) and pretty print the MSR name when possible. 1104 * Note, the caller provides the stringified name so that the name of macro is 1105 * printed, not the value the macro resolves to (due to macro expansion). 1106 */ 1107 #define TEST_ASSERT_MSR(cond, fmt, msr, str, args...) \ 1108 do { \ 1109 if (__builtin_constant_p(msr)) { \ 1110 TEST_ASSERT(cond, fmt, str, args); \ 1111 } else if (!(cond)) { \ 1112 char buf[16]; \ 1113 \ 1114 snprintf(buf, sizeof(buf), "MSR 0x%x", msr); \ 1115 TEST_ASSERT(cond, fmt, buf, args); \ 1116 } \ 1117 } while (0) 1118 1119 /* 1120 * Returns true if KVM should return the last written value when reading an MSR 1121 * from userspace, e.g. the MSR isn't a command MSR, doesn't emulate state that 1122 * is changing, etc. This is NOT an exhaustive list! The intent is to filter 1123 * out MSRs that are not durable _and_ that a selftest wants to write. 1124 */ 1125 static inline bool is_durable_msr(uint32_t msr) 1126 { 1127 return msr != MSR_IA32_TSC; 1128 } 1129 1130 #define vcpu_set_msr(vcpu, msr, val) \ 1131 do { \ 1132 uint64_t r, v = val; \ 1133 \ 1134 TEST_ASSERT_MSR(_vcpu_set_msr(vcpu, msr, v) == 1, \ 1135 "KVM_SET_MSRS failed on %s, value = 0x%lx", msr, #msr, v); \ 1136 if (!is_durable_msr(msr)) \ 1137 break; \ 1138 r = vcpu_get_msr(vcpu, msr); \ 1139 TEST_ASSERT_MSR(r == v, "Set %s to '0x%lx', got back '0x%lx'", msr, #msr, v, r);\ 1140 } while (0) 1141 1142 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits); 1143 void kvm_init_vm_address_properties(struct kvm_vm *vm); 1144 bool vm_is_unrestricted_guest(struct kvm_vm *vm); 1145 1146 struct ex_regs { 1147 uint64_t rax, rcx, rdx, rbx; 1148 uint64_t rbp, rsi, rdi; 1149 uint64_t r8, r9, r10, r11; 1150 uint64_t r12, r13, r14, r15; 1151 uint64_t vector; 1152 uint64_t error_code; 1153 uint64_t rip; 1154 uint64_t cs; 1155 uint64_t rflags; 1156 }; 1157 1158 struct idt_entry { 1159 uint16_t offset0; 1160 uint16_t selector; 1161 uint16_t ist : 3; 1162 uint16_t : 5; 1163 uint16_t type : 4; 1164 uint16_t : 1; 1165 uint16_t dpl : 2; 1166 uint16_t p : 1; 1167 uint16_t offset1; 1168 uint32_t offset2; uint32_t reserved; 1169 }; 1170 1171 void vm_install_exception_handler(struct kvm_vm *vm, int vector, 1172 void (*handler)(struct ex_regs *)); 1173 1174 /* If a toddler were to say "abracadabra". */ 1175 #define KVM_EXCEPTION_MAGIC 0xabacadabaULL 1176 1177 /* 1178 * KVM selftest exception fixup uses registers to coordinate with the exception 1179 * handler, versus the kernel's in-memory tables and KVM-Unit-Tests's in-memory 1180 * per-CPU data. Using only registers avoids having to map memory into the 1181 * guest, doesn't require a valid, stable GS.base, and reduces the risk of 1182 * for recursive faults when accessing memory in the handler. The downside to 1183 * using registers is that it restricts what registers can be used by the actual 1184 * instruction. But, selftests are 64-bit only, making register* pressure a 1185 * minor concern. Use r9-r11 as they are volatile, i.e. don't need to be saved 1186 * by the callee, and except for r11 are not implicit parameters to any 1187 * instructions. Ideally, fixup would use r8-r10 and thus avoid implicit 1188 * parameters entirely, but Hyper-V's hypercall ABI uses r8 and testing Hyper-V 1189 * is higher priority than testing non-faulting SYSCALL/SYSRET. 1190 * 1191 * Note, the fixup handler deliberately does not handle #DE, i.e. the vector 1192 * is guaranteed to be non-zero on fault. 1193 * 1194 * REGISTER INPUTS: 1195 * r9 = MAGIC 1196 * r10 = RIP 1197 * r11 = new RIP on fault 1198 * 1199 * REGISTER OUTPUTS: 1200 * r9 = exception vector (non-zero) 1201 * r10 = error code 1202 */ 1203 #define __KVM_ASM_SAFE(insn, fep) \ 1204 "mov $" __stringify(KVM_EXCEPTION_MAGIC) ", %%r9\n\t" \ 1205 "lea 1f(%%rip), %%r10\n\t" \ 1206 "lea 2f(%%rip), %%r11\n\t" \ 1207 fep "1: " insn "\n\t" \ 1208 "xor %%r9, %%r9\n\t" \ 1209 "2:\n\t" \ 1210 "mov %%r9b, %[vector]\n\t" \ 1211 "mov %%r10, %[error_code]\n\t" 1212 1213 #define KVM_ASM_SAFE(insn) __KVM_ASM_SAFE(insn, "") 1214 #define KVM_ASM_SAFE_FEP(insn) __KVM_ASM_SAFE(insn, KVM_FEP) 1215 1216 #define KVM_ASM_SAFE_OUTPUTS(v, ec) [vector] "=qm"(v), [error_code] "=rm"(ec) 1217 #define KVM_ASM_SAFE_CLOBBERS "r9", "r10", "r11" 1218 1219 #define kvm_asm_safe(insn, inputs...) \ 1220 ({ \ 1221 uint64_t ign_error_code; \ 1222 uint8_t vector; \ 1223 \ 1224 asm volatile(KVM_ASM_SAFE(insn) \ 1225 : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code) \ 1226 : inputs \ 1227 : KVM_ASM_SAFE_CLOBBERS); \ 1228 vector; \ 1229 }) 1230 1231 #define kvm_asm_safe_ec(insn, error_code, inputs...) \ 1232 ({ \ 1233 uint8_t vector; \ 1234 \ 1235 asm volatile(KVM_ASM_SAFE(insn) \ 1236 : KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1237 : inputs \ 1238 : KVM_ASM_SAFE_CLOBBERS); \ 1239 vector; \ 1240 }) 1241 1242 #define kvm_asm_safe_fep(insn, inputs...) \ 1243 ({ \ 1244 uint64_t ign_error_code; \ 1245 uint8_t vector; \ 1246 \ 1247 asm volatile(KVM_ASM_SAFE(insn) \ 1248 : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code) \ 1249 : inputs \ 1250 : KVM_ASM_SAFE_CLOBBERS); \ 1251 vector; \ 1252 }) 1253 1254 #define kvm_asm_safe_ec_fep(insn, error_code, inputs...) \ 1255 ({ \ 1256 uint8_t vector; \ 1257 \ 1258 asm volatile(KVM_ASM_SAFE_FEP(insn) \ 1259 : KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1260 : inputs \ 1261 : KVM_ASM_SAFE_CLOBBERS); \ 1262 vector; \ 1263 }) 1264 1265 #define BUILD_READ_U64_SAFE_HELPER(insn, _fep, _FEP) \ 1266 static inline uint8_t insn##_safe ##_fep(uint32_t idx, uint64_t *val) \ 1267 { \ 1268 uint64_t error_code; \ 1269 uint8_t vector; \ 1270 uint32_t a, d; \ 1271 \ 1272 asm volatile(KVM_ASM_SAFE##_FEP(#insn) \ 1273 : "=a"(a), "=d"(d), \ 1274 KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1275 : "c"(idx) \ 1276 : KVM_ASM_SAFE_CLOBBERS); \ 1277 \ 1278 *val = (uint64_t)a | ((uint64_t)d << 32); \ 1279 return vector; \ 1280 } 1281 1282 /* 1283 * Generate {insn}_safe() and {insn}_safe_fep() helpers for instructions that 1284 * use ECX as in input index, and EDX:EAX as a 64-bit output. 1285 */ 1286 #define BUILD_READ_U64_SAFE_HELPERS(insn) \ 1287 BUILD_READ_U64_SAFE_HELPER(insn, , ) \ 1288 BUILD_READ_U64_SAFE_HELPER(insn, _fep, _FEP) \ 1289 1290 BUILD_READ_U64_SAFE_HELPERS(rdmsr) 1291 BUILD_READ_U64_SAFE_HELPERS(rdpmc) 1292 BUILD_READ_U64_SAFE_HELPERS(xgetbv) 1293 1294 static inline uint8_t wrmsr_safe(uint32_t msr, uint64_t val) 1295 { 1296 return kvm_asm_safe("wrmsr", "a"(val & -1u), "d"(val >> 32), "c"(msr)); 1297 } 1298 1299 static inline uint8_t xsetbv_safe(uint32_t index, uint64_t value) 1300 { 1301 u32 eax = value; 1302 u32 edx = value >> 32; 1303 1304 return kvm_asm_safe("xsetbv", "a" (eax), "d" (edx), "c" (index)); 1305 } 1306 1307 bool kvm_is_tdp_enabled(void); 1308 1309 static inline bool kvm_is_pmu_enabled(void) 1310 { 1311 return get_kvm_param_bool("enable_pmu"); 1312 } 1313 1314 static inline bool kvm_is_forced_emulation_enabled(void) 1315 { 1316 return !!get_kvm_param_integer("force_emulation_prefix"); 1317 } 1318 1319 uint64_t *__vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr, 1320 int *level); 1321 uint64_t *vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr); 1322 1323 uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2, 1324 uint64_t a3); 1325 uint64_t __xen_hypercall(uint64_t nr, uint64_t a0, void *a1); 1326 void xen_hypercall(uint64_t nr, uint64_t a0, void *a1); 1327 1328 static inline uint64_t __kvm_hypercall_map_gpa_range(uint64_t gpa, 1329 uint64_t size, uint64_t flags) 1330 { 1331 return kvm_hypercall(KVM_HC_MAP_GPA_RANGE, gpa, size >> PAGE_SHIFT, flags, 0); 1332 } 1333 1334 static inline void kvm_hypercall_map_gpa_range(uint64_t gpa, uint64_t size, 1335 uint64_t flags) 1336 { 1337 uint64_t ret = __kvm_hypercall_map_gpa_range(gpa, size, flags); 1338 1339 GUEST_ASSERT(!ret); 1340 } 1341 1342 void __vm_xsave_require_permission(uint64_t xfeature, const char *name); 1343 1344 #define vm_xsave_require_permission(xfeature) \ 1345 __vm_xsave_require_permission(xfeature, #xfeature) 1346 1347 enum pg_level { 1348 PG_LEVEL_NONE, 1349 PG_LEVEL_4K, 1350 PG_LEVEL_2M, 1351 PG_LEVEL_1G, 1352 PG_LEVEL_512G, 1353 PG_LEVEL_NUM 1354 }; 1355 1356 #define PG_LEVEL_SHIFT(_level) ((_level - 1) * 9 + 12) 1357 #define PG_LEVEL_SIZE(_level) (1ull << PG_LEVEL_SHIFT(_level)) 1358 1359 #define PG_SIZE_4K PG_LEVEL_SIZE(PG_LEVEL_4K) 1360 #define PG_SIZE_2M PG_LEVEL_SIZE(PG_LEVEL_2M) 1361 #define PG_SIZE_1G PG_LEVEL_SIZE(PG_LEVEL_1G) 1362 1363 void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, int level); 1364 void virt_map_level(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, 1365 uint64_t nr_bytes, int level); 1366 1367 /* 1368 * Basic CPU control in CR0 1369 */ 1370 #define X86_CR0_PE (1UL<<0) /* Protection Enable */ 1371 #define X86_CR0_MP (1UL<<1) /* Monitor Coprocessor */ 1372 #define X86_CR0_EM (1UL<<2) /* Emulation */ 1373 #define X86_CR0_TS (1UL<<3) /* Task Switched */ 1374 #define X86_CR0_ET (1UL<<4) /* Extension Type */ 1375 #define X86_CR0_NE (1UL<<5) /* Numeric Error */ 1376 #define X86_CR0_WP (1UL<<16) /* Write Protect */ 1377 #define X86_CR0_AM (1UL<<18) /* Alignment Mask */ 1378 #define X86_CR0_NW (1UL<<29) /* Not Write-through */ 1379 #define X86_CR0_CD (1UL<<30) /* Cache Disable */ 1380 #define X86_CR0_PG (1UL<<31) /* Paging */ 1381 1382 #define PFERR_PRESENT_BIT 0 1383 #define PFERR_WRITE_BIT 1 1384 #define PFERR_USER_BIT 2 1385 #define PFERR_RSVD_BIT 3 1386 #define PFERR_FETCH_BIT 4 1387 #define PFERR_PK_BIT 5 1388 #define PFERR_SGX_BIT 15 1389 #define PFERR_GUEST_FINAL_BIT 32 1390 #define PFERR_GUEST_PAGE_BIT 33 1391 #define PFERR_IMPLICIT_ACCESS_BIT 48 1392 1393 #define PFERR_PRESENT_MASK BIT(PFERR_PRESENT_BIT) 1394 #define PFERR_WRITE_MASK BIT(PFERR_WRITE_BIT) 1395 #define PFERR_USER_MASK BIT(PFERR_USER_BIT) 1396 #define PFERR_RSVD_MASK BIT(PFERR_RSVD_BIT) 1397 #define PFERR_FETCH_MASK BIT(PFERR_FETCH_BIT) 1398 #define PFERR_PK_MASK BIT(PFERR_PK_BIT) 1399 #define PFERR_SGX_MASK BIT(PFERR_SGX_BIT) 1400 #define PFERR_GUEST_FINAL_MASK BIT_ULL(PFERR_GUEST_FINAL_BIT) 1401 #define PFERR_GUEST_PAGE_MASK BIT_ULL(PFERR_GUEST_PAGE_BIT) 1402 #define PFERR_IMPLICIT_ACCESS BIT_ULL(PFERR_IMPLICIT_ACCESS_BIT) 1403 1404 bool sys_clocksource_is_based_on_tsc(void); 1405 1406 #endif /* SELFTEST_KVM_PROCESSOR_H */ 1407