1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2018, Google LLC. 4 */ 5 6 #ifndef SELFTEST_KVM_PROCESSOR_H 7 #define SELFTEST_KVM_PROCESSOR_H 8 9 #include <assert.h> 10 #include <stdint.h> 11 #include <syscall.h> 12 13 #include <asm/msr-index.h> 14 #include <asm/prctl.h> 15 16 #include <linux/kvm_para.h> 17 #include <linux/stringify.h> 18 19 #include "kvm_util.h" 20 #include "ucall_common.h" 21 22 extern bool host_cpu_is_intel; 23 extern bool host_cpu_is_amd; 24 extern uint64_t guest_tsc_khz; 25 26 #ifndef MAX_NR_CPUID_ENTRIES 27 #define MAX_NR_CPUID_ENTRIES 100 28 #endif 29 30 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 31 32 /* Forced emulation prefix, used to invoke the emulator unconditionally. */ 33 #define KVM_FEP "ud2; .byte 'k', 'v', 'm';" 34 35 #define NMI_VECTOR 0x02 36 37 const char *ex_str(int vector); 38 39 #define X86_EFLAGS_FIXED (1u << 1) 40 41 #define X86_CR4_VME (1ul << 0) 42 #define X86_CR4_PVI (1ul << 1) 43 #define X86_CR4_TSD (1ul << 2) 44 #define X86_CR4_DE (1ul << 3) 45 #define X86_CR4_PSE (1ul << 4) 46 #define X86_CR4_PAE (1ul << 5) 47 #define X86_CR4_MCE (1ul << 6) 48 #define X86_CR4_PGE (1ul << 7) 49 #define X86_CR4_PCE (1ul << 8) 50 #define X86_CR4_OSFXSR (1ul << 9) 51 #define X86_CR4_OSXMMEXCPT (1ul << 10) 52 #define X86_CR4_UMIP (1ul << 11) 53 #define X86_CR4_LA57 (1ul << 12) 54 #define X86_CR4_VMXE (1ul << 13) 55 #define X86_CR4_SMXE (1ul << 14) 56 #define X86_CR4_FSGSBASE (1ul << 16) 57 #define X86_CR4_PCIDE (1ul << 17) 58 #define X86_CR4_OSXSAVE (1ul << 18) 59 #define X86_CR4_SMEP (1ul << 20) 60 #define X86_CR4_SMAP (1ul << 21) 61 #define X86_CR4_PKE (1ul << 22) 62 63 struct xstate_header { 64 u64 xstate_bv; 65 u64 xcomp_bv; 66 u64 reserved[6]; 67 } __attribute__((packed)); 68 69 struct xstate { 70 u8 i387[512]; 71 struct xstate_header header; 72 u8 extended_state_area[0]; 73 } __attribute__ ((packed, aligned (64))); 74 75 #define XFEATURE_MASK_FP BIT_ULL(0) 76 #define XFEATURE_MASK_SSE BIT_ULL(1) 77 #define XFEATURE_MASK_YMM BIT_ULL(2) 78 #define XFEATURE_MASK_BNDREGS BIT_ULL(3) 79 #define XFEATURE_MASK_BNDCSR BIT_ULL(4) 80 #define XFEATURE_MASK_OPMASK BIT_ULL(5) 81 #define XFEATURE_MASK_ZMM_Hi256 BIT_ULL(6) 82 #define XFEATURE_MASK_Hi16_ZMM BIT_ULL(7) 83 #define XFEATURE_MASK_PT BIT_ULL(8) 84 #define XFEATURE_MASK_PKRU BIT_ULL(9) 85 #define XFEATURE_MASK_PASID BIT_ULL(10) 86 #define XFEATURE_MASK_CET_USER BIT_ULL(11) 87 #define XFEATURE_MASK_CET_KERNEL BIT_ULL(12) 88 #define XFEATURE_MASK_LBR BIT_ULL(15) 89 #define XFEATURE_MASK_XTILE_CFG BIT_ULL(17) 90 #define XFEATURE_MASK_XTILE_DATA BIT_ULL(18) 91 92 #define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK | \ 93 XFEATURE_MASK_ZMM_Hi256 | \ 94 XFEATURE_MASK_Hi16_ZMM) 95 #define XFEATURE_MASK_XTILE (XFEATURE_MASK_XTILE_DATA | \ 96 XFEATURE_MASK_XTILE_CFG) 97 98 /* Note, these are ordered alphabetically to match kvm_cpuid_entry2. Eww. */ 99 enum cpuid_output_regs { 100 KVM_CPUID_EAX, 101 KVM_CPUID_EBX, 102 KVM_CPUID_ECX, 103 KVM_CPUID_EDX 104 }; 105 106 /* 107 * Pack the information into a 64-bit value so that each X86_FEATURE_XXX can be 108 * passed by value with no overhead. 109 */ 110 struct kvm_x86_cpu_feature { 111 u32 function; 112 u16 index; 113 u8 reg; 114 u8 bit; 115 }; 116 #define KVM_X86_CPU_FEATURE(fn, idx, gpr, __bit) \ 117 ({ \ 118 struct kvm_x86_cpu_feature feature = { \ 119 .function = fn, \ 120 .index = idx, \ 121 .reg = KVM_CPUID_##gpr, \ 122 .bit = __bit, \ 123 }; \ 124 \ 125 kvm_static_assert((fn & 0xc0000000) == 0 || \ 126 (fn & 0xc0000000) == 0x40000000 || \ 127 (fn & 0xc0000000) == 0x80000000 || \ 128 (fn & 0xc0000000) == 0xc0000000); \ 129 kvm_static_assert(idx < BIT(sizeof(feature.index) * BITS_PER_BYTE)); \ 130 feature; \ 131 }) 132 133 /* 134 * Basic Leafs, a.k.a. Intel defined 135 */ 136 #define X86_FEATURE_MWAIT KVM_X86_CPU_FEATURE(0x1, 0, ECX, 3) 137 #define X86_FEATURE_VMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 5) 138 #define X86_FEATURE_SMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 6) 139 #define X86_FEATURE_PDCM KVM_X86_CPU_FEATURE(0x1, 0, ECX, 15) 140 #define X86_FEATURE_PCID KVM_X86_CPU_FEATURE(0x1, 0, ECX, 17) 141 #define X86_FEATURE_X2APIC KVM_X86_CPU_FEATURE(0x1, 0, ECX, 21) 142 #define X86_FEATURE_MOVBE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 22) 143 #define X86_FEATURE_TSC_DEADLINE_TIMER KVM_X86_CPU_FEATURE(0x1, 0, ECX, 24) 144 #define X86_FEATURE_XSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 26) 145 #define X86_FEATURE_OSXSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 27) 146 #define X86_FEATURE_RDRAND KVM_X86_CPU_FEATURE(0x1, 0, ECX, 30) 147 #define X86_FEATURE_HYPERVISOR KVM_X86_CPU_FEATURE(0x1, 0, ECX, 31) 148 #define X86_FEATURE_PAE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 6) 149 #define X86_FEATURE_MCE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 7) 150 #define X86_FEATURE_APIC KVM_X86_CPU_FEATURE(0x1, 0, EDX, 9) 151 #define X86_FEATURE_CLFLUSH KVM_X86_CPU_FEATURE(0x1, 0, EDX, 19) 152 #define X86_FEATURE_XMM KVM_X86_CPU_FEATURE(0x1, 0, EDX, 25) 153 #define X86_FEATURE_XMM2 KVM_X86_CPU_FEATURE(0x1, 0, EDX, 26) 154 #define X86_FEATURE_FSGSBASE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 0) 155 #define X86_FEATURE_TSC_ADJUST KVM_X86_CPU_FEATURE(0x7, 0, EBX, 1) 156 #define X86_FEATURE_SGX KVM_X86_CPU_FEATURE(0x7, 0, EBX, 2) 157 #define X86_FEATURE_HLE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 4) 158 #define X86_FEATURE_SMEP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 7) 159 #define X86_FEATURE_INVPCID KVM_X86_CPU_FEATURE(0x7, 0, EBX, 10) 160 #define X86_FEATURE_RTM KVM_X86_CPU_FEATURE(0x7, 0, EBX, 11) 161 #define X86_FEATURE_MPX KVM_X86_CPU_FEATURE(0x7, 0, EBX, 14) 162 #define X86_FEATURE_SMAP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 20) 163 #define X86_FEATURE_PCOMMIT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 22) 164 #define X86_FEATURE_CLFLUSHOPT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 23) 165 #define X86_FEATURE_CLWB KVM_X86_CPU_FEATURE(0x7, 0, EBX, 24) 166 #define X86_FEATURE_UMIP KVM_X86_CPU_FEATURE(0x7, 0, ECX, 2) 167 #define X86_FEATURE_PKU KVM_X86_CPU_FEATURE(0x7, 0, ECX, 3) 168 #define X86_FEATURE_OSPKE KVM_X86_CPU_FEATURE(0x7, 0, ECX, 4) 169 #define X86_FEATURE_LA57 KVM_X86_CPU_FEATURE(0x7, 0, ECX, 16) 170 #define X86_FEATURE_RDPID KVM_X86_CPU_FEATURE(0x7, 0, ECX, 22) 171 #define X86_FEATURE_SGX_LC KVM_X86_CPU_FEATURE(0x7, 0, ECX, 30) 172 #define X86_FEATURE_SHSTK KVM_X86_CPU_FEATURE(0x7, 0, ECX, 7) 173 #define X86_FEATURE_IBT KVM_X86_CPU_FEATURE(0x7, 0, EDX, 20) 174 #define X86_FEATURE_AMX_TILE KVM_X86_CPU_FEATURE(0x7, 0, EDX, 24) 175 #define X86_FEATURE_SPEC_CTRL KVM_X86_CPU_FEATURE(0x7, 0, EDX, 26) 176 #define X86_FEATURE_ARCH_CAPABILITIES KVM_X86_CPU_FEATURE(0x7, 0, EDX, 29) 177 #define X86_FEATURE_PKS KVM_X86_CPU_FEATURE(0x7, 0, ECX, 31) 178 #define X86_FEATURE_XTILECFG KVM_X86_CPU_FEATURE(0xD, 0, EAX, 17) 179 #define X86_FEATURE_XTILEDATA KVM_X86_CPU_FEATURE(0xD, 0, EAX, 18) 180 #define X86_FEATURE_XSAVES KVM_X86_CPU_FEATURE(0xD, 1, EAX, 3) 181 #define X86_FEATURE_XFD KVM_X86_CPU_FEATURE(0xD, 1, EAX, 4) 182 #define X86_FEATURE_XTILEDATA_XFD KVM_X86_CPU_FEATURE(0xD, 18, ECX, 2) 183 184 /* 185 * Extended Leafs, a.k.a. AMD defined 186 */ 187 #define X86_FEATURE_SVM KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 2) 188 #define X86_FEATURE_PERFCTR_CORE KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 23) 189 #define X86_FEATURE_PERFCTR_NB KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 24) 190 #define X86_FEATURE_PERFCTR_LLC KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 28) 191 #define X86_FEATURE_NX KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 20) 192 #define X86_FEATURE_GBPAGES KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 26) 193 #define X86_FEATURE_RDTSCP KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 27) 194 #define X86_FEATURE_LM KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 29) 195 #define X86_FEATURE_INVTSC KVM_X86_CPU_FEATURE(0x80000007, 0, EDX, 8) 196 #define X86_FEATURE_RDPRU KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 4) 197 #define X86_FEATURE_AMD_IBPB KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 12) 198 #define X86_FEATURE_NPT KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 0) 199 #define X86_FEATURE_LBRV KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 1) 200 #define X86_FEATURE_NRIPS KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 3) 201 #define X86_FEATURE_TSCRATEMSR KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 4) 202 #define X86_FEATURE_PAUSEFILTER KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 10) 203 #define X86_FEATURE_PFTHRESHOLD KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 12) 204 #define X86_FEATURE_VGIF KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 16) 205 #define X86_FEATURE_IDLE_HLT KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 30) 206 #define X86_FEATURE_SEV KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 1) 207 #define X86_FEATURE_SEV_ES KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 3) 208 #define X86_FEATURE_SEV_SNP KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 4) 209 #define X86_FEATURE_PERFMON_V2 KVM_X86_CPU_FEATURE(0x80000022, 0, EAX, 0) 210 #define X86_FEATURE_LBR_PMC_FREEZE KVM_X86_CPU_FEATURE(0x80000022, 0, EAX, 2) 211 212 /* 213 * KVM defined paravirt features. 214 */ 215 #define X86_FEATURE_KVM_CLOCKSOURCE KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 0) 216 #define X86_FEATURE_KVM_NOP_IO_DELAY KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 1) 217 #define X86_FEATURE_KVM_MMU_OP KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 2) 218 #define X86_FEATURE_KVM_CLOCKSOURCE2 KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 3) 219 #define X86_FEATURE_KVM_ASYNC_PF KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 4) 220 #define X86_FEATURE_KVM_STEAL_TIME KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 5) 221 #define X86_FEATURE_KVM_PV_EOI KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 6) 222 #define X86_FEATURE_KVM_PV_UNHALT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 7) 223 /* Bit 8 apparently isn't used?!?! */ 224 #define X86_FEATURE_KVM_PV_TLB_FLUSH KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 9) 225 #define X86_FEATURE_KVM_ASYNC_PF_VMEXIT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 10) 226 #define X86_FEATURE_KVM_PV_SEND_IPI KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 11) 227 #define X86_FEATURE_KVM_POLL_CONTROL KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 12) 228 #define X86_FEATURE_KVM_PV_SCHED_YIELD KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 13) 229 #define X86_FEATURE_KVM_ASYNC_PF_INT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 14) 230 #define X86_FEATURE_KVM_MSI_EXT_DEST_ID KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 15) 231 #define X86_FEATURE_KVM_HC_MAP_GPA_RANGE KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 16) 232 #define X86_FEATURE_KVM_MIGRATION_CONTROL KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 17) 233 234 /* 235 * Same idea as X86_FEATURE_XXX, but X86_PROPERTY_XXX retrieves a multi-bit 236 * value/property as opposed to a single-bit feature. Again, pack the info 237 * into a 64-bit value to pass by value with no overhead. 238 */ 239 struct kvm_x86_cpu_property { 240 u32 function; 241 u8 index; 242 u8 reg; 243 u8 lo_bit; 244 u8 hi_bit; 245 }; 246 #define KVM_X86_CPU_PROPERTY(fn, idx, gpr, low_bit, high_bit) \ 247 ({ \ 248 struct kvm_x86_cpu_property property = { \ 249 .function = fn, \ 250 .index = idx, \ 251 .reg = KVM_CPUID_##gpr, \ 252 .lo_bit = low_bit, \ 253 .hi_bit = high_bit, \ 254 }; \ 255 \ 256 kvm_static_assert(low_bit < high_bit); \ 257 kvm_static_assert((fn & 0xc0000000) == 0 || \ 258 (fn & 0xc0000000) == 0x40000000 || \ 259 (fn & 0xc0000000) == 0x80000000 || \ 260 (fn & 0xc0000000) == 0xc0000000); \ 261 kvm_static_assert(idx < BIT(sizeof(property.index) * BITS_PER_BYTE)); \ 262 property; \ 263 }) 264 265 #define X86_PROPERTY_MAX_BASIC_LEAF KVM_X86_CPU_PROPERTY(0, 0, EAX, 0, 31) 266 #define X86_PROPERTY_PMU_VERSION KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 0, 7) 267 #define X86_PROPERTY_PMU_NR_GP_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 8, 15) 268 #define X86_PROPERTY_PMU_GP_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 16, 23) 269 #define X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 24, 31) 270 #define X86_PROPERTY_PMU_EVENTS_MASK KVM_X86_CPU_PROPERTY(0xa, 0, EBX, 0, 12) 271 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK KVM_X86_CPU_PROPERTY(0xa, 0, ECX, 0, 31) 272 #define X86_PROPERTY_PMU_NR_FIXED_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EDX, 0, 4) 273 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0, EDX, 5, 12) 274 275 #define X86_PROPERTY_SUPPORTED_XCR0_LO KVM_X86_CPU_PROPERTY(0xd, 0, EAX, 0, 31) 276 #define X86_PROPERTY_XSTATE_MAX_SIZE_XCR0 KVM_X86_CPU_PROPERTY(0xd, 0, EBX, 0, 31) 277 #define X86_PROPERTY_XSTATE_MAX_SIZE KVM_X86_CPU_PROPERTY(0xd, 0, ECX, 0, 31) 278 #define X86_PROPERTY_SUPPORTED_XCR0_HI KVM_X86_CPU_PROPERTY(0xd, 0, EDX, 0, 31) 279 280 #define X86_PROPERTY_XSTATE_TILE_SIZE KVM_X86_CPU_PROPERTY(0xd, 18, EAX, 0, 31) 281 #define X86_PROPERTY_XSTATE_TILE_OFFSET KVM_X86_CPU_PROPERTY(0xd, 18, EBX, 0, 31) 282 #define X86_PROPERTY_AMX_MAX_PALETTE_TABLES KVM_X86_CPU_PROPERTY(0x1d, 0, EAX, 0, 31) 283 #define X86_PROPERTY_AMX_TOTAL_TILE_BYTES KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 0, 15) 284 #define X86_PROPERTY_AMX_BYTES_PER_TILE KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 16, 31) 285 #define X86_PROPERTY_AMX_BYTES_PER_ROW KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 0, 15) 286 #define X86_PROPERTY_AMX_NR_TILE_REGS KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 16, 31) 287 #define X86_PROPERTY_AMX_MAX_ROWS KVM_X86_CPU_PROPERTY(0x1d, 1, ECX, 0, 15) 288 289 #define X86_PROPERTY_MAX_KVM_LEAF KVM_X86_CPU_PROPERTY(0x40000000, 0, EAX, 0, 31) 290 291 #define X86_PROPERTY_MAX_EXT_LEAF KVM_X86_CPU_PROPERTY(0x80000000, 0, EAX, 0, 31) 292 #define X86_PROPERTY_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 0, 7) 293 #define X86_PROPERTY_MAX_VIRT_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 8, 15) 294 #define X86_PROPERTY_GUEST_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 16, 23) 295 #define X86_PROPERTY_SEV_C_BIT KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 0, 5) 296 #define X86_PROPERTY_PHYS_ADDR_REDUCTION KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 6, 11) 297 #define X86_PROPERTY_NR_PERFCTR_CORE KVM_X86_CPU_PROPERTY(0x80000022, 0, EBX, 0, 3) 298 #define X86_PROPERTY_NR_PERFCTR_NB KVM_X86_CPU_PROPERTY(0x80000022, 0, EBX, 10, 15) 299 300 #define X86_PROPERTY_MAX_CENTAUR_LEAF KVM_X86_CPU_PROPERTY(0xC0000000, 0, EAX, 0, 31) 301 302 /* 303 * Intel's architectural PMU events are bizarre. They have a "feature" bit 304 * that indicates the feature is _not_ supported, and a property that states 305 * the length of the bit mask of unsupported features. A feature is supported 306 * if the size of the bit mask is larger than the "unavailable" bit, and said 307 * bit is not set. Fixed counters also bizarre enumeration, but inverted from 308 * arch events for general purpose counters. Fixed counters are supported if a 309 * feature flag is set **OR** the total number of fixed counters is greater 310 * than index of the counter. 311 * 312 * Wrap the events for general purpose and fixed counters to simplify checking 313 * whether or not a given architectural event is supported. 314 */ 315 struct kvm_x86_pmu_feature { 316 struct kvm_x86_cpu_feature f; 317 }; 318 #define KVM_X86_PMU_FEATURE(__reg, __bit) \ 319 ({ \ 320 struct kvm_x86_pmu_feature feature = { \ 321 .f = KVM_X86_CPU_FEATURE(0xa, 0, __reg, __bit), \ 322 }; \ 323 \ 324 kvm_static_assert(KVM_CPUID_##__reg == KVM_CPUID_EBX || \ 325 KVM_CPUID_##__reg == KVM_CPUID_ECX); \ 326 feature; \ 327 }) 328 329 #define X86_PMU_FEATURE_CPU_CYCLES KVM_X86_PMU_FEATURE(EBX, 0) 330 #define X86_PMU_FEATURE_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 1) 331 #define X86_PMU_FEATURE_REFERENCE_CYCLES KVM_X86_PMU_FEATURE(EBX, 2) 332 #define X86_PMU_FEATURE_LLC_REFERENCES KVM_X86_PMU_FEATURE(EBX, 3) 333 #define X86_PMU_FEATURE_LLC_MISSES KVM_X86_PMU_FEATURE(EBX, 4) 334 #define X86_PMU_FEATURE_BRANCH_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 5) 335 #define X86_PMU_FEATURE_BRANCHES_MISPREDICTED KVM_X86_PMU_FEATURE(EBX, 6) 336 #define X86_PMU_FEATURE_TOPDOWN_SLOTS KVM_X86_PMU_FEATURE(EBX, 7) 337 #define X86_PMU_FEATURE_TOPDOWN_BE_BOUND KVM_X86_PMU_FEATURE(EBX, 8) 338 #define X86_PMU_FEATURE_TOPDOWN_BAD_SPEC KVM_X86_PMU_FEATURE(EBX, 9) 339 #define X86_PMU_FEATURE_TOPDOWN_FE_BOUND KVM_X86_PMU_FEATURE(EBX, 10) 340 #define X86_PMU_FEATURE_TOPDOWN_RETIRING KVM_X86_PMU_FEATURE(EBX, 11) 341 #define X86_PMU_FEATURE_LBR_INSERTS KVM_X86_PMU_FEATURE(EBX, 12) 342 343 #define X86_PMU_FEATURE_INSNS_RETIRED_FIXED KVM_X86_PMU_FEATURE(ECX, 0) 344 #define X86_PMU_FEATURE_CPU_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX, 1) 345 #define X86_PMU_FEATURE_REFERENCE_TSC_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX, 2) 346 #define X86_PMU_FEATURE_TOPDOWN_SLOTS_FIXED KVM_X86_PMU_FEATURE(ECX, 3) 347 348 static inline unsigned int x86_family(unsigned int eax) 349 { 350 unsigned int x86; 351 352 x86 = (eax >> 8) & 0xf; 353 354 if (x86 == 0xf) 355 x86 += (eax >> 20) & 0xff; 356 357 return x86; 358 } 359 360 static inline unsigned int x86_model(unsigned int eax) 361 { 362 return ((eax >> 12) & 0xf0) | ((eax >> 4) & 0x0f); 363 } 364 365 /* Page table bitfield declarations */ 366 #define PTE_PRESENT_MASK BIT_ULL(0) 367 #define PTE_WRITABLE_MASK BIT_ULL(1) 368 #define PTE_USER_MASK BIT_ULL(2) 369 #define PTE_ACCESSED_MASK BIT_ULL(5) 370 #define PTE_DIRTY_MASK BIT_ULL(6) 371 #define PTE_LARGE_MASK BIT_ULL(7) 372 #define PTE_GLOBAL_MASK BIT_ULL(8) 373 #define PTE_NX_MASK BIT_ULL(63) 374 375 #define PHYSICAL_PAGE_MASK GENMASK_ULL(51, 12) 376 377 #define PAGE_SHIFT 12 378 #define PAGE_SIZE (1ULL << PAGE_SHIFT) 379 #define PAGE_MASK (~(PAGE_SIZE-1) & PHYSICAL_PAGE_MASK) 380 381 #define HUGEPAGE_SHIFT(x) (PAGE_SHIFT + (((x) - 1) * 9)) 382 #define HUGEPAGE_SIZE(x) (1UL << HUGEPAGE_SHIFT(x)) 383 #define HUGEPAGE_MASK(x) (~(HUGEPAGE_SIZE(x) - 1) & PHYSICAL_PAGE_MASK) 384 385 #define PTE_GET_PA(pte) ((pte) & PHYSICAL_PAGE_MASK) 386 #define PTE_GET_PFN(pte) (PTE_GET_PA(pte) >> PAGE_SHIFT) 387 388 /* General Registers in 64-Bit Mode */ 389 struct gpr64_regs { 390 u64 rax; 391 u64 rcx; 392 u64 rdx; 393 u64 rbx; 394 u64 rsp; 395 u64 rbp; 396 u64 rsi; 397 u64 rdi; 398 u64 r8; 399 u64 r9; 400 u64 r10; 401 u64 r11; 402 u64 r12; 403 u64 r13; 404 u64 r14; 405 u64 r15; 406 }; 407 408 struct desc64 { 409 uint16_t limit0; 410 uint16_t base0; 411 unsigned base1:8, type:4, s:1, dpl:2, p:1; 412 unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8; 413 uint32_t base3; 414 uint32_t zero1; 415 } __attribute__((packed)); 416 417 struct desc_ptr { 418 uint16_t size; 419 uint64_t address; 420 } __attribute__((packed)); 421 422 struct kvm_x86_state { 423 struct kvm_xsave *xsave; 424 struct kvm_vcpu_events events; 425 struct kvm_mp_state mp_state; 426 struct kvm_regs regs; 427 struct kvm_xcrs xcrs; 428 struct kvm_sregs sregs; 429 struct kvm_debugregs debugregs; 430 union { 431 struct kvm_nested_state nested; 432 char nested_[16384]; 433 }; 434 struct kvm_msrs msrs; 435 }; 436 437 static inline uint64_t get_desc64_base(const struct desc64 *desc) 438 { 439 return (uint64_t)desc->base3 << 32 | 440 (uint64_t)desc->base2 << 24 | 441 (uint64_t)desc->base1 << 16 | 442 (uint64_t)desc->base0; 443 } 444 445 static inline uint64_t rdtsc(void) 446 { 447 uint32_t eax, edx; 448 uint64_t tsc_val; 449 /* 450 * The lfence is to wait (on Intel CPUs) until all previous 451 * instructions have been executed. If software requires RDTSC to be 452 * executed prior to execution of any subsequent instruction, it can 453 * execute LFENCE immediately after RDTSC 454 */ 455 __asm__ __volatile__("lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx)); 456 tsc_val = ((uint64_t)edx) << 32 | eax; 457 return tsc_val; 458 } 459 460 static inline uint64_t rdtscp(uint32_t *aux) 461 { 462 uint32_t eax, edx; 463 464 __asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux)); 465 return ((uint64_t)edx) << 32 | eax; 466 } 467 468 static inline uint64_t rdmsr(uint32_t msr) 469 { 470 uint32_t a, d; 471 472 __asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory"); 473 474 return a | ((uint64_t) d << 32); 475 } 476 477 static inline void wrmsr(uint32_t msr, uint64_t value) 478 { 479 uint32_t a = value; 480 uint32_t d = value >> 32; 481 482 __asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory"); 483 } 484 485 486 static inline uint16_t inw(uint16_t port) 487 { 488 uint16_t tmp; 489 490 __asm__ __volatile__("in %%dx, %%ax" 491 : /* output */ "=a" (tmp) 492 : /* input */ "d" (port)); 493 494 return tmp; 495 } 496 497 static inline uint16_t get_es(void) 498 { 499 uint16_t es; 500 501 __asm__ __volatile__("mov %%es, %[es]" 502 : /* output */ [es]"=rm"(es)); 503 return es; 504 } 505 506 static inline uint16_t get_cs(void) 507 { 508 uint16_t cs; 509 510 __asm__ __volatile__("mov %%cs, %[cs]" 511 : /* output */ [cs]"=rm"(cs)); 512 return cs; 513 } 514 515 static inline uint16_t get_ss(void) 516 { 517 uint16_t ss; 518 519 __asm__ __volatile__("mov %%ss, %[ss]" 520 : /* output */ [ss]"=rm"(ss)); 521 return ss; 522 } 523 524 static inline uint16_t get_ds(void) 525 { 526 uint16_t ds; 527 528 __asm__ __volatile__("mov %%ds, %[ds]" 529 : /* output */ [ds]"=rm"(ds)); 530 return ds; 531 } 532 533 static inline uint16_t get_fs(void) 534 { 535 uint16_t fs; 536 537 __asm__ __volatile__("mov %%fs, %[fs]" 538 : /* output */ [fs]"=rm"(fs)); 539 return fs; 540 } 541 542 static inline uint16_t get_gs(void) 543 { 544 uint16_t gs; 545 546 __asm__ __volatile__("mov %%gs, %[gs]" 547 : /* output */ [gs]"=rm"(gs)); 548 return gs; 549 } 550 551 static inline uint16_t get_tr(void) 552 { 553 uint16_t tr; 554 555 __asm__ __volatile__("str %[tr]" 556 : /* output */ [tr]"=rm"(tr)); 557 return tr; 558 } 559 560 static inline uint64_t get_cr0(void) 561 { 562 uint64_t cr0; 563 564 __asm__ __volatile__("mov %%cr0, %[cr0]" 565 : /* output */ [cr0]"=r"(cr0)); 566 return cr0; 567 } 568 569 static inline uint64_t get_cr3(void) 570 { 571 uint64_t cr3; 572 573 __asm__ __volatile__("mov %%cr3, %[cr3]" 574 : /* output */ [cr3]"=r"(cr3)); 575 return cr3; 576 } 577 578 static inline uint64_t get_cr4(void) 579 { 580 uint64_t cr4; 581 582 __asm__ __volatile__("mov %%cr4, %[cr4]" 583 : /* output */ [cr4]"=r"(cr4)); 584 return cr4; 585 } 586 587 static inline void set_cr4(uint64_t val) 588 { 589 __asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory"); 590 } 591 592 static inline void set_idt(const struct desc_ptr *idt_desc) 593 { 594 __asm__ __volatile__("lidt %0"::"m"(*idt_desc)); 595 } 596 597 static inline u64 xgetbv(u32 index) 598 { 599 u32 eax, edx; 600 601 __asm__ __volatile__("xgetbv;" 602 : "=a" (eax), "=d" (edx) 603 : "c" (index)); 604 return eax | ((u64)edx << 32); 605 } 606 607 static inline void xsetbv(u32 index, u64 value) 608 { 609 u32 eax = value; 610 u32 edx = value >> 32; 611 612 __asm__ __volatile__("xsetbv" :: "a" (eax), "d" (edx), "c" (index)); 613 } 614 615 static inline void wrpkru(u32 pkru) 616 { 617 /* Note, ECX and EDX are architecturally required to be '0'. */ 618 asm volatile(".byte 0x0f,0x01,0xef\n\t" 619 : : "a" (pkru), "c"(0), "d"(0)); 620 } 621 622 static inline struct desc_ptr get_gdt(void) 623 { 624 struct desc_ptr gdt; 625 __asm__ __volatile__("sgdt %[gdt]" 626 : /* output */ [gdt]"=m"(gdt)); 627 return gdt; 628 } 629 630 static inline struct desc_ptr get_idt(void) 631 { 632 struct desc_ptr idt; 633 __asm__ __volatile__("sidt %[idt]" 634 : /* output */ [idt]"=m"(idt)); 635 return idt; 636 } 637 638 static inline void outl(uint16_t port, uint32_t value) 639 { 640 __asm__ __volatile__("outl %%eax, %%dx" : : "d"(port), "a"(value)); 641 } 642 643 static inline void __cpuid(uint32_t function, uint32_t index, 644 uint32_t *eax, uint32_t *ebx, 645 uint32_t *ecx, uint32_t *edx) 646 { 647 *eax = function; 648 *ecx = index; 649 650 asm volatile("cpuid" 651 : "=a" (*eax), 652 "=b" (*ebx), 653 "=c" (*ecx), 654 "=d" (*edx) 655 : "0" (*eax), "2" (*ecx) 656 : "memory"); 657 } 658 659 static inline void cpuid(uint32_t function, 660 uint32_t *eax, uint32_t *ebx, 661 uint32_t *ecx, uint32_t *edx) 662 { 663 return __cpuid(function, 0, eax, ebx, ecx, edx); 664 } 665 666 static inline uint32_t this_cpu_fms(void) 667 { 668 uint32_t eax, ebx, ecx, edx; 669 670 cpuid(1, &eax, &ebx, &ecx, &edx); 671 return eax; 672 } 673 674 static inline uint32_t this_cpu_family(void) 675 { 676 return x86_family(this_cpu_fms()); 677 } 678 679 static inline uint32_t this_cpu_model(void) 680 { 681 return x86_model(this_cpu_fms()); 682 } 683 684 static inline bool this_cpu_vendor_string_is(const char *vendor) 685 { 686 const uint32_t *chunk = (const uint32_t *)vendor; 687 uint32_t eax, ebx, ecx, edx; 688 689 cpuid(0, &eax, &ebx, &ecx, &edx); 690 return (ebx == chunk[0] && edx == chunk[1] && ecx == chunk[2]); 691 } 692 693 static inline bool this_cpu_is_intel(void) 694 { 695 return this_cpu_vendor_string_is("GenuineIntel"); 696 } 697 698 /* 699 * Exclude early K5 samples with a vendor string of "AMDisbetter!" 700 */ 701 static inline bool this_cpu_is_amd(void) 702 { 703 return this_cpu_vendor_string_is("AuthenticAMD"); 704 } 705 706 static inline uint32_t __this_cpu_has(uint32_t function, uint32_t index, 707 uint8_t reg, uint8_t lo, uint8_t hi) 708 { 709 uint32_t gprs[4]; 710 711 __cpuid(function, index, 712 &gprs[KVM_CPUID_EAX], &gprs[KVM_CPUID_EBX], 713 &gprs[KVM_CPUID_ECX], &gprs[KVM_CPUID_EDX]); 714 715 return (gprs[reg] & GENMASK(hi, lo)) >> lo; 716 } 717 718 static inline bool this_cpu_has(struct kvm_x86_cpu_feature feature) 719 { 720 return __this_cpu_has(feature.function, feature.index, 721 feature.reg, feature.bit, feature.bit); 722 } 723 724 static inline uint32_t this_cpu_property(struct kvm_x86_cpu_property property) 725 { 726 return __this_cpu_has(property.function, property.index, 727 property.reg, property.lo_bit, property.hi_bit); 728 } 729 730 static __always_inline bool this_cpu_has_p(struct kvm_x86_cpu_property property) 731 { 732 uint32_t max_leaf; 733 734 switch (property.function & 0xc0000000) { 735 case 0: 736 max_leaf = this_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF); 737 break; 738 case 0x40000000: 739 max_leaf = this_cpu_property(X86_PROPERTY_MAX_KVM_LEAF); 740 break; 741 case 0x80000000: 742 max_leaf = this_cpu_property(X86_PROPERTY_MAX_EXT_LEAF); 743 break; 744 case 0xc0000000: 745 max_leaf = this_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF); 746 } 747 return max_leaf >= property.function; 748 } 749 750 static inline bool this_pmu_has(struct kvm_x86_pmu_feature feature) 751 { 752 uint32_t nr_bits; 753 754 if (feature.f.reg == KVM_CPUID_EBX) { 755 nr_bits = this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); 756 return nr_bits > feature.f.bit && !this_cpu_has(feature.f); 757 } 758 759 GUEST_ASSERT(feature.f.reg == KVM_CPUID_ECX); 760 nr_bits = this_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); 761 return nr_bits > feature.f.bit || this_cpu_has(feature.f); 762 } 763 764 static __always_inline uint64_t this_cpu_supported_xcr0(void) 765 { 766 if (!this_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) 767 return 0; 768 769 return this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | 770 ((uint64_t)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); 771 } 772 773 typedef u32 __attribute__((vector_size(16))) sse128_t; 774 #define __sse128_u union { sse128_t vec; u64 as_u64[2]; u32 as_u32[4]; } 775 #define sse128_lo(x) ({ __sse128_u t; t.vec = x; t.as_u64[0]; }) 776 #define sse128_hi(x) ({ __sse128_u t; t.vec = x; t.as_u64[1]; }) 777 778 static inline void read_sse_reg(int reg, sse128_t *data) 779 { 780 switch (reg) { 781 case 0: 782 asm("movdqa %%xmm0, %0" : "=m"(*data)); 783 break; 784 case 1: 785 asm("movdqa %%xmm1, %0" : "=m"(*data)); 786 break; 787 case 2: 788 asm("movdqa %%xmm2, %0" : "=m"(*data)); 789 break; 790 case 3: 791 asm("movdqa %%xmm3, %0" : "=m"(*data)); 792 break; 793 case 4: 794 asm("movdqa %%xmm4, %0" : "=m"(*data)); 795 break; 796 case 5: 797 asm("movdqa %%xmm5, %0" : "=m"(*data)); 798 break; 799 case 6: 800 asm("movdqa %%xmm6, %0" : "=m"(*data)); 801 break; 802 case 7: 803 asm("movdqa %%xmm7, %0" : "=m"(*data)); 804 break; 805 default: 806 BUG(); 807 } 808 } 809 810 static inline void write_sse_reg(int reg, const sse128_t *data) 811 { 812 switch (reg) { 813 case 0: 814 asm("movdqa %0, %%xmm0" : : "m"(*data)); 815 break; 816 case 1: 817 asm("movdqa %0, %%xmm1" : : "m"(*data)); 818 break; 819 case 2: 820 asm("movdqa %0, %%xmm2" : : "m"(*data)); 821 break; 822 case 3: 823 asm("movdqa %0, %%xmm3" : : "m"(*data)); 824 break; 825 case 4: 826 asm("movdqa %0, %%xmm4" : : "m"(*data)); 827 break; 828 case 5: 829 asm("movdqa %0, %%xmm5" : : "m"(*data)); 830 break; 831 case 6: 832 asm("movdqa %0, %%xmm6" : : "m"(*data)); 833 break; 834 case 7: 835 asm("movdqa %0, %%xmm7" : : "m"(*data)); 836 break; 837 default: 838 BUG(); 839 } 840 } 841 842 static inline void cpu_relax(void) 843 { 844 asm volatile("rep; nop" ::: "memory"); 845 } 846 847 static inline void udelay(unsigned long usec) 848 { 849 uint64_t start, now, cycles; 850 851 GUEST_ASSERT(guest_tsc_khz); 852 cycles = guest_tsc_khz / 1000 * usec; 853 854 /* 855 * Deliberately don't PAUSE, a.k.a. cpu_relax(), so that the delay is 856 * as accurate as possible, e.g. doesn't trigger PAUSE-Loop VM-Exits. 857 */ 858 start = rdtsc(); 859 do { 860 now = rdtsc(); 861 } while (now - start < cycles); 862 } 863 864 #define ud2() \ 865 __asm__ __volatile__( \ 866 "ud2\n" \ 867 ) 868 869 #define hlt() \ 870 __asm__ __volatile__( \ 871 "hlt\n" \ 872 ) 873 874 struct kvm_x86_state *vcpu_save_state(struct kvm_vcpu *vcpu); 875 void vcpu_load_state(struct kvm_vcpu *vcpu, struct kvm_x86_state *state); 876 void kvm_x86_state_cleanup(struct kvm_x86_state *state); 877 878 const struct kvm_msr_list *kvm_get_msr_index_list(void); 879 const struct kvm_msr_list *kvm_get_feature_msr_index_list(void); 880 bool kvm_msr_is_in_save_restore_list(uint32_t msr_index); 881 uint64_t kvm_get_feature_msr(uint64_t msr_index); 882 883 static inline void vcpu_msrs_get(struct kvm_vcpu *vcpu, 884 struct kvm_msrs *msrs) 885 { 886 int r = __vcpu_ioctl(vcpu, KVM_GET_MSRS, msrs); 887 888 TEST_ASSERT(r == msrs->nmsrs, 889 "KVM_GET_MSRS failed, r: %i (failed on MSR %x)", 890 r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index); 891 } 892 static inline void vcpu_msrs_set(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs) 893 { 894 int r = __vcpu_ioctl(vcpu, KVM_SET_MSRS, msrs); 895 896 TEST_ASSERT(r == msrs->nmsrs, 897 "KVM_SET_MSRS failed, r: %i (failed on MSR %x)", 898 r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index); 899 } 900 static inline void vcpu_debugregs_get(struct kvm_vcpu *vcpu, 901 struct kvm_debugregs *debugregs) 902 { 903 vcpu_ioctl(vcpu, KVM_GET_DEBUGREGS, debugregs); 904 } 905 static inline void vcpu_debugregs_set(struct kvm_vcpu *vcpu, 906 struct kvm_debugregs *debugregs) 907 { 908 vcpu_ioctl(vcpu, KVM_SET_DEBUGREGS, debugregs); 909 } 910 static inline void vcpu_xsave_get(struct kvm_vcpu *vcpu, 911 struct kvm_xsave *xsave) 912 { 913 vcpu_ioctl(vcpu, KVM_GET_XSAVE, xsave); 914 } 915 static inline void vcpu_xsave2_get(struct kvm_vcpu *vcpu, 916 struct kvm_xsave *xsave) 917 { 918 vcpu_ioctl(vcpu, KVM_GET_XSAVE2, xsave); 919 } 920 static inline void vcpu_xsave_set(struct kvm_vcpu *vcpu, 921 struct kvm_xsave *xsave) 922 { 923 vcpu_ioctl(vcpu, KVM_SET_XSAVE, xsave); 924 } 925 static inline void vcpu_xcrs_get(struct kvm_vcpu *vcpu, 926 struct kvm_xcrs *xcrs) 927 { 928 vcpu_ioctl(vcpu, KVM_GET_XCRS, xcrs); 929 } 930 static inline void vcpu_xcrs_set(struct kvm_vcpu *vcpu, struct kvm_xcrs *xcrs) 931 { 932 vcpu_ioctl(vcpu, KVM_SET_XCRS, xcrs); 933 } 934 935 const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid, 936 uint32_t function, uint32_t index); 937 const struct kvm_cpuid2 *kvm_get_supported_cpuid(void); 938 939 static inline uint32_t kvm_cpu_fms(void) 940 { 941 return get_cpuid_entry(kvm_get_supported_cpuid(), 0x1, 0)->eax; 942 } 943 944 static inline uint32_t kvm_cpu_family(void) 945 { 946 return x86_family(kvm_cpu_fms()); 947 } 948 949 static inline uint32_t kvm_cpu_model(void) 950 { 951 return x86_model(kvm_cpu_fms()); 952 } 953 954 bool kvm_cpuid_has(const struct kvm_cpuid2 *cpuid, 955 struct kvm_x86_cpu_feature feature); 956 957 static inline bool kvm_cpu_has(struct kvm_x86_cpu_feature feature) 958 { 959 return kvm_cpuid_has(kvm_get_supported_cpuid(), feature); 960 } 961 962 uint32_t kvm_cpuid_property(const struct kvm_cpuid2 *cpuid, 963 struct kvm_x86_cpu_property property); 964 965 static inline uint32_t kvm_cpu_property(struct kvm_x86_cpu_property property) 966 { 967 return kvm_cpuid_property(kvm_get_supported_cpuid(), property); 968 } 969 970 static __always_inline bool kvm_cpu_has_p(struct kvm_x86_cpu_property property) 971 { 972 uint32_t max_leaf; 973 974 switch (property.function & 0xc0000000) { 975 case 0: 976 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF); 977 break; 978 case 0x40000000: 979 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_KVM_LEAF); 980 break; 981 case 0x80000000: 982 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_EXT_LEAF); 983 break; 984 case 0xc0000000: 985 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF); 986 } 987 return max_leaf >= property.function; 988 } 989 990 static inline bool kvm_pmu_has(struct kvm_x86_pmu_feature feature) 991 { 992 uint32_t nr_bits; 993 994 if (feature.f.reg == KVM_CPUID_EBX) { 995 nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); 996 return nr_bits > feature.f.bit && !kvm_cpu_has(feature.f); 997 } 998 999 TEST_ASSERT_EQ(feature.f.reg, KVM_CPUID_ECX); 1000 nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); 1001 return nr_bits > feature.f.bit || kvm_cpu_has(feature.f); 1002 } 1003 1004 static __always_inline uint64_t kvm_cpu_supported_xcr0(void) 1005 { 1006 if (!kvm_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) 1007 return 0; 1008 1009 return kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | 1010 ((uint64_t)kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); 1011 } 1012 1013 static inline size_t kvm_cpuid2_size(int nr_entries) 1014 { 1015 return sizeof(struct kvm_cpuid2) + 1016 sizeof(struct kvm_cpuid_entry2) * nr_entries; 1017 } 1018 1019 /* 1020 * Allocate a "struct kvm_cpuid2* instance, with the 0-length arrary of 1021 * entries sized to hold @nr_entries. The caller is responsible for freeing 1022 * the struct. 1023 */ 1024 static inline struct kvm_cpuid2 *allocate_kvm_cpuid2(int nr_entries) 1025 { 1026 struct kvm_cpuid2 *cpuid; 1027 1028 cpuid = malloc(kvm_cpuid2_size(nr_entries)); 1029 TEST_ASSERT(cpuid, "-ENOMEM when allocating kvm_cpuid2"); 1030 1031 cpuid->nent = nr_entries; 1032 1033 return cpuid; 1034 } 1035 1036 void vcpu_init_cpuid(struct kvm_vcpu *vcpu, const struct kvm_cpuid2 *cpuid); 1037 1038 static inline void vcpu_get_cpuid(struct kvm_vcpu *vcpu) 1039 { 1040 vcpu_ioctl(vcpu, KVM_GET_CPUID2, vcpu->cpuid); 1041 } 1042 1043 static inline struct kvm_cpuid_entry2 *__vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu, 1044 uint32_t function, 1045 uint32_t index) 1046 { 1047 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first (or equivalent)"); 1048 1049 vcpu_get_cpuid(vcpu); 1050 1051 return (struct kvm_cpuid_entry2 *)get_cpuid_entry(vcpu->cpuid, 1052 function, index); 1053 } 1054 1055 static inline struct kvm_cpuid_entry2 *vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu, 1056 uint32_t function) 1057 { 1058 return __vcpu_get_cpuid_entry(vcpu, function, 0); 1059 } 1060 1061 static inline int __vcpu_set_cpuid(struct kvm_vcpu *vcpu) 1062 { 1063 int r; 1064 1065 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first"); 1066 r = __vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid); 1067 if (r) 1068 return r; 1069 1070 /* On success, refresh the cache to pick up adjustments made by KVM. */ 1071 vcpu_get_cpuid(vcpu); 1072 return 0; 1073 } 1074 1075 static inline void vcpu_set_cpuid(struct kvm_vcpu *vcpu) 1076 { 1077 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first"); 1078 vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid); 1079 1080 /* Refresh the cache to pick up adjustments made by KVM. */ 1081 vcpu_get_cpuid(vcpu); 1082 } 1083 1084 void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu, 1085 struct kvm_x86_cpu_property property, 1086 uint32_t value); 1087 void vcpu_set_cpuid_maxphyaddr(struct kvm_vcpu *vcpu, uint8_t maxphyaddr); 1088 1089 void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, uint32_t function); 1090 1091 static inline bool vcpu_cpuid_has(struct kvm_vcpu *vcpu, 1092 struct kvm_x86_cpu_feature feature) 1093 { 1094 struct kvm_cpuid_entry2 *entry; 1095 1096 entry = __vcpu_get_cpuid_entry(vcpu, feature.function, feature.index); 1097 return *((&entry->eax) + feature.reg) & BIT(feature.bit); 1098 } 1099 1100 void vcpu_set_or_clear_cpuid_feature(struct kvm_vcpu *vcpu, 1101 struct kvm_x86_cpu_feature feature, 1102 bool set); 1103 1104 static inline void vcpu_set_cpuid_feature(struct kvm_vcpu *vcpu, 1105 struct kvm_x86_cpu_feature feature) 1106 { 1107 vcpu_set_or_clear_cpuid_feature(vcpu, feature, true); 1108 1109 } 1110 1111 static inline void vcpu_clear_cpuid_feature(struct kvm_vcpu *vcpu, 1112 struct kvm_x86_cpu_feature feature) 1113 { 1114 vcpu_set_or_clear_cpuid_feature(vcpu, feature, false); 1115 } 1116 1117 uint64_t vcpu_get_msr(struct kvm_vcpu *vcpu, uint64_t msr_index); 1118 int _vcpu_set_msr(struct kvm_vcpu *vcpu, uint64_t msr_index, uint64_t msr_value); 1119 1120 /* 1121 * Assert on an MSR access(es) and pretty print the MSR name when possible. 1122 * Note, the caller provides the stringified name so that the name of macro is 1123 * printed, not the value the macro resolves to (due to macro expansion). 1124 */ 1125 #define TEST_ASSERT_MSR(cond, fmt, msr, str, args...) \ 1126 do { \ 1127 if (__builtin_constant_p(msr)) { \ 1128 TEST_ASSERT(cond, fmt, str, args); \ 1129 } else if (!(cond)) { \ 1130 char buf[16]; \ 1131 \ 1132 snprintf(buf, sizeof(buf), "MSR 0x%x", msr); \ 1133 TEST_ASSERT(cond, fmt, buf, args); \ 1134 } \ 1135 } while (0) 1136 1137 /* 1138 * Returns true if KVM should return the last written value when reading an MSR 1139 * from userspace, e.g. the MSR isn't a command MSR, doesn't emulate state that 1140 * is changing, etc. This is NOT an exhaustive list! The intent is to filter 1141 * out MSRs that are not durable _and_ that a selftest wants to write. 1142 */ 1143 static inline bool is_durable_msr(uint32_t msr) 1144 { 1145 return msr != MSR_IA32_TSC; 1146 } 1147 1148 #define vcpu_set_msr(vcpu, msr, val) \ 1149 do { \ 1150 uint64_t r, v = val; \ 1151 \ 1152 TEST_ASSERT_MSR(_vcpu_set_msr(vcpu, msr, v) == 1, \ 1153 "KVM_SET_MSRS failed on %s, value = 0x%lx", msr, #msr, v); \ 1154 if (!is_durable_msr(msr)) \ 1155 break; \ 1156 r = vcpu_get_msr(vcpu, msr); \ 1157 TEST_ASSERT_MSR(r == v, "Set %s to '0x%lx', got back '0x%lx'", msr, #msr, v, r);\ 1158 } while (0) 1159 1160 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits); 1161 void kvm_init_vm_address_properties(struct kvm_vm *vm); 1162 1163 struct ex_regs { 1164 uint64_t rax, rcx, rdx, rbx; 1165 uint64_t rbp, rsi, rdi; 1166 uint64_t r8, r9, r10, r11; 1167 uint64_t r12, r13, r14, r15; 1168 uint64_t vector; 1169 uint64_t error_code; 1170 uint64_t rip; 1171 uint64_t cs; 1172 uint64_t rflags; 1173 }; 1174 1175 struct idt_entry { 1176 uint16_t offset0; 1177 uint16_t selector; 1178 uint16_t ist : 3; 1179 uint16_t : 5; 1180 uint16_t type : 4; 1181 uint16_t : 1; 1182 uint16_t dpl : 2; 1183 uint16_t p : 1; 1184 uint16_t offset1; 1185 uint32_t offset2; uint32_t reserved; 1186 }; 1187 1188 void vm_install_exception_handler(struct kvm_vm *vm, int vector, 1189 void (*handler)(struct ex_regs *)); 1190 1191 /* 1192 * Exception fixup morphs #DE to an arbitrary magic vector so that '0' can be 1193 * used to signal "no expcetion". 1194 */ 1195 #define KVM_MAGIC_DE_VECTOR 0xff 1196 1197 /* If a toddler were to say "abracadabra". */ 1198 #define KVM_EXCEPTION_MAGIC 0xabacadabaULL 1199 1200 /* 1201 * KVM selftest exception fixup uses registers to coordinate with the exception 1202 * handler, versus the kernel's in-memory tables and KVM-Unit-Tests's in-memory 1203 * per-CPU data. Using only registers avoids having to map memory into the 1204 * guest, doesn't require a valid, stable GS.base, and reduces the risk of 1205 * for recursive faults when accessing memory in the handler. The downside to 1206 * using registers is that it restricts what registers can be used by the actual 1207 * instruction. But, selftests are 64-bit only, making register* pressure a 1208 * minor concern. Use r9-r11 as they are volatile, i.e. don't need to be saved 1209 * by the callee, and except for r11 are not implicit parameters to any 1210 * instructions. Ideally, fixup would use r8-r10 and thus avoid implicit 1211 * parameters entirely, but Hyper-V's hypercall ABI uses r8 and testing Hyper-V 1212 * is higher priority than testing non-faulting SYSCALL/SYSRET. 1213 * 1214 * Note, the fixup handler deliberately does not handle #DE, i.e. the vector 1215 * is guaranteed to be non-zero on fault. 1216 * 1217 * REGISTER INPUTS: 1218 * r9 = MAGIC 1219 * r10 = RIP 1220 * r11 = new RIP on fault 1221 * 1222 * REGISTER OUTPUTS: 1223 * r9 = exception vector (non-zero) 1224 * r10 = error code 1225 */ 1226 #define __KVM_ASM_SAFE(insn, fep) \ 1227 "mov $" __stringify(KVM_EXCEPTION_MAGIC) ", %%r9\n\t" \ 1228 "lea 1f(%%rip), %%r10\n\t" \ 1229 "lea 2f(%%rip), %%r11\n\t" \ 1230 fep "1: " insn "\n\t" \ 1231 "xor %%r9, %%r9\n\t" \ 1232 "2:\n\t" \ 1233 "mov %%r9b, %[vector]\n\t" \ 1234 "mov %%r10, %[error_code]\n\t" 1235 1236 #define KVM_ASM_SAFE(insn) __KVM_ASM_SAFE(insn, "") 1237 #define KVM_ASM_SAFE_FEP(insn) __KVM_ASM_SAFE(insn, KVM_FEP) 1238 1239 #define KVM_ASM_SAFE_OUTPUTS(v, ec) [vector] "=qm"(v), [error_code] "=rm"(ec) 1240 #define KVM_ASM_SAFE_CLOBBERS "r9", "r10", "r11" 1241 1242 #define kvm_asm_safe(insn, inputs...) \ 1243 ({ \ 1244 uint64_t ign_error_code; \ 1245 uint8_t vector; \ 1246 \ 1247 asm volatile(KVM_ASM_SAFE(insn) \ 1248 : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code) \ 1249 : inputs \ 1250 : KVM_ASM_SAFE_CLOBBERS); \ 1251 vector; \ 1252 }) 1253 1254 #define kvm_asm_safe_ec(insn, error_code, inputs...) \ 1255 ({ \ 1256 uint8_t vector; \ 1257 \ 1258 asm volatile(KVM_ASM_SAFE(insn) \ 1259 : KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1260 : inputs \ 1261 : KVM_ASM_SAFE_CLOBBERS); \ 1262 vector; \ 1263 }) 1264 1265 #define kvm_asm_safe_fep(insn, inputs...) \ 1266 ({ \ 1267 uint64_t ign_error_code; \ 1268 uint8_t vector; \ 1269 \ 1270 asm volatile(KVM_ASM_SAFE_FEP(insn) \ 1271 : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code) \ 1272 : inputs \ 1273 : KVM_ASM_SAFE_CLOBBERS); \ 1274 vector; \ 1275 }) 1276 1277 #define kvm_asm_safe_ec_fep(insn, error_code, inputs...) \ 1278 ({ \ 1279 uint8_t vector; \ 1280 \ 1281 asm volatile(KVM_ASM_SAFE_FEP(insn) \ 1282 : KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1283 : inputs \ 1284 : KVM_ASM_SAFE_CLOBBERS); \ 1285 vector; \ 1286 }) 1287 1288 #define BUILD_READ_U64_SAFE_HELPER(insn, _fep, _FEP) \ 1289 static inline uint8_t insn##_safe ##_fep(uint32_t idx, uint64_t *val) \ 1290 { \ 1291 uint64_t error_code; \ 1292 uint8_t vector; \ 1293 uint32_t a, d; \ 1294 \ 1295 asm volatile(KVM_ASM_SAFE##_FEP(#insn) \ 1296 : "=a"(a), "=d"(d), \ 1297 KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1298 : "c"(idx) \ 1299 : KVM_ASM_SAFE_CLOBBERS); \ 1300 \ 1301 *val = (uint64_t)a | ((uint64_t)d << 32); \ 1302 return vector; \ 1303 } 1304 1305 /* 1306 * Generate {insn}_safe() and {insn}_safe_fep() helpers for instructions that 1307 * use ECX as in input index, and EDX:EAX as a 64-bit output. 1308 */ 1309 #define BUILD_READ_U64_SAFE_HELPERS(insn) \ 1310 BUILD_READ_U64_SAFE_HELPER(insn, , ) \ 1311 BUILD_READ_U64_SAFE_HELPER(insn, _fep, _FEP) \ 1312 1313 BUILD_READ_U64_SAFE_HELPERS(rdmsr) 1314 BUILD_READ_U64_SAFE_HELPERS(rdpmc) 1315 BUILD_READ_U64_SAFE_HELPERS(xgetbv) 1316 1317 static inline uint8_t wrmsr_safe(uint32_t msr, uint64_t val) 1318 { 1319 return kvm_asm_safe("wrmsr", "a"(val & -1u), "d"(val >> 32), "c"(msr)); 1320 } 1321 1322 static inline uint8_t xsetbv_safe(uint32_t index, uint64_t value) 1323 { 1324 u32 eax = value; 1325 u32 edx = value >> 32; 1326 1327 return kvm_asm_safe("xsetbv", "a" (eax), "d" (edx), "c" (index)); 1328 } 1329 1330 bool kvm_is_tdp_enabled(void); 1331 1332 static inline bool get_kvm_intel_param_bool(const char *param) 1333 { 1334 return kvm_get_module_param_bool("kvm_intel", param); 1335 } 1336 1337 static inline bool get_kvm_amd_param_bool(const char *param) 1338 { 1339 return kvm_get_module_param_bool("kvm_amd", param); 1340 } 1341 1342 static inline int get_kvm_intel_param_integer(const char *param) 1343 { 1344 return kvm_get_module_param_integer("kvm_intel", param); 1345 } 1346 1347 static inline int get_kvm_amd_param_integer(const char *param) 1348 { 1349 return kvm_get_module_param_integer("kvm_amd", param); 1350 } 1351 1352 static inline bool kvm_is_pmu_enabled(void) 1353 { 1354 return get_kvm_param_bool("enable_pmu"); 1355 } 1356 1357 static inline bool kvm_is_forced_emulation_enabled(void) 1358 { 1359 return !!get_kvm_param_integer("force_emulation_prefix"); 1360 } 1361 1362 static inline bool kvm_is_unrestricted_guest_enabled(void) 1363 { 1364 return get_kvm_intel_param_bool("unrestricted_guest"); 1365 } 1366 1367 static inline bool kvm_is_ignore_msrs(void) 1368 { 1369 return get_kvm_param_bool("ignore_msrs"); 1370 } 1371 1372 uint64_t *vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr); 1373 1374 uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2, 1375 uint64_t a3); 1376 uint64_t __xen_hypercall(uint64_t nr, uint64_t a0, void *a1); 1377 void xen_hypercall(uint64_t nr, uint64_t a0, void *a1); 1378 1379 static inline uint64_t __kvm_hypercall_map_gpa_range(uint64_t gpa, 1380 uint64_t size, uint64_t flags) 1381 { 1382 return kvm_hypercall(KVM_HC_MAP_GPA_RANGE, gpa, size >> PAGE_SHIFT, flags, 0); 1383 } 1384 1385 static inline void kvm_hypercall_map_gpa_range(uint64_t gpa, uint64_t size, 1386 uint64_t flags) 1387 { 1388 uint64_t ret = __kvm_hypercall_map_gpa_range(gpa, size, flags); 1389 1390 GUEST_ASSERT(!ret); 1391 } 1392 1393 /* 1394 * Execute HLT in an STI interrupt shadow to ensure that a pending IRQ that's 1395 * intended to be a wake event arrives *after* HLT is executed. Modern CPUs, 1396 * except for a few oddballs that KVM is unlikely to run on, block IRQs for one 1397 * instruction after STI, *if* RFLAGS.IF=0 before STI. Note, Intel CPUs may 1398 * block other events beyond regular IRQs, e.g. may block NMIs and SMIs too. 1399 */ 1400 static inline void safe_halt(void) 1401 { 1402 asm volatile("sti; hlt"); 1403 } 1404 1405 /* 1406 * Enable interrupts and ensure that interrupts are evaluated upon return from 1407 * this function, i.e. execute a nop to consume the STi interrupt shadow. 1408 */ 1409 static inline void sti_nop(void) 1410 { 1411 asm volatile ("sti; nop"); 1412 } 1413 1414 /* 1415 * Enable interrupts for one instruction (nop), to allow the CPU to process all 1416 * interrupts that are already pending. 1417 */ 1418 static inline void sti_nop_cli(void) 1419 { 1420 asm volatile ("sti; nop; cli"); 1421 } 1422 1423 static inline void sti(void) 1424 { 1425 asm volatile("sti"); 1426 } 1427 1428 static inline void cli(void) 1429 { 1430 asm volatile ("cli"); 1431 } 1432 1433 void __vm_xsave_require_permission(uint64_t xfeature, const char *name); 1434 1435 #define vm_xsave_require_permission(xfeature) \ 1436 __vm_xsave_require_permission(xfeature, #xfeature) 1437 1438 enum pg_level { 1439 PG_LEVEL_NONE, 1440 PG_LEVEL_4K, 1441 PG_LEVEL_2M, 1442 PG_LEVEL_1G, 1443 PG_LEVEL_512G, 1444 PG_LEVEL_256T 1445 }; 1446 1447 #define PG_LEVEL_SHIFT(_level) ((_level - 1) * 9 + 12) 1448 #define PG_LEVEL_SIZE(_level) (1ull << PG_LEVEL_SHIFT(_level)) 1449 1450 #define PG_SIZE_4K PG_LEVEL_SIZE(PG_LEVEL_4K) 1451 #define PG_SIZE_2M PG_LEVEL_SIZE(PG_LEVEL_2M) 1452 #define PG_SIZE_1G PG_LEVEL_SIZE(PG_LEVEL_1G) 1453 1454 void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, int level); 1455 void virt_map_level(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, 1456 uint64_t nr_bytes, int level); 1457 1458 /* 1459 * Basic CPU control in CR0 1460 */ 1461 #define X86_CR0_PE (1UL<<0) /* Protection Enable */ 1462 #define X86_CR0_MP (1UL<<1) /* Monitor Coprocessor */ 1463 #define X86_CR0_EM (1UL<<2) /* Emulation */ 1464 #define X86_CR0_TS (1UL<<3) /* Task Switched */ 1465 #define X86_CR0_ET (1UL<<4) /* Extension Type */ 1466 #define X86_CR0_NE (1UL<<5) /* Numeric Error */ 1467 #define X86_CR0_WP (1UL<<16) /* Write Protect */ 1468 #define X86_CR0_AM (1UL<<18) /* Alignment Mask */ 1469 #define X86_CR0_NW (1UL<<29) /* Not Write-through */ 1470 #define X86_CR0_CD (1UL<<30) /* Cache Disable */ 1471 #define X86_CR0_PG (1UL<<31) /* Paging */ 1472 1473 #define PFERR_PRESENT_BIT 0 1474 #define PFERR_WRITE_BIT 1 1475 #define PFERR_USER_BIT 2 1476 #define PFERR_RSVD_BIT 3 1477 #define PFERR_FETCH_BIT 4 1478 #define PFERR_PK_BIT 5 1479 #define PFERR_SGX_BIT 15 1480 #define PFERR_GUEST_FINAL_BIT 32 1481 #define PFERR_GUEST_PAGE_BIT 33 1482 #define PFERR_IMPLICIT_ACCESS_BIT 48 1483 1484 #define PFERR_PRESENT_MASK BIT(PFERR_PRESENT_BIT) 1485 #define PFERR_WRITE_MASK BIT(PFERR_WRITE_BIT) 1486 #define PFERR_USER_MASK BIT(PFERR_USER_BIT) 1487 #define PFERR_RSVD_MASK BIT(PFERR_RSVD_BIT) 1488 #define PFERR_FETCH_MASK BIT(PFERR_FETCH_BIT) 1489 #define PFERR_PK_MASK BIT(PFERR_PK_BIT) 1490 #define PFERR_SGX_MASK BIT(PFERR_SGX_BIT) 1491 #define PFERR_GUEST_FINAL_MASK BIT_ULL(PFERR_GUEST_FINAL_BIT) 1492 #define PFERR_GUEST_PAGE_MASK BIT_ULL(PFERR_GUEST_PAGE_BIT) 1493 #define PFERR_IMPLICIT_ACCESS BIT_ULL(PFERR_IMPLICIT_ACCESS_BIT) 1494 1495 bool sys_clocksource_is_based_on_tsc(void); 1496 1497 #endif /* SELFTEST_KVM_PROCESSOR_H */ 1498