1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2018, Google LLC. 4 */ 5 6 #ifndef SELFTEST_KVM_PROCESSOR_H 7 #define SELFTEST_KVM_PROCESSOR_H 8 9 #include <assert.h> 10 #include <stdint.h> 11 #include <syscall.h> 12 13 #include <asm/msr-index.h> 14 #include <asm/prctl.h> 15 16 #include <linux/kvm_para.h> 17 #include <linux/stringify.h> 18 19 #include "kvm_util.h" 20 #include "ucall_common.h" 21 22 extern bool host_cpu_is_intel; 23 extern bool host_cpu_is_amd; 24 extern uint64_t guest_tsc_khz; 25 26 #ifndef MAX_NR_CPUID_ENTRIES 27 #define MAX_NR_CPUID_ENTRIES 100 28 #endif 29 30 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 31 32 /* Forced emulation prefix, used to invoke the emulator unconditionally. */ 33 #define KVM_FEP "ud2; .byte 'k', 'v', 'm';" 34 35 #define NMI_VECTOR 0x02 36 37 #define X86_EFLAGS_FIXED (1u << 1) 38 39 #define X86_CR4_VME (1ul << 0) 40 #define X86_CR4_PVI (1ul << 1) 41 #define X86_CR4_TSD (1ul << 2) 42 #define X86_CR4_DE (1ul << 3) 43 #define X86_CR4_PSE (1ul << 4) 44 #define X86_CR4_PAE (1ul << 5) 45 #define X86_CR4_MCE (1ul << 6) 46 #define X86_CR4_PGE (1ul << 7) 47 #define X86_CR4_PCE (1ul << 8) 48 #define X86_CR4_OSFXSR (1ul << 9) 49 #define X86_CR4_OSXMMEXCPT (1ul << 10) 50 #define X86_CR4_UMIP (1ul << 11) 51 #define X86_CR4_LA57 (1ul << 12) 52 #define X86_CR4_VMXE (1ul << 13) 53 #define X86_CR4_SMXE (1ul << 14) 54 #define X86_CR4_FSGSBASE (1ul << 16) 55 #define X86_CR4_PCIDE (1ul << 17) 56 #define X86_CR4_OSXSAVE (1ul << 18) 57 #define X86_CR4_SMEP (1ul << 20) 58 #define X86_CR4_SMAP (1ul << 21) 59 #define X86_CR4_PKE (1ul << 22) 60 61 struct xstate_header { 62 u64 xstate_bv; 63 u64 xcomp_bv; 64 u64 reserved[6]; 65 } __attribute__((packed)); 66 67 struct xstate { 68 u8 i387[512]; 69 struct xstate_header header; 70 u8 extended_state_area[0]; 71 } __attribute__ ((packed, aligned (64))); 72 73 #define XFEATURE_MASK_FP BIT_ULL(0) 74 #define XFEATURE_MASK_SSE BIT_ULL(1) 75 #define XFEATURE_MASK_YMM BIT_ULL(2) 76 #define XFEATURE_MASK_BNDREGS BIT_ULL(3) 77 #define XFEATURE_MASK_BNDCSR BIT_ULL(4) 78 #define XFEATURE_MASK_OPMASK BIT_ULL(5) 79 #define XFEATURE_MASK_ZMM_Hi256 BIT_ULL(6) 80 #define XFEATURE_MASK_Hi16_ZMM BIT_ULL(7) 81 #define XFEATURE_MASK_PT BIT_ULL(8) 82 #define XFEATURE_MASK_PKRU BIT_ULL(9) 83 #define XFEATURE_MASK_PASID BIT_ULL(10) 84 #define XFEATURE_MASK_CET_USER BIT_ULL(11) 85 #define XFEATURE_MASK_CET_KERNEL BIT_ULL(12) 86 #define XFEATURE_MASK_LBR BIT_ULL(15) 87 #define XFEATURE_MASK_XTILE_CFG BIT_ULL(17) 88 #define XFEATURE_MASK_XTILE_DATA BIT_ULL(18) 89 90 #define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK | \ 91 XFEATURE_MASK_ZMM_Hi256 | \ 92 XFEATURE_MASK_Hi16_ZMM) 93 #define XFEATURE_MASK_XTILE (XFEATURE_MASK_XTILE_DATA | \ 94 XFEATURE_MASK_XTILE_CFG) 95 96 /* Note, these are ordered alphabetically to match kvm_cpuid_entry2. Eww. */ 97 enum cpuid_output_regs { 98 KVM_CPUID_EAX, 99 KVM_CPUID_EBX, 100 KVM_CPUID_ECX, 101 KVM_CPUID_EDX 102 }; 103 104 /* 105 * Pack the information into a 64-bit value so that each X86_FEATURE_XXX can be 106 * passed by value with no overhead. 107 */ 108 struct kvm_x86_cpu_feature { 109 u32 function; 110 u16 index; 111 u8 reg; 112 u8 bit; 113 }; 114 #define KVM_X86_CPU_FEATURE(fn, idx, gpr, __bit) \ 115 ({ \ 116 struct kvm_x86_cpu_feature feature = { \ 117 .function = fn, \ 118 .index = idx, \ 119 .reg = KVM_CPUID_##gpr, \ 120 .bit = __bit, \ 121 }; \ 122 \ 123 kvm_static_assert((fn & 0xc0000000) == 0 || \ 124 (fn & 0xc0000000) == 0x40000000 || \ 125 (fn & 0xc0000000) == 0x80000000 || \ 126 (fn & 0xc0000000) == 0xc0000000); \ 127 kvm_static_assert(idx < BIT(sizeof(feature.index) * BITS_PER_BYTE)); \ 128 feature; \ 129 }) 130 131 /* 132 * Basic Leafs, a.k.a. Intel defined 133 */ 134 #define X86_FEATURE_MWAIT KVM_X86_CPU_FEATURE(0x1, 0, ECX, 3) 135 #define X86_FEATURE_VMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 5) 136 #define X86_FEATURE_SMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 6) 137 #define X86_FEATURE_PDCM KVM_X86_CPU_FEATURE(0x1, 0, ECX, 15) 138 #define X86_FEATURE_PCID KVM_X86_CPU_FEATURE(0x1, 0, ECX, 17) 139 #define X86_FEATURE_X2APIC KVM_X86_CPU_FEATURE(0x1, 0, ECX, 21) 140 #define X86_FEATURE_MOVBE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 22) 141 #define X86_FEATURE_TSC_DEADLINE_TIMER KVM_X86_CPU_FEATURE(0x1, 0, ECX, 24) 142 #define X86_FEATURE_XSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 26) 143 #define X86_FEATURE_OSXSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 27) 144 #define X86_FEATURE_RDRAND KVM_X86_CPU_FEATURE(0x1, 0, ECX, 30) 145 #define X86_FEATURE_HYPERVISOR KVM_X86_CPU_FEATURE(0x1, 0, ECX, 31) 146 #define X86_FEATURE_PAE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 6) 147 #define X86_FEATURE_MCE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 7) 148 #define X86_FEATURE_APIC KVM_X86_CPU_FEATURE(0x1, 0, EDX, 9) 149 #define X86_FEATURE_CLFLUSH KVM_X86_CPU_FEATURE(0x1, 0, EDX, 19) 150 #define X86_FEATURE_XMM KVM_X86_CPU_FEATURE(0x1, 0, EDX, 25) 151 #define X86_FEATURE_XMM2 KVM_X86_CPU_FEATURE(0x1, 0, EDX, 26) 152 #define X86_FEATURE_FSGSBASE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 0) 153 #define X86_FEATURE_TSC_ADJUST KVM_X86_CPU_FEATURE(0x7, 0, EBX, 1) 154 #define X86_FEATURE_SGX KVM_X86_CPU_FEATURE(0x7, 0, EBX, 2) 155 #define X86_FEATURE_HLE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 4) 156 #define X86_FEATURE_SMEP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 7) 157 #define X86_FEATURE_INVPCID KVM_X86_CPU_FEATURE(0x7, 0, EBX, 10) 158 #define X86_FEATURE_RTM KVM_X86_CPU_FEATURE(0x7, 0, EBX, 11) 159 #define X86_FEATURE_MPX KVM_X86_CPU_FEATURE(0x7, 0, EBX, 14) 160 #define X86_FEATURE_SMAP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 20) 161 #define X86_FEATURE_PCOMMIT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 22) 162 #define X86_FEATURE_CLFLUSHOPT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 23) 163 #define X86_FEATURE_CLWB KVM_X86_CPU_FEATURE(0x7, 0, EBX, 24) 164 #define X86_FEATURE_UMIP KVM_X86_CPU_FEATURE(0x7, 0, ECX, 2) 165 #define X86_FEATURE_PKU KVM_X86_CPU_FEATURE(0x7, 0, ECX, 3) 166 #define X86_FEATURE_OSPKE KVM_X86_CPU_FEATURE(0x7, 0, ECX, 4) 167 #define X86_FEATURE_LA57 KVM_X86_CPU_FEATURE(0x7, 0, ECX, 16) 168 #define X86_FEATURE_RDPID KVM_X86_CPU_FEATURE(0x7, 0, ECX, 22) 169 #define X86_FEATURE_SGX_LC KVM_X86_CPU_FEATURE(0x7, 0, ECX, 30) 170 #define X86_FEATURE_SHSTK KVM_X86_CPU_FEATURE(0x7, 0, ECX, 7) 171 #define X86_FEATURE_IBT KVM_X86_CPU_FEATURE(0x7, 0, EDX, 20) 172 #define X86_FEATURE_AMX_TILE KVM_X86_CPU_FEATURE(0x7, 0, EDX, 24) 173 #define X86_FEATURE_SPEC_CTRL KVM_X86_CPU_FEATURE(0x7, 0, EDX, 26) 174 #define X86_FEATURE_ARCH_CAPABILITIES KVM_X86_CPU_FEATURE(0x7, 0, EDX, 29) 175 #define X86_FEATURE_PKS KVM_X86_CPU_FEATURE(0x7, 0, ECX, 31) 176 #define X86_FEATURE_XTILECFG KVM_X86_CPU_FEATURE(0xD, 0, EAX, 17) 177 #define X86_FEATURE_XTILEDATA KVM_X86_CPU_FEATURE(0xD, 0, EAX, 18) 178 #define X86_FEATURE_XSAVES KVM_X86_CPU_FEATURE(0xD, 1, EAX, 3) 179 #define X86_FEATURE_XFD KVM_X86_CPU_FEATURE(0xD, 1, EAX, 4) 180 #define X86_FEATURE_XTILEDATA_XFD KVM_X86_CPU_FEATURE(0xD, 18, ECX, 2) 181 182 /* 183 * Extended Leafs, a.k.a. AMD defined 184 */ 185 #define X86_FEATURE_SVM KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 2) 186 #define X86_FEATURE_NX KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 20) 187 #define X86_FEATURE_GBPAGES KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 26) 188 #define X86_FEATURE_RDTSCP KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 27) 189 #define X86_FEATURE_LM KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 29) 190 #define X86_FEATURE_INVTSC KVM_X86_CPU_FEATURE(0x80000007, 0, EDX, 8) 191 #define X86_FEATURE_RDPRU KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 4) 192 #define X86_FEATURE_AMD_IBPB KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 12) 193 #define X86_FEATURE_NPT KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 0) 194 #define X86_FEATURE_LBRV KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 1) 195 #define X86_FEATURE_NRIPS KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 3) 196 #define X86_FEATURE_TSCRATEMSR KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 4) 197 #define X86_FEATURE_PAUSEFILTER KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 10) 198 #define X86_FEATURE_PFTHRESHOLD KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 12) 199 #define X86_FEATURE_VGIF KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 16) 200 #define X86_FEATURE_IDLE_HLT KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 30) 201 #define X86_FEATURE_SEV KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 1) 202 #define X86_FEATURE_SEV_ES KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 3) 203 204 /* 205 * KVM defined paravirt features. 206 */ 207 #define X86_FEATURE_KVM_CLOCKSOURCE KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 0) 208 #define X86_FEATURE_KVM_NOP_IO_DELAY KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 1) 209 #define X86_FEATURE_KVM_MMU_OP KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 2) 210 #define X86_FEATURE_KVM_CLOCKSOURCE2 KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 3) 211 #define X86_FEATURE_KVM_ASYNC_PF KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 4) 212 #define X86_FEATURE_KVM_STEAL_TIME KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 5) 213 #define X86_FEATURE_KVM_PV_EOI KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 6) 214 #define X86_FEATURE_KVM_PV_UNHALT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 7) 215 /* Bit 8 apparently isn't used?!?! */ 216 #define X86_FEATURE_KVM_PV_TLB_FLUSH KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 9) 217 #define X86_FEATURE_KVM_ASYNC_PF_VMEXIT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 10) 218 #define X86_FEATURE_KVM_PV_SEND_IPI KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 11) 219 #define X86_FEATURE_KVM_POLL_CONTROL KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 12) 220 #define X86_FEATURE_KVM_PV_SCHED_YIELD KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 13) 221 #define X86_FEATURE_KVM_ASYNC_PF_INT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 14) 222 #define X86_FEATURE_KVM_MSI_EXT_DEST_ID KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 15) 223 #define X86_FEATURE_KVM_HC_MAP_GPA_RANGE KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 16) 224 #define X86_FEATURE_KVM_MIGRATION_CONTROL KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 17) 225 226 /* 227 * Same idea as X86_FEATURE_XXX, but X86_PROPERTY_XXX retrieves a multi-bit 228 * value/property as opposed to a single-bit feature. Again, pack the info 229 * into a 64-bit value to pass by value with no overhead. 230 */ 231 struct kvm_x86_cpu_property { 232 u32 function; 233 u8 index; 234 u8 reg; 235 u8 lo_bit; 236 u8 hi_bit; 237 }; 238 #define KVM_X86_CPU_PROPERTY(fn, idx, gpr, low_bit, high_bit) \ 239 ({ \ 240 struct kvm_x86_cpu_property property = { \ 241 .function = fn, \ 242 .index = idx, \ 243 .reg = KVM_CPUID_##gpr, \ 244 .lo_bit = low_bit, \ 245 .hi_bit = high_bit, \ 246 }; \ 247 \ 248 kvm_static_assert(low_bit < high_bit); \ 249 kvm_static_assert((fn & 0xc0000000) == 0 || \ 250 (fn & 0xc0000000) == 0x40000000 || \ 251 (fn & 0xc0000000) == 0x80000000 || \ 252 (fn & 0xc0000000) == 0xc0000000); \ 253 kvm_static_assert(idx < BIT(sizeof(property.index) * BITS_PER_BYTE)); \ 254 property; \ 255 }) 256 257 #define X86_PROPERTY_MAX_BASIC_LEAF KVM_X86_CPU_PROPERTY(0, 0, EAX, 0, 31) 258 #define X86_PROPERTY_PMU_VERSION KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 0, 7) 259 #define X86_PROPERTY_PMU_NR_GP_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 8, 15) 260 #define X86_PROPERTY_PMU_GP_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 16, 23) 261 #define X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 24, 31) 262 #define X86_PROPERTY_PMU_EVENTS_MASK KVM_X86_CPU_PROPERTY(0xa, 0, EBX, 0, 7) 263 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK KVM_X86_CPU_PROPERTY(0xa, 0, ECX, 0, 31) 264 #define X86_PROPERTY_PMU_NR_FIXED_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EDX, 0, 4) 265 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0, EDX, 5, 12) 266 267 #define X86_PROPERTY_SUPPORTED_XCR0_LO KVM_X86_CPU_PROPERTY(0xd, 0, EAX, 0, 31) 268 #define X86_PROPERTY_XSTATE_MAX_SIZE_XCR0 KVM_X86_CPU_PROPERTY(0xd, 0, EBX, 0, 31) 269 #define X86_PROPERTY_XSTATE_MAX_SIZE KVM_X86_CPU_PROPERTY(0xd, 0, ECX, 0, 31) 270 #define X86_PROPERTY_SUPPORTED_XCR0_HI KVM_X86_CPU_PROPERTY(0xd, 0, EDX, 0, 31) 271 272 #define X86_PROPERTY_XSTATE_TILE_SIZE KVM_X86_CPU_PROPERTY(0xd, 18, EAX, 0, 31) 273 #define X86_PROPERTY_XSTATE_TILE_OFFSET KVM_X86_CPU_PROPERTY(0xd, 18, EBX, 0, 31) 274 #define X86_PROPERTY_AMX_MAX_PALETTE_TABLES KVM_X86_CPU_PROPERTY(0x1d, 0, EAX, 0, 31) 275 #define X86_PROPERTY_AMX_TOTAL_TILE_BYTES KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 0, 15) 276 #define X86_PROPERTY_AMX_BYTES_PER_TILE KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 16, 31) 277 #define X86_PROPERTY_AMX_BYTES_PER_ROW KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 0, 15) 278 #define X86_PROPERTY_AMX_NR_TILE_REGS KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 16, 31) 279 #define X86_PROPERTY_AMX_MAX_ROWS KVM_X86_CPU_PROPERTY(0x1d, 1, ECX, 0, 15) 280 281 #define X86_PROPERTY_MAX_KVM_LEAF KVM_X86_CPU_PROPERTY(0x40000000, 0, EAX, 0, 31) 282 283 #define X86_PROPERTY_MAX_EXT_LEAF KVM_X86_CPU_PROPERTY(0x80000000, 0, EAX, 0, 31) 284 #define X86_PROPERTY_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 0, 7) 285 #define X86_PROPERTY_MAX_VIRT_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 8, 15) 286 #define X86_PROPERTY_GUEST_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 16, 23) 287 #define X86_PROPERTY_SEV_C_BIT KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 0, 5) 288 #define X86_PROPERTY_PHYS_ADDR_REDUCTION KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 6, 11) 289 290 #define X86_PROPERTY_MAX_CENTAUR_LEAF KVM_X86_CPU_PROPERTY(0xC0000000, 0, EAX, 0, 31) 291 292 /* 293 * Intel's architectural PMU events are bizarre. They have a "feature" bit 294 * that indicates the feature is _not_ supported, and a property that states 295 * the length of the bit mask of unsupported features. A feature is supported 296 * if the size of the bit mask is larger than the "unavailable" bit, and said 297 * bit is not set. Fixed counters also bizarre enumeration, but inverted from 298 * arch events for general purpose counters. Fixed counters are supported if a 299 * feature flag is set **OR** the total number of fixed counters is greater 300 * than index of the counter. 301 * 302 * Wrap the events for general purpose and fixed counters to simplify checking 303 * whether or not a given architectural event is supported. 304 */ 305 struct kvm_x86_pmu_feature { 306 struct kvm_x86_cpu_feature f; 307 }; 308 #define KVM_X86_PMU_FEATURE(__reg, __bit) \ 309 ({ \ 310 struct kvm_x86_pmu_feature feature = { \ 311 .f = KVM_X86_CPU_FEATURE(0xa, 0, __reg, __bit), \ 312 }; \ 313 \ 314 kvm_static_assert(KVM_CPUID_##__reg == KVM_CPUID_EBX || \ 315 KVM_CPUID_##__reg == KVM_CPUID_ECX); \ 316 feature; \ 317 }) 318 319 #define X86_PMU_FEATURE_CPU_CYCLES KVM_X86_PMU_FEATURE(EBX, 0) 320 #define X86_PMU_FEATURE_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 1) 321 #define X86_PMU_FEATURE_REFERENCE_CYCLES KVM_X86_PMU_FEATURE(EBX, 2) 322 #define X86_PMU_FEATURE_LLC_REFERENCES KVM_X86_PMU_FEATURE(EBX, 3) 323 #define X86_PMU_FEATURE_LLC_MISSES KVM_X86_PMU_FEATURE(EBX, 4) 324 #define X86_PMU_FEATURE_BRANCH_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 5) 325 #define X86_PMU_FEATURE_BRANCHES_MISPREDICTED KVM_X86_PMU_FEATURE(EBX, 6) 326 #define X86_PMU_FEATURE_TOPDOWN_SLOTS KVM_X86_PMU_FEATURE(EBX, 7) 327 328 #define X86_PMU_FEATURE_INSNS_RETIRED_FIXED KVM_X86_PMU_FEATURE(ECX, 0) 329 #define X86_PMU_FEATURE_CPU_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX, 1) 330 #define X86_PMU_FEATURE_REFERENCE_TSC_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX, 2) 331 #define X86_PMU_FEATURE_TOPDOWN_SLOTS_FIXED KVM_X86_PMU_FEATURE(ECX, 3) 332 333 static inline unsigned int x86_family(unsigned int eax) 334 { 335 unsigned int x86; 336 337 x86 = (eax >> 8) & 0xf; 338 339 if (x86 == 0xf) 340 x86 += (eax >> 20) & 0xff; 341 342 return x86; 343 } 344 345 static inline unsigned int x86_model(unsigned int eax) 346 { 347 return ((eax >> 12) & 0xf0) | ((eax >> 4) & 0x0f); 348 } 349 350 /* Page table bitfield declarations */ 351 #define PTE_PRESENT_MASK BIT_ULL(0) 352 #define PTE_WRITABLE_MASK BIT_ULL(1) 353 #define PTE_USER_MASK BIT_ULL(2) 354 #define PTE_ACCESSED_MASK BIT_ULL(5) 355 #define PTE_DIRTY_MASK BIT_ULL(6) 356 #define PTE_LARGE_MASK BIT_ULL(7) 357 #define PTE_GLOBAL_MASK BIT_ULL(8) 358 #define PTE_NX_MASK BIT_ULL(63) 359 360 #define PHYSICAL_PAGE_MASK GENMASK_ULL(51, 12) 361 362 #define PAGE_SHIFT 12 363 #define PAGE_SIZE (1ULL << PAGE_SHIFT) 364 #define PAGE_MASK (~(PAGE_SIZE-1) & PHYSICAL_PAGE_MASK) 365 366 #define HUGEPAGE_SHIFT(x) (PAGE_SHIFT + (((x) - 1) * 9)) 367 #define HUGEPAGE_SIZE(x) (1UL << HUGEPAGE_SHIFT(x)) 368 #define HUGEPAGE_MASK(x) (~(HUGEPAGE_SIZE(x) - 1) & PHYSICAL_PAGE_MASK) 369 370 #define PTE_GET_PA(pte) ((pte) & PHYSICAL_PAGE_MASK) 371 #define PTE_GET_PFN(pte) (PTE_GET_PA(pte) >> PAGE_SHIFT) 372 373 /* General Registers in 64-Bit Mode */ 374 struct gpr64_regs { 375 u64 rax; 376 u64 rcx; 377 u64 rdx; 378 u64 rbx; 379 u64 rsp; 380 u64 rbp; 381 u64 rsi; 382 u64 rdi; 383 u64 r8; 384 u64 r9; 385 u64 r10; 386 u64 r11; 387 u64 r12; 388 u64 r13; 389 u64 r14; 390 u64 r15; 391 }; 392 393 struct desc64 { 394 uint16_t limit0; 395 uint16_t base0; 396 unsigned base1:8, type:4, s:1, dpl:2, p:1; 397 unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8; 398 uint32_t base3; 399 uint32_t zero1; 400 } __attribute__((packed)); 401 402 struct desc_ptr { 403 uint16_t size; 404 uint64_t address; 405 } __attribute__((packed)); 406 407 struct kvm_x86_state { 408 struct kvm_xsave *xsave; 409 struct kvm_vcpu_events events; 410 struct kvm_mp_state mp_state; 411 struct kvm_regs regs; 412 struct kvm_xcrs xcrs; 413 struct kvm_sregs sregs; 414 struct kvm_debugregs debugregs; 415 union { 416 struct kvm_nested_state nested; 417 char nested_[16384]; 418 }; 419 struct kvm_msrs msrs; 420 }; 421 422 static inline uint64_t get_desc64_base(const struct desc64 *desc) 423 { 424 return ((uint64_t)desc->base3 << 32) | 425 (desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24)); 426 } 427 428 static inline uint64_t rdtsc(void) 429 { 430 uint32_t eax, edx; 431 uint64_t tsc_val; 432 /* 433 * The lfence is to wait (on Intel CPUs) until all previous 434 * instructions have been executed. If software requires RDTSC to be 435 * executed prior to execution of any subsequent instruction, it can 436 * execute LFENCE immediately after RDTSC 437 */ 438 __asm__ __volatile__("lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx)); 439 tsc_val = ((uint64_t)edx) << 32 | eax; 440 return tsc_val; 441 } 442 443 static inline uint64_t rdtscp(uint32_t *aux) 444 { 445 uint32_t eax, edx; 446 447 __asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux)); 448 return ((uint64_t)edx) << 32 | eax; 449 } 450 451 static inline uint64_t rdmsr(uint32_t msr) 452 { 453 uint32_t a, d; 454 455 __asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory"); 456 457 return a | ((uint64_t) d << 32); 458 } 459 460 static inline void wrmsr(uint32_t msr, uint64_t value) 461 { 462 uint32_t a = value; 463 uint32_t d = value >> 32; 464 465 __asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory"); 466 } 467 468 469 static inline uint16_t inw(uint16_t port) 470 { 471 uint16_t tmp; 472 473 __asm__ __volatile__("in %%dx, %%ax" 474 : /* output */ "=a" (tmp) 475 : /* input */ "d" (port)); 476 477 return tmp; 478 } 479 480 static inline uint16_t get_es(void) 481 { 482 uint16_t es; 483 484 __asm__ __volatile__("mov %%es, %[es]" 485 : /* output */ [es]"=rm"(es)); 486 return es; 487 } 488 489 static inline uint16_t get_cs(void) 490 { 491 uint16_t cs; 492 493 __asm__ __volatile__("mov %%cs, %[cs]" 494 : /* output */ [cs]"=rm"(cs)); 495 return cs; 496 } 497 498 static inline uint16_t get_ss(void) 499 { 500 uint16_t ss; 501 502 __asm__ __volatile__("mov %%ss, %[ss]" 503 : /* output */ [ss]"=rm"(ss)); 504 return ss; 505 } 506 507 static inline uint16_t get_ds(void) 508 { 509 uint16_t ds; 510 511 __asm__ __volatile__("mov %%ds, %[ds]" 512 : /* output */ [ds]"=rm"(ds)); 513 return ds; 514 } 515 516 static inline uint16_t get_fs(void) 517 { 518 uint16_t fs; 519 520 __asm__ __volatile__("mov %%fs, %[fs]" 521 : /* output */ [fs]"=rm"(fs)); 522 return fs; 523 } 524 525 static inline uint16_t get_gs(void) 526 { 527 uint16_t gs; 528 529 __asm__ __volatile__("mov %%gs, %[gs]" 530 : /* output */ [gs]"=rm"(gs)); 531 return gs; 532 } 533 534 static inline uint16_t get_tr(void) 535 { 536 uint16_t tr; 537 538 __asm__ __volatile__("str %[tr]" 539 : /* output */ [tr]"=rm"(tr)); 540 return tr; 541 } 542 543 static inline uint64_t get_cr0(void) 544 { 545 uint64_t cr0; 546 547 __asm__ __volatile__("mov %%cr0, %[cr0]" 548 : /* output */ [cr0]"=r"(cr0)); 549 return cr0; 550 } 551 552 static inline uint64_t get_cr3(void) 553 { 554 uint64_t cr3; 555 556 __asm__ __volatile__("mov %%cr3, %[cr3]" 557 : /* output */ [cr3]"=r"(cr3)); 558 return cr3; 559 } 560 561 static inline uint64_t get_cr4(void) 562 { 563 uint64_t cr4; 564 565 __asm__ __volatile__("mov %%cr4, %[cr4]" 566 : /* output */ [cr4]"=r"(cr4)); 567 return cr4; 568 } 569 570 static inline void set_cr4(uint64_t val) 571 { 572 __asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory"); 573 } 574 575 static inline void set_idt(const struct desc_ptr *idt_desc) 576 { 577 __asm__ __volatile__("lidt %0"::"m"(*idt_desc)); 578 } 579 580 static inline u64 xgetbv(u32 index) 581 { 582 u32 eax, edx; 583 584 __asm__ __volatile__("xgetbv;" 585 : "=a" (eax), "=d" (edx) 586 : "c" (index)); 587 return eax | ((u64)edx << 32); 588 } 589 590 static inline void xsetbv(u32 index, u64 value) 591 { 592 u32 eax = value; 593 u32 edx = value >> 32; 594 595 __asm__ __volatile__("xsetbv" :: "a" (eax), "d" (edx), "c" (index)); 596 } 597 598 static inline void wrpkru(u32 pkru) 599 { 600 /* Note, ECX and EDX are architecturally required to be '0'. */ 601 asm volatile(".byte 0x0f,0x01,0xef\n\t" 602 : : "a" (pkru), "c"(0), "d"(0)); 603 } 604 605 static inline struct desc_ptr get_gdt(void) 606 { 607 struct desc_ptr gdt; 608 __asm__ __volatile__("sgdt %[gdt]" 609 : /* output */ [gdt]"=m"(gdt)); 610 return gdt; 611 } 612 613 static inline struct desc_ptr get_idt(void) 614 { 615 struct desc_ptr idt; 616 __asm__ __volatile__("sidt %[idt]" 617 : /* output */ [idt]"=m"(idt)); 618 return idt; 619 } 620 621 static inline void outl(uint16_t port, uint32_t value) 622 { 623 __asm__ __volatile__("outl %%eax, %%dx" : : "d"(port), "a"(value)); 624 } 625 626 static inline void __cpuid(uint32_t function, uint32_t index, 627 uint32_t *eax, uint32_t *ebx, 628 uint32_t *ecx, uint32_t *edx) 629 { 630 *eax = function; 631 *ecx = index; 632 633 asm volatile("cpuid" 634 : "=a" (*eax), 635 "=b" (*ebx), 636 "=c" (*ecx), 637 "=d" (*edx) 638 : "0" (*eax), "2" (*ecx) 639 : "memory"); 640 } 641 642 static inline void cpuid(uint32_t function, 643 uint32_t *eax, uint32_t *ebx, 644 uint32_t *ecx, uint32_t *edx) 645 { 646 return __cpuid(function, 0, eax, ebx, ecx, edx); 647 } 648 649 static inline uint32_t this_cpu_fms(void) 650 { 651 uint32_t eax, ebx, ecx, edx; 652 653 cpuid(1, &eax, &ebx, &ecx, &edx); 654 return eax; 655 } 656 657 static inline uint32_t this_cpu_family(void) 658 { 659 return x86_family(this_cpu_fms()); 660 } 661 662 static inline uint32_t this_cpu_model(void) 663 { 664 return x86_model(this_cpu_fms()); 665 } 666 667 static inline bool this_cpu_vendor_string_is(const char *vendor) 668 { 669 const uint32_t *chunk = (const uint32_t *)vendor; 670 uint32_t eax, ebx, ecx, edx; 671 672 cpuid(0, &eax, &ebx, &ecx, &edx); 673 return (ebx == chunk[0] && edx == chunk[1] && ecx == chunk[2]); 674 } 675 676 static inline bool this_cpu_is_intel(void) 677 { 678 return this_cpu_vendor_string_is("GenuineIntel"); 679 } 680 681 /* 682 * Exclude early K5 samples with a vendor string of "AMDisbetter!" 683 */ 684 static inline bool this_cpu_is_amd(void) 685 { 686 return this_cpu_vendor_string_is("AuthenticAMD"); 687 } 688 689 static inline uint32_t __this_cpu_has(uint32_t function, uint32_t index, 690 uint8_t reg, uint8_t lo, uint8_t hi) 691 { 692 uint32_t gprs[4]; 693 694 __cpuid(function, index, 695 &gprs[KVM_CPUID_EAX], &gprs[KVM_CPUID_EBX], 696 &gprs[KVM_CPUID_ECX], &gprs[KVM_CPUID_EDX]); 697 698 return (gprs[reg] & GENMASK(hi, lo)) >> lo; 699 } 700 701 static inline bool this_cpu_has(struct kvm_x86_cpu_feature feature) 702 { 703 return __this_cpu_has(feature.function, feature.index, 704 feature.reg, feature.bit, feature.bit); 705 } 706 707 static inline uint32_t this_cpu_property(struct kvm_x86_cpu_property property) 708 { 709 return __this_cpu_has(property.function, property.index, 710 property.reg, property.lo_bit, property.hi_bit); 711 } 712 713 static __always_inline bool this_cpu_has_p(struct kvm_x86_cpu_property property) 714 { 715 uint32_t max_leaf; 716 717 switch (property.function & 0xc0000000) { 718 case 0: 719 max_leaf = this_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF); 720 break; 721 case 0x40000000: 722 max_leaf = this_cpu_property(X86_PROPERTY_MAX_KVM_LEAF); 723 break; 724 case 0x80000000: 725 max_leaf = this_cpu_property(X86_PROPERTY_MAX_EXT_LEAF); 726 break; 727 case 0xc0000000: 728 max_leaf = this_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF); 729 } 730 return max_leaf >= property.function; 731 } 732 733 static inline bool this_pmu_has(struct kvm_x86_pmu_feature feature) 734 { 735 uint32_t nr_bits; 736 737 if (feature.f.reg == KVM_CPUID_EBX) { 738 nr_bits = this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); 739 return nr_bits > feature.f.bit && !this_cpu_has(feature.f); 740 } 741 742 GUEST_ASSERT(feature.f.reg == KVM_CPUID_ECX); 743 nr_bits = this_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); 744 return nr_bits > feature.f.bit || this_cpu_has(feature.f); 745 } 746 747 static __always_inline uint64_t this_cpu_supported_xcr0(void) 748 { 749 if (!this_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) 750 return 0; 751 752 return this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | 753 ((uint64_t)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); 754 } 755 756 typedef u32 __attribute__((vector_size(16))) sse128_t; 757 #define __sse128_u union { sse128_t vec; u64 as_u64[2]; u32 as_u32[4]; } 758 #define sse128_lo(x) ({ __sse128_u t; t.vec = x; t.as_u64[0]; }) 759 #define sse128_hi(x) ({ __sse128_u t; t.vec = x; t.as_u64[1]; }) 760 761 static inline void read_sse_reg(int reg, sse128_t *data) 762 { 763 switch (reg) { 764 case 0: 765 asm("movdqa %%xmm0, %0" : "=m"(*data)); 766 break; 767 case 1: 768 asm("movdqa %%xmm1, %0" : "=m"(*data)); 769 break; 770 case 2: 771 asm("movdqa %%xmm2, %0" : "=m"(*data)); 772 break; 773 case 3: 774 asm("movdqa %%xmm3, %0" : "=m"(*data)); 775 break; 776 case 4: 777 asm("movdqa %%xmm4, %0" : "=m"(*data)); 778 break; 779 case 5: 780 asm("movdqa %%xmm5, %0" : "=m"(*data)); 781 break; 782 case 6: 783 asm("movdqa %%xmm6, %0" : "=m"(*data)); 784 break; 785 case 7: 786 asm("movdqa %%xmm7, %0" : "=m"(*data)); 787 break; 788 default: 789 BUG(); 790 } 791 } 792 793 static inline void write_sse_reg(int reg, const sse128_t *data) 794 { 795 switch (reg) { 796 case 0: 797 asm("movdqa %0, %%xmm0" : : "m"(*data)); 798 break; 799 case 1: 800 asm("movdqa %0, %%xmm1" : : "m"(*data)); 801 break; 802 case 2: 803 asm("movdqa %0, %%xmm2" : : "m"(*data)); 804 break; 805 case 3: 806 asm("movdqa %0, %%xmm3" : : "m"(*data)); 807 break; 808 case 4: 809 asm("movdqa %0, %%xmm4" : : "m"(*data)); 810 break; 811 case 5: 812 asm("movdqa %0, %%xmm5" : : "m"(*data)); 813 break; 814 case 6: 815 asm("movdqa %0, %%xmm6" : : "m"(*data)); 816 break; 817 case 7: 818 asm("movdqa %0, %%xmm7" : : "m"(*data)); 819 break; 820 default: 821 BUG(); 822 } 823 } 824 825 static inline void cpu_relax(void) 826 { 827 asm volatile("rep; nop" ::: "memory"); 828 } 829 830 static inline void udelay(unsigned long usec) 831 { 832 uint64_t start, now, cycles; 833 834 GUEST_ASSERT(guest_tsc_khz); 835 cycles = guest_tsc_khz / 1000 * usec; 836 837 /* 838 * Deliberately don't PAUSE, a.k.a. cpu_relax(), so that the delay is 839 * as accurate as possible, e.g. doesn't trigger PAUSE-Loop VM-Exits. 840 */ 841 start = rdtsc(); 842 do { 843 now = rdtsc(); 844 } while (now - start < cycles); 845 } 846 847 #define ud2() \ 848 __asm__ __volatile__( \ 849 "ud2\n" \ 850 ) 851 852 #define hlt() \ 853 __asm__ __volatile__( \ 854 "hlt\n" \ 855 ) 856 857 struct kvm_x86_state *vcpu_save_state(struct kvm_vcpu *vcpu); 858 void vcpu_load_state(struct kvm_vcpu *vcpu, struct kvm_x86_state *state); 859 void kvm_x86_state_cleanup(struct kvm_x86_state *state); 860 861 const struct kvm_msr_list *kvm_get_msr_index_list(void); 862 const struct kvm_msr_list *kvm_get_feature_msr_index_list(void); 863 bool kvm_msr_is_in_save_restore_list(uint32_t msr_index); 864 uint64_t kvm_get_feature_msr(uint64_t msr_index); 865 866 static inline void vcpu_msrs_get(struct kvm_vcpu *vcpu, 867 struct kvm_msrs *msrs) 868 { 869 int r = __vcpu_ioctl(vcpu, KVM_GET_MSRS, msrs); 870 871 TEST_ASSERT(r == msrs->nmsrs, 872 "KVM_GET_MSRS failed, r: %i (failed on MSR %x)", 873 r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index); 874 } 875 static inline void vcpu_msrs_set(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs) 876 { 877 int r = __vcpu_ioctl(vcpu, KVM_SET_MSRS, msrs); 878 879 TEST_ASSERT(r == msrs->nmsrs, 880 "KVM_SET_MSRS failed, r: %i (failed on MSR %x)", 881 r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index); 882 } 883 static inline void vcpu_debugregs_get(struct kvm_vcpu *vcpu, 884 struct kvm_debugregs *debugregs) 885 { 886 vcpu_ioctl(vcpu, KVM_GET_DEBUGREGS, debugregs); 887 } 888 static inline void vcpu_debugregs_set(struct kvm_vcpu *vcpu, 889 struct kvm_debugregs *debugregs) 890 { 891 vcpu_ioctl(vcpu, KVM_SET_DEBUGREGS, debugregs); 892 } 893 static inline void vcpu_xsave_get(struct kvm_vcpu *vcpu, 894 struct kvm_xsave *xsave) 895 { 896 vcpu_ioctl(vcpu, KVM_GET_XSAVE, xsave); 897 } 898 static inline void vcpu_xsave2_get(struct kvm_vcpu *vcpu, 899 struct kvm_xsave *xsave) 900 { 901 vcpu_ioctl(vcpu, KVM_GET_XSAVE2, xsave); 902 } 903 static inline void vcpu_xsave_set(struct kvm_vcpu *vcpu, 904 struct kvm_xsave *xsave) 905 { 906 vcpu_ioctl(vcpu, KVM_SET_XSAVE, xsave); 907 } 908 static inline void vcpu_xcrs_get(struct kvm_vcpu *vcpu, 909 struct kvm_xcrs *xcrs) 910 { 911 vcpu_ioctl(vcpu, KVM_GET_XCRS, xcrs); 912 } 913 static inline void vcpu_xcrs_set(struct kvm_vcpu *vcpu, struct kvm_xcrs *xcrs) 914 { 915 vcpu_ioctl(vcpu, KVM_SET_XCRS, xcrs); 916 } 917 918 const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid, 919 uint32_t function, uint32_t index); 920 const struct kvm_cpuid2 *kvm_get_supported_cpuid(void); 921 922 static inline uint32_t kvm_cpu_fms(void) 923 { 924 return get_cpuid_entry(kvm_get_supported_cpuid(), 0x1, 0)->eax; 925 } 926 927 static inline uint32_t kvm_cpu_family(void) 928 { 929 return x86_family(kvm_cpu_fms()); 930 } 931 932 static inline uint32_t kvm_cpu_model(void) 933 { 934 return x86_model(kvm_cpu_fms()); 935 } 936 937 bool kvm_cpuid_has(const struct kvm_cpuid2 *cpuid, 938 struct kvm_x86_cpu_feature feature); 939 940 static inline bool kvm_cpu_has(struct kvm_x86_cpu_feature feature) 941 { 942 return kvm_cpuid_has(kvm_get_supported_cpuid(), feature); 943 } 944 945 uint32_t kvm_cpuid_property(const struct kvm_cpuid2 *cpuid, 946 struct kvm_x86_cpu_property property); 947 948 static inline uint32_t kvm_cpu_property(struct kvm_x86_cpu_property property) 949 { 950 return kvm_cpuid_property(kvm_get_supported_cpuid(), property); 951 } 952 953 static __always_inline bool kvm_cpu_has_p(struct kvm_x86_cpu_property property) 954 { 955 uint32_t max_leaf; 956 957 switch (property.function & 0xc0000000) { 958 case 0: 959 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF); 960 break; 961 case 0x40000000: 962 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_KVM_LEAF); 963 break; 964 case 0x80000000: 965 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_EXT_LEAF); 966 break; 967 case 0xc0000000: 968 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF); 969 } 970 return max_leaf >= property.function; 971 } 972 973 static inline bool kvm_pmu_has(struct kvm_x86_pmu_feature feature) 974 { 975 uint32_t nr_bits; 976 977 if (feature.f.reg == KVM_CPUID_EBX) { 978 nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); 979 return nr_bits > feature.f.bit && !kvm_cpu_has(feature.f); 980 } 981 982 TEST_ASSERT_EQ(feature.f.reg, KVM_CPUID_ECX); 983 nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); 984 return nr_bits > feature.f.bit || kvm_cpu_has(feature.f); 985 } 986 987 static __always_inline uint64_t kvm_cpu_supported_xcr0(void) 988 { 989 if (!kvm_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) 990 return 0; 991 992 return kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | 993 ((uint64_t)kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); 994 } 995 996 static inline size_t kvm_cpuid2_size(int nr_entries) 997 { 998 return sizeof(struct kvm_cpuid2) + 999 sizeof(struct kvm_cpuid_entry2) * nr_entries; 1000 } 1001 1002 /* 1003 * Allocate a "struct kvm_cpuid2* instance, with the 0-length arrary of 1004 * entries sized to hold @nr_entries. The caller is responsible for freeing 1005 * the struct. 1006 */ 1007 static inline struct kvm_cpuid2 *allocate_kvm_cpuid2(int nr_entries) 1008 { 1009 struct kvm_cpuid2 *cpuid; 1010 1011 cpuid = malloc(kvm_cpuid2_size(nr_entries)); 1012 TEST_ASSERT(cpuid, "-ENOMEM when allocating kvm_cpuid2"); 1013 1014 cpuid->nent = nr_entries; 1015 1016 return cpuid; 1017 } 1018 1019 void vcpu_init_cpuid(struct kvm_vcpu *vcpu, const struct kvm_cpuid2 *cpuid); 1020 1021 static inline void vcpu_get_cpuid(struct kvm_vcpu *vcpu) 1022 { 1023 vcpu_ioctl(vcpu, KVM_GET_CPUID2, vcpu->cpuid); 1024 } 1025 1026 static inline struct kvm_cpuid_entry2 *__vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu, 1027 uint32_t function, 1028 uint32_t index) 1029 { 1030 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first (or equivalent)"); 1031 1032 vcpu_get_cpuid(vcpu); 1033 1034 return (struct kvm_cpuid_entry2 *)get_cpuid_entry(vcpu->cpuid, 1035 function, index); 1036 } 1037 1038 static inline struct kvm_cpuid_entry2 *vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu, 1039 uint32_t function) 1040 { 1041 return __vcpu_get_cpuid_entry(vcpu, function, 0); 1042 } 1043 1044 static inline int __vcpu_set_cpuid(struct kvm_vcpu *vcpu) 1045 { 1046 int r; 1047 1048 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first"); 1049 r = __vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid); 1050 if (r) 1051 return r; 1052 1053 /* On success, refresh the cache to pick up adjustments made by KVM. */ 1054 vcpu_get_cpuid(vcpu); 1055 return 0; 1056 } 1057 1058 static inline void vcpu_set_cpuid(struct kvm_vcpu *vcpu) 1059 { 1060 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first"); 1061 vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid); 1062 1063 /* Refresh the cache to pick up adjustments made by KVM. */ 1064 vcpu_get_cpuid(vcpu); 1065 } 1066 1067 void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu, 1068 struct kvm_x86_cpu_property property, 1069 uint32_t value); 1070 void vcpu_set_cpuid_maxphyaddr(struct kvm_vcpu *vcpu, uint8_t maxphyaddr); 1071 1072 void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, uint32_t function); 1073 1074 static inline bool vcpu_cpuid_has(struct kvm_vcpu *vcpu, 1075 struct kvm_x86_cpu_feature feature) 1076 { 1077 struct kvm_cpuid_entry2 *entry; 1078 1079 entry = __vcpu_get_cpuid_entry(vcpu, feature.function, feature.index); 1080 return *((&entry->eax) + feature.reg) & BIT(feature.bit); 1081 } 1082 1083 void vcpu_set_or_clear_cpuid_feature(struct kvm_vcpu *vcpu, 1084 struct kvm_x86_cpu_feature feature, 1085 bool set); 1086 1087 static inline void vcpu_set_cpuid_feature(struct kvm_vcpu *vcpu, 1088 struct kvm_x86_cpu_feature feature) 1089 { 1090 vcpu_set_or_clear_cpuid_feature(vcpu, feature, true); 1091 1092 } 1093 1094 static inline void vcpu_clear_cpuid_feature(struct kvm_vcpu *vcpu, 1095 struct kvm_x86_cpu_feature feature) 1096 { 1097 vcpu_set_or_clear_cpuid_feature(vcpu, feature, false); 1098 } 1099 1100 uint64_t vcpu_get_msr(struct kvm_vcpu *vcpu, uint64_t msr_index); 1101 int _vcpu_set_msr(struct kvm_vcpu *vcpu, uint64_t msr_index, uint64_t msr_value); 1102 1103 /* 1104 * Assert on an MSR access(es) and pretty print the MSR name when possible. 1105 * Note, the caller provides the stringified name so that the name of macro is 1106 * printed, not the value the macro resolves to (due to macro expansion). 1107 */ 1108 #define TEST_ASSERT_MSR(cond, fmt, msr, str, args...) \ 1109 do { \ 1110 if (__builtin_constant_p(msr)) { \ 1111 TEST_ASSERT(cond, fmt, str, args); \ 1112 } else if (!(cond)) { \ 1113 char buf[16]; \ 1114 \ 1115 snprintf(buf, sizeof(buf), "MSR 0x%x", msr); \ 1116 TEST_ASSERT(cond, fmt, buf, args); \ 1117 } \ 1118 } while (0) 1119 1120 /* 1121 * Returns true if KVM should return the last written value when reading an MSR 1122 * from userspace, e.g. the MSR isn't a command MSR, doesn't emulate state that 1123 * is changing, etc. This is NOT an exhaustive list! The intent is to filter 1124 * out MSRs that are not durable _and_ that a selftest wants to write. 1125 */ 1126 static inline bool is_durable_msr(uint32_t msr) 1127 { 1128 return msr != MSR_IA32_TSC; 1129 } 1130 1131 #define vcpu_set_msr(vcpu, msr, val) \ 1132 do { \ 1133 uint64_t r, v = val; \ 1134 \ 1135 TEST_ASSERT_MSR(_vcpu_set_msr(vcpu, msr, v) == 1, \ 1136 "KVM_SET_MSRS failed on %s, value = 0x%lx", msr, #msr, v); \ 1137 if (!is_durable_msr(msr)) \ 1138 break; \ 1139 r = vcpu_get_msr(vcpu, msr); \ 1140 TEST_ASSERT_MSR(r == v, "Set %s to '0x%lx', got back '0x%lx'", msr, #msr, v, r);\ 1141 } while (0) 1142 1143 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits); 1144 void kvm_init_vm_address_properties(struct kvm_vm *vm); 1145 bool vm_is_unrestricted_guest(struct kvm_vm *vm); 1146 1147 struct ex_regs { 1148 uint64_t rax, rcx, rdx, rbx; 1149 uint64_t rbp, rsi, rdi; 1150 uint64_t r8, r9, r10, r11; 1151 uint64_t r12, r13, r14, r15; 1152 uint64_t vector; 1153 uint64_t error_code; 1154 uint64_t rip; 1155 uint64_t cs; 1156 uint64_t rflags; 1157 }; 1158 1159 struct idt_entry { 1160 uint16_t offset0; 1161 uint16_t selector; 1162 uint16_t ist : 3; 1163 uint16_t : 5; 1164 uint16_t type : 4; 1165 uint16_t : 1; 1166 uint16_t dpl : 2; 1167 uint16_t p : 1; 1168 uint16_t offset1; 1169 uint32_t offset2; uint32_t reserved; 1170 }; 1171 1172 void vm_install_exception_handler(struct kvm_vm *vm, int vector, 1173 void (*handler)(struct ex_regs *)); 1174 1175 /* If a toddler were to say "abracadabra". */ 1176 #define KVM_EXCEPTION_MAGIC 0xabacadabaULL 1177 1178 /* 1179 * KVM selftest exception fixup uses registers to coordinate with the exception 1180 * handler, versus the kernel's in-memory tables and KVM-Unit-Tests's in-memory 1181 * per-CPU data. Using only registers avoids having to map memory into the 1182 * guest, doesn't require a valid, stable GS.base, and reduces the risk of 1183 * for recursive faults when accessing memory in the handler. The downside to 1184 * using registers is that it restricts what registers can be used by the actual 1185 * instruction. But, selftests are 64-bit only, making register* pressure a 1186 * minor concern. Use r9-r11 as they are volatile, i.e. don't need to be saved 1187 * by the callee, and except for r11 are not implicit parameters to any 1188 * instructions. Ideally, fixup would use r8-r10 and thus avoid implicit 1189 * parameters entirely, but Hyper-V's hypercall ABI uses r8 and testing Hyper-V 1190 * is higher priority than testing non-faulting SYSCALL/SYSRET. 1191 * 1192 * Note, the fixup handler deliberately does not handle #DE, i.e. the vector 1193 * is guaranteed to be non-zero on fault. 1194 * 1195 * REGISTER INPUTS: 1196 * r9 = MAGIC 1197 * r10 = RIP 1198 * r11 = new RIP on fault 1199 * 1200 * REGISTER OUTPUTS: 1201 * r9 = exception vector (non-zero) 1202 * r10 = error code 1203 */ 1204 #define __KVM_ASM_SAFE(insn, fep) \ 1205 "mov $" __stringify(KVM_EXCEPTION_MAGIC) ", %%r9\n\t" \ 1206 "lea 1f(%%rip), %%r10\n\t" \ 1207 "lea 2f(%%rip), %%r11\n\t" \ 1208 fep "1: " insn "\n\t" \ 1209 "xor %%r9, %%r9\n\t" \ 1210 "2:\n\t" \ 1211 "mov %%r9b, %[vector]\n\t" \ 1212 "mov %%r10, %[error_code]\n\t" 1213 1214 #define KVM_ASM_SAFE(insn) __KVM_ASM_SAFE(insn, "") 1215 #define KVM_ASM_SAFE_FEP(insn) __KVM_ASM_SAFE(insn, KVM_FEP) 1216 1217 #define KVM_ASM_SAFE_OUTPUTS(v, ec) [vector] "=qm"(v), [error_code] "=rm"(ec) 1218 #define KVM_ASM_SAFE_CLOBBERS "r9", "r10", "r11" 1219 1220 #define kvm_asm_safe(insn, inputs...) \ 1221 ({ \ 1222 uint64_t ign_error_code; \ 1223 uint8_t vector; \ 1224 \ 1225 asm volatile(KVM_ASM_SAFE(insn) \ 1226 : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code) \ 1227 : inputs \ 1228 : KVM_ASM_SAFE_CLOBBERS); \ 1229 vector; \ 1230 }) 1231 1232 #define kvm_asm_safe_ec(insn, error_code, inputs...) \ 1233 ({ \ 1234 uint8_t vector; \ 1235 \ 1236 asm volatile(KVM_ASM_SAFE(insn) \ 1237 : KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1238 : inputs \ 1239 : KVM_ASM_SAFE_CLOBBERS); \ 1240 vector; \ 1241 }) 1242 1243 #define kvm_asm_safe_fep(insn, inputs...) \ 1244 ({ \ 1245 uint64_t ign_error_code; \ 1246 uint8_t vector; \ 1247 \ 1248 asm volatile(KVM_ASM_SAFE_FEP(insn) \ 1249 : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code) \ 1250 : inputs \ 1251 : KVM_ASM_SAFE_CLOBBERS); \ 1252 vector; \ 1253 }) 1254 1255 #define kvm_asm_safe_ec_fep(insn, error_code, inputs...) \ 1256 ({ \ 1257 uint8_t vector; \ 1258 \ 1259 asm volatile(KVM_ASM_SAFE_FEP(insn) \ 1260 : KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1261 : inputs \ 1262 : KVM_ASM_SAFE_CLOBBERS); \ 1263 vector; \ 1264 }) 1265 1266 #define BUILD_READ_U64_SAFE_HELPER(insn, _fep, _FEP) \ 1267 static inline uint8_t insn##_safe ##_fep(uint32_t idx, uint64_t *val) \ 1268 { \ 1269 uint64_t error_code; \ 1270 uint8_t vector; \ 1271 uint32_t a, d; \ 1272 \ 1273 asm volatile(KVM_ASM_SAFE##_FEP(#insn) \ 1274 : "=a"(a), "=d"(d), \ 1275 KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1276 : "c"(idx) \ 1277 : KVM_ASM_SAFE_CLOBBERS); \ 1278 \ 1279 *val = (uint64_t)a | ((uint64_t)d << 32); \ 1280 return vector; \ 1281 } 1282 1283 /* 1284 * Generate {insn}_safe() and {insn}_safe_fep() helpers for instructions that 1285 * use ECX as in input index, and EDX:EAX as a 64-bit output. 1286 */ 1287 #define BUILD_READ_U64_SAFE_HELPERS(insn) \ 1288 BUILD_READ_U64_SAFE_HELPER(insn, , ) \ 1289 BUILD_READ_U64_SAFE_HELPER(insn, _fep, _FEP) \ 1290 1291 BUILD_READ_U64_SAFE_HELPERS(rdmsr) 1292 BUILD_READ_U64_SAFE_HELPERS(rdpmc) 1293 BUILD_READ_U64_SAFE_HELPERS(xgetbv) 1294 1295 static inline uint8_t wrmsr_safe(uint32_t msr, uint64_t val) 1296 { 1297 return kvm_asm_safe("wrmsr", "a"(val & -1u), "d"(val >> 32), "c"(msr)); 1298 } 1299 1300 static inline uint8_t xsetbv_safe(uint32_t index, uint64_t value) 1301 { 1302 u32 eax = value; 1303 u32 edx = value >> 32; 1304 1305 return kvm_asm_safe("xsetbv", "a" (eax), "d" (edx), "c" (index)); 1306 } 1307 1308 bool kvm_is_tdp_enabled(void); 1309 1310 static inline bool kvm_is_pmu_enabled(void) 1311 { 1312 return get_kvm_param_bool("enable_pmu"); 1313 } 1314 1315 static inline bool kvm_is_forced_emulation_enabled(void) 1316 { 1317 return !!get_kvm_param_integer("force_emulation_prefix"); 1318 } 1319 1320 uint64_t *__vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr, 1321 int *level); 1322 uint64_t *vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr); 1323 1324 uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2, 1325 uint64_t a3); 1326 uint64_t __xen_hypercall(uint64_t nr, uint64_t a0, void *a1); 1327 void xen_hypercall(uint64_t nr, uint64_t a0, void *a1); 1328 1329 static inline uint64_t __kvm_hypercall_map_gpa_range(uint64_t gpa, 1330 uint64_t size, uint64_t flags) 1331 { 1332 return kvm_hypercall(KVM_HC_MAP_GPA_RANGE, gpa, size >> PAGE_SHIFT, flags, 0); 1333 } 1334 1335 static inline void kvm_hypercall_map_gpa_range(uint64_t gpa, uint64_t size, 1336 uint64_t flags) 1337 { 1338 uint64_t ret = __kvm_hypercall_map_gpa_range(gpa, size, flags); 1339 1340 GUEST_ASSERT(!ret); 1341 } 1342 1343 void __vm_xsave_require_permission(uint64_t xfeature, const char *name); 1344 1345 #define vm_xsave_require_permission(xfeature) \ 1346 __vm_xsave_require_permission(xfeature, #xfeature) 1347 1348 enum pg_level { 1349 PG_LEVEL_NONE, 1350 PG_LEVEL_4K, 1351 PG_LEVEL_2M, 1352 PG_LEVEL_1G, 1353 PG_LEVEL_512G, 1354 PG_LEVEL_NUM 1355 }; 1356 1357 #define PG_LEVEL_SHIFT(_level) ((_level - 1) * 9 + 12) 1358 #define PG_LEVEL_SIZE(_level) (1ull << PG_LEVEL_SHIFT(_level)) 1359 1360 #define PG_SIZE_4K PG_LEVEL_SIZE(PG_LEVEL_4K) 1361 #define PG_SIZE_2M PG_LEVEL_SIZE(PG_LEVEL_2M) 1362 #define PG_SIZE_1G PG_LEVEL_SIZE(PG_LEVEL_1G) 1363 1364 void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, int level); 1365 void virt_map_level(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, 1366 uint64_t nr_bytes, int level); 1367 1368 /* 1369 * Basic CPU control in CR0 1370 */ 1371 #define X86_CR0_PE (1UL<<0) /* Protection Enable */ 1372 #define X86_CR0_MP (1UL<<1) /* Monitor Coprocessor */ 1373 #define X86_CR0_EM (1UL<<2) /* Emulation */ 1374 #define X86_CR0_TS (1UL<<3) /* Task Switched */ 1375 #define X86_CR0_ET (1UL<<4) /* Extension Type */ 1376 #define X86_CR0_NE (1UL<<5) /* Numeric Error */ 1377 #define X86_CR0_WP (1UL<<16) /* Write Protect */ 1378 #define X86_CR0_AM (1UL<<18) /* Alignment Mask */ 1379 #define X86_CR0_NW (1UL<<29) /* Not Write-through */ 1380 #define X86_CR0_CD (1UL<<30) /* Cache Disable */ 1381 #define X86_CR0_PG (1UL<<31) /* Paging */ 1382 1383 #define PFERR_PRESENT_BIT 0 1384 #define PFERR_WRITE_BIT 1 1385 #define PFERR_USER_BIT 2 1386 #define PFERR_RSVD_BIT 3 1387 #define PFERR_FETCH_BIT 4 1388 #define PFERR_PK_BIT 5 1389 #define PFERR_SGX_BIT 15 1390 #define PFERR_GUEST_FINAL_BIT 32 1391 #define PFERR_GUEST_PAGE_BIT 33 1392 #define PFERR_IMPLICIT_ACCESS_BIT 48 1393 1394 #define PFERR_PRESENT_MASK BIT(PFERR_PRESENT_BIT) 1395 #define PFERR_WRITE_MASK BIT(PFERR_WRITE_BIT) 1396 #define PFERR_USER_MASK BIT(PFERR_USER_BIT) 1397 #define PFERR_RSVD_MASK BIT(PFERR_RSVD_BIT) 1398 #define PFERR_FETCH_MASK BIT(PFERR_FETCH_BIT) 1399 #define PFERR_PK_MASK BIT(PFERR_PK_BIT) 1400 #define PFERR_SGX_MASK BIT(PFERR_SGX_BIT) 1401 #define PFERR_GUEST_FINAL_MASK BIT_ULL(PFERR_GUEST_FINAL_BIT) 1402 #define PFERR_GUEST_PAGE_MASK BIT_ULL(PFERR_GUEST_PAGE_BIT) 1403 #define PFERR_IMPLICIT_ACCESS BIT_ULL(PFERR_IMPLICIT_ACCESS_BIT) 1404 1405 bool sys_clocksource_is_based_on_tsc(void); 1406 1407 #endif /* SELFTEST_KVM_PROCESSOR_H */ 1408