1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2018, Google LLC. 4 */ 5 6 #ifndef SELFTEST_KVM_PROCESSOR_H 7 #define SELFTEST_KVM_PROCESSOR_H 8 9 #include <assert.h> 10 #include <stdint.h> 11 #include <syscall.h> 12 13 #include <asm/msr-index.h> 14 #include <asm/prctl.h> 15 16 #include <linux/kvm_para.h> 17 #include <linux/stringify.h> 18 19 #include "kvm_util.h" 20 #include "ucall_common.h" 21 22 extern bool host_cpu_is_intel; 23 extern bool host_cpu_is_amd; 24 extern bool host_cpu_is_hygon; 25 extern bool host_cpu_is_amd_compatible; 26 extern u64 guest_tsc_khz; 27 extern struct kvm_mmu guest_mmu; 28 29 #ifndef MAX_NR_CPUID_ENTRIES 30 #define MAX_NR_CPUID_ENTRIES 100 31 #endif 32 33 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 34 35 /* Forced emulation prefix, used to invoke the emulator unconditionally. */ 36 #define KVM_FEP "ud2; .byte 'k', 'v', 'm';" 37 38 #define NMI_VECTOR 0x02 39 40 const char *ex_str(int vector); 41 42 #define X86_EFLAGS_CF BIT(0) /* Carry Flag */ 43 #define X86_EFLAGS_FIXED BIT(1) /* Bit 1 - always on */ 44 #define X86_EFLAGS_PF BIT(2) /* Parity Flag */ 45 #define X86_EFLAGS_AF BIT(4) /* Auxiliary carry Flag */ 46 #define X86_EFLAGS_ZF BIT(6) /* Zero Flag */ 47 #define X86_EFLAGS_SF BIT(7) /* Sign Flag */ 48 #define X86_EFLAGS_TF BIT(8) /* Trap Flag */ 49 #define X86_EFLAGS_IF BIT(9) /* Interrupt Flag */ 50 #define X86_EFLAGS_DF BIT(10) /* Direction Flag */ 51 #define X86_EFLAGS_OF BIT(11) /* Overflow Flag */ 52 #define X86_EFLAGS_IOPL BIT(12) /* I/O Privilege Level (2 bits) */ 53 #define X86_EFLAGS_NT BIT(14) /* Nested Task */ 54 #define X86_EFLAGS_RF BIT(16) /* Resume Flag */ 55 #define X86_EFLAGS_VM BIT(17) /* Virtual Mode */ 56 #define X86_EFLAGS_AC BIT(18) /* Alignment Check/Access Control */ 57 #define X86_EFLAGS_VIF BIT(19) /* Virtual Interrupt Flag */ 58 #define X86_EFLAGS_VIP BIT(20) /* Virtual Interrupt Pending */ 59 #define X86_EFLAGS_ID BIT(21) /* CPUID detection */ 60 61 #define X86_CR4_VME (1ul << 0) 62 #define X86_CR4_PVI (1ul << 1) 63 #define X86_CR4_TSD (1ul << 2) 64 #define X86_CR4_DE (1ul << 3) 65 #define X86_CR4_PSE (1ul << 4) 66 #define X86_CR4_PAE (1ul << 5) 67 #define X86_CR4_MCE (1ul << 6) 68 #define X86_CR4_PGE (1ul << 7) 69 #define X86_CR4_PCE (1ul << 8) 70 #define X86_CR4_OSFXSR (1ul << 9) 71 #define X86_CR4_OSXMMEXCPT (1ul << 10) 72 #define X86_CR4_UMIP (1ul << 11) 73 #define X86_CR4_LA57 (1ul << 12) 74 #define X86_CR4_VMXE (1ul << 13) 75 #define X86_CR4_SMXE (1ul << 14) 76 #define X86_CR4_FSGSBASE (1ul << 16) 77 #define X86_CR4_PCIDE (1ul << 17) 78 #define X86_CR4_OSXSAVE (1ul << 18) 79 #define X86_CR4_SMEP (1ul << 20) 80 #define X86_CR4_SMAP (1ul << 21) 81 #define X86_CR4_PKE (1ul << 22) 82 83 struct xstate_header { 84 u64 xstate_bv; 85 u64 xcomp_bv; 86 u64 reserved[6]; 87 } __attribute__((packed)); 88 89 struct xstate { 90 u8 i387[512]; 91 struct xstate_header header; 92 u8 extended_state_area[0]; 93 } __attribute__ ((packed, aligned (64))); 94 95 #define XFEATURE_MASK_FP BIT_ULL(0) 96 #define XFEATURE_MASK_SSE BIT_ULL(1) 97 #define XFEATURE_MASK_YMM BIT_ULL(2) 98 #define XFEATURE_MASK_BNDREGS BIT_ULL(3) 99 #define XFEATURE_MASK_BNDCSR BIT_ULL(4) 100 #define XFEATURE_MASK_OPMASK BIT_ULL(5) 101 #define XFEATURE_MASK_ZMM_Hi256 BIT_ULL(6) 102 #define XFEATURE_MASK_Hi16_ZMM BIT_ULL(7) 103 #define XFEATURE_MASK_PT BIT_ULL(8) 104 #define XFEATURE_MASK_PKRU BIT_ULL(9) 105 #define XFEATURE_MASK_PASID BIT_ULL(10) 106 #define XFEATURE_MASK_CET_USER BIT_ULL(11) 107 #define XFEATURE_MASK_CET_KERNEL BIT_ULL(12) 108 #define XFEATURE_MASK_LBR BIT_ULL(15) 109 #define XFEATURE_MASK_XTILE_CFG BIT_ULL(17) 110 #define XFEATURE_MASK_XTILE_DATA BIT_ULL(18) 111 112 #define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK | \ 113 XFEATURE_MASK_ZMM_Hi256 | \ 114 XFEATURE_MASK_Hi16_ZMM) 115 #define XFEATURE_MASK_XTILE (XFEATURE_MASK_XTILE_DATA | \ 116 XFEATURE_MASK_XTILE_CFG) 117 118 /* Note, these are ordered alphabetically to match kvm_cpuid_entry2. Eww. */ 119 enum cpuid_output_regs { 120 KVM_CPUID_EAX, 121 KVM_CPUID_EBX, 122 KVM_CPUID_ECX, 123 KVM_CPUID_EDX 124 }; 125 126 /* 127 * Pack the information into a 64-bit value so that each X86_FEATURE_XXX can be 128 * passed by value with no overhead. 129 */ 130 struct kvm_x86_cpu_feature { 131 u32 function; 132 u16 index; 133 u8 reg; 134 u8 bit; 135 }; 136 #define KVM_X86_CPU_FEATURE(fn, idx, gpr, __bit) \ 137 ({ \ 138 struct kvm_x86_cpu_feature feature = { \ 139 .function = fn, \ 140 .index = idx, \ 141 .reg = KVM_CPUID_##gpr, \ 142 .bit = __bit, \ 143 }; \ 144 \ 145 kvm_static_assert((fn & 0xc0000000) == 0 || \ 146 (fn & 0xc0000000) == 0x40000000 || \ 147 (fn & 0xc0000000) == 0x80000000 || \ 148 (fn & 0xc0000000) == 0xc0000000); \ 149 kvm_static_assert(idx < BIT(sizeof(feature.index) * BITS_PER_BYTE)); \ 150 feature; \ 151 }) 152 153 /* 154 * Basic Leafs, a.k.a. Intel defined 155 */ 156 #define X86_FEATURE_MWAIT KVM_X86_CPU_FEATURE(0x1, 0, ECX, 3) 157 #define X86_FEATURE_VMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 5) 158 #define X86_FEATURE_SMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 6) 159 #define X86_FEATURE_PDCM KVM_X86_CPU_FEATURE(0x1, 0, ECX, 15) 160 #define X86_FEATURE_PCID KVM_X86_CPU_FEATURE(0x1, 0, ECX, 17) 161 #define X86_FEATURE_X2APIC KVM_X86_CPU_FEATURE(0x1, 0, ECX, 21) 162 #define X86_FEATURE_MOVBE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 22) 163 #define X86_FEATURE_TSC_DEADLINE_TIMER KVM_X86_CPU_FEATURE(0x1, 0, ECX, 24) 164 #define X86_FEATURE_XSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 26) 165 #define X86_FEATURE_OSXSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 27) 166 #define X86_FEATURE_RDRAND KVM_X86_CPU_FEATURE(0x1, 0, ECX, 30) 167 #define X86_FEATURE_HYPERVISOR KVM_X86_CPU_FEATURE(0x1, 0, ECX, 31) 168 #define X86_FEATURE_PAE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 6) 169 #define X86_FEATURE_MCE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 7) 170 #define X86_FEATURE_APIC KVM_X86_CPU_FEATURE(0x1, 0, EDX, 9) 171 #define X86_FEATURE_CLFLUSH KVM_X86_CPU_FEATURE(0x1, 0, EDX, 19) 172 #define X86_FEATURE_XMM KVM_X86_CPU_FEATURE(0x1, 0, EDX, 25) 173 #define X86_FEATURE_XMM2 KVM_X86_CPU_FEATURE(0x1, 0, EDX, 26) 174 #define X86_FEATURE_FSGSBASE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 0) 175 #define X86_FEATURE_TSC_ADJUST KVM_X86_CPU_FEATURE(0x7, 0, EBX, 1) 176 #define X86_FEATURE_SGX KVM_X86_CPU_FEATURE(0x7, 0, EBX, 2) 177 #define X86_FEATURE_HLE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 4) 178 #define X86_FEATURE_SMEP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 7) 179 #define X86_FEATURE_INVPCID KVM_X86_CPU_FEATURE(0x7, 0, EBX, 10) 180 #define X86_FEATURE_RTM KVM_X86_CPU_FEATURE(0x7, 0, EBX, 11) 181 #define X86_FEATURE_MPX KVM_X86_CPU_FEATURE(0x7, 0, EBX, 14) 182 #define X86_FEATURE_SMAP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 20) 183 #define X86_FEATURE_PCOMMIT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 22) 184 #define X86_FEATURE_CLFLUSHOPT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 23) 185 #define X86_FEATURE_CLWB KVM_X86_CPU_FEATURE(0x7, 0, EBX, 24) 186 #define X86_FEATURE_UMIP KVM_X86_CPU_FEATURE(0x7, 0, ECX, 2) 187 #define X86_FEATURE_PKU KVM_X86_CPU_FEATURE(0x7, 0, ECX, 3) 188 #define X86_FEATURE_OSPKE KVM_X86_CPU_FEATURE(0x7, 0, ECX, 4) 189 #define X86_FEATURE_LA57 KVM_X86_CPU_FEATURE(0x7, 0, ECX, 16) 190 #define X86_FEATURE_RDPID KVM_X86_CPU_FEATURE(0x7, 0, ECX, 22) 191 #define X86_FEATURE_SGX_LC KVM_X86_CPU_FEATURE(0x7, 0, ECX, 30) 192 #define X86_FEATURE_SHSTK KVM_X86_CPU_FEATURE(0x7, 0, ECX, 7) 193 #define X86_FEATURE_IBT KVM_X86_CPU_FEATURE(0x7, 0, EDX, 20) 194 #define X86_FEATURE_AMX_TILE KVM_X86_CPU_FEATURE(0x7, 0, EDX, 24) 195 #define X86_FEATURE_SPEC_CTRL KVM_X86_CPU_FEATURE(0x7, 0, EDX, 26) 196 #define X86_FEATURE_ARCH_CAPABILITIES KVM_X86_CPU_FEATURE(0x7, 0, EDX, 29) 197 #define X86_FEATURE_PKS KVM_X86_CPU_FEATURE(0x7, 0, ECX, 31) 198 #define X86_FEATURE_XTILECFG KVM_X86_CPU_FEATURE(0xD, 0, EAX, 17) 199 #define X86_FEATURE_XTILEDATA KVM_X86_CPU_FEATURE(0xD, 0, EAX, 18) 200 #define X86_FEATURE_XSAVES KVM_X86_CPU_FEATURE(0xD, 1, EAX, 3) 201 #define X86_FEATURE_XFD KVM_X86_CPU_FEATURE(0xD, 1, EAX, 4) 202 #define X86_FEATURE_XTILEDATA_XFD KVM_X86_CPU_FEATURE(0xD, 18, ECX, 2) 203 204 /* 205 * Extended Leafs, a.k.a. AMD defined 206 */ 207 #define X86_FEATURE_SVM KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 2) 208 #define X86_FEATURE_PERFCTR_CORE KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 23) 209 #define X86_FEATURE_PERFCTR_NB KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 24) 210 #define X86_FEATURE_PERFCTR_LLC KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 28) 211 #define X86_FEATURE_NX KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 20) 212 #define X86_FEATURE_GBPAGES KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 26) 213 #define X86_FEATURE_RDTSCP KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 27) 214 #define X86_FEATURE_LM KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 29) 215 #define X86_FEATURE_INVTSC KVM_X86_CPU_FEATURE(0x80000007, 0, EDX, 8) 216 #define X86_FEATURE_RDPRU KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 4) 217 #define X86_FEATURE_AMD_IBPB KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 12) 218 #define X86_FEATURE_NPT KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 0) 219 #define X86_FEATURE_LBRV KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 1) 220 #define X86_FEATURE_NRIPS KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 3) 221 #define X86_FEATURE_TSCRATEMSR KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 4) 222 #define X86_FEATURE_PAUSEFILTER KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 10) 223 #define X86_FEATURE_PFTHRESHOLD KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 12) 224 #define X86_FEATURE_V_VMSAVE_VMLOAD KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 15) 225 #define X86_FEATURE_VGIF KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 16) 226 #define X86_FEATURE_IDLE_HLT KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 30) 227 #define X86_FEATURE_SEV KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 1) 228 #define X86_FEATURE_SEV_ES KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 3) 229 #define X86_FEATURE_SEV_SNP KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 4) 230 #define X86_FEATURE_GP_ON_USER_CPUID KVM_X86_CPU_FEATURE(0x80000021, 0, EAX, 17) 231 #define X86_FEATURE_PERFMON_V2 KVM_X86_CPU_FEATURE(0x80000022, 0, EAX, 0) 232 #define X86_FEATURE_LBR_PMC_FREEZE KVM_X86_CPU_FEATURE(0x80000022, 0, EAX, 2) 233 234 /* 235 * KVM defined paravirt features. 236 */ 237 #define X86_FEATURE_KVM_CLOCKSOURCE KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 0) 238 #define X86_FEATURE_KVM_NOP_IO_DELAY KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 1) 239 #define X86_FEATURE_KVM_MMU_OP KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 2) 240 #define X86_FEATURE_KVM_CLOCKSOURCE2 KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 3) 241 #define X86_FEATURE_KVM_ASYNC_PF KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 4) 242 #define X86_FEATURE_KVM_STEAL_TIME KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 5) 243 #define X86_FEATURE_KVM_PV_EOI KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 6) 244 #define X86_FEATURE_KVM_PV_UNHALT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 7) 245 /* Bit 8 apparently isn't used?!?! */ 246 #define X86_FEATURE_KVM_PV_TLB_FLUSH KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 9) 247 #define X86_FEATURE_KVM_ASYNC_PF_VMEXIT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 10) 248 #define X86_FEATURE_KVM_PV_SEND_IPI KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 11) 249 #define X86_FEATURE_KVM_POLL_CONTROL KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 12) 250 #define X86_FEATURE_KVM_PV_SCHED_YIELD KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 13) 251 #define X86_FEATURE_KVM_ASYNC_PF_INT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 14) 252 #define X86_FEATURE_KVM_MSI_EXT_DEST_ID KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 15) 253 #define X86_FEATURE_KVM_HC_MAP_GPA_RANGE KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 16) 254 #define X86_FEATURE_KVM_MIGRATION_CONTROL KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 17) 255 256 /* 257 * Same idea as X86_FEATURE_XXX, but X86_PROPERTY_XXX retrieves a multi-bit 258 * value/property as opposed to a single-bit feature. Again, pack the info 259 * into a 64-bit value to pass by value with no overhead. 260 */ 261 struct kvm_x86_cpu_property { 262 u32 function; 263 u8 index; 264 u8 reg; 265 u8 lo_bit; 266 u8 hi_bit; 267 }; 268 #define KVM_X86_CPU_PROPERTY(fn, idx, gpr, low_bit, high_bit) \ 269 ({ \ 270 struct kvm_x86_cpu_property property = { \ 271 .function = fn, \ 272 .index = idx, \ 273 .reg = KVM_CPUID_##gpr, \ 274 .lo_bit = low_bit, \ 275 .hi_bit = high_bit, \ 276 }; \ 277 \ 278 kvm_static_assert(low_bit < high_bit); \ 279 kvm_static_assert((fn & 0xc0000000) == 0 || \ 280 (fn & 0xc0000000) == 0x40000000 || \ 281 (fn & 0xc0000000) == 0x80000000 || \ 282 (fn & 0xc0000000) == 0xc0000000); \ 283 kvm_static_assert(idx < BIT(sizeof(property.index) * BITS_PER_BYTE)); \ 284 property; \ 285 }) 286 287 #define X86_PROPERTY_MAX_BASIC_LEAF KVM_X86_CPU_PROPERTY(0, 0, EAX, 0, 31) 288 #define X86_PROPERTY_PMU_VERSION KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 0, 7) 289 #define X86_PROPERTY_PMU_NR_GP_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 8, 15) 290 #define X86_PROPERTY_PMU_GP_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 16, 23) 291 #define X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 24, 31) 292 #define X86_PROPERTY_PMU_EVENTS_MASK KVM_X86_CPU_PROPERTY(0xa, 0, EBX, 0, 12) 293 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK KVM_X86_CPU_PROPERTY(0xa, 0, ECX, 0, 31) 294 #define X86_PROPERTY_PMU_NR_FIXED_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EDX, 0, 4) 295 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0, EDX, 5, 12) 296 297 #define X86_PROPERTY_SUPPORTED_XCR0_LO KVM_X86_CPU_PROPERTY(0xd, 0, EAX, 0, 31) 298 #define X86_PROPERTY_XSTATE_MAX_SIZE_XCR0 KVM_X86_CPU_PROPERTY(0xd, 0, EBX, 0, 31) 299 #define X86_PROPERTY_XSTATE_MAX_SIZE KVM_X86_CPU_PROPERTY(0xd, 0, ECX, 0, 31) 300 #define X86_PROPERTY_SUPPORTED_XCR0_HI KVM_X86_CPU_PROPERTY(0xd, 0, EDX, 0, 31) 301 302 #define X86_PROPERTY_XSTATE_TILE_SIZE KVM_X86_CPU_PROPERTY(0xd, 18, EAX, 0, 31) 303 #define X86_PROPERTY_XSTATE_TILE_OFFSET KVM_X86_CPU_PROPERTY(0xd, 18, EBX, 0, 31) 304 #define X86_PROPERTY_AMX_MAX_PALETTE_TABLES KVM_X86_CPU_PROPERTY(0x1d, 0, EAX, 0, 31) 305 #define X86_PROPERTY_AMX_TOTAL_TILE_BYTES KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 0, 15) 306 #define X86_PROPERTY_AMX_BYTES_PER_TILE KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 16, 31) 307 #define X86_PROPERTY_AMX_BYTES_PER_ROW KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 0, 15) 308 #define X86_PROPERTY_AMX_NR_TILE_REGS KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 16, 31) 309 #define X86_PROPERTY_AMX_MAX_ROWS KVM_X86_CPU_PROPERTY(0x1d, 1, ECX, 0, 15) 310 311 #define X86_PROPERTY_MAX_KVM_LEAF KVM_X86_CPU_PROPERTY(0x40000000, 0, EAX, 0, 31) 312 313 #define X86_PROPERTY_MAX_EXT_LEAF KVM_X86_CPU_PROPERTY(0x80000000, 0, EAX, 0, 31) 314 #define X86_PROPERTY_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 0, 7) 315 #define X86_PROPERTY_MAX_VIRT_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 8, 15) 316 #define X86_PROPERTY_GUEST_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 16, 23) 317 #define X86_PROPERTY_SEV_C_BIT KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 0, 5) 318 #define X86_PROPERTY_PHYS_ADDR_REDUCTION KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 6, 11) 319 #define X86_PROPERTY_NR_PERFCTR_CORE KVM_X86_CPU_PROPERTY(0x80000022, 0, EBX, 0, 3) 320 #define X86_PROPERTY_NR_PERFCTR_NB KVM_X86_CPU_PROPERTY(0x80000022, 0, EBX, 10, 15) 321 322 #define X86_PROPERTY_MAX_CENTAUR_LEAF KVM_X86_CPU_PROPERTY(0xC0000000, 0, EAX, 0, 31) 323 324 /* 325 * Intel's architectural PMU events are bizarre. They have a "feature" bit 326 * that indicates the feature is _not_ supported, and a property that states 327 * the length of the bit mask of unsupported features. A feature is supported 328 * if the size of the bit mask is larger than the "unavailable" bit, and said 329 * bit is not set. Fixed counters also bizarre enumeration, but inverted from 330 * arch events for general purpose counters. Fixed counters are supported if a 331 * feature flag is set **OR** the total number of fixed counters is greater 332 * than index of the counter. 333 * 334 * Wrap the events for general purpose and fixed counters to simplify checking 335 * whether or not a given architectural event is supported. 336 */ 337 struct kvm_x86_pmu_feature { 338 struct kvm_x86_cpu_feature f; 339 }; 340 #define KVM_X86_PMU_FEATURE(__reg, __bit) \ 341 ({ \ 342 struct kvm_x86_pmu_feature feature = { \ 343 .f = KVM_X86_CPU_FEATURE(0xa, 0, __reg, __bit), \ 344 }; \ 345 \ 346 kvm_static_assert(KVM_CPUID_##__reg == KVM_CPUID_EBX || \ 347 KVM_CPUID_##__reg == KVM_CPUID_ECX); \ 348 feature; \ 349 }) 350 351 #define X86_PMU_FEATURE_CPU_CYCLES KVM_X86_PMU_FEATURE(EBX, 0) 352 #define X86_PMU_FEATURE_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 1) 353 #define X86_PMU_FEATURE_REFERENCE_CYCLES KVM_X86_PMU_FEATURE(EBX, 2) 354 #define X86_PMU_FEATURE_LLC_REFERENCES KVM_X86_PMU_FEATURE(EBX, 3) 355 #define X86_PMU_FEATURE_LLC_MISSES KVM_X86_PMU_FEATURE(EBX, 4) 356 #define X86_PMU_FEATURE_BRANCH_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 5) 357 #define X86_PMU_FEATURE_BRANCHES_MISPREDICTED KVM_X86_PMU_FEATURE(EBX, 6) 358 #define X86_PMU_FEATURE_TOPDOWN_SLOTS KVM_X86_PMU_FEATURE(EBX, 7) 359 #define X86_PMU_FEATURE_TOPDOWN_BE_BOUND KVM_X86_PMU_FEATURE(EBX, 8) 360 #define X86_PMU_FEATURE_TOPDOWN_BAD_SPEC KVM_X86_PMU_FEATURE(EBX, 9) 361 #define X86_PMU_FEATURE_TOPDOWN_FE_BOUND KVM_X86_PMU_FEATURE(EBX, 10) 362 #define X86_PMU_FEATURE_TOPDOWN_RETIRING KVM_X86_PMU_FEATURE(EBX, 11) 363 #define X86_PMU_FEATURE_LBR_INSERTS KVM_X86_PMU_FEATURE(EBX, 12) 364 365 #define X86_PMU_FEATURE_INSNS_RETIRED_FIXED KVM_X86_PMU_FEATURE(ECX, 0) 366 #define X86_PMU_FEATURE_CPU_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX, 1) 367 #define X86_PMU_FEATURE_REFERENCE_TSC_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX, 2) 368 #define X86_PMU_FEATURE_TOPDOWN_SLOTS_FIXED KVM_X86_PMU_FEATURE(ECX, 3) 369 370 static inline unsigned int x86_family(unsigned int eax) 371 { 372 unsigned int x86; 373 374 x86 = (eax >> 8) & 0xf; 375 376 if (x86 == 0xf) 377 x86 += (eax >> 20) & 0xff; 378 379 return x86; 380 } 381 382 static inline unsigned int x86_model(unsigned int eax) 383 { 384 return ((eax >> 12) & 0xf0) | ((eax >> 4) & 0x0f); 385 } 386 387 #define PHYSICAL_PAGE_MASK GENMASK_ULL(51, 12) 388 389 #define PAGE_SHIFT 12 390 #define PAGE_SIZE (1ULL << PAGE_SHIFT) 391 #define PAGE_MASK (~(PAGE_SIZE-1) & PHYSICAL_PAGE_MASK) 392 393 #define HUGEPAGE_SHIFT(x) (PAGE_SHIFT + (((x) - 1) * 9)) 394 #define HUGEPAGE_SIZE(x) (1UL << HUGEPAGE_SHIFT(x)) 395 #define HUGEPAGE_MASK(x) (~(HUGEPAGE_SIZE(x) - 1) & PHYSICAL_PAGE_MASK) 396 397 #define PTE_GET_PA(pte) ((pte) & PHYSICAL_PAGE_MASK) 398 #define PTE_GET_PFN(pte) (PTE_GET_PA(pte) >> PAGE_SHIFT) 399 400 struct guest_regs { 401 u64 rax; 402 u64 rcx; 403 u64 rdx; 404 u64 rbx; 405 u64 rsp; 406 u64 rbp; 407 u64 rsi; 408 u64 rdi; 409 u64 r8; 410 u64 r9; 411 u64 r10; 412 u64 r11; 413 u64 r12; 414 u64 r13; 415 u64 r14; 416 u64 r15; 417 u64 rflags; 418 }; 419 420 extern struct guest_regs guest_regs; 421 422 #define GUEST_REG_OFFSET(name) \ 423 [off_##name] "i" (offsetof(struct guest_regs, name)) 424 425 #define GUEST_REGS_OFFSETS \ 426 GUEST_REG_OFFSET(rax), \ 427 GUEST_REG_OFFSET(rcx), \ 428 GUEST_REG_OFFSET(rdx), \ 429 GUEST_REG_OFFSET(rbx), \ 430 GUEST_REG_OFFSET(rsp), \ 431 GUEST_REG_OFFSET(rbp), \ 432 GUEST_REG_OFFSET(rsi), \ 433 GUEST_REG_OFFSET(rdi), \ 434 GUEST_REG_OFFSET(r8), \ 435 GUEST_REG_OFFSET(r9), \ 436 GUEST_REG_OFFSET(r10), \ 437 GUEST_REG_OFFSET(r11), \ 438 GUEST_REG_OFFSET(r12), \ 439 GUEST_REG_OFFSET(r13), \ 440 GUEST_REG_OFFSET(r14), \ 441 GUEST_REG_OFFSET(r15), \ 442 GUEST_REG_OFFSET(rflags) 443 444 #define GUEST_REG(name) "guest_regs + %c[off_" #name "]" 445 446 #define GUEST_SWITCH_GPR_ASM(name) \ 447 "xchg %%" #name ", " GUEST_REG(name) "\n\t" 448 449 struct desc64 { 450 u16 limit0; 451 u16 base0; 452 unsigned base1:8, type:4, s:1, dpl:2, p:1; 453 unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8; 454 u32 base3; 455 u32 zero1; 456 } __attribute__((packed)); 457 458 struct desc_ptr { 459 u16 size; 460 u64 address; 461 } __attribute__((packed)); 462 463 struct kvm_x86_state { 464 struct kvm_xsave *xsave; 465 struct kvm_vcpu_events events; 466 struct kvm_mp_state mp_state; 467 struct kvm_regs regs; 468 struct kvm_xcrs xcrs; 469 struct kvm_sregs sregs; 470 struct kvm_debugregs debugregs; 471 union { 472 struct kvm_nested_state nested; 473 char nested_[16384]; 474 }; 475 struct kvm_msrs msrs; 476 }; 477 478 static inline u64 get_desc64_base(const struct desc64 *desc) 479 { 480 return (u64)desc->base3 << 32 | 481 (u64)desc->base2 << 24 | 482 (u64)desc->base1 << 16 | 483 (u64)desc->base0; 484 } 485 486 static inline u64 rdtsc(void) 487 { 488 u32 eax, edx; 489 u64 tsc_val; 490 /* 491 * The lfence is to wait (on Intel CPUs) until all previous 492 * instructions have been executed. If software requires RDTSC to be 493 * executed prior to execution of any subsequent instruction, it can 494 * execute LFENCE immediately after RDTSC 495 */ 496 __asm__ __volatile__("lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx)); 497 tsc_val = ((u64)edx) << 32 | eax; 498 return tsc_val; 499 } 500 501 static inline u64 rdtscp(u32 *aux) 502 { 503 u32 eax, edx; 504 505 __asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux)); 506 return ((u64)edx) << 32 | eax; 507 } 508 509 static inline u64 rdmsr(u32 msr) 510 { 511 u32 a, d; 512 513 __asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory"); 514 515 return a | ((u64)d << 32); 516 } 517 518 static inline void wrmsr(u32 msr, u64 value) 519 { 520 u32 a = value; 521 u32 d = value >> 32; 522 523 __asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory"); 524 } 525 526 527 static inline u16 inw(u16 port) 528 { 529 u16 tmp; 530 531 __asm__ __volatile__("in %%dx, %%ax" 532 : /* output */ "=a" (tmp) 533 : /* input */ "d" (port)); 534 535 return tmp; 536 } 537 538 static inline u16 get_es(void) 539 { 540 u16 es; 541 542 __asm__ __volatile__("mov %%es, %[es]" 543 : /* output */ [es]"=rm"(es)); 544 return es; 545 } 546 547 static inline u16 get_cs(void) 548 { 549 u16 cs; 550 551 __asm__ __volatile__("mov %%cs, %[cs]" 552 : /* output */ [cs]"=rm"(cs)); 553 return cs; 554 } 555 556 static inline u16 get_ss(void) 557 { 558 u16 ss; 559 560 __asm__ __volatile__("mov %%ss, %[ss]" 561 : /* output */ [ss]"=rm"(ss)); 562 return ss; 563 } 564 565 static inline u16 get_ds(void) 566 { 567 u16 ds; 568 569 __asm__ __volatile__("mov %%ds, %[ds]" 570 : /* output */ [ds]"=rm"(ds)); 571 return ds; 572 } 573 574 static inline u16 get_fs(void) 575 { 576 u16 fs; 577 578 __asm__ __volatile__("mov %%fs, %[fs]" 579 : /* output */ [fs]"=rm"(fs)); 580 return fs; 581 } 582 583 static inline u16 get_gs(void) 584 { 585 u16 gs; 586 587 __asm__ __volatile__("mov %%gs, %[gs]" 588 : /* output */ [gs]"=rm"(gs)); 589 return gs; 590 } 591 592 static inline u16 get_tr(void) 593 { 594 u16 tr; 595 596 __asm__ __volatile__("str %[tr]" 597 : /* output */ [tr]"=rm"(tr)); 598 return tr; 599 } 600 601 static inline u64 get_cr0(void) 602 { 603 u64 cr0; 604 605 __asm__ __volatile__("mov %%cr0, %[cr0]" 606 : /* output */ [cr0]"=r"(cr0)); 607 return cr0; 608 } 609 610 static inline void set_cr0(u64 val) 611 { 612 __asm__ __volatile__("mov %0, %%cr0" : : "r" (val) : "memory"); 613 } 614 615 static inline u64 get_cr2(void) 616 { 617 u64 cr2; 618 619 __asm__ __volatile__("mov %%cr2, %[cr2]" : [cr2]"=r"(cr2)); 620 return cr2; 621 } 622 623 static inline u64 get_cr3(void) 624 { 625 u64 cr3; 626 627 __asm__ __volatile__("mov %%cr3, %[cr3]" 628 : /* output */ [cr3]"=r"(cr3)); 629 return cr3; 630 } 631 632 static inline void set_cr3(u64 val) 633 { 634 __asm__ __volatile__("mov %0, %%cr3" : : "r" (val) : "memory"); 635 } 636 637 static inline u64 get_cr4(void) 638 { 639 u64 cr4; 640 641 __asm__ __volatile__("mov %%cr4, %[cr4]" 642 : /* output */ [cr4]"=r"(cr4)); 643 return cr4; 644 } 645 646 static inline void set_cr4(u64 val) 647 { 648 __asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory"); 649 } 650 651 static inline u64 get_cr8(void) 652 { 653 u64 cr8; 654 655 __asm__ __volatile__("mov %%cr8, %[cr8]" : [cr8]"=r"(cr8)); 656 return cr8; 657 } 658 659 static inline void set_cr8(u64 val) 660 { 661 __asm__ __volatile__("mov %0, %%cr8" : : "r" (val) : "memory"); 662 } 663 664 static inline void set_idt(const struct desc_ptr *idt_desc) 665 { 666 __asm__ __volatile__("lidt %0"::"m"(*idt_desc)); 667 } 668 669 static inline u64 xgetbv(u32 index) 670 { 671 u32 eax, edx; 672 673 __asm__ __volatile__("xgetbv;" 674 : "=a" (eax), "=d" (edx) 675 : "c" (index)); 676 return eax | ((u64)edx << 32); 677 } 678 679 static inline void xsetbv(u32 index, u64 value) 680 { 681 u32 eax = value; 682 u32 edx = value >> 32; 683 684 __asm__ __volatile__("xsetbv" :: "a" (eax), "d" (edx), "c" (index)); 685 } 686 687 static inline void wrpkru(u32 pkru) 688 { 689 /* Note, ECX and EDX are architecturally required to be '0'. */ 690 asm volatile(".byte 0x0f,0x01,0xef\n\t" 691 : : "a" (pkru), "c"(0), "d"(0)); 692 } 693 694 static inline struct desc_ptr get_gdt(void) 695 { 696 struct desc_ptr gdt; 697 __asm__ __volatile__("sgdt %[gdt]" 698 : /* output */ [gdt]"=m"(gdt)); 699 return gdt; 700 } 701 702 static inline struct desc_ptr get_idt(void) 703 { 704 struct desc_ptr idt; 705 __asm__ __volatile__("sidt %[idt]" 706 : /* output */ [idt]"=m"(idt)); 707 return idt; 708 } 709 710 static inline void outl(u16 port, u32 value) 711 { 712 __asm__ __volatile__("outl %%eax, %%dx" : : "d"(port), "a"(value)); 713 } 714 715 static inline void __cpuid(u32 function, u32 index, 716 u32 *eax, u32 *ebx, 717 u32 *ecx, u32 *edx) 718 { 719 *eax = function; 720 *ecx = index; 721 722 asm volatile("cpuid" 723 : "=a" (*eax), 724 "=b" (*ebx), 725 "=c" (*ecx), 726 "=d" (*edx) 727 : "0" (*eax), "2" (*ecx) 728 : "memory"); 729 } 730 731 static inline void cpuid(u32 function, 732 u32 *eax, u32 *ebx, 733 u32 *ecx, u32 *edx) 734 { 735 return __cpuid(function, 0, eax, ebx, ecx, edx); 736 } 737 738 static inline u32 this_cpu_fms(void) 739 { 740 u32 eax, ebx, ecx, edx; 741 742 cpuid(1, &eax, &ebx, &ecx, &edx); 743 return eax; 744 } 745 746 static inline u32 this_cpu_family(void) 747 { 748 return x86_family(this_cpu_fms()); 749 } 750 751 static inline u32 this_cpu_model(void) 752 { 753 return x86_model(this_cpu_fms()); 754 } 755 756 static inline bool this_cpu_vendor_string_is(const char *vendor) 757 { 758 const u32 *chunk = (const u32 *)vendor; 759 u32 eax, ebx, ecx, edx; 760 761 cpuid(0, &eax, &ebx, &ecx, &edx); 762 return (ebx == chunk[0] && edx == chunk[1] && ecx == chunk[2]); 763 } 764 765 static inline bool this_cpu_is_intel(void) 766 { 767 return this_cpu_vendor_string_is("GenuineIntel"); 768 } 769 770 /* 771 * Exclude early K5 samples with a vendor string of "AMDisbetter!" 772 */ 773 static inline bool this_cpu_is_amd(void) 774 { 775 return this_cpu_vendor_string_is("AuthenticAMD"); 776 } 777 778 static inline bool this_cpu_is_hygon(void) 779 { 780 return this_cpu_vendor_string_is("HygonGenuine"); 781 } 782 783 static inline u32 __this_cpu_has(u32 function, u32 index, u8 reg, u8 lo, u8 hi) 784 { 785 u32 gprs[4]; 786 787 __cpuid(function, index, 788 &gprs[KVM_CPUID_EAX], &gprs[KVM_CPUID_EBX], 789 &gprs[KVM_CPUID_ECX], &gprs[KVM_CPUID_EDX]); 790 791 return (gprs[reg] & GENMASK(hi, lo)) >> lo; 792 } 793 794 static inline bool this_cpu_has(struct kvm_x86_cpu_feature feature) 795 { 796 return __this_cpu_has(feature.function, feature.index, 797 feature.reg, feature.bit, feature.bit); 798 } 799 800 static inline u32 this_cpu_property(struct kvm_x86_cpu_property property) 801 { 802 return __this_cpu_has(property.function, property.index, 803 property.reg, property.lo_bit, property.hi_bit); 804 } 805 806 static __always_inline bool this_cpu_has_p(struct kvm_x86_cpu_property property) 807 { 808 u32 max_leaf; 809 810 switch (property.function & 0xc0000000) { 811 case 0: 812 max_leaf = this_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF); 813 break; 814 case 0x40000000: 815 max_leaf = this_cpu_property(X86_PROPERTY_MAX_KVM_LEAF); 816 break; 817 case 0x80000000: 818 max_leaf = this_cpu_property(X86_PROPERTY_MAX_EXT_LEAF); 819 break; 820 case 0xc0000000: 821 max_leaf = this_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF); 822 } 823 return max_leaf >= property.function; 824 } 825 826 static inline bool this_pmu_has(struct kvm_x86_pmu_feature feature) 827 { 828 u32 nr_bits; 829 830 if (feature.f.reg == KVM_CPUID_EBX) { 831 nr_bits = this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); 832 return nr_bits > feature.f.bit && !this_cpu_has(feature.f); 833 } 834 835 GUEST_ASSERT(feature.f.reg == KVM_CPUID_ECX); 836 nr_bits = this_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); 837 return nr_bits > feature.f.bit || this_cpu_has(feature.f); 838 } 839 840 static __always_inline u64 this_cpu_supported_xcr0(void) 841 { 842 if (!this_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) 843 return 0; 844 845 return this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | 846 ((u64)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); 847 } 848 849 typedef u32 __attribute__((vector_size(16))) sse128_t; 850 #define __sse128_u union { sse128_t vec; u64 as_u64[2]; u32 as_u32[4]; } 851 #define sse128_lo(x) ({ __sse128_u t; t.vec = x; t.as_u64[0]; }) 852 #define sse128_hi(x) ({ __sse128_u t; t.vec = x; t.as_u64[1]; }) 853 854 static inline void read_sse_reg(int reg, sse128_t *data) 855 { 856 switch (reg) { 857 case 0: 858 asm("movdqa %%xmm0, %0" : "=m"(*data)); 859 break; 860 case 1: 861 asm("movdqa %%xmm1, %0" : "=m"(*data)); 862 break; 863 case 2: 864 asm("movdqa %%xmm2, %0" : "=m"(*data)); 865 break; 866 case 3: 867 asm("movdqa %%xmm3, %0" : "=m"(*data)); 868 break; 869 case 4: 870 asm("movdqa %%xmm4, %0" : "=m"(*data)); 871 break; 872 case 5: 873 asm("movdqa %%xmm5, %0" : "=m"(*data)); 874 break; 875 case 6: 876 asm("movdqa %%xmm6, %0" : "=m"(*data)); 877 break; 878 case 7: 879 asm("movdqa %%xmm7, %0" : "=m"(*data)); 880 break; 881 default: 882 BUG(); 883 } 884 } 885 886 static inline void write_sse_reg(int reg, const sse128_t *data) 887 { 888 switch (reg) { 889 case 0: 890 asm("movdqa %0, %%xmm0" : : "m"(*data)); 891 break; 892 case 1: 893 asm("movdqa %0, %%xmm1" : : "m"(*data)); 894 break; 895 case 2: 896 asm("movdqa %0, %%xmm2" : : "m"(*data)); 897 break; 898 case 3: 899 asm("movdqa %0, %%xmm3" : : "m"(*data)); 900 break; 901 case 4: 902 asm("movdqa %0, %%xmm4" : : "m"(*data)); 903 break; 904 case 5: 905 asm("movdqa %0, %%xmm5" : : "m"(*data)); 906 break; 907 case 6: 908 asm("movdqa %0, %%xmm6" : : "m"(*data)); 909 break; 910 case 7: 911 asm("movdqa %0, %%xmm7" : : "m"(*data)); 912 break; 913 default: 914 BUG(); 915 } 916 } 917 918 static inline void invlpg(u64 addr) 919 { 920 __asm__ __volatile__("invlpg (%0)" : : "r"(addr) : "memory"); 921 } 922 923 static inline void cpu_relax(void) 924 { 925 asm volatile("rep; nop" ::: "memory"); 926 } 927 928 static inline void udelay(unsigned long usec) 929 { 930 u64 start, now, cycles; 931 932 GUEST_ASSERT(guest_tsc_khz); 933 cycles = guest_tsc_khz / 1000 * usec; 934 935 /* 936 * Deliberately don't PAUSE, a.k.a. cpu_relax(), so that the delay is 937 * as accurate as possible, e.g. doesn't trigger PAUSE-Loop VM-Exits. 938 */ 939 start = rdtsc(); 940 do { 941 now = rdtsc(); 942 } while (now - start < cycles); 943 } 944 945 #define ud2() \ 946 __asm__ __volatile__( \ 947 "ud2\n" \ 948 ) 949 950 #define hlt() \ 951 __asm__ __volatile__( \ 952 "hlt\n" \ 953 ) 954 955 struct kvm_x86_state *vcpu_save_state(struct kvm_vcpu *vcpu); 956 void vcpu_load_state(struct kvm_vcpu *vcpu, struct kvm_x86_state *state); 957 void kvm_x86_state_cleanup(struct kvm_x86_state *state); 958 959 static inline bool kvm_x86_state_is_guest_mode(struct kvm_x86_state *state) 960 { 961 return state->nested.size && (state->nested.flags & KVM_STATE_NESTED_GUEST_MODE); 962 } 963 964 const struct kvm_msr_list *kvm_get_msr_index_list(void); 965 const struct kvm_msr_list *kvm_get_feature_msr_index_list(void); 966 bool kvm_msr_is_in_save_restore_list(u32 msr_index); 967 u64 kvm_get_feature_msr(u64 msr_index); 968 969 static inline void vcpu_msrs_get(struct kvm_vcpu *vcpu, 970 struct kvm_msrs *msrs) 971 { 972 int r = __vcpu_ioctl(vcpu, KVM_GET_MSRS, msrs); 973 974 TEST_ASSERT(r == msrs->nmsrs, 975 "KVM_GET_MSRS failed, r: %i (failed on MSR %x)", 976 r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index); 977 } 978 static inline void vcpu_msrs_set(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs) 979 { 980 int r = __vcpu_ioctl(vcpu, KVM_SET_MSRS, msrs); 981 982 TEST_ASSERT(r == msrs->nmsrs, 983 "KVM_SET_MSRS failed, r: %i (failed on MSR %x)", 984 r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index); 985 } 986 static inline void vcpu_debugregs_get(struct kvm_vcpu *vcpu, 987 struct kvm_debugregs *debugregs) 988 { 989 vcpu_ioctl(vcpu, KVM_GET_DEBUGREGS, debugregs); 990 } 991 static inline void vcpu_debugregs_set(struct kvm_vcpu *vcpu, 992 struct kvm_debugregs *debugregs) 993 { 994 vcpu_ioctl(vcpu, KVM_SET_DEBUGREGS, debugregs); 995 } 996 static inline void vcpu_xsave_get(struct kvm_vcpu *vcpu, 997 struct kvm_xsave *xsave) 998 { 999 vcpu_ioctl(vcpu, KVM_GET_XSAVE, xsave); 1000 } 1001 static inline void vcpu_xsave2_get(struct kvm_vcpu *vcpu, 1002 struct kvm_xsave *xsave) 1003 { 1004 vcpu_ioctl(vcpu, KVM_GET_XSAVE2, xsave); 1005 } 1006 static inline void vcpu_xsave_set(struct kvm_vcpu *vcpu, 1007 struct kvm_xsave *xsave) 1008 { 1009 vcpu_ioctl(vcpu, KVM_SET_XSAVE, xsave); 1010 } 1011 static inline void vcpu_xcrs_get(struct kvm_vcpu *vcpu, 1012 struct kvm_xcrs *xcrs) 1013 { 1014 vcpu_ioctl(vcpu, KVM_GET_XCRS, xcrs); 1015 } 1016 static inline void vcpu_xcrs_set(struct kvm_vcpu *vcpu, struct kvm_xcrs *xcrs) 1017 { 1018 vcpu_ioctl(vcpu, KVM_SET_XCRS, xcrs); 1019 } 1020 1021 const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid, 1022 u32 function, u32 index); 1023 const struct kvm_cpuid2 *kvm_get_supported_cpuid(void); 1024 1025 static inline u32 kvm_cpu_fms(void) 1026 { 1027 return get_cpuid_entry(kvm_get_supported_cpuid(), 0x1, 0)->eax; 1028 } 1029 1030 static inline u32 kvm_cpu_family(void) 1031 { 1032 return x86_family(kvm_cpu_fms()); 1033 } 1034 1035 static inline u32 kvm_cpu_model(void) 1036 { 1037 return x86_model(kvm_cpu_fms()); 1038 } 1039 1040 bool kvm_cpuid_has(const struct kvm_cpuid2 *cpuid, 1041 struct kvm_x86_cpu_feature feature); 1042 1043 static inline bool kvm_cpu_has(struct kvm_x86_cpu_feature feature) 1044 { 1045 return kvm_cpuid_has(kvm_get_supported_cpuid(), feature); 1046 } 1047 1048 u32 kvm_cpuid_property(const struct kvm_cpuid2 *cpuid, 1049 struct kvm_x86_cpu_property property); 1050 1051 static inline u32 kvm_cpu_property(struct kvm_x86_cpu_property property) 1052 { 1053 return kvm_cpuid_property(kvm_get_supported_cpuid(), property); 1054 } 1055 1056 static __always_inline bool kvm_cpu_has_p(struct kvm_x86_cpu_property property) 1057 { 1058 u32 max_leaf; 1059 1060 switch (property.function & 0xc0000000) { 1061 case 0: 1062 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF); 1063 break; 1064 case 0x40000000: 1065 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_KVM_LEAF); 1066 break; 1067 case 0x80000000: 1068 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_EXT_LEAF); 1069 break; 1070 case 0xc0000000: 1071 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF); 1072 } 1073 return max_leaf >= property.function; 1074 } 1075 1076 static inline bool kvm_pmu_has(struct kvm_x86_pmu_feature feature) 1077 { 1078 u32 nr_bits; 1079 1080 if (feature.f.reg == KVM_CPUID_EBX) { 1081 nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); 1082 return nr_bits > feature.f.bit && !kvm_cpu_has(feature.f); 1083 } 1084 1085 TEST_ASSERT_EQ(feature.f.reg, KVM_CPUID_ECX); 1086 nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); 1087 return nr_bits > feature.f.bit || kvm_cpu_has(feature.f); 1088 } 1089 1090 static __always_inline u64 kvm_cpu_supported_xcr0(void) 1091 { 1092 if (!kvm_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) 1093 return 0; 1094 1095 return kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | 1096 ((u64)kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); 1097 } 1098 1099 static inline size_t kvm_cpuid2_size(int nr_entries) 1100 { 1101 return sizeof(struct kvm_cpuid2) + 1102 sizeof(struct kvm_cpuid_entry2) * nr_entries; 1103 } 1104 1105 /* 1106 * Allocate a "struct kvm_cpuid2* instance, with the 0-length arrary of 1107 * entries sized to hold @nr_entries. The caller is responsible for freeing 1108 * the struct. 1109 */ 1110 static inline struct kvm_cpuid2 *allocate_kvm_cpuid2(int nr_entries) 1111 { 1112 struct kvm_cpuid2 *cpuid; 1113 1114 cpuid = malloc(kvm_cpuid2_size(nr_entries)); 1115 TEST_ASSERT(cpuid, "-ENOMEM when allocating kvm_cpuid2"); 1116 1117 cpuid->nent = nr_entries; 1118 1119 return cpuid; 1120 } 1121 1122 void vcpu_init_cpuid(struct kvm_vcpu *vcpu, const struct kvm_cpuid2 *cpuid); 1123 1124 static inline void vcpu_get_cpuid(struct kvm_vcpu *vcpu) 1125 { 1126 vcpu_ioctl(vcpu, KVM_GET_CPUID2, vcpu->cpuid); 1127 } 1128 1129 static inline struct kvm_cpuid_entry2 *__vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu, 1130 u32 function, 1131 u32 index) 1132 { 1133 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first (or equivalent)"); 1134 1135 vcpu_get_cpuid(vcpu); 1136 1137 return (struct kvm_cpuid_entry2 *)get_cpuid_entry(vcpu->cpuid, 1138 function, index); 1139 } 1140 1141 static inline struct kvm_cpuid_entry2 *vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu, 1142 u32 function) 1143 { 1144 return __vcpu_get_cpuid_entry(vcpu, function, 0); 1145 } 1146 1147 static inline int __vcpu_set_cpuid(struct kvm_vcpu *vcpu) 1148 { 1149 int r; 1150 1151 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first"); 1152 r = __vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid); 1153 if (r) 1154 return r; 1155 1156 /* On success, refresh the cache to pick up adjustments made by KVM. */ 1157 vcpu_get_cpuid(vcpu); 1158 return 0; 1159 } 1160 1161 static inline void vcpu_set_cpuid(struct kvm_vcpu *vcpu) 1162 { 1163 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first"); 1164 vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid); 1165 1166 /* Refresh the cache to pick up adjustments made by KVM. */ 1167 vcpu_get_cpuid(vcpu); 1168 } 1169 1170 void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu, 1171 struct kvm_x86_cpu_property property, 1172 u32 value); 1173 void vcpu_set_cpuid_maxphyaddr(struct kvm_vcpu *vcpu, u8 maxphyaddr); 1174 1175 void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, u32 function); 1176 1177 static inline bool vcpu_cpuid_has(struct kvm_vcpu *vcpu, 1178 struct kvm_x86_cpu_feature feature) 1179 { 1180 struct kvm_cpuid_entry2 *entry; 1181 1182 entry = __vcpu_get_cpuid_entry(vcpu, feature.function, feature.index); 1183 return *((&entry->eax) + feature.reg) & BIT(feature.bit); 1184 } 1185 1186 void vcpu_set_or_clear_cpuid_feature(struct kvm_vcpu *vcpu, 1187 struct kvm_x86_cpu_feature feature, 1188 bool set); 1189 1190 static inline void vcpu_set_cpuid_feature(struct kvm_vcpu *vcpu, 1191 struct kvm_x86_cpu_feature feature) 1192 { 1193 vcpu_set_or_clear_cpuid_feature(vcpu, feature, true); 1194 1195 } 1196 1197 static inline void vcpu_clear_cpuid_feature(struct kvm_vcpu *vcpu, 1198 struct kvm_x86_cpu_feature feature) 1199 { 1200 vcpu_set_or_clear_cpuid_feature(vcpu, feature, false); 1201 } 1202 1203 u64 vcpu_get_msr(struct kvm_vcpu *vcpu, u64 msr_index); 1204 int _vcpu_set_msr(struct kvm_vcpu *vcpu, u64 msr_index, u64 msr_value); 1205 1206 /* 1207 * Assert on an MSR access(es) and pretty print the MSR name when possible. 1208 * Note, the caller provides the stringified name so that the name of macro is 1209 * printed, not the value the macro resolves to (due to macro expansion). 1210 */ 1211 #define TEST_ASSERT_MSR(cond, fmt, msr, str, args...) \ 1212 do { \ 1213 if (__builtin_constant_p(msr)) { \ 1214 TEST_ASSERT(cond, fmt, str, args); \ 1215 } else if (!(cond)) { \ 1216 char buf[16]; \ 1217 \ 1218 snprintf(buf, sizeof(buf), "MSR 0x%x", msr); \ 1219 TEST_ASSERT(cond, fmt, buf, args); \ 1220 } \ 1221 } while (0) 1222 1223 /* 1224 * Returns true if KVM should return the last written value when reading an MSR 1225 * from userspace, e.g. the MSR isn't a command MSR, doesn't emulate state that 1226 * is changing, etc. This is NOT an exhaustive list! The intent is to filter 1227 * out MSRs that are not durable _and_ that a selftest wants to write. 1228 */ 1229 static inline bool is_durable_msr(u32 msr) 1230 { 1231 return msr != MSR_IA32_TSC; 1232 } 1233 1234 #define vcpu_set_msr(vcpu, msr, val) \ 1235 do { \ 1236 u64 r, v = val; \ 1237 \ 1238 TEST_ASSERT_MSR(_vcpu_set_msr(vcpu, msr, v) == 1, \ 1239 "KVM_SET_MSRS failed on %s, value = 0x%lx", msr, #msr, v); \ 1240 if (!is_durable_msr(msr)) \ 1241 break; \ 1242 r = vcpu_get_msr(vcpu, msr); \ 1243 TEST_ASSERT_MSR(r == v, "Set %s to '0x%lx', got back '0x%lx'", msr, #msr, v, r);\ 1244 } while (0) 1245 1246 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits); 1247 void kvm_init_vm_address_properties(struct kvm_vm *vm); 1248 1249 struct ex_regs { 1250 u64 rax, rcx, rdx, rbx; 1251 u64 rbp, rsi, rdi; 1252 u64 r8, r9, r10, r11; 1253 u64 r12, r13, r14, r15; 1254 u64 vector; 1255 u64 error_code; 1256 u64 rip; 1257 u64 cs; 1258 u64 rflags; 1259 }; 1260 1261 struct idt_entry { 1262 u16 offset0; 1263 u16 selector; 1264 u16 ist : 3; 1265 u16 : 5; 1266 u16 type : 4; 1267 u16 : 1; 1268 u16 dpl : 2; 1269 u16 p : 1; 1270 u16 offset1; 1271 u32 offset2; u32 reserved; 1272 }; 1273 1274 void vm_install_exception_handler(struct kvm_vm *vm, int vector, 1275 void (*handler)(struct ex_regs *)); 1276 1277 gva_t vm_alloc_stack(struct kvm_vm *vm, int nr_pages); 1278 1279 /* 1280 * Exception fixup morphs #DE to an arbitrary magic vector so that '0' can be 1281 * used to signal "no expcetion". 1282 */ 1283 #define KVM_MAGIC_DE_VECTOR 0xff 1284 1285 /* If a toddler were to say "abracadabra". */ 1286 #define KVM_EXCEPTION_MAGIC 0xabacadabaULL 1287 1288 /* 1289 * KVM selftest exception fixup uses registers to coordinate with the exception 1290 * handler, versus the kernel's in-memory tables and KVM-Unit-Tests's in-memory 1291 * per-CPU data. Using only registers avoids having to map memory into the 1292 * guest, doesn't require a valid, stable GS.base, and reduces the risk of 1293 * for recursive faults when accessing memory in the handler. The downside to 1294 * using registers is that it restricts what registers can be used by the actual 1295 * instruction. But, selftests are 64-bit only, making register* pressure a 1296 * minor concern. Use r9-r11 as they are volatile, i.e. don't need to be saved 1297 * by the callee, and except for r11 are not implicit parameters to any 1298 * instructions. Ideally, fixup would use r8-r10 and thus avoid implicit 1299 * parameters entirely, but Hyper-V's hypercall ABI uses r8 and testing Hyper-V 1300 * is higher priority than testing non-faulting SYSCALL/SYSRET. 1301 * 1302 * Note, the fixup handler deliberately does not handle #DE, i.e. the vector 1303 * is guaranteed to be non-zero on fault. 1304 * 1305 * REGISTER INPUTS: 1306 * r9 = MAGIC 1307 * r10 = RIP 1308 * r11 = new RIP on fault 1309 * 1310 * REGISTER OUTPUTS: 1311 * r9 = exception vector (non-zero) 1312 * r10 = error code 1313 */ 1314 #define __KVM_ASM_SAFE(insn, fep) \ 1315 "mov $" __stringify(KVM_EXCEPTION_MAGIC) ", %%r9\n\t" \ 1316 "lea 1f(%%rip), %%r10\n\t" \ 1317 "lea 2f(%%rip), %%r11\n\t" \ 1318 fep "1: " insn "\n\t" \ 1319 "xor %%r9, %%r9\n\t" \ 1320 "2:\n\t" \ 1321 "mov %%r9b, %[vector]\n\t" \ 1322 "mov %%r10, %[error_code]\n\t" 1323 1324 #define KVM_ASM_SAFE(insn) __KVM_ASM_SAFE(insn, "") 1325 #define KVM_ASM_SAFE_FEP(insn) __KVM_ASM_SAFE(insn, KVM_FEP) 1326 1327 #define KVM_ASM_SAFE_OUTPUTS(v, ec) [vector] "=qm"(v), [error_code] "=rm"(ec) 1328 #define KVM_ASM_SAFE_CLOBBERS "r9", "r10", "r11" 1329 1330 #define kvm_asm_safe(insn, inputs...) \ 1331 ({ \ 1332 u64 ign_error_code; \ 1333 u8 vector; \ 1334 \ 1335 asm volatile(KVM_ASM_SAFE(insn) \ 1336 : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code) \ 1337 : inputs \ 1338 : KVM_ASM_SAFE_CLOBBERS); \ 1339 vector; \ 1340 }) 1341 1342 #define kvm_asm_safe_ec(insn, error_code, inputs...) \ 1343 ({ \ 1344 u8 vector; \ 1345 \ 1346 asm volatile(KVM_ASM_SAFE(insn) \ 1347 : KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1348 : inputs \ 1349 : KVM_ASM_SAFE_CLOBBERS); \ 1350 vector; \ 1351 }) 1352 1353 #define kvm_asm_safe_fep(insn, inputs...) \ 1354 ({ \ 1355 u64 ign_error_code; \ 1356 u8 vector; \ 1357 \ 1358 asm volatile(KVM_ASM_SAFE_FEP(insn) \ 1359 : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code) \ 1360 : inputs \ 1361 : KVM_ASM_SAFE_CLOBBERS); \ 1362 vector; \ 1363 }) 1364 1365 #define kvm_asm_safe_ec_fep(insn, error_code, inputs...) \ 1366 ({ \ 1367 u8 vector; \ 1368 \ 1369 asm volatile(KVM_ASM_SAFE_FEP(insn) \ 1370 : KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1371 : inputs \ 1372 : KVM_ASM_SAFE_CLOBBERS); \ 1373 vector; \ 1374 }) 1375 1376 #define BUILD_READ_U64_SAFE_HELPER(insn, _fep, _FEP) \ 1377 static inline u8 insn##_safe ##_fep(u32 idx, u64 *val) \ 1378 { \ 1379 u64 error_code; \ 1380 u8 vector; \ 1381 u32 a, d; \ 1382 \ 1383 asm volatile(KVM_ASM_SAFE##_FEP(#insn) \ 1384 : "=a"(a), "=d"(d), \ 1385 KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1386 : "c"(idx) \ 1387 : KVM_ASM_SAFE_CLOBBERS); \ 1388 \ 1389 *val = (u64)a | ((u64)d << 32); \ 1390 return vector; \ 1391 } 1392 1393 /* 1394 * Generate {insn}_safe() and {insn}_safe_fep() helpers for instructions that 1395 * use ECX as in input index, and EDX:EAX as a 64-bit output. 1396 */ 1397 #define BUILD_READ_U64_SAFE_HELPERS(insn) \ 1398 BUILD_READ_U64_SAFE_HELPER(insn, , ) \ 1399 BUILD_READ_U64_SAFE_HELPER(insn, _fep, _FEP) \ 1400 1401 BUILD_READ_U64_SAFE_HELPERS(rdmsr) 1402 BUILD_READ_U64_SAFE_HELPERS(rdpmc) 1403 BUILD_READ_U64_SAFE_HELPERS(xgetbv) 1404 1405 static inline u8 wrmsr_safe(u32 msr, u64 val) 1406 { 1407 return kvm_asm_safe("wrmsr", "a"(val & -1u), "d"(val >> 32), "c"(msr)); 1408 } 1409 1410 static inline u8 xsetbv_safe(u32 index, u64 value) 1411 { 1412 u32 eax = value; 1413 u32 edx = value >> 32; 1414 1415 return kvm_asm_safe("xsetbv", "a" (eax), "d" (edx), "c" (index)); 1416 } 1417 1418 bool kvm_is_tdp_enabled(void); 1419 1420 static inline bool get_kvm_intel_param_bool(const char *param) 1421 { 1422 return kvm_get_module_param_bool("kvm_intel", param); 1423 } 1424 1425 static inline bool get_kvm_amd_param_bool(const char *param) 1426 { 1427 return kvm_get_module_param_bool("kvm_amd", param); 1428 } 1429 1430 static inline int get_kvm_intel_param_integer(const char *param) 1431 { 1432 return kvm_get_module_param_integer("kvm_intel", param); 1433 } 1434 1435 static inline int get_kvm_amd_param_integer(const char *param) 1436 { 1437 return kvm_get_module_param_integer("kvm_amd", param); 1438 } 1439 1440 static inline bool kvm_is_pmu_enabled(void) 1441 { 1442 return get_kvm_param_bool("enable_pmu"); 1443 } 1444 1445 static inline bool kvm_is_mediated_pmu_enabled(void) 1446 { 1447 if (host_cpu_is_intel) 1448 return get_kvm_intel_param_bool("enable_mediated_pmu"); 1449 1450 return get_kvm_amd_param_bool("enable_mediated_pmu"); 1451 } 1452 1453 static inline bool kvm_is_forced_emulation_enabled(void) 1454 { 1455 return !!get_kvm_param_integer("force_emulation_prefix"); 1456 } 1457 1458 static inline bool kvm_is_unrestricted_guest_enabled(void) 1459 { 1460 return get_kvm_intel_param_bool("unrestricted_guest"); 1461 } 1462 1463 static inline bool kvm_is_ignore_msrs(void) 1464 { 1465 return get_kvm_param_bool("ignore_msrs"); 1466 } 1467 1468 static inline bool kvm_is_lbrv_enabled(void) 1469 { 1470 return !!get_kvm_amd_param_integer("lbrv"); 1471 } 1472 1473 u64 *vm_get_pte(struct kvm_vm *vm, gva_t gva); 1474 1475 u64 kvm_hypercall(u64 nr, u64 a0, u64 a1, u64 a2, u64 a3); 1476 u64 __xen_hypercall(u64 nr, u64 a0, void *a1); 1477 void xen_hypercall(u64 nr, u64 a0, void *a1); 1478 1479 static inline u64 __kvm_hypercall_map_gpa_range(gpa_t gpa, u64 size, u64 flags) 1480 { 1481 return kvm_hypercall(KVM_HC_MAP_GPA_RANGE, gpa, size >> PAGE_SHIFT, flags, 0); 1482 } 1483 1484 static inline void kvm_hypercall_map_gpa_range(gpa_t gpa, u64 size, u64 flags) 1485 { 1486 u64 ret = __kvm_hypercall_map_gpa_range(gpa, size, flags); 1487 1488 GUEST_ASSERT(!ret); 1489 } 1490 1491 /* 1492 * Execute HLT in an STI interrupt shadow to ensure that a pending IRQ that's 1493 * intended to be a wake event arrives *after* HLT is executed. Modern CPUs, 1494 * except for a few oddballs that KVM is unlikely to run on, block IRQs for one 1495 * instruction after STI, *if* RFLAGS.IF=0 before STI. Note, Intel CPUs may 1496 * block other events beyond regular IRQs, e.g. may block NMIs and SMIs too. 1497 */ 1498 static inline void safe_halt(void) 1499 { 1500 asm volatile("sti; hlt"); 1501 } 1502 1503 /* 1504 * Enable interrupts and ensure that interrupts are evaluated upon return from 1505 * this function, i.e. execute a nop to consume the STi interrupt shadow. 1506 */ 1507 static inline void sti_nop(void) 1508 { 1509 asm volatile ("sti; nop"); 1510 } 1511 1512 /* 1513 * Enable interrupts for one instruction (nop), to allow the CPU to process all 1514 * interrupts that are already pending. 1515 */ 1516 static inline void sti_nop_cli(void) 1517 { 1518 asm volatile ("sti; nop; cli"); 1519 } 1520 1521 static inline void sti(void) 1522 { 1523 asm volatile("sti"); 1524 } 1525 1526 static inline void cli(void) 1527 { 1528 asm volatile ("cli"); 1529 } 1530 1531 void __vm_xsave_require_permission(u64 xfeature, const char *name); 1532 1533 #define vm_xsave_require_permission(xfeature) \ 1534 __vm_xsave_require_permission(xfeature, #xfeature) 1535 1536 enum pg_level { 1537 PG_LEVEL_NONE, 1538 PG_LEVEL_4K, 1539 PG_LEVEL_2M, 1540 PG_LEVEL_1G, 1541 PG_LEVEL_512G, 1542 PG_LEVEL_256T 1543 }; 1544 1545 #define PG_LEVEL_SHIFT(_level) ((_level - 1) * 9 + 12) 1546 #define PG_LEVEL_SIZE(_level) (1ull << PG_LEVEL_SHIFT(_level)) 1547 1548 #define PG_SIZE_4K PG_LEVEL_SIZE(PG_LEVEL_4K) 1549 #define PG_SIZE_2M PG_LEVEL_SIZE(PG_LEVEL_2M) 1550 #define PG_SIZE_1G PG_LEVEL_SIZE(PG_LEVEL_1G) 1551 1552 #define PTE_PRESENT_MASK(mmu) ((mmu)->arch.pte_masks.present) 1553 #define PTE_WRITABLE_MASK(mmu) ((mmu)->arch.pte_masks.writable) 1554 #define PTE_USER_MASK(mmu) ((mmu)->arch.pte_masks.user) 1555 #define PTE_READABLE_MASK(mmu) ((mmu)->arch.pte_masks.readable) 1556 #define PTE_EXECUTABLE_MASK(mmu) ((mmu)->arch.pte_masks.executable) 1557 #define PTE_ACCESSED_MASK(mmu) ((mmu)->arch.pte_masks.accessed) 1558 #define PTE_DIRTY_MASK(mmu) ((mmu)->arch.pte_masks.dirty) 1559 #define PTE_HUGE_MASK(mmu) ((mmu)->arch.pte_masks.huge) 1560 #define PTE_NX_MASK(mmu) ((mmu)->arch.pte_masks.nx) 1561 #define PTE_C_BIT_MASK(mmu) ((mmu)->arch.pte_masks.c) 1562 #define PTE_S_BIT_MASK(mmu) ((mmu)->arch.pte_masks.s) 1563 #define PTE_ALWAYS_SET_MASK(mmu) ((mmu)->arch.pte_masks.always_set) 1564 1565 /* 1566 * For PTEs without a PRESENT bit (i.e. EPT entries), treat the PTE as present 1567 * if it's executable or readable, as EPT supports execute-only PTEs, but not 1568 * write-only PTEs. 1569 */ 1570 #define is_present_pte(mmu, pte) \ 1571 (PTE_PRESENT_MASK(mmu) ? \ 1572 !!(*(pte) & PTE_PRESENT_MASK(mmu)) : \ 1573 !!(*(pte) & (PTE_READABLE_MASK(mmu) | PTE_EXECUTABLE_MASK(mmu)))) 1574 #define is_executable_pte(mmu, pte) \ 1575 ((*(pte) & (PTE_EXECUTABLE_MASK(mmu) | PTE_NX_MASK(mmu))) == PTE_EXECUTABLE_MASK(mmu)) 1576 #define is_writable_pte(mmu, pte) (!!(*(pte) & PTE_WRITABLE_MASK(mmu))) 1577 #define is_user_pte(mmu, pte) (!!(*(pte) & PTE_USER_MASK(mmu))) 1578 #define is_accessed_pte(mmu, pte) (!!(*(pte) & PTE_ACCESSED_MASK(mmu))) 1579 #define is_dirty_pte(mmu, pte) (!!(*(pte) & PTE_DIRTY_MASK(mmu))) 1580 #define is_huge_pte(mmu, pte) (!!(*(pte) & PTE_HUGE_MASK(mmu))) 1581 #define is_nx_pte(mmu, pte) (!is_executable_pte(mmu, pte)) 1582 1583 void tdp_mmu_init(struct kvm_vm *vm, int pgtable_levels, 1584 struct pte_masks *pte_masks); 1585 1586 void __virt_pg_map(struct kvm_vm *vm, struct kvm_mmu *mmu, gva_t gva, 1587 gpa_t gpa, int level); 1588 void virt_map_level(struct kvm_vm *vm, gva_t gva, gpa_t gpa, 1589 u64 nr_bytes, int level); 1590 1591 void vm_enable_tdp(struct kvm_vm *vm); 1592 bool kvm_cpu_has_tdp(void); 1593 void tdp_map(struct kvm_vm *vm, gpa_t l2_gpa, gpa_t gpa, u64 size); 1594 void tdp_identity_map_default_memslots(struct kvm_vm *vm); 1595 void tdp_identity_map_1g(struct kvm_vm *vm, u64 addr, u64 size); 1596 u64 *tdp_get_pte(struct kvm_vm *vm, u64 l2_gpa); 1597 1598 /* 1599 * Basic CPU control in CR0 1600 */ 1601 #define X86_CR0_PE (1UL<<0) /* Protection Enable */ 1602 #define X86_CR0_MP (1UL<<1) /* Monitor Coprocessor */ 1603 #define X86_CR0_EM (1UL<<2) /* Emulation */ 1604 #define X86_CR0_TS (1UL<<3) /* Task Switched */ 1605 #define X86_CR0_ET (1UL<<4) /* Extension Type */ 1606 #define X86_CR0_NE (1UL<<5) /* Numeric Error */ 1607 #define X86_CR0_WP (1UL<<16) /* Write Protect */ 1608 #define X86_CR0_AM (1UL<<18) /* Alignment Mask */ 1609 #define X86_CR0_NW (1UL<<29) /* Not Write-through */ 1610 #define X86_CR0_CD (1UL<<30) /* Cache Disable */ 1611 #define X86_CR0_PG (1UL<<31) /* Paging */ 1612 1613 #define PFERR_PRESENT_BIT 0 1614 #define PFERR_WRITE_BIT 1 1615 #define PFERR_USER_BIT 2 1616 #define PFERR_RSVD_BIT 3 1617 #define PFERR_FETCH_BIT 4 1618 #define PFERR_PK_BIT 5 1619 #define PFERR_SGX_BIT 15 1620 #define PFERR_GUEST_FINAL_BIT 32 1621 #define PFERR_GUEST_PAGE_BIT 33 1622 #define PFERR_IMPLICIT_ACCESS_BIT 48 1623 1624 #define PFERR_PRESENT_MASK BIT(PFERR_PRESENT_BIT) 1625 #define PFERR_WRITE_MASK BIT(PFERR_WRITE_BIT) 1626 #define PFERR_USER_MASK BIT(PFERR_USER_BIT) 1627 #define PFERR_RSVD_MASK BIT(PFERR_RSVD_BIT) 1628 #define PFERR_FETCH_MASK BIT(PFERR_FETCH_BIT) 1629 #define PFERR_PK_MASK BIT(PFERR_PK_BIT) 1630 #define PFERR_SGX_MASK BIT(PFERR_SGX_BIT) 1631 #define PFERR_GUEST_FINAL_MASK BIT_ULL(PFERR_GUEST_FINAL_BIT) 1632 #define PFERR_GUEST_PAGE_MASK BIT_ULL(PFERR_GUEST_PAGE_BIT) 1633 #define PFERR_IMPLICIT_ACCESS BIT_ULL(PFERR_IMPLICIT_ACCESS_BIT) 1634 1635 #define EPT_VIOLATION_ACC_READ BIT(0) 1636 #define EPT_VIOLATION_ACC_WRITE BIT(1) 1637 #define EPT_VIOLATION_ACC_INSTR BIT(2) 1638 #define EPT_VIOLATION_PROT_READ BIT(3) 1639 #define EPT_VIOLATION_PROT_WRITE BIT(4) 1640 #define EPT_VIOLATION_PROT_EXEC BIT(5) 1641 #define EPT_VIOLATION_GVA_IS_VALID BIT(7) 1642 #define EPT_VIOLATION_GVA_TRANSLATED BIT(8) 1643 1644 bool sys_clocksource_is_based_on_tsc(void); 1645 1646 #endif /* SELFTEST_KVM_PROCESSOR_H */ 1647