1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2018, Google LLC. 4 */ 5 6 #ifndef SELFTEST_KVM_PROCESSOR_H 7 #define SELFTEST_KVM_PROCESSOR_H 8 9 #include <assert.h> 10 #include <stdint.h> 11 #include <syscall.h> 12 13 #include <asm/msr-index.h> 14 #include <asm/prctl.h> 15 16 #include <linux/kvm_para.h> 17 #include <linux/stringify.h> 18 19 #include "kvm_util.h" 20 #include "ucall_common.h" 21 22 extern bool host_cpu_is_intel; 23 extern bool host_cpu_is_amd; 24 extern uint64_t guest_tsc_khz; 25 26 #ifndef MAX_NR_CPUID_ENTRIES 27 #define MAX_NR_CPUID_ENTRIES 100 28 #endif 29 30 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 31 32 /* Forced emulation prefix, used to invoke the emulator unconditionally. */ 33 #define KVM_FEP "ud2; .byte 'k', 'v', 'm';" 34 35 #define NMI_VECTOR 0x02 36 37 #define X86_EFLAGS_FIXED (1u << 1) 38 39 #define X86_CR4_VME (1ul << 0) 40 #define X86_CR4_PVI (1ul << 1) 41 #define X86_CR4_TSD (1ul << 2) 42 #define X86_CR4_DE (1ul << 3) 43 #define X86_CR4_PSE (1ul << 4) 44 #define X86_CR4_PAE (1ul << 5) 45 #define X86_CR4_MCE (1ul << 6) 46 #define X86_CR4_PGE (1ul << 7) 47 #define X86_CR4_PCE (1ul << 8) 48 #define X86_CR4_OSFXSR (1ul << 9) 49 #define X86_CR4_OSXMMEXCPT (1ul << 10) 50 #define X86_CR4_UMIP (1ul << 11) 51 #define X86_CR4_LA57 (1ul << 12) 52 #define X86_CR4_VMXE (1ul << 13) 53 #define X86_CR4_SMXE (1ul << 14) 54 #define X86_CR4_FSGSBASE (1ul << 16) 55 #define X86_CR4_PCIDE (1ul << 17) 56 #define X86_CR4_OSXSAVE (1ul << 18) 57 #define X86_CR4_SMEP (1ul << 20) 58 #define X86_CR4_SMAP (1ul << 21) 59 #define X86_CR4_PKE (1ul << 22) 60 61 struct xstate_header { 62 u64 xstate_bv; 63 u64 xcomp_bv; 64 u64 reserved[6]; 65 } __attribute__((packed)); 66 67 struct xstate { 68 u8 i387[512]; 69 struct xstate_header header; 70 u8 extended_state_area[0]; 71 } __attribute__ ((packed, aligned (64))); 72 73 #define XFEATURE_MASK_FP BIT_ULL(0) 74 #define XFEATURE_MASK_SSE BIT_ULL(1) 75 #define XFEATURE_MASK_YMM BIT_ULL(2) 76 #define XFEATURE_MASK_BNDREGS BIT_ULL(3) 77 #define XFEATURE_MASK_BNDCSR BIT_ULL(4) 78 #define XFEATURE_MASK_OPMASK BIT_ULL(5) 79 #define XFEATURE_MASK_ZMM_Hi256 BIT_ULL(6) 80 #define XFEATURE_MASK_Hi16_ZMM BIT_ULL(7) 81 #define XFEATURE_MASK_PT BIT_ULL(8) 82 #define XFEATURE_MASK_PKRU BIT_ULL(9) 83 #define XFEATURE_MASK_PASID BIT_ULL(10) 84 #define XFEATURE_MASK_CET_USER BIT_ULL(11) 85 #define XFEATURE_MASK_CET_KERNEL BIT_ULL(12) 86 #define XFEATURE_MASK_LBR BIT_ULL(15) 87 #define XFEATURE_MASK_XTILE_CFG BIT_ULL(17) 88 #define XFEATURE_MASK_XTILE_DATA BIT_ULL(18) 89 90 #define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK | \ 91 XFEATURE_MASK_ZMM_Hi256 | \ 92 XFEATURE_MASK_Hi16_ZMM) 93 #define XFEATURE_MASK_XTILE (XFEATURE_MASK_XTILE_DATA | \ 94 XFEATURE_MASK_XTILE_CFG) 95 96 /* Note, these are ordered alphabetically to match kvm_cpuid_entry2. Eww. */ 97 enum cpuid_output_regs { 98 KVM_CPUID_EAX, 99 KVM_CPUID_EBX, 100 KVM_CPUID_ECX, 101 KVM_CPUID_EDX 102 }; 103 104 /* 105 * Pack the information into a 64-bit value so that each X86_FEATURE_XXX can be 106 * passed by value with no overhead. 107 */ 108 struct kvm_x86_cpu_feature { 109 u32 function; 110 u16 index; 111 u8 reg; 112 u8 bit; 113 }; 114 #define KVM_X86_CPU_FEATURE(fn, idx, gpr, __bit) \ 115 ({ \ 116 struct kvm_x86_cpu_feature feature = { \ 117 .function = fn, \ 118 .index = idx, \ 119 .reg = KVM_CPUID_##gpr, \ 120 .bit = __bit, \ 121 }; \ 122 \ 123 kvm_static_assert((fn & 0xc0000000) == 0 || \ 124 (fn & 0xc0000000) == 0x40000000 || \ 125 (fn & 0xc0000000) == 0x80000000 || \ 126 (fn & 0xc0000000) == 0xc0000000); \ 127 kvm_static_assert(idx < BIT(sizeof(feature.index) * BITS_PER_BYTE)); \ 128 feature; \ 129 }) 130 131 /* 132 * Basic Leafs, a.k.a. Intel defined 133 */ 134 #define X86_FEATURE_MWAIT KVM_X86_CPU_FEATURE(0x1, 0, ECX, 3) 135 #define X86_FEATURE_VMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 5) 136 #define X86_FEATURE_SMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 6) 137 #define X86_FEATURE_PDCM KVM_X86_CPU_FEATURE(0x1, 0, ECX, 15) 138 #define X86_FEATURE_PCID KVM_X86_CPU_FEATURE(0x1, 0, ECX, 17) 139 #define X86_FEATURE_X2APIC KVM_X86_CPU_FEATURE(0x1, 0, ECX, 21) 140 #define X86_FEATURE_MOVBE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 22) 141 #define X86_FEATURE_TSC_DEADLINE_TIMER KVM_X86_CPU_FEATURE(0x1, 0, ECX, 24) 142 #define X86_FEATURE_XSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 26) 143 #define X86_FEATURE_OSXSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 27) 144 #define X86_FEATURE_RDRAND KVM_X86_CPU_FEATURE(0x1, 0, ECX, 30) 145 #define X86_FEATURE_HYPERVISOR KVM_X86_CPU_FEATURE(0x1, 0, ECX, 31) 146 #define X86_FEATURE_PAE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 6) 147 #define X86_FEATURE_MCE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 7) 148 #define X86_FEATURE_APIC KVM_X86_CPU_FEATURE(0x1, 0, EDX, 9) 149 #define X86_FEATURE_CLFLUSH KVM_X86_CPU_FEATURE(0x1, 0, EDX, 19) 150 #define X86_FEATURE_XMM KVM_X86_CPU_FEATURE(0x1, 0, EDX, 25) 151 #define X86_FEATURE_XMM2 KVM_X86_CPU_FEATURE(0x1, 0, EDX, 26) 152 #define X86_FEATURE_FSGSBASE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 0) 153 #define X86_FEATURE_TSC_ADJUST KVM_X86_CPU_FEATURE(0x7, 0, EBX, 1) 154 #define X86_FEATURE_SGX KVM_X86_CPU_FEATURE(0x7, 0, EBX, 2) 155 #define X86_FEATURE_HLE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 4) 156 #define X86_FEATURE_SMEP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 7) 157 #define X86_FEATURE_INVPCID KVM_X86_CPU_FEATURE(0x7, 0, EBX, 10) 158 #define X86_FEATURE_RTM KVM_X86_CPU_FEATURE(0x7, 0, EBX, 11) 159 #define X86_FEATURE_MPX KVM_X86_CPU_FEATURE(0x7, 0, EBX, 14) 160 #define X86_FEATURE_SMAP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 20) 161 #define X86_FEATURE_PCOMMIT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 22) 162 #define X86_FEATURE_CLFLUSHOPT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 23) 163 #define X86_FEATURE_CLWB KVM_X86_CPU_FEATURE(0x7, 0, EBX, 24) 164 #define X86_FEATURE_UMIP KVM_X86_CPU_FEATURE(0x7, 0, ECX, 2) 165 #define X86_FEATURE_PKU KVM_X86_CPU_FEATURE(0x7, 0, ECX, 3) 166 #define X86_FEATURE_OSPKE KVM_X86_CPU_FEATURE(0x7, 0, ECX, 4) 167 #define X86_FEATURE_LA57 KVM_X86_CPU_FEATURE(0x7, 0, ECX, 16) 168 #define X86_FEATURE_RDPID KVM_X86_CPU_FEATURE(0x7, 0, ECX, 22) 169 #define X86_FEATURE_SGX_LC KVM_X86_CPU_FEATURE(0x7, 0, ECX, 30) 170 #define X86_FEATURE_SHSTK KVM_X86_CPU_FEATURE(0x7, 0, ECX, 7) 171 #define X86_FEATURE_IBT KVM_X86_CPU_FEATURE(0x7, 0, EDX, 20) 172 #define X86_FEATURE_AMX_TILE KVM_X86_CPU_FEATURE(0x7, 0, EDX, 24) 173 #define X86_FEATURE_SPEC_CTRL KVM_X86_CPU_FEATURE(0x7, 0, EDX, 26) 174 #define X86_FEATURE_ARCH_CAPABILITIES KVM_X86_CPU_FEATURE(0x7, 0, EDX, 29) 175 #define X86_FEATURE_PKS KVM_X86_CPU_FEATURE(0x7, 0, ECX, 31) 176 #define X86_FEATURE_XTILECFG KVM_X86_CPU_FEATURE(0xD, 0, EAX, 17) 177 #define X86_FEATURE_XTILEDATA KVM_X86_CPU_FEATURE(0xD, 0, EAX, 18) 178 #define X86_FEATURE_XSAVES KVM_X86_CPU_FEATURE(0xD, 1, EAX, 3) 179 #define X86_FEATURE_XFD KVM_X86_CPU_FEATURE(0xD, 1, EAX, 4) 180 #define X86_FEATURE_XTILEDATA_XFD KVM_X86_CPU_FEATURE(0xD, 18, ECX, 2) 181 182 /* 183 * Extended Leafs, a.k.a. AMD defined 184 */ 185 #define X86_FEATURE_SVM KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 2) 186 #define X86_FEATURE_PERFCTR_CORE KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 23) 187 #define X86_FEATURE_PERFCTR_NB KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 24) 188 #define X86_FEATURE_PERFCTR_LLC KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 28) 189 #define X86_FEATURE_NX KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 20) 190 #define X86_FEATURE_GBPAGES KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 26) 191 #define X86_FEATURE_RDTSCP KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 27) 192 #define X86_FEATURE_LM KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 29) 193 #define X86_FEATURE_INVTSC KVM_X86_CPU_FEATURE(0x80000007, 0, EDX, 8) 194 #define X86_FEATURE_RDPRU KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 4) 195 #define X86_FEATURE_AMD_IBPB KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 12) 196 #define X86_FEATURE_NPT KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 0) 197 #define X86_FEATURE_LBRV KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 1) 198 #define X86_FEATURE_NRIPS KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 3) 199 #define X86_FEATURE_TSCRATEMSR KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 4) 200 #define X86_FEATURE_PAUSEFILTER KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 10) 201 #define X86_FEATURE_PFTHRESHOLD KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 12) 202 #define X86_FEATURE_VGIF KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 16) 203 #define X86_FEATURE_IDLE_HLT KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 30) 204 #define X86_FEATURE_SEV KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 1) 205 #define X86_FEATURE_SEV_ES KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 3) 206 #define X86_FEATURE_SEV_SNP KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 4) 207 #define X86_FEATURE_PERFMON_V2 KVM_X86_CPU_FEATURE(0x80000022, 0, EAX, 0) 208 #define X86_FEATURE_LBR_PMC_FREEZE KVM_X86_CPU_FEATURE(0x80000022, 0, EAX, 2) 209 210 /* 211 * KVM defined paravirt features. 212 */ 213 #define X86_FEATURE_KVM_CLOCKSOURCE KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 0) 214 #define X86_FEATURE_KVM_NOP_IO_DELAY KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 1) 215 #define X86_FEATURE_KVM_MMU_OP KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 2) 216 #define X86_FEATURE_KVM_CLOCKSOURCE2 KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 3) 217 #define X86_FEATURE_KVM_ASYNC_PF KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 4) 218 #define X86_FEATURE_KVM_STEAL_TIME KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 5) 219 #define X86_FEATURE_KVM_PV_EOI KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 6) 220 #define X86_FEATURE_KVM_PV_UNHALT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 7) 221 /* Bit 8 apparently isn't used?!?! */ 222 #define X86_FEATURE_KVM_PV_TLB_FLUSH KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 9) 223 #define X86_FEATURE_KVM_ASYNC_PF_VMEXIT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 10) 224 #define X86_FEATURE_KVM_PV_SEND_IPI KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 11) 225 #define X86_FEATURE_KVM_POLL_CONTROL KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 12) 226 #define X86_FEATURE_KVM_PV_SCHED_YIELD KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 13) 227 #define X86_FEATURE_KVM_ASYNC_PF_INT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 14) 228 #define X86_FEATURE_KVM_MSI_EXT_DEST_ID KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 15) 229 #define X86_FEATURE_KVM_HC_MAP_GPA_RANGE KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 16) 230 #define X86_FEATURE_KVM_MIGRATION_CONTROL KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 17) 231 232 /* 233 * Same idea as X86_FEATURE_XXX, but X86_PROPERTY_XXX retrieves a multi-bit 234 * value/property as opposed to a single-bit feature. Again, pack the info 235 * into a 64-bit value to pass by value with no overhead. 236 */ 237 struct kvm_x86_cpu_property { 238 u32 function; 239 u8 index; 240 u8 reg; 241 u8 lo_bit; 242 u8 hi_bit; 243 }; 244 #define KVM_X86_CPU_PROPERTY(fn, idx, gpr, low_bit, high_bit) \ 245 ({ \ 246 struct kvm_x86_cpu_property property = { \ 247 .function = fn, \ 248 .index = idx, \ 249 .reg = KVM_CPUID_##gpr, \ 250 .lo_bit = low_bit, \ 251 .hi_bit = high_bit, \ 252 }; \ 253 \ 254 kvm_static_assert(low_bit < high_bit); \ 255 kvm_static_assert((fn & 0xc0000000) == 0 || \ 256 (fn & 0xc0000000) == 0x40000000 || \ 257 (fn & 0xc0000000) == 0x80000000 || \ 258 (fn & 0xc0000000) == 0xc0000000); \ 259 kvm_static_assert(idx < BIT(sizeof(property.index) * BITS_PER_BYTE)); \ 260 property; \ 261 }) 262 263 #define X86_PROPERTY_MAX_BASIC_LEAF KVM_X86_CPU_PROPERTY(0, 0, EAX, 0, 31) 264 #define X86_PROPERTY_PMU_VERSION KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 0, 7) 265 #define X86_PROPERTY_PMU_NR_GP_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 8, 15) 266 #define X86_PROPERTY_PMU_GP_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 16, 23) 267 #define X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 24, 31) 268 #define X86_PROPERTY_PMU_EVENTS_MASK KVM_X86_CPU_PROPERTY(0xa, 0, EBX, 0, 12) 269 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK KVM_X86_CPU_PROPERTY(0xa, 0, ECX, 0, 31) 270 #define X86_PROPERTY_PMU_NR_FIXED_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EDX, 0, 4) 271 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0, EDX, 5, 12) 272 273 #define X86_PROPERTY_SUPPORTED_XCR0_LO KVM_X86_CPU_PROPERTY(0xd, 0, EAX, 0, 31) 274 #define X86_PROPERTY_XSTATE_MAX_SIZE_XCR0 KVM_X86_CPU_PROPERTY(0xd, 0, EBX, 0, 31) 275 #define X86_PROPERTY_XSTATE_MAX_SIZE KVM_X86_CPU_PROPERTY(0xd, 0, ECX, 0, 31) 276 #define X86_PROPERTY_SUPPORTED_XCR0_HI KVM_X86_CPU_PROPERTY(0xd, 0, EDX, 0, 31) 277 278 #define X86_PROPERTY_XSTATE_TILE_SIZE KVM_X86_CPU_PROPERTY(0xd, 18, EAX, 0, 31) 279 #define X86_PROPERTY_XSTATE_TILE_OFFSET KVM_X86_CPU_PROPERTY(0xd, 18, EBX, 0, 31) 280 #define X86_PROPERTY_AMX_MAX_PALETTE_TABLES KVM_X86_CPU_PROPERTY(0x1d, 0, EAX, 0, 31) 281 #define X86_PROPERTY_AMX_TOTAL_TILE_BYTES KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 0, 15) 282 #define X86_PROPERTY_AMX_BYTES_PER_TILE KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 16, 31) 283 #define X86_PROPERTY_AMX_BYTES_PER_ROW KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 0, 15) 284 #define X86_PROPERTY_AMX_NR_TILE_REGS KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 16, 31) 285 #define X86_PROPERTY_AMX_MAX_ROWS KVM_X86_CPU_PROPERTY(0x1d, 1, ECX, 0, 15) 286 287 #define X86_PROPERTY_MAX_KVM_LEAF KVM_X86_CPU_PROPERTY(0x40000000, 0, EAX, 0, 31) 288 289 #define X86_PROPERTY_MAX_EXT_LEAF KVM_X86_CPU_PROPERTY(0x80000000, 0, EAX, 0, 31) 290 #define X86_PROPERTY_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 0, 7) 291 #define X86_PROPERTY_MAX_VIRT_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 8, 15) 292 #define X86_PROPERTY_GUEST_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 16, 23) 293 #define X86_PROPERTY_SEV_C_BIT KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 0, 5) 294 #define X86_PROPERTY_PHYS_ADDR_REDUCTION KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 6, 11) 295 #define X86_PROPERTY_NR_PERFCTR_CORE KVM_X86_CPU_PROPERTY(0x80000022, 0, EBX, 0, 3) 296 #define X86_PROPERTY_NR_PERFCTR_NB KVM_X86_CPU_PROPERTY(0x80000022, 0, EBX, 10, 15) 297 298 #define X86_PROPERTY_MAX_CENTAUR_LEAF KVM_X86_CPU_PROPERTY(0xC0000000, 0, EAX, 0, 31) 299 300 /* 301 * Intel's architectural PMU events are bizarre. They have a "feature" bit 302 * that indicates the feature is _not_ supported, and a property that states 303 * the length of the bit mask of unsupported features. A feature is supported 304 * if the size of the bit mask is larger than the "unavailable" bit, and said 305 * bit is not set. Fixed counters also bizarre enumeration, but inverted from 306 * arch events for general purpose counters. Fixed counters are supported if a 307 * feature flag is set **OR** the total number of fixed counters is greater 308 * than index of the counter. 309 * 310 * Wrap the events for general purpose and fixed counters to simplify checking 311 * whether or not a given architectural event is supported. 312 */ 313 struct kvm_x86_pmu_feature { 314 struct kvm_x86_cpu_feature f; 315 }; 316 #define KVM_X86_PMU_FEATURE(__reg, __bit) \ 317 ({ \ 318 struct kvm_x86_pmu_feature feature = { \ 319 .f = KVM_X86_CPU_FEATURE(0xa, 0, __reg, __bit), \ 320 }; \ 321 \ 322 kvm_static_assert(KVM_CPUID_##__reg == KVM_CPUID_EBX || \ 323 KVM_CPUID_##__reg == KVM_CPUID_ECX); \ 324 feature; \ 325 }) 326 327 #define X86_PMU_FEATURE_CPU_CYCLES KVM_X86_PMU_FEATURE(EBX, 0) 328 #define X86_PMU_FEATURE_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 1) 329 #define X86_PMU_FEATURE_REFERENCE_CYCLES KVM_X86_PMU_FEATURE(EBX, 2) 330 #define X86_PMU_FEATURE_LLC_REFERENCES KVM_X86_PMU_FEATURE(EBX, 3) 331 #define X86_PMU_FEATURE_LLC_MISSES KVM_X86_PMU_FEATURE(EBX, 4) 332 #define X86_PMU_FEATURE_BRANCH_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 5) 333 #define X86_PMU_FEATURE_BRANCHES_MISPREDICTED KVM_X86_PMU_FEATURE(EBX, 6) 334 #define X86_PMU_FEATURE_TOPDOWN_SLOTS KVM_X86_PMU_FEATURE(EBX, 7) 335 #define X86_PMU_FEATURE_TOPDOWN_BE_BOUND KVM_X86_PMU_FEATURE(EBX, 8) 336 #define X86_PMU_FEATURE_TOPDOWN_BAD_SPEC KVM_X86_PMU_FEATURE(EBX, 9) 337 #define X86_PMU_FEATURE_TOPDOWN_FE_BOUND KVM_X86_PMU_FEATURE(EBX, 10) 338 #define X86_PMU_FEATURE_TOPDOWN_RETIRING KVM_X86_PMU_FEATURE(EBX, 11) 339 #define X86_PMU_FEATURE_LBR_INSERTS KVM_X86_PMU_FEATURE(EBX, 12) 340 341 #define X86_PMU_FEATURE_INSNS_RETIRED_FIXED KVM_X86_PMU_FEATURE(ECX, 0) 342 #define X86_PMU_FEATURE_CPU_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX, 1) 343 #define X86_PMU_FEATURE_REFERENCE_TSC_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX, 2) 344 #define X86_PMU_FEATURE_TOPDOWN_SLOTS_FIXED KVM_X86_PMU_FEATURE(ECX, 3) 345 346 static inline unsigned int x86_family(unsigned int eax) 347 { 348 unsigned int x86; 349 350 x86 = (eax >> 8) & 0xf; 351 352 if (x86 == 0xf) 353 x86 += (eax >> 20) & 0xff; 354 355 return x86; 356 } 357 358 static inline unsigned int x86_model(unsigned int eax) 359 { 360 return ((eax >> 12) & 0xf0) | ((eax >> 4) & 0x0f); 361 } 362 363 /* Page table bitfield declarations */ 364 #define PTE_PRESENT_MASK BIT_ULL(0) 365 #define PTE_WRITABLE_MASK BIT_ULL(1) 366 #define PTE_USER_MASK BIT_ULL(2) 367 #define PTE_ACCESSED_MASK BIT_ULL(5) 368 #define PTE_DIRTY_MASK BIT_ULL(6) 369 #define PTE_LARGE_MASK BIT_ULL(7) 370 #define PTE_GLOBAL_MASK BIT_ULL(8) 371 #define PTE_NX_MASK BIT_ULL(63) 372 373 #define PHYSICAL_PAGE_MASK GENMASK_ULL(51, 12) 374 375 #define PAGE_SHIFT 12 376 #define PAGE_SIZE (1ULL << PAGE_SHIFT) 377 #define PAGE_MASK (~(PAGE_SIZE-1) & PHYSICAL_PAGE_MASK) 378 379 #define HUGEPAGE_SHIFT(x) (PAGE_SHIFT + (((x) - 1) * 9)) 380 #define HUGEPAGE_SIZE(x) (1UL << HUGEPAGE_SHIFT(x)) 381 #define HUGEPAGE_MASK(x) (~(HUGEPAGE_SIZE(x) - 1) & PHYSICAL_PAGE_MASK) 382 383 #define PTE_GET_PA(pte) ((pte) & PHYSICAL_PAGE_MASK) 384 #define PTE_GET_PFN(pte) (PTE_GET_PA(pte) >> PAGE_SHIFT) 385 386 /* General Registers in 64-Bit Mode */ 387 struct gpr64_regs { 388 u64 rax; 389 u64 rcx; 390 u64 rdx; 391 u64 rbx; 392 u64 rsp; 393 u64 rbp; 394 u64 rsi; 395 u64 rdi; 396 u64 r8; 397 u64 r9; 398 u64 r10; 399 u64 r11; 400 u64 r12; 401 u64 r13; 402 u64 r14; 403 u64 r15; 404 }; 405 406 struct desc64 { 407 uint16_t limit0; 408 uint16_t base0; 409 unsigned base1:8, type:4, s:1, dpl:2, p:1; 410 unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8; 411 uint32_t base3; 412 uint32_t zero1; 413 } __attribute__((packed)); 414 415 struct desc_ptr { 416 uint16_t size; 417 uint64_t address; 418 } __attribute__((packed)); 419 420 struct kvm_x86_state { 421 struct kvm_xsave *xsave; 422 struct kvm_vcpu_events events; 423 struct kvm_mp_state mp_state; 424 struct kvm_regs regs; 425 struct kvm_xcrs xcrs; 426 struct kvm_sregs sregs; 427 struct kvm_debugregs debugregs; 428 union { 429 struct kvm_nested_state nested; 430 char nested_[16384]; 431 }; 432 struct kvm_msrs msrs; 433 }; 434 435 static inline uint64_t get_desc64_base(const struct desc64 *desc) 436 { 437 return ((uint64_t)desc->base3 << 32) | 438 (desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24)); 439 } 440 441 static inline uint64_t rdtsc(void) 442 { 443 uint32_t eax, edx; 444 uint64_t tsc_val; 445 /* 446 * The lfence is to wait (on Intel CPUs) until all previous 447 * instructions have been executed. If software requires RDTSC to be 448 * executed prior to execution of any subsequent instruction, it can 449 * execute LFENCE immediately after RDTSC 450 */ 451 __asm__ __volatile__("lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx)); 452 tsc_val = ((uint64_t)edx) << 32 | eax; 453 return tsc_val; 454 } 455 456 static inline uint64_t rdtscp(uint32_t *aux) 457 { 458 uint32_t eax, edx; 459 460 __asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux)); 461 return ((uint64_t)edx) << 32 | eax; 462 } 463 464 static inline uint64_t rdmsr(uint32_t msr) 465 { 466 uint32_t a, d; 467 468 __asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory"); 469 470 return a | ((uint64_t) d << 32); 471 } 472 473 static inline void wrmsr(uint32_t msr, uint64_t value) 474 { 475 uint32_t a = value; 476 uint32_t d = value >> 32; 477 478 __asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory"); 479 } 480 481 482 static inline uint16_t inw(uint16_t port) 483 { 484 uint16_t tmp; 485 486 __asm__ __volatile__("in %%dx, %%ax" 487 : /* output */ "=a" (tmp) 488 : /* input */ "d" (port)); 489 490 return tmp; 491 } 492 493 static inline uint16_t get_es(void) 494 { 495 uint16_t es; 496 497 __asm__ __volatile__("mov %%es, %[es]" 498 : /* output */ [es]"=rm"(es)); 499 return es; 500 } 501 502 static inline uint16_t get_cs(void) 503 { 504 uint16_t cs; 505 506 __asm__ __volatile__("mov %%cs, %[cs]" 507 : /* output */ [cs]"=rm"(cs)); 508 return cs; 509 } 510 511 static inline uint16_t get_ss(void) 512 { 513 uint16_t ss; 514 515 __asm__ __volatile__("mov %%ss, %[ss]" 516 : /* output */ [ss]"=rm"(ss)); 517 return ss; 518 } 519 520 static inline uint16_t get_ds(void) 521 { 522 uint16_t ds; 523 524 __asm__ __volatile__("mov %%ds, %[ds]" 525 : /* output */ [ds]"=rm"(ds)); 526 return ds; 527 } 528 529 static inline uint16_t get_fs(void) 530 { 531 uint16_t fs; 532 533 __asm__ __volatile__("mov %%fs, %[fs]" 534 : /* output */ [fs]"=rm"(fs)); 535 return fs; 536 } 537 538 static inline uint16_t get_gs(void) 539 { 540 uint16_t gs; 541 542 __asm__ __volatile__("mov %%gs, %[gs]" 543 : /* output */ [gs]"=rm"(gs)); 544 return gs; 545 } 546 547 static inline uint16_t get_tr(void) 548 { 549 uint16_t tr; 550 551 __asm__ __volatile__("str %[tr]" 552 : /* output */ [tr]"=rm"(tr)); 553 return tr; 554 } 555 556 static inline uint64_t get_cr0(void) 557 { 558 uint64_t cr0; 559 560 __asm__ __volatile__("mov %%cr0, %[cr0]" 561 : /* output */ [cr0]"=r"(cr0)); 562 return cr0; 563 } 564 565 static inline uint64_t get_cr3(void) 566 { 567 uint64_t cr3; 568 569 __asm__ __volatile__("mov %%cr3, %[cr3]" 570 : /* output */ [cr3]"=r"(cr3)); 571 return cr3; 572 } 573 574 static inline uint64_t get_cr4(void) 575 { 576 uint64_t cr4; 577 578 __asm__ __volatile__("mov %%cr4, %[cr4]" 579 : /* output */ [cr4]"=r"(cr4)); 580 return cr4; 581 } 582 583 static inline void set_cr4(uint64_t val) 584 { 585 __asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory"); 586 } 587 588 static inline void set_idt(const struct desc_ptr *idt_desc) 589 { 590 __asm__ __volatile__("lidt %0"::"m"(*idt_desc)); 591 } 592 593 static inline u64 xgetbv(u32 index) 594 { 595 u32 eax, edx; 596 597 __asm__ __volatile__("xgetbv;" 598 : "=a" (eax), "=d" (edx) 599 : "c" (index)); 600 return eax | ((u64)edx << 32); 601 } 602 603 static inline void xsetbv(u32 index, u64 value) 604 { 605 u32 eax = value; 606 u32 edx = value >> 32; 607 608 __asm__ __volatile__("xsetbv" :: "a" (eax), "d" (edx), "c" (index)); 609 } 610 611 static inline void wrpkru(u32 pkru) 612 { 613 /* Note, ECX and EDX are architecturally required to be '0'. */ 614 asm volatile(".byte 0x0f,0x01,0xef\n\t" 615 : : "a" (pkru), "c"(0), "d"(0)); 616 } 617 618 static inline struct desc_ptr get_gdt(void) 619 { 620 struct desc_ptr gdt; 621 __asm__ __volatile__("sgdt %[gdt]" 622 : /* output */ [gdt]"=m"(gdt)); 623 return gdt; 624 } 625 626 static inline struct desc_ptr get_idt(void) 627 { 628 struct desc_ptr idt; 629 __asm__ __volatile__("sidt %[idt]" 630 : /* output */ [idt]"=m"(idt)); 631 return idt; 632 } 633 634 static inline void outl(uint16_t port, uint32_t value) 635 { 636 __asm__ __volatile__("outl %%eax, %%dx" : : "d"(port), "a"(value)); 637 } 638 639 static inline void __cpuid(uint32_t function, uint32_t index, 640 uint32_t *eax, uint32_t *ebx, 641 uint32_t *ecx, uint32_t *edx) 642 { 643 *eax = function; 644 *ecx = index; 645 646 asm volatile("cpuid" 647 : "=a" (*eax), 648 "=b" (*ebx), 649 "=c" (*ecx), 650 "=d" (*edx) 651 : "0" (*eax), "2" (*ecx) 652 : "memory"); 653 } 654 655 static inline void cpuid(uint32_t function, 656 uint32_t *eax, uint32_t *ebx, 657 uint32_t *ecx, uint32_t *edx) 658 { 659 return __cpuid(function, 0, eax, ebx, ecx, edx); 660 } 661 662 static inline uint32_t this_cpu_fms(void) 663 { 664 uint32_t eax, ebx, ecx, edx; 665 666 cpuid(1, &eax, &ebx, &ecx, &edx); 667 return eax; 668 } 669 670 static inline uint32_t this_cpu_family(void) 671 { 672 return x86_family(this_cpu_fms()); 673 } 674 675 static inline uint32_t this_cpu_model(void) 676 { 677 return x86_model(this_cpu_fms()); 678 } 679 680 static inline bool this_cpu_vendor_string_is(const char *vendor) 681 { 682 const uint32_t *chunk = (const uint32_t *)vendor; 683 uint32_t eax, ebx, ecx, edx; 684 685 cpuid(0, &eax, &ebx, &ecx, &edx); 686 return (ebx == chunk[0] && edx == chunk[1] && ecx == chunk[2]); 687 } 688 689 static inline bool this_cpu_is_intel(void) 690 { 691 return this_cpu_vendor_string_is("GenuineIntel"); 692 } 693 694 /* 695 * Exclude early K5 samples with a vendor string of "AMDisbetter!" 696 */ 697 static inline bool this_cpu_is_amd(void) 698 { 699 return this_cpu_vendor_string_is("AuthenticAMD"); 700 } 701 702 static inline uint32_t __this_cpu_has(uint32_t function, uint32_t index, 703 uint8_t reg, uint8_t lo, uint8_t hi) 704 { 705 uint32_t gprs[4]; 706 707 __cpuid(function, index, 708 &gprs[KVM_CPUID_EAX], &gprs[KVM_CPUID_EBX], 709 &gprs[KVM_CPUID_ECX], &gprs[KVM_CPUID_EDX]); 710 711 return (gprs[reg] & GENMASK(hi, lo)) >> lo; 712 } 713 714 static inline bool this_cpu_has(struct kvm_x86_cpu_feature feature) 715 { 716 return __this_cpu_has(feature.function, feature.index, 717 feature.reg, feature.bit, feature.bit); 718 } 719 720 static inline uint32_t this_cpu_property(struct kvm_x86_cpu_property property) 721 { 722 return __this_cpu_has(property.function, property.index, 723 property.reg, property.lo_bit, property.hi_bit); 724 } 725 726 static __always_inline bool this_cpu_has_p(struct kvm_x86_cpu_property property) 727 { 728 uint32_t max_leaf; 729 730 switch (property.function & 0xc0000000) { 731 case 0: 732 max_leaf = this_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF); 733 break; 734 case 0x40000000: 735 max_leaf = this_cpu_property(X86_PROPERTY_MAX_KVM_LEAF); 736 break; 737 case 0x80000000: 738 max_leaf = this_cpu_property(X86_PROPERTY_MAX_EXT_LEAF); 739 break; 740 case 0xc0000000: 741 max_leaf = this_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF); 742 } 743 return max_leaf >= property.function; 744 } 745 746 static inline bool this_pmu_has(struct kvm_x86_pmu_feature feature) 747 { 748 uint32_t nr_bits; 749 750 if (feature.f.reg == KVM_CPUID_EBX) { 751 nr_bits = this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); 752 return nr_bits > feature.f.bit && !this_cpu_has(feature.f); 753 } 754 755 GUEST_ASSERT(feature.f.reg == KVM_CPUID_ECX); 756 nr_bits = this_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); 757 return nr_bits > feature.f.bit || this_cpu_has(feature.f); 758 } 759 760 static __always_inline uint64_t this_cpu_supported_xcr0(void) 761 { 762 if (!this_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) 763 return 0; 764 765 return this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | 766 ((uint64_t)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); 767 } 768 769 typedef u32 __attribute__((vector_size(16))) sse128_t; 770 #define __sse128_u union { sse128_t vec; u64 as_u64[2]; u32 as_u32[4]; } 771 #define sse128_lo(x) ({ __sse128_u t; t.vec = x; t.as_u64[0]; }) 772 #define sse128_hi(x) ({ __sse128_u t; t.vec = x; t.as_u64[1]; }) 773 774 static inline void read_sse_reg(int reg, sse128_t *data) 775 { 776 switch (reg) { 777 case 0: 778 asm("movdqa %%xmm0, %0" : "=m"(*data)); 779 break; 780 case 1: 781 asm("movdqa %%xmm1, %0" : "=m"(*data)); 782 break; 783 case 2: 784 asm("movdqa %%xmm2, %0" : "=m"(*data)); 785 break; 786 case 3: 787 asm("movdqa %%xmm3, %0" : "=m"(*data)); 788 break; 789 case 4: 790 asm("movdqa %%xmm4, %0" : "=m"(*data)); 791 break; 792 case 5: 793 asm("movdqa %%xmm5, %0" : "=m"(*data)); 794 break; 795 case 6: 796 asm("movdqa %%xmm6, %0" : "=m"(*data)); 797 break; 798 case 7: 799 asm("movdqa %%xmm7, %0" : "=m"(*data)); 800 break; 801 default: 802 BUG(); 803 } 804 } 805 806 static inline void write_sse_reg(int reg, const sse128_t *data) 807 { 808 switch (reg) { 809 case 0: 810 asm("movdqa %0, %%xmm0" : : "m"(*data)); 811 break; 812 case 1: 813 asm("movdqa %0, %%xmm1" : : "m"(*data)); 814 break; 815 case 2: 816 asm("movdqa %0, %%xmm2" : : "m"(*data)); 817 break; 818 case 3: 819 asm("movdqa %0, %%xmm3" : : "m"(*data)); 820 break; 821 case 4: 822 asm("movdqa %0, %%xmm4" : : "m"(*data)); 823 break; 824 case 5: 825 asm("movdqa %0, %%xmm5" : : "m"(*data)); 826 break; 827 case 6: 828 asm("movdqa %0, %%xmm6" : : "m"(*data)); 829 break; 830 case 7: 831 asm("movdqa %0, %%xmm7" : : "m"(*data)); 832 break; 833 default: 834 BUG(); 835 } 836 } 837 838 static inline void cpu_relax(void) 839 { 840 asm volatile("rep; nop" ::: "memory"); 841 } 842 843 static inline void udelay(unsigned long usec) 844 { 845 uint64_t start, now, cycles; 846 847 GUEST_ASSERT(guest_tsc_khz); 848 cycles = guest_tsc_khz / 1000 * usec; 849 850 /* 851 * Deliberately don't PAUSE, a.k.a. cpu_relax(), so that the delay is 852 * as accurate as possible, e.g. doesn't trigger PAUSE-Loop VM-Exits. 853 */ 854 start = rdtsc(); 855 do { 856 now = rdtsc(); 857 } while (now - start < cycles); 858 } 859 860 #define ud2() \ 861 __asm__ __volatile__( \ 862 "ud2\n" \ 863 ) 864 865 #define hlt() \ 866 __asm__ __volatile__( \ 867 "hlt\n" \ 868 ) 869 870 struct kvm_x86_state *vcpu_save_state(struct kvm_vcpu *vcpu); 871 void vcpu_load_state(struct kvm_vcpu *vcpu, struct kvm_x86_state *state); 872 void kvm_x86_state_cleanup(struct kvm_x86_state *state); 873 874 const struct kvm_msr_list *kvm_get_msr_index_list(void); 875 const struct kvm_msr_list *kvm_get_feature_msr_index_list(void); 876 bool kvm_msr_is_in_save_restore_list(uint32_t msr_index); 877 uint64_t kvm_get_feature_msr(uint64_t msr_index); 878 879 static inline void vcpu_msrs_get(struct kvm_vcpu *vcpu, 880 struct kvm_msrs *msrs) 881 { 882 int r = __vcpu_ioctl(vcpu, KVM_GET_MSRS, msrs); 883 884 TEST_ASSERT(r == msrs->nmsrs, 885 "KVM_GET_MSRS failed, r: %i (failed on MSR %x)", 886 r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index); 887 } 888 static inline void vcpu_msrs_set(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs) 889 { 890 int r = __vcpu_ioctl(vcpu, KVM_SET_MSRS, msrs); 891 892 TEST_ASSERT(r == msrs->nmsrs, 893 "KVM_SET_MSRS failed, r: %i (failed on MSR %x)", 894 r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index); 895 } 896 static inline void vcpu_debugregs_get(struct kvm_vcpu *vcpu, 897 struct kvm_debugregs *debugregs) 898 { 899 vcpu_ioctl(vcpu, KVM_GET_DEBUGREGS, debugregs); 900 } 901 static inline void vcpu_debugregs_set(struct kvm_vcpu *vcpu, 902 struct kvm_debugregs *debugregs) 903 { 904 vcpu_ioctl(vcpu, KVM_SET_DEBUGREGS, debugregs); 905 } 906 static inline void vcpu_xsave_get(struct kvm_vcpu *vcpu, 907 struct kvm_xsave *xsave) 908 { 909 vcpu_ioctl(vcpu, KVM_GET_XSAVE, xsave); 910 } 911 static inline void vcpu_xsave2_get(struct kvm_vcpu *vcpu, 912 struct kvm_xsave *xsave) 913 { 914 vcpu_ioctl(vcpu, KVM_GET_XSAVE2, xsave); 915 } 916 static inline void vcpu_xsave_set(struct kvm_vcpu *vcpu, 917 struct kvm_xsave *xsave) 918 { 919 vcpu_ioctl(vcpu, KVM_SET_XSAVE, xsave); 920 } 921 static inline void vcpu_xcrs_get(struct kvm_vcpu *vcpu, 922 struct kvm_xcrs *xcrs) 923 { 924 vcpu_ioctl(vcpu, KVM_GET_XCRS, xcrs); 925 } 926 static inline void vcpu_xcrs_set(struct kvm_vcpu *vcpu, struct kvm_xcrs *xcrs) 927 { 928 vcpu_ioctl(vcpu, KVM_SET_XCRS, xcrs); 929 } 930 931 const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid, 932 uint32_t function, uint32_t index); 933 const struct kvm_cpuid2 *kvm_get_supported_cpuid(void); 934 935 static inline uint32_t kvm_cpu_fms(void) 936 { 937 return get_cpuid_entry(kvm_get_supported_cpuid(), 0x1, 0)->eax; 938 } 939 940 static inline uint32_t kvm_cpu_family(void) 941 { 942 return x86_family(kvm_cpu_fms()); 943 } 944 945 static inline uint32_t kvm_cpu_model(void) 946 { 947 return x86_model(kvm_cpu_fms()); 948 } 949 950 bool kvm_cpuid_has(const struct kvm_cpuid2 *cpuid, 951 struct kvm_x86_cpu_feature feature); 952 953 static inline bool kvm_cpu_has(struct kvm_x86_cpu_feature feature) 954 { 955 return kvm_cpuid_has(kvm_get_supported_cpuid(), feature); 956 } 957 958 uint32_t kvm_cpuid_property(const struct kvm_cpuid2 *cpuid, 959 struct kvm_x86_cpu_property property); 960 961 static inline uint32_t kvm_cpu_property(struct kvm_x86_cpu_property property) 962 { 963 return kvm_cpuid_property(kvm_get_supported_cpuid(), property); 964 } 965 966 static __always_inline bool kvm_cpu_has_p(struct kvm_x86_cpu_property property) 967 { 968 uint32_t max_leaf; 969 970 switch (property.function & 0xc0000000) { 971 case 0: 972 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF); 973 break; 974 case 0x40000000: 975 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_KVM_LEAF); 976 break; 977 case 0x80000000: 978 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_EXT_LEAF); 979 break; 980 case 0xc0000000: 981 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF); 982 } 983 return max_leaf >= property.function; 984 } 985 986 static inline bool kvm_pmu_has(struct kvm_x86_pmu_feature feature) 987 { 988 uint32_t nr_bits; 989 990 if (feature.f.reg == KVM_CPUID_EBX) { 991 nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); 992 return nr_bits > feature.f.bit && !kvm_cpu_has(feature.f); 993 } 994 995 TEST_ASSERT_EQ(feature.f.reg, KVM_CPUID_ECX); 996 nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); 997 return nr_bits > feature.f.bit || kvm_cpu_has(feature.f); 998 } 999 1000 static __always_inline uint64_t kvm_cpu_supported_xcr0(void) 1001 { 1002 if (!kvm_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) 1003 return 0; 1004 1005 return kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | 1006 ((uint64_t)kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); 1007 } 1008 1009 static inline size_t kvm_cpuid2_size(int nr_entries) 1010 { 1011 return sizeof(struct kvm_cpuid2) + 1012 sizeof(struct kvm_cpuid_entry2) * nr_entries; 1013 } 1014 1015 /* 1016 * Allocate a "struct kvm_cpuid2* instance, with the 0-length arrary of 1017 * entries sized to hold @nr_entries. The caller is responsible for freeing 1018 * the struct. 1019 */ 1020 static inline struct kvm_cpuid2 *allocate_kvm_cpuid2(int nr_entries) 1021 { 1022 struct kvm_cpuid2 *cpuid; 1023 1024 cpuid = malloc(kvm_cpuid2_size(nr_entries)); 1025 TEST_ASSERT(cpuid, "-ENOMEM when allocating kvm_cpuid2"); 1026 1027 cpuid->nent = nr_entries; 1028 1029 return cpuid; 1030 } 1031 1032 void vcpu_init_cpuid(struct kvm_vcpu *vcpu, const struct kvm_cpuid2 *cpuid); 1033 1034 static inline void vcpu_get_cpuid(struct kvm_vcpu *vcpu) 1035 { 1036 vcpu_ioctl(vcpu, KVM_GET_CPUID2, vcpu->cpuid); 1037 } 1038 1039 static inline struct kvm_cpuid_entry2 *__vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu, 1040 uint32_t function, 1041 uint32_t index) 1042 { 1043 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first (or equivalent)"); 1044 1045 vcpu_get_cpuid(vcpu); 1046 1047 return (struct kvm_cpuid_entry2 *)get_cpuid_entry(vcpu->cpuid, 1048 function, index); 1049 } 1050 1051 static inline struct kvm_cpuid_entry2 *vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu, 1052 uint32_t function) 1053 { 1054 return __vcpu_get_cpuid_entry(vcpu, function, 0); 1055 } 1056 1057 static inline int __vcpu_set_cpuid(struct kvm_vcpu *vcpu) 1058 { 1059 int r; 1060 1061 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first"); 1062 r = __vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid); 1063 if (r) 1064 return r; 1065 1066 /* On success, refresh the cache to pick up adjustments made by KVM. */ 1067 vcpu_get_cpuid(vcpu); 1068 return 0; 1069 } 1070 1071 static inline void vcpu_set_cpuid(struct kvm_vcpu *vcpu) 1072 { 1073 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first"); 1074 vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid); 1075 1076 /* Refresh the cache to pick up adjustments made by KVM. */ 1077 vcpu_get_cpuid(vcpu); 1078 } 1079 1080 void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu, 1081 struct kvm_x86_cpu_property property, 1082 uint32_t value); 1083 void vcpu_set_cpuid_maxphyaddr(struct kvm_vcpu *vcpu, uint8_t maxphyaddr); 1084 1085 void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, uint32_t function); 1086 1087 static inline bool vcpu_cpuid_has(struct kvm_vcpu *vcpu, 1088 struct kvm_x86_cpu_feature feature) 1089 { 1090 struct kvm_cpuid_entry2 *entry; 1091 1092 entry = __vcpu_get_cpuid_entry(vcpu, feature.function, feature.index); 1093 return *((&entry->eax) + feature.reg) & BIT(feature.bit); 1094 } 1095 1096 void vcpu_set_or_clear_cpuid_feature(struct kvm_vcpu *vcpu, 1097 struct kvm_x86_cpu_feature feature, 1098 bool set); 1099 1100 static inline void vcpu_set_cpuid_feature(struct kvm_vcpu *vcpu, 1101 struct kvm_x86_cpu_feature feature) 1102 { 1103 vcpu_set_or_clear_cpuid_feature(vcpu, feature, true); 1104 1105 } 1106 1107 static inline void vcpu_clear_cpuid_feature(struct kvm_vcpu *vcpu, 1108 struct kvm_x86_cpu_feature feature) 1109 { 1110 vcpu_set_or_clear_cpuid_feature(vcpu, feature, false); 1111 } 1112 1113 uint64_t vcpu_get_msr(struct kvm_vcpu *vcpu, uint64_t msr_index); 1114 int _vcpu_set_msr(struct kvm_vcpu *vcpu, uint64_t msr_index, uint64_t msr_value); 1115 1116 /* 1117 * Assert on an MSR access(es) and pretty print the MSR name when possible. 1118 * Note, the caller provides the stringified name so that the name of macro is 1119 * printed, not the value the macro resolves to (due to macro expansion). 1120 */ 1121 #define TEST_ASSERT_MSR(cond, fmt, msr, str, args...) \ 1122 do { \ 1123 if (__builtin_constant_p(msr)) { \ 1124 TEST_ASSERT(cond, fmt, str, args); \ 1125 } else if (!(cond)) { \ 1126 char buf[16]; \ 1127 \ 1128 snprintf(buf, sizeof(buf), "MSR 0x%x", msr); \ 1129 TEST_ASSERT(cond, fmt, buf, args); \ 1130 } \ 1131 } while (0) 1132 1133 /* 1134 * Returns true if KVM should return the last written value when reading an MSR 1135 * from userspace, e.g. the MSR isn't a command MSR, doesn't emulate state that 1136 * is changing, etc. This is NOT an exhaustive list! The intent is to filter 1137 * out MSRs that are not durable _and_ that a selftest wants to write. 1138 */ 1139 static inline bool is_durable_msr(uint32_t msr) 1140 { 1141 return msr != MSR_IA32_TSC; 1142 } 1143 1144 #define vcpu_set_msr(vcpu, msr, val) \ 1145 do { \ 1146 uint64_t r, v = val; \ 1147 \ 1148 TEST_ASSERT_MSR(_vcpu_set_msr(vcpu, msr, v) == 1, \ 1149 "KVM_SET_MSRS failed on %s, value = 0x%lx", msr, #msr, v); \ 1150 if (!is_durable_msr(msr)) \ 1151 break; \ 1152 r = vcpu_get_msr(vcpu, msr); \ 1153 TEST_ASSERT_MSR(r == v, "Set %s to '0x%lx', got back '0x%lx'", msr, #msr, v, r);\ 1154 } while (0) 1155 1156 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits); 1157 void kvm_init_vm_address_properties(struct kvm_vm *vm); 1158 1159 struct ex_regs { 1160 uint64_t rax, rcx, rdx, rbx; 1161 uint64_t rbp, rsi, rdi; 1162 uint64_t r8, r9, r10, r11; 1163 uint64_t r12, r13, r14, r15; 1164 uint64_t vector; 1165 uint64_t error_code; 1166 uint64_t rip; 1167 uint64_t cs; 1168 uint64_t rflags; 1169 }; 1170 1171 struct idt_entry { 1172 uint16_t offset0; 1173 uint16_t selector; 1174 uint16_t ist : 3; 1175 uint16_t : 5; 1176 uint16_t type : 4; 1177 uint16_t : 1; 1178 uint16_t dpl : 2; 1179 uint16_t p : 1; 1180 uint16_t offset1; 1181 uint32_t offset2; uint32_t reserved; 1182 }; 1183 1184 void vm_install_exception_handler(struct kvm_vm *vm, int vector, 1185 void (*handler)(struct ex_regs *)); 1186 1187 /* 1188 * Exception fixup morphs #DE to an arbitrary magic vector so that '0' can be 1189 * used to signal "no expcetion". 1190 */ 1191 #define KVM_MAGIC_DE_VECTOR 0xff 1192 1193 /* If a toddler were to say "abracadabra". */ 1194 #define KVM_EXCEPTION_MAGIC 0xabacadabaULL 1195 1196 /* 1197 * KVM selftest exception fixup uses registers to coordinate with the exception 1198 * handler, versus the kernel's in-memory tables and KVM-Unit-Tests's in-memory 1199 * per-CPU data. Using only registers avoids having to map memory into the 1200 * guest, doesn't require a valid, stable GS.base, and reduces the risk of 1201 * for recursive faults when accessing memory in the handler. The downside to 1202 * using registers is that it restricts what registers can be used by the actual 1203 * instruction. But, selftests are 64-bit only, making register* pressure a 1204 * minor concern. Use r9-r11 as they are volatile, i.e. don't need to be saved 1205 * by the callee, and except for r11 are not implicit parameters to any 1206 * instructions. Ideally, fixup would use r8-r10 and thus avoid implicit 1207 * parameters entirely, but Hyper-V's hypercall ABI uses r8 and testing Hyper-V 1208 * is higher priority than testing non-faulting SYSCALL/SYSRET. 1209 * 1210 * Note, the fixup handler deliberately does not handle #DE, i.e. the vector 1211 * is guaranteed to be non-zero on fault. 1212 * 1213 * REGISTER INPUTS: 1214 * r9 = MAGIC 1215 * r10 = RIP 1216 * r11 = new RIP on fault 1217 * 1218 * REGISTER OUTPUTS: 1219 * r9 = exception vector (non-zero) 1220 * r10 = error code 1221 */ 1222 #define __KVM_ASM_SAFE(insn, fep) \ 1223 "mov $" __stringify(KVM_EXCEPTION_MAGIC) ", %%r9\n\t" \ 1224 "lea 1f(%%rip), %%r10\n\t" \ 1225 "lea 2f(%%rip), %%r11\n\t" \ 1226 fep "1: " insn "\n\t" \ 1227 "xor %%r9, %%r9\n\t" \ 1228 "2:\n\t" \ 1229 "mov %%r9b, %[vector]\n\t" \ 1230 "mov %%r10, %[error_code]\n\t" 1231 1232 #define KVM_ASM_SAFE(insn) __KVM_ASM_SAFE(insn, "") 1233 #define KVM_ASM_SAFE_FEP(insn) __KVM_ASM_SAFE(insn, KVM_FEP) 1234 1235 #define KVM_ASM_SAFE_OUTPUTS(v, ec) [vector] "=qm"(v), [error_code] "=rm"(ec) 1236 #define KVM_ASM_SAFE_CLOBBERS "r9", "r10", "r11" 1237 1238 #define kvm_asm_safe(insn, inputs...) \ 1239 ({ \ 1240 uint64_t ign_error_code; \ 1241 uint8_t vector; \ 1242 \ 1243 asm volatile(KVM_ASM_SAFE(insn) \ 1244 : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code) \ 1245 : inputs \ 1246 : KVM_ASM_SAFE_CLOBBERS); \ 1247 vector; \ 1248 }) 1249 1250 #define kvm_asm_safe_ec(insn, error_code, inputs...) \ 1251 ({ \ 1252 uint8_t vector; \ 1253 \ 1254 asm volatile(KVM_ASM_SAFE(insn) \ 1255 : KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1256 : inputs \ 1257 : KVM_ASM_SAFE_CLOBBERS); \ 1258 vector; \ 1259 }) 1260 1261 #define kvm_asm_safe_fep(insn, inputs...) \ 1262 ({ \ 1263 uint64_t ign_error_code; \ 1264 uint8_t vector; \ 1265 \ 1266 asm volatile(KVM_ASM_SAFE_FEP(insn) \ 1267 : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code) \ 1268 : inputs \ 1269 : KVM_ASM_SAFE_CLOBBERS); \ 1270 vector; \ 1271 }) 1272 1273 #define kvm_asm_safe_ec_fep(insn, error_code, inputs...) \ 1274 ({ \ 1275 uint8_t vector; \ 1276 \ 1277 asm volatile(KVM_ASM_SAFE_FEP(insn) \ 1278 : KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1279 : inputs \ 1280 : KVM_ASM_SAFE_CLOBBERS); \ 1281 vector; \ 1282 }) 1283 1284 #define BUILD_READ_U64_SAFE_HELPER(insn, _fep, _FEP) \ 1285 static inline uint8_t insn##_safe ##_fep(uint32_t idx, uint64_t *val) \ 1286 { \ 1287 uint64_t error_code; \ 1288 uint8_t vector; \ 1289 uint32_t a, d; \ 1290 \ 1291 asm volatile(KVM_ASM_SAFE##_FEP(#insn) \ 1292 : "=a"(a), "=d"(d), \ 1293 KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1294 : "c"(idx) \ 1295 : KVM_ASM_SAFE_CLOBBERS); \ 1296 \ 1297 *val = (uint64_t)a | ((uint64_t)d << 32); \ 1298 return vector; \ 1299 } 1300 1301 /* 1302 * Generate {insn}_safe() and {insn}_safe_fep() helpers for instructions that 1303 * use ECX as in input index, and EDX:EAX as a 64-bit output. 1304 */ 1305 #define BUILD_READ_U64_SAFE_HELPERS(insn) \ 1306 BUILD_READ_U64_SAFE_HELPER(insn, , ) \ 1307 BUILD_READ_U64_SAFE_HELPER(insn, _fep, _FEP) \ 1308 1309 BUILD_READ_U64_SAFE_HELPERS(rdmsr) 1310 BUILD_READ_U64_SAFE_HELPERS(rdpmc) 1311 BUILD_READ_U64_SAFE_HELPERS(xgetbv) 1312 1313 static inline uint8_t wrmsr_safe(uint32_t msr, uint64_t val) 1314 { 1315 return kvm_asm_safe("wrmsr", "a"(val & -1u), "d"(val >> 32), "c"(msr)); 1316 } 1317 1318 static inline uint8_t xsetbv_safe(uint32_t index, uint64_t value) 1319 { 1320 u32 eax = value; 1321 u32 edx = value >> 32; 1322 1323 return kvm_asm_safe("xsetbv", "a" (eax), "d" (edx), "c" (index)); 1324 } 1325 1326 bool kvm_is_tdp_enabled(void); 1327 1328 static inline bool get_kvm_intel_param_bool(const char *param) 1329 { 1330 return kvm_get_module_param_bool("kvm_intel", param); 1331 } 1332 1333 static inline bool get_kvm_amd_param_bool(const char *param) 1334 { 1335 return kvm_get_module_param_bool("kvm_amd", param); 1336 } 1337 1338 static inline int get_kvm_intel_param_integer(const char *param) 1339 { 1340 return kvm_get_module_param_integer("kvm_intel", param); 1341 } 1342 1343 static inline int get_kvm_amd_param_integer(const char *param) 1344 { 1345 return kvm_get_module_param_integer("kvm_amd", param); 1346 } 1347 1348 static inline bool kvm_is_pmu_enabled(void) 1349 { 1350 return get_kvm_param_bool("enable_pmu"); 1351 } 1352 1353 static inline bool kvm_is_forced_emulation_enabled(void) 1354 { 1355 return !!get_kvm_param_integer("force_emulation_prefix"); 1356 } 1357 1358 static inline bool kvm_is_unrestricted_guest_enabled(void) 1359 { 1360 return get_kvm_intel_param_bool("unrestricted_guest"); 1361 } 1362 1363 uint64_t *__vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr, 1364 int *level); 1365 uint64_t *vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr); 1366 1367 uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2, 1368 uint64_t a3); 1369 uint64_t __xen_hypercall(uint64_t nr, uint64_t a0, void *a1); 1370 void xen_hypercall(uint64_t nr, uint64_t a0, void *a1); 1371 1372 static inline uint64_t __kvm_hypercall_map_gpa_range(uint64_t gpa, 1373 uint64_t size, uint64_t flags) 1374 { 1375 return kvm_hypercall(KVM_HC_MAP_GPA_RANGE, gpa, size >> PAGE_SHIFT, flags, 0); 1376 } 1377 1378 static inline void kvm_hypercall_map_gpa_range(uint64_t gpa, uint64_t size, 1379 uint64_t flags) 1380 { 1381 uint64_t ret = __kvm_hypercall_map_gpa_range(gpa, size, flags); 1382 1383 GUEST_ASSERT(!ret); 1384 } 1385 1386 /* 1387 * Execute HLT in an STI interrupt shadow to ensure that a pending IRQ that's 1388 * intended to be a wake event arrives *after* HLT is executed. Modern CPUs, 1389 * except for a few oddballs that KVM is unlikely to run on, block IRQs for one 1390 * instruction after STI, *if* RFLAGS.IF=0 before STI. Note, Intel CPUs may 1391 * block other events beyond regular IRQs, e.g. may block NMIs and SMIs too. 1392 */ 1393 static inline void safe_halt(void) 1394 { 1395 asm volatile("sti; hlt"); 1396 } 1397 1398 /* 1399 * Enable interrupts and ensure that interrupts are evaluated upon return from 1400 * this function, i.e. execute a nop to consume the STi interrupt shadow. 1401 */ 1402 static inline void sti_nop(void) 1403 { 1404 asm volatile ("sti; nop"); 1405 } 1406 1407 /* 1408 * Enable interrupts for one instruction (nop), to allow the CPU to process all 1409 * interrupts that are already pending. 1410 */ 1411 static inline void sti_nop_cli(void) 1412 { 1413 asm volatile ("sti; nop; cli"); 1414 } 1415 1416 static inline void sti(void) 1417 { 1418 asm volatile("sti"); 1419 } 1420 1421 static inline void cli(void) 1422 { 1423 asm volatile ("cli"); 1424 } 1425 1426 void __vm_xsave_require_permission(uint64_t xfeature, const char *name); 1427 1428 #define vm_xsave_require_permission(xfeature) \ 1429 __vm_xsave_require_permission(xfeature, #xfeature) 1430 1431 enum pg_level { 1432 PG_LEVEL_NONE, 1433 PG_LEVEL_4K, 1434 PG_LEVEL_2M, 1435 PG_LEVEL_1G, 1436 PG_LEVEL_512G, 1437 PG_LEVEL_NUM 1438 }; 1439 1440 #define PG_LEVEL_SHIFT(_level) ((_level - 1) * 9 + 12) 1441 #define PG_LEVEL_SIZE(_level) (1ull << PG_LEVEL_SHIFT(_level)) 1442 1443 #define PG_SIZE_4K PG_LEVEL_SIZE(PG_LEVEL_4K) 1444 #define PG_SIZE_2M PG_LEVEL_SIZE(PG_LEVEL_2M) 1445 #define PG_SIZE_1G PG_LEVEL_SIZE(PG_LEVEL_1G) 1446 1447 void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, int level); 1448 void virt_map_level(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, 1449 uint64_t nr_bytes, int level); 1450 1451 /* 1452 * Basic CPU control in CR0 1453 */ 1454 #define X86_CR0_PE (1UL<<0) /* Protection Enable */ 1455 #define X86_CR0_MP (1UL<<1) /* Monitor Coprocessor */ 1456 #define X86_CR0_EM (1UL<<2) /* Emulation */ 1457 #define X86_CR0_TS (1UL<<3) /* Task Switched */ 1458 #define X86_CR0_ET (1UL<<4) /* Extension Type */ 1459 #define X86_CR0_NE (1UL<<5) /* Numeric Error */ 1460 #define X86_CR0_WP (1UL<<16) /* Write Protect */ 1461 #define X86_CR0_AM (1UL<<18) /* Alignment Mask */ 1462 #define X86_CR0_NW (1UL<<29) /* Not Write-through */ 1463 #define X86_CR0_CD (1UL<<30) /* Cache Disable */ 1464 #define X86_CR0_PG (1UL<<31) /* Paging */ 1465 1466 #define PFERR_PRESENT_BIT 0 1467 #define PFERR_WRITE_BIT 1 1468 #define PFERR_USER_BIT 2 1469 #define PFERR_RSVD_BIT 3 1470 #define PFERR_FETCH_BIT 4 1471 #define PFERR_PK_BIT 5 1472 #define PFERR_SGX_BIT 15 1473 #define PFERR_GUEST_FINAL_BIT 32 1474 #define PFERR_GUEST_PAGE_BIT 33 1475 #define PFERR_IMPLICIT_ACCESS_BIT 48 1476 1477 #define PFERR_PRESENT_MASK BIT(PFERR_PRESENT_BIT) 1478 #define PFERR_WRITE_MASK BIT(PFERR_WRITE_BIT) 1479 #define PFERR_USER_MASK BIT(PFERR_USER_BIT) 1480 #define PFERR_RSVD_MASK BIT(PFERR_RSVD_BIT) 1481 #define PFERR_FETCH_MASK BIT(PFERR_FETCH_BIT) 1482 #define PFERR_PK_MASK BIT(PFERR_PK_BIT) 1483 #define PFERR_SGX_MASK BIT(PFERR_SGX_BIT) 1484 #define PFERR_GUEST_FINAL_MASK BIT_ULL(PFERR_GUEST_FINAL_BIT) 1485 #define PFERR_GUEST_PAGE_MASK BIT_ULL(PFERR_GUEST_PAGE_BIT) 1486 #define PFERR_IMPLICIT_ACCESS BIT_ULL(PFERR_IMPLICIT_ACCESS_BIT) 1487 1488 bool sys_clocksource_is_based_on_tsc(void); 1489 1490 #endif /* SELFTEST_KVM_PROCESSOR_H */ 1491