1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2021, Google LLC. 4 */ 5 6 #ifndef SELFTEST_KVM_APIC_H 7 #define SELFTEST_KVM_APIC_H 8 9 #include <stdint.h> 10 11 #include "processor.h" 12 #include "ucall_common.h" 13 14 #define APIC_DEFAULT_GPA 0xfee00000ULL 15 16 /* APIC base address MSR and fields */ 17 #define MSR_IA32_APICBASE 0x0000001b 18 #define MSR_IA32_APICBASE_BSP (1<<8) 19 #define MSR_IA32_APICBASE_EXTD (1<<10) 20 #define MSR_IA32_APICBASE_ENABLE (1<<11) 21 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 22 #define GET_APIC_BASE(x) (((x) >> 12) << 12) 23 24 #define APIC_BASE_MSR 0x800 25 #define X2APIC_ENABLE (1UL << 10) 26 #define APIC_ID 0x20 27 #define APIC_LVR 0x30 28 #define GET_APIC_ID_FIELD(x) (((x) >> 24) & 0xFF) 29 #define APIC_TASKPRI 0x80 30 #define APIC_PROCPRI 0xA0 31 #define APIC_EOI 0xB0 32 #define APIC_SPIV 0xF0 33 #define APIC_SPIV_FOCUS_DISABLED (1 << 9) 34 #define APIC_SPIV_APIC_ENABLED (1 << 8) 35 #define APIC_ISR 0x100 36 #define APIC_IRR 0x200 37 #define APIC_ICR 0x300 38 #define APIC_LVTCMCI 0x2f0 39 #define APIC_DEST_SELF 0x40000 40 #define APIC_DEST_ALLINC 0x80000 41 #define APIC_DEST_ALLBUT 0xC0000 42 #define APIC_ICR_RR_MASK 0x30000 43 #define APIC_ICR_RR_INVALID 0x00000 44 #define APIC_ICR_RR_INPROG 0x10000 45 #define APIC_ICR_RR_VALID 0x20000 46 #define APIC_INT_LEVELTRIG 0x08000 47 #define APIC_INT_ASSERT 0x04000 48 #define APIC_ICR_BUSY 0x01000 49 #define APIC_DEST_LOGICAL 0x00800 50 #define APIC_DEST_PHYSICAL 0x00000 51 #define APIC_DM_FIXED 0x00000 52 #define APIC_DM_FIXED_MASK 0x00700 53 #define APIC_DM_LOWEST 0x00100 54 #define APIC_DM_SMI 0x00200 55 #define APIC_DM_REMRD 0x00300 56 #define APIC_DM_NMI 0x00400 57 #define APIC_DM_INIT 0x00500 58 #define APIC_DM_STARTUP 0x00600 59 #define APIC_DM_EXTINT 0x00700 60 #define APIC_VECTOR_MASK 0x000FF 61 #define APIC_ICR2 0x310 62 #define SET_APIC_DEST_FIELD(x) ((x) << 24) 63 #define APIC_LVTT 0x320 64 #define APIC_LVT_TIMER_ONESHOT (0 << 17) 65 #define APIC_LVT_TIMER_PERIODIC (1 << 17) 66 #define APIC_LVT_TIMER_TSCDEADLINE (2 << 17) 67 #define APIC_LVT_MASKED (1 << 16) 68 #define APIC_TMICT 0x380 69 #define APIC_TMCCT 0x390 70 #define APIC_TDCR 0x3E0 71 72 #define APIC_VECTOR_TO_BIT_NUMBER(v) ((unsigned int)(v) % 32) 73 #define APIC_VECTOR_TO_REG_OFFSET(v) ((unsigned int)(v) / 32 * 0x10) 74 75 void apic_disable(void); 76 void xapic_enable(void); 77 void x2apic_enable(void); 78 79 static inline uint32_t get_bsp_flag(void) 80 { 81 return rdmsr(MSR_IA32_APICBASE) & MSR_IA32_APICBASE_BSP; 82 } 83 84 static inline uint32_t xapic_read_reg(unsigned int reg) 85 { 86 return ((volatile uint32_t *)APIC_DEFAULT_GPA)[reg >> 2]; 87 } 88 89 static inline void xapic_write_reg(unsigned int reg, uint32_t val) 90 { 91 ((volatile uint32_t *)APIC_DEFAULT_GPA)[reg >> 2] = val; 92 } 93 94 static inline uint64_t x2apic_read_reg(unsigned int reg) 95 { 96 return rdmsr(APIC_BASE_MSR + (reg >> 4)); 97 } 98 99 static inline uint8_t x2apic_write_reg_safe(unsigned int reg, uint64_t value) 100 { 101 return wrmsr_safe(APIC_BASE_MSR + (reg >> 4), value); 102 } 103 104 static inline void x2apic_write_reg(unsigned int reg, uint64_t value) 105 { 106 uint8_t fault = x2apic_write_reg_safe(reg, value); 107 108 __GUEST_ASSERT(!fault, "Unexpected fault 0x%x on WRMSR(%x) = %lx\n", 109 fault, APIC_BASE_MSR + (reg >> 4), value); 110 } 111 112 static inline void x2apic_write_reg_fault(unsigned int reg, uint64_t value) 113 { 114 uint8_t fault = x2apic_write_reg_safe(reg, value); 115 116 __GUEST_ASSERT(fault == GP_VECTOR, 117 "Wanted #GP on WRMSR(%x) = %lx, got 0x%x\n", 118 APIC_BASE_MSR + (reg >> 4), value, fault); 119 } 120 121 122 #endif /* SELFTEST_KVM_APIC_H */ 123