1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SELFTEST_KVM_PROCESSOR_H 4 #define SELFTEST_KVM_PROCESSOR_H 5 6 #ifndef __ASSEMBLER__ 7 #include "ucall_common.h" 8 9 #else 10 /* general registers */ 11 #define zero $r0 12 #define ra $r1 13 #define tp $r2 14 #define sp $r3 15 #define a0 $r4 16 #define a1 $r5 17 #define a2 $r6 18 #define a3 $r7 19 #define a4 $r8 20 #define a5 $r9 21 #define a6 $r10 22 #define a7 $r11 23 #define t0 $r12 24 #define t1 $r13 25 #define t2 $r14 26 #define t3 $r15 27 #define t4 $r16 28 #define t5 $r17 29 #define t6 $r18 30 #define t7 $r19 31 #define t8 $r20 32 #define u0 $r21 33 #define fp $r22 34 #define s0 $r23 35 #define s1 $r24 36 #define s2 $r25 37 #define s3 $r26 38 #define s4 $r27 39 #define s5 $r28 40 #define s6 $r29 41 #define s7 $r30 42 #define s8 $r31 43 #endif 44 45 /* 46 * LoongArch page table entry definition 47 * Original header file arch/loongarch/include/asm/loongarch.h 48 */ 49 #define _PAGE_VALID_SHIFT 0 50 #define _PAGE_DIRTY_SHIFT 1 51 #define _PAGE_PLV_SHIFT 2 /* 2~3, two bits */ 52 #define PLV_KERN 0 53 #define PLV_USER 3 54 #define PLV_MASK 0x3 55 #define _CACHE_SHIFT 4 /* 4~5, two bits */ 56 #define _PAGE_PRESENT_SHIFT 7 57 #define _PAGE_WRITE_SHIFT 8 58 59 #define _PAGE_VALID BIT_ULL(_PAGE_VALID_SHIFT) 60 #define _PAGE_PRESENT BIT_ULL(_PAGE_PRESENT_SHIFT) 61 #define _PAGE_WRITE BIT_ULL(_PAGE_WRITE_SHIFT) 62 #define _PAGE_DIRTY BIT_ULL(_PAGE_DIRTY_SHIFT) 63 #define _PAGE_USER (PLV_USER << _PAGE_PLV_SHIFT) 64 #define __READABLE (_PAGE_VALID) 65 #define __WRITEABLE (_PAGE_DIRTY | _PAGE_WRITE) 66 /* Coherent Cached */ 67 #define _CACHE_CC BIT_ULL(_CACHE_SHIFT) 68 #define PS_4K 0x0000000c 69 #define PS_16K 0x0000000e 70 #define PS_64K 0x00000010 71 #define PS_DEFAULT_SIZE PS_16K 72 73 /* LoongArch Basic CSR registers */ 74 #define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */ 75 #define CSR_CRMD_PG_SHIFT 4 76 #define CSR_CRMD_PG BIT_ULL(CSR_CRMD_PG_SHIFT) 77 #define CSR_CRMD_IE_SHIFT 2 78 #define CSR_CRMD_IE BIT_ULL(CSR_CRMD_IE_SHIFT) 79 #define CSR_CRMD_PLV_SHIFT 0 80 #define CSR_CRMD_PLV_WIDTH 2 81 #define CSR_CRMD_PLV (0x3UL << CSR_CRMD_PLV_SHIFT) 82 #define PLV_MASK 0x3 83 #define LOONGARCH_CSR_PRMD 0x1 84 #define LOONGARCH_CSR_EUEN 0x2 85 #define LOONGARCH_CSR_ECFG 0x4 86 #define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */ 87 #define CSR_ESTAT_EXC_SHIFT 16 88 #define CSR_ESTAT_EXC_WIDTH 6 89 #define CSR_ESTAT_EXC (0x3f << CSR_ESTAT_EXC_SHIFT) 90 #define EXCCODE_INT 0 /* Interrupt */ 91 #define INT_TI 11 /* Timer interrupt*/ 92 #define LOONGARCH_CSR_ERA 0x6 /* ERA */ 93 #define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */ 94 #define LOONGARCH_CSR_EENTRY 0xc 95 #define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize */ 96 #define CSR_TLBIDX_PS_SHIFT 24 97 #define CSR_TLBIDX_PS_WIDTH 6 98 #define CSR_TLBIDX_PS (0x3fUL << CSR_TLBIDX_PS_SHIFT) 99 #define CSR_TLBIDX_SIZEM 0x3f000000 100 #define CSR_TLBIDX_SIZE CSR_TLBIDX_PS_SHIFT 101 #define LOONGARCH_CSR_ASID 0x18 /* ASID */ 102 #define LOONGARCH_CSR_PGDL 0x19 103 #define LOONGARCH_CSR_PGDH 0x1a 104 /* Page table base */ 105 #define LOONGARCH_CSR_PGD 0x1b 106 #define LOONGARCH_CSR_PWCTL0 0x1c 107 #define LOONGARCH_CSR_PWCTL1 0x1d 108 #define LOONGARCH_CSR_STLBPGSIZE 0x1e 109 #define LOONGARCH_CSR_CPUID 0x20 110 #define LOONGARCH_CSR_KS0 0x30 111 #define LOONGARCH_CSR_KS1 0x31 112 #define LOONGARCH_CSR_TMID 0x40 113 #define LOONGARCH_CSR_TCFG 0x41 114 /* TLB refill exception entry */ 115 #define LOONGARCH_CSR_TLBRENTRY 0x88 116 #define LOONGARCH_CSR_TLBRSAVE 0x8b 117 #define LOONGARCH_CSR_TLBREHI 0x8e 118 #define CSR_TLBREHI_PS_SHIFT 0 119 #define CSR_TLBREHI_PS (0x3fUL << CSR_TLBREHI_PS_SHIFT) 120 121 #define csr_read(csr) \ 122 ({ \ 123 register unsigned long __v; \ 124 __asm__ __volatile__( \ 125 "csrrd %[val], %[reg]\n\t" \ 126 : [val] "=r" (__v) \ 127 : [reg] "i" (csr) \ 128 : "memory"); \ 129 __v; \ 130 }) 131 132 #define csr_write(v, csr) \ 133 ({ \ 134 register unsigned long __v = v; \ 135 __asm__ __volatile__ ( \ 136 "csrwr %[val], %[reg]\n\t" \ 137 : [val] "+r" (__v) \ 138 : [reg] "i" (csr) \ 139 : "memory"); \ 140 __v; \ 141 }) 142 143 #define EXREGS_GPRS (32) 144 145 #ifndef __ASSEMBLER__ 146 void handle_tlb_refill(void); 147 void handle_exception(void); 148 149 struct ex_regs { 150 unsigned long regs[EXREGS_GPRS]; 151 unsigned long pc; 152 unsigned long estat; 153 unsigned long badv; 154 unsigned long prmd; 155 }; 156 157 #define PC_OFFSET_EXREGS offsetof(struct ex_regs, pc) 158 #define ESTAT_OFFSET_EXREGS offsetof(struct ex_regs, estat) 159 #define BADV_OFFSET_EXREGS offsetof(struct ex_regs, badv) 160 #define PRMD_OFFSET_EXREGS offsetof(struct ex_regs, prmd) 161 #define EXREGS_SIZE sizeof(struct ex_regs) 162 163 #define VECTOR_NUM 64 164 165 typedef void(*handler_fn)(struct ex_regs *); 166 167 struct handlers { 168 handler_fn exception_handlers[VECTOR_NUM]; 169 }; 170 171 void vm_init_descriptor_tables(struct kvm_vm *vm); 172 void vm_install_exception_handler(struct kvm_vm *vm, int vector, handler_fn handler); 173 174 static inline void cpu_relax(void) 175 { 176 asm volatile("nop" ::: "memory"); 177 } 178 179 static inline void local_irq_enable(void) 180 { 181 unsigned int flags = CSR_CRMD_IE; 182 register unsigned int mask asm("$t0") = CSR_CRMD_IE; 183 184 __asm__ __volatile__( 185 "csrxchg %[val], %[mask], %[reg]\n\t" 186 : [val] "+r" (flags) 187 : [mask] "r" (mask), [reg] "i" (LOONGARCH_CSR_CRMD) 188 : "memory"); 189 } 190 191 static inline void local_irq_disable(void) 192 { 193 unsigned int flags = 0; 194 register unsigned int mask asm("$t0") = CSR_CRMD_IE; 195 196 __asm__ __volatile__( 197 "csrxchg %[val], %[mask], %[reg]\n\t" 198 : [val] "+r" (flags) 199 : [mask] "r" (mask), [reg] "i" (LOONGARCH_CSR_CRMD) 200 : "memory"); 201 } 202 #else 203 #define PC_OFFSET_EXREGS ((EXREGS_GPRS + 0) * 8) 204 #define ESTAT_OFFSET_EXREGS ((EXREGS_GPRS + 1) * 8) 205 #define BADV_OFFSET_EXREGS ((EXREGS_GPRS + 2) * 8) 206 #define PRMD_OFFSET_EXREGS ((EXREGS_GPRS + 3) * 8) 207 #define EXREGS_SIZE ((EXREGS_GPRS + 4) * 8) 208 #endif 209 210 #endif /* SELFTEST_KVM_PROCESSOR_H */ 211