1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SELFTEST_KVM_PROCESSOR_H 4 #define SELFTEST_KVM_PROCESSOR_H 5 6 #ifndef __ASSEMBLER__ 7 #include "ucall_common.h" 8 9 #else 10 /* general registers */ 11 #define zero $r0 12 #define ra $r1 13 #define tp $r2 14 #define sp $r3 15 #define a0 $r4 16 #define a1 $r5 17 #define a2 $r6 18 #define a3 $r7 19 #define a4 $r8 20 #define a5 $r9 21 #define a6 $r10 22 #define a7 $r11 23 #define t0 $r12 24 #define t1 $r13 25 #define t2 $r14 26 #define t3 $r15 27 #define t4 $r16 28 #define t5 $r17 29 #define t6 $r18 30 #define t7 $r19 31 #define t8 $r20 32 #define u0 $r21 33 #define fp $r22 34 #define s0 $r23 35 #define s1 $r24 36 #define s2 $r25 37 #define s3 $r26 38 #define s4 $r27 39 #define s5 $r28 40 #define s6 $r29 41 #define s7 $r30 42 #define s8 $r31 43 #endif 44 45 /* 46 * LoongArch page table entry definition 47 * Original header file arch/loongarch/include/asm/loongarch.h 48 */ 49 #define _PAGE_VALID_SHIFT 0 50 #define _PAGE_DIRTY_SHIFT 1 51 #define _PAGE_PLV_SHIFT 2 /* 2~3, two bits */ 52 #define PLV_KERN 0 53 #define PLV_USER 3 54 #define PLV_MASK 0x3 55 #define _CACHE_SHIFT 4 /* 4~5, two bits */ 56 #define _PAGE_PRESENT_SHIFT 7 57 #define _PAGE_WRITE_SHIFT 8 58 59 #define _PAGE_VALID BIT_ULL(_PAGE_VALID_SHIFT) 60 #define _PAGE_PRESENT BIT_ULL(_PAGE_PRESENT_SHIFT) 61 #define _PAGE_WRITE BIT_ULL(_PAGE_WRITE_SHIFT) 62 #define _PAGE_DIRTY BIT_ULL(_PAGE_DIRTY_SHIFT) 63 #define _PAGE_USER (PLV_USER << _PAGE_PLV_SHIFT) 64 #define __READABLE (_PAGE_VALID) 65 #define __WRITEABLE (_PAGE_DIRTY | _PAGE_WRITE) 66 /* Coherent Cached */ 67 #define _CACHE_CC BIT_ULL(_CACHE_SHIFT) 68 #define PS_4K 0x0000000c 69 #define PS_16K 0x0000000e 70 #define PS_64K 0x00000010 71 #define PS_DEFAULT_SIZE PS_16K 72 73 #define LOONGARCH_CPUCFG2 0x2 74 #define CPUCFG2_FP BIT(0) 75 #define CPUCFG2_FPSP BIT(1) 76 #define CPUCFG2_FPDP BIT(2) 77 #define CPUCFG2_FPVERS GENMASK(5, 3) 78 #define CPUCFG2_LSX BIT(6) 79 #define CPUCFG2_LASX BIT(7) 80 #define CPUCFG2_LLFTP BIT(14) 81 #define CPUCFG2_LLFTPREV GENMASK(17, 15) 82 83 /* LoongArch Basic CSR registers */ 84 #define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */ 85 #define CSR_CRMD_PG_SHIFT 4 86 #define CSR_CRMD_PG BIT_ULL(CSR_CRMD_PG_SHIFT) 87 #define CSR_CRMD_IE_SHIFT 2 88 #define CSR_CRMD_IE BIT_ULL(CSR_CRMD_IE_SHIFT) 89 #define CSR_CRMD_PLV_SHIFT 0 90 #define CSR_CRMD_PLV_WIDTH 2 91 #define CSR_CRMD_PLV (0x3UL << CSR_CRMD_PLV_SHIFT) 92 #define PLV_MASK 0x3 93 #define LOONGARCH_CSR_PRMD 0x1 94 #define LOONGARCH_CSR_EUEN 0x2 95 #define CSR_EUEN_LBTEN_SHIFT 3 96 #define CSR_EUEN_LBTEN BIT_ULL(CSR_EUEN_LBTEN_SHIFT) 97 #define CSR_EUEN_LASXEN_SHIFT 2 98 #define CSR_EUEN_LASXEN BIT_ULL(CSR_EUEN_LASXEN_SHIFT) 99 #define CSR_EUEN_LSXEN_SHIFT 1 100 #define CSR_EUEN_LSXEN BIT_ULL(CSR_EUEN_LSXEN_SHIFT) 101 #define CSR_EUEN_FPEN_SHIFT 0 102 #define CSR_EUEN_FPEN BIT_ULL(CSR_EUEN_FPEN_SHIFT) 103 #define LOONGARCH_CSR_ECFG 0x4 104 #define ECFGB_PMU 10 105 #define ECFGF_PMU (BIT_ULL(ECFGB_PMU)) 106 #define ECFGB_TIMER 11 107 #define ECFGF_TIMER (BIT_ULL(ECFGB_TIMER)) 108 #define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */ 109 #define CSR_ESTAT_EXC_SHIFT 16 110 #define CSR_ESTAT_EXC_WIDTH 6 111 #define CSR_ESTAT_EXC (0x3f << CSR_ESTAT_EXC_SHIFT) 112 #define EXCCODE_INT 0 /* Interrupt */ 113 #define INT_PMI 10 /* PMU interrupt */ 114 #define INT_TI 11 /* Timer interrupt*/ 115 #define LOONGARCH_CSR_ERA 0x6 /* ERA */ 116 #define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */ 117 #define LOONGARCH_CSR_EENTRY 0xc 118 #define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize */ 119 #define CSR_TLBIDX_PS_SHIFT 24 120 #define CSR_TLBIDX_PS_WIDTH 6 121 #define CSR_TLBIDX_PS (0x3fUL << CSR_TLBIDX_PS_SHIFT) 122 #define CSR_TLBIDX_SIZEM 0x3f000000 123 #define CSR_TLBIDX_SIZE CSR_TLBIDX_PS_SHIFT 124 #define LOONGARCH_CSR_ASID 0x18 /* ASID */ 125 #define LOONGARCH_CSR_PGDL 0x19 126 #define LOONGARCH_CSR_PGDH 0x1a 127 /* Page table base */ 128 #define LOONGARCH_CSR_PGD 0x1b 129 #define LOONGARCH_CSR_PWCTL0 0x1c 130 #define LOONGARCH_CSR_PWCTL1 0x1d 131 #define LOONGARCH_CSR_STLBPGSIZE 0x1e 132 #define LOONGARCH_CSR_CPUID 0x20 133 #define LOONGARCH_CSR_KS0 0x30 134 #define LOONGARCH_CSR_KS1 0x31 135 #define LOONGARCH_CSR_TMID 0x40 136 #define LOONGARCH_CSR_TCFG 0x41 137 #define CSR_TCFG_VAL (BIT_ULL(48) - BIT_ULL(2)) 138 #define CSR_TCFG_PERIOD_SHIFT 1 139 #define CSR_TCFG_PERIOD (0x1UL << CSR_TCFG_PERIOD_SHIFT) 140 #define CSR_TCFG_EN (0x1UL) 141 #define LOONGARCH_CSR_TVAL 0x42 142 #define LOONGARCH_CSR_TINTCLR 0x44 /* Timer interrupt clear */ 143 #define CSR_TINTCLR_TI_SHIFT 0 144 #define CSR_TINTCLR_TI (1 << CSR_TINTCLR_TI_SHIFT) 145 /* TLB refill exception entry */ 146 #define LOONGARCH_CSR_TLBRENTRY 0x88 147 #define LOONGARCH_CSR_TLBRSAVE 0x8b 148 #define LOONGARCH_CSR_TLBREHI 0x8e 149 #define CSR_TLBREHI_PS_SHIFT 0 150 #define CSR_TLBREHI_PS (0x3fUL << CSR_TLBREHI_PS_SHIFT) 151 152 #define read_cpucfg(reg) \ 153 ({ \ 154 register unsigned long __v; \ 155 __asm__ __volatile__( \ 156 "cpucfg %0, %1\n\t" \ 157 : "=r" (__v) \ 158 : "r" (reg) \ 159 : "memory"); \ 160 __v; \ 161 }) 162 163 #define csr_read(csr) \ 164 ({ \ 165 register unsigned long __v; \ 166 __asm__ __volatile__( \ 167 "csrrd %[val], %[reg]\n\t" \ 168 : [val] "=r" (__v) \ 169 : [reg] "i" (csr) \ 170 : "memory"); \ 171 __v; \ 172 }) 173 174 #define csr_write(v, csr) \ 175 ({ \ 176 register unsigned long __v = v; \ 177 __asm__ __volatile__ ( \ 178 "csrwr %[val], %[reg]\n\t" \ 179 : [val] "+r" (__v) \ 180 : [reg] "i" (csr) \ 181 : "memory"); \ 182 __v; \ 183 }) 184 185 #define EXREGS_GPRS (32) 186 187 #ifndef __ASSEMBLER__ 188 void handle_tlb_refill(void); 189 void handle_exception(void); 190 191 struct ex_regs { 192 unsigned long regs[EXREGS_GPRS]; 193 unsigned long pc; 194 unsigned long estat; 195 unsigned long badv; 196 unsigned long prmd; 197 }; 198 199 #define PC_OFFSET_EXREGS offsetof(struct ex_regs, pc) 200 #define ESTAT_OFFSET_EXREGS offsetof(struct ex_regs, estat) 201 #define BADV_OFFSET_EXREGS offsetof(struct ex_regs, badv) 202 #define PRMD_OFFSET_EXREGS offsetof(struct ex_regs, prmd) 203 #define EXREGS_SIZE sizeof(struct ex_regs) 204 205 #define VECTOR_NUM 64 206 207 typedef void(*handler_fn)(struct ex_regs *); 208 209 struct handlers { 210 handler_fn exception_handlers[VECTOR_NUM]; 211 }; 212 213 void loongarch_vcpu_setup(struct kvm_vcpu *vcpu); 214 void vm_init_descriptor_tables(struct kvm_vm *vm); 215 void vm_install_exception_handler(struct kvm_vm *vm, int vector, handler_fn handler); 216 217 static inline void cpu_relax(void) 218 { 219 asm volatile("nop" ::: "memory"); 220 } 221 222 static inline void local_irq_enable(void) 223 { 224 unsigned int flags = CSR_CRMD_IE; 225 register unsigned int mask asm("$t0") = CSR_CRMD_IE; 226 227 __asm__ __volatile__( 228 "csrxchg %[val], %[mask], %[reg]\n\t" 229 : [val] "+r" (flags) 230 : [mask] "r" (mask), [reg] "i" (LOONGARCH_CSR_CRMD) 231 : "memory"); 232 } 233 234 static inline void local_irq_disable(void) 235 { 236 unsigned int flags = 0; 237 register unsigned int mask asm("$t0") = CSR_CRMD_IE; 238 239 __asm__ __volatile__( 240 "csrxchg %[val], %[mask], %[reg]\n\t" 241 : [val] "+r" (flags) 242 : [mask] "r" (mask), [reg] "i" (LOONGARCH_CSR_CRMD) 243 : "memory"); 244 } 245 #else 246 #define PC_OFFSET_EXREGS ((EXREGS_GPRS + 0) * 8) 247 #define ESTAT_OFFSET_EXREGS ((EXREGS_GPRS + 1) * 8) 248 #define BADV_OFFSET_EXREGS ((EXREGS_GPRS + 2) * 8) 249 #define PRMD_OFFSET_EXREGS ((EXREGS_GPRS + 3) * 8) 250 #define EXREGS_SIZE ((EXREGS_GPRS + 4) * 8) 251 #endif 252 253 #endif /* SELFTEST_KVM_PROCESSOR_H */ 254