1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * set_id_regs - Test for setting ID register from usersapce. 4 * 5 * Copyright (c) 2023 Google LLC. 6 * 7 * 8 * Test that KVM supports setting ID registers from userspace and handles the 9 * feature set correctly. 10 */ 11 12 #include <stdint.h> 13 #include "kvm_util.h" 14 #include "processor.h" 15 #include "test_util.h" 16 #include <linux/bitfield.h> 17 18 enum ftr_type { 19 FTR_EXACT, /* Use a predefined safe value */ 20 FTR_LOWER_SAFE, /* Smaller value is safe */ 21 FTR_HIGHER_SAFE, /* Bigger value is safe */ 22 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */ 23 FTR_END, /* Mark the last ftr bits */ 24 }; 25 26 #define FTR_SIGNED true /* Value should be treated as signed */ 27 #define FTR_UNSIGNED false /* Value should be treated as unsigned */ 28 29 struct reg_ftr_bits { 30 char *name; 31 bool sign; 32 enum ftr_type type; 33 uint8_t shift; 34 uint64_t mask; 35 /* 36 * For FTR_EXACT, safe_val is used as the exact safe value. 37 * For FTR_LOWER_SAFE, safe_val is used as the minimal safe value. 38 */ 39 int64_t safe_val; 40 }; 41 42 struct test_feature_reg { 43 uint32_t reg; 44 const struct reg_ftr_bits *ftr_bits; 45 }; 46 47 #define __REG_FTR_BITS(NAME, SIGNED, TYPE, SHIFT, MASK, SAFE_VAL) \ 48 { \ 49 .name = #NAME, \ 50 .sign = SIGNED, \ 51 .type = TYPE, \ 52 .shift = SHIFT, \ 53 .mask = MASK, \ 54 .safe_val = SAFE_VAL, \ 55 } 56 57 #define REG_FTR_BITS(type, reg, field, safe_val) \ 58 __REG_FTR_BITS(reg##_##field, FTR_UNSIGNED, type, reg##_##field##_SHIFT, \ 59 reg##_##field##_MASK, safe_val) 60 61 #define S_REG_FTR_BITS(type, reg, field, safe_val) \ 62 __REG_FTR_BITS(reg##_##field, FTR_SIGNED, type, reg##_##field##_SHIFT, \ 63 reg##_##field##_MASK, safe_val) 64 65 #define REG_FTR_END \ 66 { \ 67 .type = FTR_END, \ 68 } 69 70 static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = { 71 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DoubleLock, 0), 72 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, WRPs, 0), 73 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0), 74 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, ID_AA64DFR0_EL1_DebugVer_IMP), 75 REG_FTR_END, 76 }; 77 78 static const struct reg_ftr_bits ftr_id_dfr0_el1[] = { 79 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, PerfMon, ID_DFR0_EL1_PerfMon_PMUv3), 80 REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, CopDbg, ID_DFR0_EL1_CopDbg_Armv8), 81 REG_FTR_END, 82 }; 83 84 static const struct reg_ftr_bits ftr_id_aa64isar0_el1[] = { 85 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RNDR, 0), 86 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TLB, 0), 87 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TS, 0), 88 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, FHM, 0), 89 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, DP, 0), 90 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM4, 0), 91 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM3, 0), 92 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA3, 0), 93 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RDM, 0), 94 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TME, 0), 95 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, ATOMIC, 0), 96 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, CRC32, 0), 97 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA2, 0), 98 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA1, 0), 99 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, AES, 0), 100 REG_FTR_END, 101 }; 102 103 static const struct reg_ftr_bits ftr_id_aa64isar1_el1[] = { 104 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LS64, 0), 105 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, XS, 0), 106 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, I8MM, 0), 107 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DGH, 0), 108 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, BF16, 0), 109 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SPECRES, 0), 110 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SB, 0), 111 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FRINTTS, 0), 112 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LRCPC, 0), 113 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FCMA, 0), 114 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, JSCVT, 0), 115 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DPB, 0), 116 REG_FTR_END, 117 }; 118 119 static const struct reg_ftr_bits ftr_id_aa64isar2_el1[] = { 120 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, BC, 0), 121 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, RPRES, 0), 122 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, WFxT, 0), 123 REG_FTR_END, 124 }; 125 126 static const struct reg_ftr_bits ftr_id_aa64isar3_el1[] = { 127 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR3_EL1, FPRCVT, 0), 128 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR3_EL1, LSFE, 0), 129 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR3_EL1, FAMINMAX, 0), 130 REG_FTR_END, 131 }; 132 133 static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = { 134 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV3, 0), 135 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV2, 0), 136 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, DIT, 0), 137 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, SEL2, 0), 138 REG_FTR_BITS(FTR_EXACT, ID_AA64PFR0_EL1, GIC, 0), 139 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL3, 1), 140 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL2, 1), 141 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL1, 1), 142 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL0, 1), 143 REG_FTR_END, 144 }; 145 146 static const struct reg_ftr_bits ftr_id_aa64pfr1_el1[] = { 147 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, DF2, 0), 148 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, CSV2_frac, 0), 149 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, SSBS, ID_AA64PFR1_EL1_SSBS_NI), 150 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, BT, 0), 151 REG_FTR_END, 152 }; 153 154 static const struct reg_ftr_bits ftr_id_aa64mmfr0_el1[] = { 155 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ECV, 0), 156 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, EXS, 0), 157 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN4_2, 1), 158 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN64_2, 1), 159 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN16_2, 1), 160 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN4, 0), 161 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN64, 0), 162 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN16, 0), 163 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGENDEL0, 0), 164 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, SNSMEM, 0), 165 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGEND, 0), 166 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, PARANGE, 0), 167 REG_FTR_END, 168 }; 169 170 static const struct reg_ftr_bits ftr_id_aa64mmfr1_el1[] = { 171 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, TIDCP1, 0), 172 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, AFP, 0), 173 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HCX, 0), 174 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, ETS, 0), 175 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, TWED, 0), 176 REG_FTR_BITS(FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1, SpecSEI, 0), 177 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, PAN, 0), 178 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, LO, 0), 179 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HPDS, 0), 180 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HAFDBS, 0), 181 REG_FTR_END, 182 }; 183 184 static const struct reg_ftr_bits ftr_id_aa64mmfr2_el1[] = { 185 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, E0PD, 0), 186 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, BBM, 0), 187 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, TTL, 0), 188 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, AT, 0), 189 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, ST, 0), 190 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, VARange, 0), 191 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, IESB, 0), 192 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, LSM, 0), 193 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, UAO, 0), 194 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, CnP, 0), 195 REG_FTR_END, 196 }; 197 198 static const struct reg_ftr_bits ftr_id_aa64mmfr3_el1[] = { 199 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, S1POE, 0), 200 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, S1PIE, 0), 201 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, SCTLRX, 0), 202 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, TCRX, 0), 203 REG_FTR_END, 204 }; 205 206 static const struct reg_ftr_bits ftr_id_aa64zfr0_el1[] = { 207 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F64MM, 0), 208 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F32MM, 0), 209 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, I8MM, 0), 210 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SM4, 0), 211 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SHA3, 0), 212 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BF16, 0), 213 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BitPerm, 0), 214 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, AES, 0), 215 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SVEver, 0), 216 REG_FTR_END, 217 }; 218 219 #define TEST_REG(id, table) \ 220 { \ 221 .reg = id, \ 222 .ftr_bits = &((table)[0]), \ 223 } 224 225 static struct test_feature_reg test_regs[] = { 226 TEST_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0_el1), 227 TEST_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0_el1), 228 TEST_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0_el1), 229 TEST_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1_el1), 230 TEST_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2_el1), 231 TEST_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3_el1), 232 TEST_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0_el1), 233 TEST_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1_el1), 234 TEST_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0_el1), 235 TEST_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1), 236 TEST_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1), 237 TEST_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3_el1), 238 TEST_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0_el1), 239 }; 240 241 #define GUEST_REG_SYNC(id) GUEST_SYNC_ARGS(0, id, read_sysreg_s(id), 0, 0); 242 243 static void guest_code(void) 244 { 245 GUEST_REG_SYNC(SYS_ID_AA64DFR0_EL1); 246 GUEST_REG_SYNC(SYS_ID_DFR0_EL1); 247 GUEST_REG_SYNC(SYS_ID_AA64ISAR0_EL1); 248 GUEST_REG_SYNC(SYS_ID_AA64ISAR1_EL1); 249 GUEST_REG_SYNC(SYS_ID_AA64ISAR2_EL1); 250 GUEST_REG_SYNC(SYS_ID_AA64ISAR3_EL1); 251 GUEST_REG_SYNC(SYS_ID_AA64PFR0_EL1); 252 GUEST_REG_SYNC(SYS_ID_AA64PFR1_EL1); 253 GUEST_REG_SYNC(SYS_ID_AA64MMFR0_EL1); 254 GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1); 255 GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1); 256 GUEST_REG_SYNC(SYS_ID_AA64MMFR3_EL1); 257 GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1); 258 GUEST_REG_SYNC(SYS_MPIDR_EL1); 259 GUEST_REG_SYNC(SYS_CLIDR_EL1); 260 GUEST_REG_SYNC(SYS_CTR_EL0); 261 GUEST_REG_SYNC(SYS_MIDR_EL1); 262 GUEST_REG_SYNC(SYS_REVIDR_EL1); 263 GUEST_REG_SYNC(SYS_AIDR_EL1); 264 265 GUEST_DONE(); 266 } 267 268 /* Return a safe value to a given ftr_bits an ftr value */ 269 uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr) 270 { 271 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0); 272 273 if (ftr_bits->sign == FTR_UNSIGNED) { 274 switch (ftr_bits->type) { 275 case FTR_EXACT: 276 ftr = ftr_bits->safe_val; 277 break; 278 case FTR_LOWER_SAFE: 279 if (ftr > ftr_bits->safe_val) 280 ftr--; 281 break; 282 case FTR_HIGHER_SAFE: 283 if (ftr < ftr_max) 284 ftr++; 285 break; 286 case FTR_HIGHER_OR_ZERO_SAFE: 287 if (ftr == ftr_max) 288 ftr = 0; 289 else if (ftr != 0) 290 ftr++; 291 break; 292 default: 293 break; 294 } 295 } else if (ftr != ftr_max) { 296 switch (ftr_bits->type) { 297 case FTR_EXACT: 298 ftr = ftr_bits->safe_val; 299 break; 300 case FTR_LOWER_SAFE: 301 if (ftr > ftr_bits->safe_val) 302 ftr--; 303 break; 304 case FTR_HIGHER_SAFE: 305 if (ftr < ftr_max - 1) 306 ftr++; 307 break; 308 case FTR_HIGHER_OR_ZERO_SAFE: 309 if (ftr != 0 && ftr != ftr_max - 1) 310 ftr++; 311 break; 312 default: 313 break; 314 } 315 } 316 317 return ftr; 318 } 319 320 /* Return an invalid value to a given ftr_bits an ftr value */ 321 uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr) 322 { 323 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0); 324 325 if (ftr_bits->sign == FTR_UNSIGNED) { 326 switch (ftr_bits->type) { 327 case FTR_EXACT: 328 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1); 329 break; 330 case FTR_LOWER_SAFE: 331 ftr++; 332 break; 333 case FTR_HIGHER_SAFE: 334 ftr--; 335 break; 336 case FTR_HIGHER_OR_ZERO_SAFE: 337 if (ftr == 0) 338 ftr = ftr_max; 339 else 340 ftr--; 341 break; 342 default: 343 break; 344 } 345 } else if (ftr != ftr_max) { 346 switch (ftr_bits->type) { 347 case FTR_EXACT: 348 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1); 349 break; 350 case FTR_LOWER_SAFE: 351 ftr++; 352 break; 353 case FTR_HIGHER_SAFE: 354 ftr--; 355 break; 356 case FTR_HIGHER_OR_ZERO_SAFE: 357 if (ftr == 0) 358 ftr = ftr_max - 1; 359 else 360 ftr--; 361 break; 362 default: 363 break; 364 } 365 } else { 366 ftr = 0; 367 } 368 369 return ftr; 370 } 371 372 static uint64_t test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg, 373 const struct reg_ftr_bits *ftr_bits) 374 { 375 uint8_t shift = ftr_bits->shift; 376 uint64_t mask = ftr_bits->mask; 377 uint64_t val, new_val, ftr; 378 379 val = vcpu_get_reg(vcpu, reg); 380 ftr = (val & mask) >> shift; 381 382 ftr = get_safe_value(ftr_bits, ftr); 383 384 ftr <<= shift; 385 val &= ~mask; 386 val |= ftr; 387 388 vcpu_set_reg(vcpu, reg, val); 389 new_val = vcpu_get_reg(vcpu, reg); 390 TEST_ASSERT_EQ(new_val, val); 391 392 return new_val; 393 } 394 395 static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg, 396 const struct reg_ftr_bits *ftr_bits) 397 { 398 uint8_t shift = ftr_bits->shift; 399 uint64_t mask = ftr_bits->mask; 400 uint64_t val, old_val, ftr; 401 int r; 402 403 val = vcpu_get_reg(vcpu, reg); 404 ftr = (val & mask) >> shift; 405 406 ftr = get_invalid_value(ftr_bits, ftr); 407 408 old_val = val; 409 ftr <<= shift; 410 val &= ~mask; 411 val |= ftr; 412 413 r = __vcpu_set_reg(vcpu, reg, val); 414 TEST_ASSERT(r < 0 && errno == EINVAL, 415 "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno); 416 417 val = vcpu_get_reg(vcpu, reg); 418 TEST_ASSERT_EQ(val, old_val); 419 } 420 421 static uint64_t test_reg_vals[KVM_ARM_FEATURE_ID_RANGE_SIZE]; 422 423 #define encoding_to_range_idx(encoding) \ 424 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(encoding), sys_reg_Op1(encoding), \ 425 sys_reg_CRn(encoding), sys_reg_CRm(encoding), \ 426 sys_reg_Op2(encoding)) 427 428 429 static void test_vm_ftr_id_regs(struct kvm_vcpu *vcpu, bool aarch64_only) 430 { 431 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE]; 432 struct reg_mask_range range = { 433 .addr = (__u64)masks, 434 }; 435 int ret; 436 437 /* KVM should return error when reserved field is not zero */ 438 range.reserved[0] = 1; 439 ret = __vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range); 440 TEST_ASSERT(ret, "KVM doesn't check invalid parameters."); 441 442 /* Get writable masks for feature ID registers */ 443 memset(range.reserved, 0, sizeof(range.reserved)); 444 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range); 445 446 for (int i = 0; i < ARRAY_SIZE(test_regs); i++) { 447 const struct reg_ftr_bits *ftr_bits = test_regs[i].ftr_bits; 448 uint32_t reg_id = test_regs[i].reg; 449 uint64_t reg = KVM_ARM64_SYS_REG(reg_id); 450 int idx; 451 452 /* Get the index to masks array for the idreg */ 453 idx = encoding_to_range_idx(reg_id); 454 455 for (int j = 0; ftr_bits[j].type != FTR_END; j++) { 456 /* Skip aarch32 reg on aarch64 only system, since they are RAZ/WI. */ 457 if (aarch64_only && sys_reg_CRm(reg_id) < 4) { 458 ksft_test_result_skip("%s on AARCH64 only system\n", 459 ftr_bits[j].name); 460 continue; 461 } 462 463 /* Make sure the feature field is writable */ 464 TEST_ASSERT_EQ(masks[idx] & ftr_bits[j].mask, ftr_bits[j].mask); 465 466 test_reg_set_fail(vcpu, reg, &ftr_bits[j]); 467 468 test_reg_vals[idx] = test_reg_set_success(vcpu, reg, 469 &ftr_bits[j]); 470 471 ksft_test_result_pass("%s\n", ftr_bits[j].name); 472 } 473 } 474 } 475 476 #define MPAM_IDREG_TEST 6 477 static void test_user_set_mpam_reg(struct kvm_vcpu *vcpu) 478 { 479 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE]; 480 struct reg_mask_range range = { 481 .addr = (__u64)masks, 482 }; 483 uint64_t val; 484 int idx, err; 485 486 /* 487 * If ID_AA64PFR0.MPAM is _not_ officially modifiable and is zero, 488 * check that if it can be set to 1, (i.e. it is supported by the 489 * hardware), that it can't be set to other values. 490 */ 491 492 /* Get writable masks for feature ID registers */ 493 memset(range.reserved, 0, sizeof(range.reserved)); 494 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range); 495 496 /* Writeable? Nothing to test! */ 497 idx = encoding_to_range_idx(SYS_ID_AA64PFR0_EL1); 498 if ((masks[idx] & ID_AA64PFR0_EL1_MPAM_MASK) == ID_AA64PFR0_EL1_MPAM_MASK) { 499 ksft_test_result_skip("ID_AA64PFR0_EL1.MPAM is officially writable, nothing to test\n"); 500 return; 501 } 502 503 /* Get the id register value */ 504 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1)); 505 506 /* Try to set MPAM=0. This should always be possible. */ 507 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 508 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 0); 509 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val); 510 if (err) 511 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM=0 was not accepted\n"); 512 else 513 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM=0 worked\n"); 514 515 /* Try to set MPAM=1 */ 516 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 517 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 1); 518 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val); 519 if (err) 520 ksft_test_result_skip("ID_AA64PFR0_EL1.MPAM is not writable, nothing to test\n"); 521 else 522 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM=1 was writable\n"); 523 524 /* Try to set MPAM=2 */ 525 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 526 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 2); 527 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val); 528 if (err) 529 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM not arbitrarily modifiable\n"); 530 else 531 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM value should not be ignored\n"); 532 533 /* And again for ID_AA64PFR1_EL1.MPAM_frac */ 534 idx = encoding_to_range_idx(SYS_ID_AA64PFR1_EL1); 535 if ((masks[idx] & ID_AA64PFR1_EL1_MPAM_frac_MASK) == ID_AA64PFR1_EL1_MPAM_frac_MASK) { 536 ksft_test_result_skip("ID_AA64PFR1_EL1.MPAM_frac is officially writable, nothing to test\n"); 537 return; 538 } 539 540 /* Get the id register value */ 541 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1)); 542 543 /* Try to set MPAM_frac=0. This should always be possible. */ 544 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 545 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 0); 546 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val); 547 if (err) 548 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM_frac=0 was not accepted\n"); 549 else 550 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM_frac=0 worked\n"); 551 552 /* Try to set MPAM_frac=1 */ 553 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 554 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 1); 555 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val); 556 if (err) 557 ksft_test_result_skip("ID_AA64PFR1_EL1.MPAM_frac is not writable, nothing to test\n"); 558 else 559 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM_frac=1 was writable\n"); 560 561 /* Try to set MPAM_frac=2 */ 562 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 563 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 2); 564 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val); 565 if (err) 566 ksft_test_result_pass("ID_AA64PFR1_EL1.MPAM_frac not arbitrarily modifiable\n"); 567 else 568 ksft_test_result_fail("ID_AA64PFR1_EL1.MPAM_frac value should not be ignored\n"); 569 } 570 571 #define MTE_IDREG_TEST 1 572 static void test_user_set_mte_reg(struct kvm_vcpu *vcpu) 573 { 574 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE]; 575 struct reg_mask_range range = { 576 .addr = (__u64)masks, 577 }; 578 uint64_t val; 579 uint64_t mte; 580 uint64_t mte_frac; 581 int idx, err; 582 583 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1)); 584 mte = FIELD_GET(ID_AA64PFR1_EL1_MTE, val); 585 if (!mte) { 586 ksft_test_result_skip("MTE capability not supported, nothing to test\n"); 587 return; 588 } 589 590 /* Get writable masks for feature ID registers */ 591 memset(range.reserved, 0, sizeof(range.reserved)); 592 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range); 593 594 idx = encoding_to_range_idx(SYS_ID_AA64PFR1_EL1); 595 if ((masks[idx] & ID_AA64PFR1_EL1_MTE_frac_MASK) == ID_AA64PFR1_EL1_MTE_frac_MASK) { 596 ksft_test_result_skip("ID_AA64PFR1_EL1.MTE_frac is officially writable, nothing to test\n"); 597 return; 598 } 599 600 /* 601 * When MTE is supported but MTE_ASYMM is not (ID_AA64PFR1_EL1.MTE == 2) 602 * ID_AA64PFR1_EL1.MTE_frac == 0xF indicates MTE_ASYNC is unsupported 603 * and MTE_frac == 0 indicates it is supported. 604 * 605 * As MTE_frac was previously unconditionally read as 0, check 606 * that the set to 0 succeeds but does not change MTE_frac 607 * from unsupported (0xF) to supported (0). 608 * 609 */ 610 mte_frac = FIELD_GET(ID_AA64PFR1_EL1_MTE_frac, val); 611 if (mte != ID_AA64PFR1_EL1_MTE_MTE2 || 612 mte_frac != ID_AA64PFR1_EL1_MTE_frac_NI) { 613 ksft_test_result_skip("MTE_ASYNC or MTE_ASYMM are supported, nothing to test\n"); 614 return; 615 } 616 617 /* Try to set MTE_frac=0. */ 618 val &= ~ID_AA64PFR1_EL1_MTE_frac_MASK; 619 val |= FIELD_PREP(ID_AA64PFR1_EL1_MTE_frac_MASK, 0); 620 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val); 621 if (err) { 622 ksft_test_result_fail("ID_AA64PFR1_EL1.MTE_frac=0 was not accepted\n"); 623 return; 624 } 625 626 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1)); 627 mte_frac = FIELD_GET(ID_AA64PFR1_EL1_MTE_frac, val); 628 if (mte_frac == ID_AA64PFR1_EL1_MTE_frac_NI) 629 ksft_test_result_pass("ID_AA64PFR1_EL1.MTE_frac=0 accepted and still 0xF\n"); 630 else 631 ksft_test_result_pass("ID_AA64PFR1_EL1.MTE_frac no longer 0xF\n"); 632 } 633 634 static void test_guest_reg_read(struct kvm_vcpu *vcpu) 635 { 636 bool done = false; 637 struct ucall uc; 638 639 while (!done) { 640 vcpu_run(vcpu); 641 642 switch (get_ucall(vcpu, &uc)) { 643 case UCALL_ABORT: 644 REPORT_GUEST_ASSERT(uc); 645 break; 646 case UCALL_SYNC: 647 /* Make sure the written values are seen by guest */ 648 TEST_ASSERT_EQ(test_reg_vals[encoding_to_range_idx(uc.args[2])], 649 uc.args[3]); 650 break; 651 case UCALL_DONE: 652 done = true; 653 break; 654 default: 655 TEST_FAIL("Unexpected ucall: %lu", uc.cmd); 656 } 657 } 658 } 659 660 /* Politely lifted from arch/arm64/include/asm/cache.h */ 661 /* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */ 662 #define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) 663 #define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) 664 #define CLIDR_CTYPE(clidr, level) \ 665 (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) 666 667 static void test_clidr(struct kvm_vcpu *vcpu) 668 { 669 uint64_t clidr; 670 int level; 671 672 clidr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1)); 673 674 /* find the first empty level in the cache hierarchy */ 675 for (level = 1; level < 7; level++) { 676 if (!CLIDR_CTYPE(clidr, level)) 677 break; 678 } 679 680 /* 681 * If you have a mind-boggling 7 levels of cache, congratulations, you 682 * get to fix this. 683 */ 684 TEST_ASSERT(level <= 7, "can't find an empty level in cache hierarchy"); 685 686 /* stick in a unified cache level */ 687 clidr |= BIT(2) << CLIDR_CTYPE_SHIFT(level); 688 689 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1), clidr); 690 test_reg_vals[encoding_to_range_idx(SYS_CLIDR_EL1)] = clidr; 691 } 692 693 static void test_ctr(struct kvm_vcpu *vcpu) 694 { 695 u64 ctr; 696 697 ctr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0)); 698 ctr &= ~CTR_EL0_DIC_MASK; 699 if (ctr & CTR_EL0_IminLine_MASK) 700 ctr--; 701 702 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0), ctr); 703 test_reg_vals[encoding_to_range_idx(SYS_CTR_EL0)] = ctr; 704 } 705 706 static void test_id_reg(struct kvm_vcpu *vcpu, u32 id) 707 { 708 u64 val; 709 710 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(id)); 711 val++; 712 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(id), val); 713 test_reg_vals[encoding_to_range_idx(id)] = val; 714 } 715 716 static void test_vcpu_ftr_id_regs(struct kvm_vcpu *vcpu) 717 { 718 test_clidr(vcpu); 719 test_ctr(vcpu); 720 721 test_id_reg(vcpu, SYS_MPIDR_EL1); 722 ksft_test_result_pass("%s\n", __func__); 723 } 724 725 static void test_vcpu_non_ftr_id_regs(struct kvm_vcpu *vcpu) 726 { 727 test_id_reg(vcpu, SYS_MIDR_EL1); 728 test_id_reg(vcpu, SYS_REVIDR_EL1); 729 test_id_reg(vcpu, SYS_AIDR_EL1); 730 731 ksft_test_result_pass("%s\n", __func__); 732 } 733 734 static void test_assert_id_reg_unchanged(struct kvm_vcpu *vcpu, uint32_t encoding) 735 { 736 size_t idx = encoding_to_range_idx(encoding); 737 uint64_t observed; 738 739 observed = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding)); 740 TEST_ASSERT_EQ(test_reg_vals[idx], observed); 741 } 742 743 static void test_reset_preserves_id_regs(struct kvm_vcpu *vcpu) 744 { 745 /* 746 * Calls KVM_ARM_VCPU_INIT behind the scenes, which will do an 747 * architectural reset of the vCPU. 748 */ 749 aarch64_vcpu_setup(vcpu, NULL); 750 751 for (int i = 0; i < ARRAY_SIZE(test_regs); i++) 752 test_assert_id_reg_unchanged(vcpu, test_regs[i].reg); 753 754 test_assert_id_reg_unchanged(vcpu, SYS_MPIDR_EL1); 755 test_assert_id_reg_unchanged(vcpu, SYS_CLIDR_EL1); 756 test_assert_id_reg_unchanged(vcpu, SYS_CTR_EL0); 757 test_assert_id_reg_unchanged(vcpu, SYS_MIDR_EL1); 758 test_assert_id_reg_unchanged(vcpu, SYS_REVIDR_EL1); 759 test_assert_id_reg_unchanged(vcpu, SYS_AIDR_EL1); 760 761 ksft_test_result_pass("%s\n", __func__); 762 } 763 764 int main(void) 765 { 766 struct kvm_vcpu *vcpu; 767 struct kvm_vm *vm; 768 bool aarch64_only; 769 uint64_t val, el0; 770 int test_cnt, i, j; 771 772 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES)); 773 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_WRITABLE_IMP_ID_REGS)); 774 775 test_wants_mte(); 776 777 vm = vm_create(1); 778 vm_enable_cap(vm, KVM_CAP_ARM_WRITABLE_IMP_ID_REGS, 0); 779 vcpu = vm_vcpu_add(vm, 0, guest_code); 780 kvm_arch_vm_finalize_vcpus(vm); 781 782 /* Check for AARCH64 only system */ 783 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1)); 784 el0 = FIELD_GET(ID_AA64PFR0_EL1_EL0, val); 785 aarch64_only = (el0 == ID_AA64PFR0_EL1_EL0_IMP); 786 787 ksft_print_header(); 788 789 test_cnt = 3 + MPAM_IDREG_TEST + MTE_IDREG_TEST; 790 for (i = 0; i < ARRAY_SIZE(test_regs); i++) 791 for (j = 0; test_regs[i].ftr_bits[j].type != FTR_END; j++) 792 test_cnt++; 793 794 ksft_set_plan(test_cnt); 795 796 test_vm_ftr_id_regs(vcpu, aarch64_only); 797 test_vcpu_ftr_id_regs(vcpu); 798 test_vcpu_non_ftr_id_regs(vcpu); 799 test_user_set_mpam_reg(vcpu); 800 test_user_set_mte_reg(vcpu); 801 802 test_guest_reg_read(vcpu); 803 804 test_reset_preserves_id_regs(vcpu); 805 806 kvm_vm_free(vm); 807 808 ksft_finished(); 809 } 810