1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * set_id_regs - Test for setting ID register from usersapce. 4 * 5 * Copyright (c) 2023 Google LLC. 6 * 7 * 8 * Test that KVM supports setting ID registers from userspace and handles the 9 * feature set correctly. 10 */ 11 12 #include <stdint.h> 13 #include "kvm_util.h" 14 #include "processor.h" 15 #include "test_util.h" 16 #include <linux/bitfield.h> 17 18 enum ftr_type { 19 FTR_EXACT, /* Use a predefined safe value */ 20 FTR_LOWER_SAFE, /* Smaller value is safe */ 21 FTR_HIGHER_SAFE, /* Bigger value is safe */ 22 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */ 23 FTR_END, /* Mark the last ftr bits */ 24 }; 25 26 #define FTR_SIGNED true /* Value should be treated as signed */ 27 #define FTR_UNSIGNED false /* Value should be treated as unsigned */ 28 29 struct reg_ftr_bits { 30 char *name; 31 bool sign; 32 enum ftr_type type; 33 uint8_t shift; 34 uint64_t mask; 35 /* 36 * For FTR_EXACT, safe_val is used as the exact safe value. 37 * For FTR_LOWER_SAFE, safe_val is used as the minimal safe value. 38 */ 39 int64_t safe_val; 40 }; 41 42 struct test_feature_reg { 43 uint32_t reg; 44 const struct reg_ftr_bits *ftr_bits; 45 }; 46 47 #define __REG_FTR_BITS(NAME, SIGNED, TYPE, SHIFT, MASK, SAFE_VAL) \ 48 { \ 49 .name = #NAME, \ 50 .sign = SIGNED, \ 51 .type = TYPE, \ 52 .shift = SHIFT, \ 53 .mask = MASK, \ 54 .safe_val = SAFE_VAL, \ 55 } 56 57 #define REG_FTR_BITS(type, reg, field, safe_val) \ 58 __REG_FTR_BITS(reg##_##field, FTR_UNSIGNED, type, reg##_##field##_SHIFT, \ 59 reg##_##field##_MASK, safe_val) 60 61 #define S_REG_FTR_BITS(type, reg, field, safe_val) \ 62 __REG_FTR_BITS(reg##_##field, FTR_SIGNED, type, reg##_##field##_SHIFT, \ 63 reg##_##field##_MASK, safe_val) 64 65 #define REG_FTR_END \ 66 { \ 67 .type = FTR_END, \ 68 } 69 70 static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = { 71 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DoubleLock, 0), 72 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, WRPs, 0), 73 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0), 74 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, ID_AA64DFR0_EL1_DebugVer_IMP), 75 REG_FTR_END, 76 }; 77 78 static const struct reg_ftr_bits ftr_id_dfr0_el1[] = { 79 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, PerfMon, ID_DFR0_EL1_PerfMon_PMUv3), 80 REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, CopDbg, ID_DFR0_EL1_CopDbg_Armv8), 81 REG_FTR_END, 82 }; 83 84 static const struct reg_ftr_bits ftr_id_aa64isar0_el1[] = { 85 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RNDR, 0), 86 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TLB, 0), 87 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TS, 0), 88 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, FHM, 0), 89 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, DP, 0), 90 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM4, 0), 91 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM3, 0), 92 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA3, 0), 93 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RDM, 0), 94 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TME, 0), 95 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, ATOMIC, 0), 96 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, CRC32, 0), 97 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA2, 0), 98 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA1, 0), 99 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, AES, 0), 100 REG_FTR_END, 101 }; 102 103 static const struct reg_ftr_bits ftr_id_aa64isar1_el1[] = { 104 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LS64, 0), 105 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, XS, 0), 106 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, I8MM, 0), 107 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DGH, 0), 108 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, BF16, 0), 109 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SPECRES, 0), 110 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SB, 0), 111 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FRINTTS, 0), 112 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LRCPC, 0), 113 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FCMA, 0), 114 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, JSCVT, 0), 115 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DPB, 0), 116 REG_FTR_END, 117 }; 118 119 static const struct reg_ftr_bits ftr_id_aa64isar2_el1[] = { 120 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, BC, 0), 121 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, RPRES, 0), 122 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, WFxT, 0), 123 REG_FTR_END, 124 }; 125 126 static const struct reg_ftr_bits ftr_id_aa64isar3_el1[] = { 127 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR3_EL1, FPRCVT, 0), 128 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR3_EL1, LSFE, 0), 129 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR3_EL1, FAMINMAX, 0), 130 REG_FTR_END, 131 }; 132 133 static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = { 134 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV3, 0), 135 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV2, 0), 136 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, DIT, 0), 137 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, SEL2, 0), 138 REG_FTR_BITS(FTR_EXACT, ID_AA64PFR0_EL1, GIC, 0), 139 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL3, 1), 140 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL2, 1), 141 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL1, 1), 142 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL0, 1), 143 REG_FTR_END, 144 }; 145 146 static const struct reg_ftr_bits ftr_id_aa64pfr1_el1[] = { 147 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, DF2, 0), 148 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, CSV2_frac, 0), 149 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, SSBS, ID_AA64PFR1_EL1_SSBS_NI), 150 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, BT, 0), 151 REG_FTR_END, 152 }; 153 154 static const struct reg_ftr_bits ftr_id_aa64mmfr0_el1[] = { 155 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ECV, 0), 156 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, EXS, 0), 157 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN4_2, 1), 158 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN64_2, 1), 159 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN16_2, 1), 160 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN4, 0), 161 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN64, 0), 162 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN16, 0), 163 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGENDEL0, 0), 164 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, SNSMEM, 0), 165 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGEND, 0), 166 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, PARANGE, 0), 167 REG_FTR_END, 168 }; 169 170 static const struct reg_ftr_bits ftr_id_aa64mmfr1_el1[] = { 171 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, TIDCP1, 0), 172 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, AFP, 0), 173 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HCX, 0), 174 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, ETS, 0), 175 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, TWED, 0), 176 REG_FTR_BITS(FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1, SpecSEI, 0), 177 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, PAN, 0), 178 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, LO, 0), 179 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HPDS, 0), 180 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HAFDBS, 0), 181 REG_FTR_END, 182 }; 183 184 static const struct reg_ftr_bits ftr_id_aa64mmfr2_el1[] = { 185 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, E0PD, 0), 186 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, BBM, 0), 187 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, TTL, 0), 188 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, AT, 0), 189 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, ST, 0), 190 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, VARange, 0), 191 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, IESB, 0), 192 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, LSM, 0), 193 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, UAO, 0), 194 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, CnP, 0), 195 REG_FTR_END, 196 }; 197 198 static const struct reg_ftr_bits ftr_id_aa64mmfr3_el1[] = { 199 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, S1POE, 0), 200 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, S1PIE, 0), 201 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, SCTLRX, 0), 202 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, TCRX, 0), 203 REG_FTR_END, 204 }; 205 206 static const struct reg_ftr_bits ftr_id_aa64zfr0_el1[] = { 207 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F64MM, 0), 208 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F32MM, 0), 209 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, I8MM, 0), 210 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SM4, 0), 211 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SHA3, 0), 212 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BF16, 0), 213 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BitPerm, 0), 214 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, AES, 0), 215 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SVEver, 0), 216 REG_FTR_END, 217 }; 218 219 #define TEST_REG(id, table) \ 220 { \ 221 .reg = id, \ 222 .ftr_bits = &((table)[0]), \ 223 } 224 225 static struct test_feature_reg test_regs[] = { 226 TEST_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0_el1), 227 TEST_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0_el1), 228 TEST_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0_el1), 229 TEST_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1_el1), 230 TEST_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2_el1), 231 TEST_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3_el1), 232 TEST_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0_el1), 233 TEST_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1_el1), 234 TEST_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0_el1), 235 TEST_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1), 236 TEST_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1), 237 TEST_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3_el1), 238 TEST_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0_el1), 239 }; 240 241 #define GUEST_REG_SYNC(id) GUEST_SYNC_ARGS(0, id, read_sysreg_s(id), 0, 0); 242 243 static void guest_code(void) 244 { 245 GUEST_REG_SYNC(SYS_ID_AA64DFR0_EL1); 246 GUEST_REG_SYNC(SYS_ID_DFR0_EL1); 247 GUEST_REG_SYNC(SYS_ID_AA64ISAR0_EL1); 248 GUEST_REG_SYNC(SYS_ID_AA64ISAR1_EL1); 249 GUEST_REG_SYNC(SYS_ID_AA64ISAR2_EL1); 250 GUEST_REG_SYNC(SYS_ID_AA64ISAR3_EL1); 251 GUEST_REG_SYNC(SYS_ID_AA64PFR0_EL1); 252 GUEST_REG_SYNC(SYS_ID_AA64MMFR0_EL1); 253 GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1); 254 GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1); 255 GUEST_REG_SYNC(SYS_ID_AA64MMFR3_EL1); 256 GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1); 257 GUEST_REG_SYNC(SYS_CTR_EL0); 258 GUEST_REG_SYNC(SYS_MIDR_EL1); 259 GUEST_REG_SYNC(SYS_REVIDR_EL1); 260 GUEST_REG_SYNC(SYS_AIDR_EL1); 261 262 GUEST_DONE(); 263 } 264 265 /* Return a safe value to a given ftr_bits an ftr value */ 266 uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr) 267 { 268 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0); 269 270 if (ftr_bits->sign == FTR_UNSIGNED) { 271 switch (ftr_bits->type) { 272 case FTR_EXACT: 273 ftr = ftr_bits->safe_val; 274 break; 275 case FTR_LOWER_SAFE: 276 if (ftr > ftr_bits->safe_val) 277 ftr--; 278 break; 279 case FTR_HIGHER_SAFE: 280 if (ftr < ftr_max) 281 ftr++; 282 break; 283 case FTR_HIGHER_OR_ZERO_SAFE: 284 if (ftr == ftr_max) 285 ftr = 0; 286 else if (ftr != 0) 287 ftr++; 288 break; 289 default: 290 break; 291 } 292 } else if (ftr != ftr_max) { 293 switch (ftr_bits->type) { 294 case FTR_EXACT: 295 ftr = ftr_bits->safe_val; 296 break; 297 case FTR_LOWER_SAFE: 298 if (ftr > ftr_bits->safe_val) 299 ftr--; 300 break; 301 case FTR_HIGHER_SAFE: 302 if (ftr < ftr_max - 1) 303 ftr++; 304 break; 305 case FTR_HIGHER_OR_ZERO_SAFE: 306 if (ftr != 0 && ftr != ftr_max - 1) 307 ftr++; 308 break; 309 default: 310 break; 311 } 312 } 313 314 return ftr; 315 } 316 317 /* Return an invalid value to a given ftr_bits an ftr value */ 318 uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr) 319 { 320 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0); 321 322 if (ftr_bits->sign == FTR_UNSIGNED) { 323 switch (ftr_bits->type) { 324 case FTR_EXACT: 325 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1); 326 break; 327 case FTR_LOWER_SAFE: 328 ftr++; 329 break; 330 case FTR_HIGHER_SAFE: 331 ftr--; 332 break; 333 case FTR_HIGHER_OR_ZERO_SAFE: 334 if (ftr == 0) 335 ftr = ftr_max; 336 else 337 ftr--; 338 break; 339 default: 340 break; 341 } 342 } else if (ftr != ftr_max) { 343 switch (ftr_bits->type) { 344 case FTR_EXACT: 345 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1); 346 break; 347 case FTR_LOWER_SAFE: 348 ftr++; 349 break; 350 case FTR_HIGHER_SAFE: 351 ftr--; 352 break; 353 case FTR_HIGHER_OR_ZERO_SAFE: 354 if (ftr == 0) 355 ftr = ftr_max - 1; 356 else 357 ftr--; 358 break; 359 default: 360 break; 361 } 362 } else { 363 ftr = 0; 364 } 365 366 return ftr; 367 } 368 369 static uint64_t test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg, 370 const struct reg_ftr_bits *ftr_bits) 371 { 372 uint8_t shift = ftr_bits->shift; 373 uint64_t mask = ftr_bits->mask; 374 uint64_t val, new_val, ftr; 375 376 val = vcpu_get_reg(vcpu, reg); 377 ftr = (val & mask) >> shift; 378 379 ftr = get_safe_value(ftr_bits, ftr); 380 381 ftr <<= shift; 382 val &= ~mask; 383 val |= ftr; 384 385 vcpu_set_reg(vcpu, reg, val); 386 new_val = vcpu_get_reg(vcpu, reg); 387 TEST_ASSERT_EQ(new_val, val); 388 389 return new_val; 390 } 391 392 static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg, 393 const struct reg_ftr_bits *ftr_bits) 394 { 395 uint8_t shift = ftr_bits->shift; 396 uint64_t mask = ftr_bits->mask; 397 uint64_t val, old_val, ftr; 398 int r; 399 400 val = vcpu_get_reg(vcpu, reg); 401 ftr = (val & mask) >> shift; 402 403 ftr = get_invalid_value(ftr_bits, ftr); 404 405 old_val = val; 406 ftr <<= shift; 407 val &= ~mask; 408 val |= ftr; 409 410 r = __vcpu_set_reg(vcpu, reg, val); 411 TEST_ASSERT(r < 0 && errno == EINVAL, 412 "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno); 413 414 val = vcpu_get_reg(vcpu, reg); 415 TEST_ASSERT_EQ(val, old_val); 416 } 417 418 static uint64_t test_reg_vals[KVM_ARM_FEATURE_ID_RANGE_SIZE]; 419 420 #define encoding_to_range_idx(encoding) \ 421 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(encoding), sys_reg_Op1(encoding), \ 422 sys_reg_CRn(encoding), sys_reg_CRm(encoding), \ 423 sys_reg_Op2(encoding)) 424 425 426 static void test_vm_ftr_id_regs(struct kvm_vcpu *vcpu, bool aarch64_only) 427 { 428 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE]; 429 struct reg_mask_range range = { 430 .addr = (__u64)masks, 431 }; 432 int ret; 433 434 /* KVM should return error when reserved field is not zero */ 435 range.reserved[0] = 1; 436 ret = __vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range); 437 TEST_ASSERT(ret, "KVM doesn't check invalid parameters."); 438 439 /* Get writable masks for feature ID registers */ 440 memset(range.reserved, 0, sizeof(range.reserved)); 441 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range); 442 443 for (int i = 0; i < ARRAY_SIZE(test_regs); i++) { 444 const struct reg_ftr_bits *ftr_bits = test_regs[i].ftr_bits; 445 uint32_t reg_id = test_regs[i].reg; 446 uint64_t reg = KVM_ARM64_SYS_REG(reg_id); 447 int idx; 448 449 /* Get the index to masks array for the idreg */ 450 idx = encoding_to_range_idx(reg_id); 451 452 for (int j = 0; ftr_bits[j].type != FTR_END; j++) { 453 /* Skip aarch32 reg on aarch64 only system, since they are RAZ/WI. */ 454 if (aarch64_only && sys_reg_CRm(reg_id) < 4) { 455 ksft_test_result_skip("%s on AARCH64 only system\n", 456 ftr_bits[j].name); 457 continue; 458 } 459 460 /* Make sure the feature field is writable */ 461 TEST_ASSERT_EQ(masks[idx] & ftr_bits[j].mask, ftr_bits[j].mask); 462 463 test_reg_set_fail(vcpu, reg, &ftr_bits[j]); 464 465 test_reg_vals[idx] = test_reg_set_success(vcpu, reg, 466 &ftr_bits[j]); 467 468 ksft_test_result_pass("%s\n", ftr_bits[j].name); 469 } 470 } 471 } 472 473 #define MPAM_IDREG_TEST 6 474 static void test_user_set_mpam_reg(struct kvm_vcpu *vcpu) 475 { 476 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE]; 477 struct reg_mask_range range = { 478 .addr = (__u64)masks, 479 }; 480 uint64_t val; 481 int idx, err; 482 483 /* 484 * If ID_AA64PFR0.MPAM is _not_ officially modifiable and is zero, 485 * check that if it can be set to 1, (i.e. it is supported by the 486 * hardware), that it can't be set to other values. 487 */ 488 489 /* Get writable masks for feature ID registers */ 490 memset(range.reserved, 0, sizeof(range.reserved)); 491 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range); 492 493 /* Writeable? Nothing to test! */ 494 idx = encoding_to_range_idx(SYS_ID_AA64PFR0_EL1); 495 if ((masks[idx] & ID_AA64PFR0_EL1_MPAM_MASK) == ID_AA64PFR0_EL1_MPAM_MASK) { 496 ksft_test_result_skip("ID_AA64PFR0_EL1.MPAM is officially writable, nothing to test\n"); 497 return; 498 } 499 500 /* Get the id register value */ 501 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1)); 502 503 /* Try to set MPAM=0. This should always be possible. */ 504 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 505 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 0); 506 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val); 507 if (err) 508 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM=0 was not accepted\n"); 509 else 510 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM=0 worked\n"); 511 512 /* Try to set MPAM=1 */ 513 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 514 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 1); 515 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val); 516 if (err) 517 ksft_test_result_skip("ID_AA64PFR0_EL1.MPAM is not writable, nothing to test\n"); 518 else 519 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM=1 was writable\n"); 520 521 /* Try to set MPAM=2 */ 522 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 523 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 2); 524 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val); 525 if (err) 526 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM not arbitrarily modifiable\n"); 527 else 528 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM value should not be ignored\n"); 529 530 /* And again for ID_AA64PFR1_EL1.MPAM_frac */ 531 idx = encoding_to_range_idx(SYS_ID_AA64PFR1_EL1); 532 if ((masks[idx] & ID_AA64PFR1_EL1_MPAM_frac_MASK) == ID_AA64PFR1_EL1_MPAM_frac_MASK) { 533 ksft_test_result_skip("ID_AA64PFR1_EL1.MPAM_frac is officially writable, nothing to test\n"); 534 return; 535 } 536 537 /* Get the id register value */ 538 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1)); 539 540 /* Try to set MPAM_frac=0. This should always be possible. */ 541 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 542 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 0); 543 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val); 544 if (err) 545 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM_frac=0 was not accepted\n"); 546 else 547 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM_frac=0 worked\n"); 548 549 /* Try to set MPAM_frac=1 */ 550 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 551 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 1); 552 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val); 553 if (err) 554 ksft_test_result_skip("ID_AA64PFR1_EL1.MPAM_frac is not writable, nothing to test\n"); 555 else 556 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM_frac=1 was writable\n"); 557 558 /* Try to set MPAM_frac=2 */ 559 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 560 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 2); 561 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val); 562 if (err) 563 ksft_test_result_pass("ID_AA64PFR1_EL1.MPAM_frac not arbitrarily modifiable\n"); 564 else 565 ksft_test_result_fail("ID_AA64PFR1_EL1.MPAM_frac value should not be ignored\n"); 566 } 567 568 #define MTE_IDREG_TEST 1 569 static void test_user_set_mte_reg(struct kvm_vcpu *vcpu) 570 { 571 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE]; 572 struct reg_mask_range range = { 573 .addr = (__u64)masks, 574 }; 575 uint64_t val; 576 uint64_t mte; 577 uint64_t mte_frac; 578 int idx, err; 579 580 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1)); 581 mte = FIELD_GET(ID_AA64PFR1_EL1_MTE, val); 582 if (!mte) { 583 ksft_test_result_skip("MTE capability not supported, nothing to test\n"); 584 return; 585 } 586 587 /* Get writable masks for feature ID registers */ 588 memset(range.reserved, 0, sizeof(range.reserved)); 589 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range); 590 591 idx = encoding_to_range_idx(SYS_ID_AA64PFR1_EL1); 592 if ((masks[idx] & ID_AA64PFR1_EL1_MTE_frac_MASK) == ID_AA64PFR1_EL1_MTE_frac_MASK) { 593 ksft_test_result_skip("ID_AA64PFR1_EL1.MTE_frac is officially writable, nothing to test\n"); 594 return; 595 } 596 597 /* 598 * When MTE is supported but MTE_ASYMM is not (ID_AA64PFR1_EL1.MTE == 2) 599 * ID_AA64PFR1_EL1.MTE_frac == 0xF indicates MTE_ASYNC is unsupported 600 * and MTE_frac == 0 indicates it is supported. 601 * 602 * As MTE_frac was previously unconditionally read as 0, check 603 * that the set to 0 succeeds but does not change MTE_frac 604 * from unsupported (0xF) to supported (0). 605 * 606 */ 607 mte_frac = FIELD_GET(ID_AA64PFR1_EL1_MTE_frac, val); 608 if (mte != ID_AA64PFR1_EL1_MTE_MTE2 || 609 mte_frac != ID_AA64PFR1_EL1_MTE_frac_NI) { 610 ksft_test_result_skip("MTE_ASYNC or MTE_ASYMM are supported, nothing to test\n"); 611 return; 612 } 613 614 /* Try to set MTE_frac=0. */ 615 val &= ~ID_AA64PFR1_EL1_MTE_frac_MASK; 616 val |= FIELD_PREP(ID_AA64PFR1_EL1_MTE_frac_MASK, 0); 617 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val); 618 if (err) { 619 ksft_test_result_fail("ID_AA64PFR1_EL1.MTE_frac=0 was not accepted\n"); 620 return; 621 } 622 623 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1)); 624 mte_frac = FIELD_GET(ID_AA64PFR1_EL1_MTE_frac, val); 625 if (mte_frac == ID_AA64PFR1_EL1_MTE_frac_NI) 626 ksft_test_result_pass("ID_AA64PFR1_EL1.MTE_frac=0 accepted and still 0xF\n"); 627 else 628 ksft_test_result_pass("ID_AA64PFR1_EL1.MTE_frac no longer 0xF\n"); 629 } 630 631 static void test_guest_reg_read(struct kvm_vcpu *vcpu) 632 { 633 bool done = false; 634 struct ucall uc; 635 636 while (!done) { 637 vcpu_run(vcpu); 638 639 switch (get_ucall(vcpu, &uc)) { 640 case UCALL_ABORT: 641 REPORT_GUEST_ASSERT(uc); 642 break; 643 case UCALL_SYNC: 644 /* Make sure the written values are seen by guest */ 645 TEST_ASSERT_EQ(test_reg_vals[encoding_to_range_idx(uc.args[2])], 646 uc.args[3]); 647 break; 648 case UCALL_DONE: 649 done = true; 650 break; 651 default: 652 TEST_FAIL("Unexpected ucall: %lu", uc.cmd); 653 } 654 } 655 } 656 657 /* Politely lifted from arch/arm64/include/asm/cache.h */ 658 /* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */ 659 #define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) 660 #define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) 661 #define CLIDR_CTYPE(clidr, level) \ 662 (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) 663 664 static void test_clidr(struct kvm_vcpu *vcpu) 665 { 666 uint64_t clidr; 667 int level; 668 669 clidr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1)); 670 671 /* find the first empty level in the cache hierarchy */ 672 for (level = 1; level < 7; level++) { 673 if (!CLIDR_CTYPE(clidr, level)) 674 break; 675 } 676 677 /* 678 * If you have a mind-boggling 7 levels of cache, congratulations, you 679 * get to fix this. 680 */ 681 TEST_ASSERT(level <= 7, "can't find an empty level in cache hierarchy"); 682 683 /* stick in a unified cache level */ 684 clidr |= BIT(2) << CLIDR_CTYPE_SHIFT(level); 685 686 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1), clidr); 687 test_reg_vals[encoding_to_range_idx(SYS_CLIDR_EL1)] = clidr; 688 } 689 690 static void test_ctr(struct kvm_vcpu *vcpu) 691 { 692 u64 ctr; 693 694 ctr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0)); 695 ctr &= ~CTR_EL0_DIC_MASK; 696 if (ctr & CTR_EL0_IminLine_MASK) 697 ctr--; 698 699 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0), ctr); 700 test_reg_vals[encoding_to_range_idx(SYS_CTR_EL0)] = ctr; 701 } 702 703 static void test_id_reg(struct kvm_vcpu *vcpu, u32 id) 704 { 705 u64 val; 706 707 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(id)); 708 val++; 709 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(id), val); 710 test_reg_vals[encoding_to_range_idx(id)] = val; 711 } 712 713 static void test_vcpu_ftr_id_regs(struct kvm_vcpu *vcpu) 714 { 715 test_clidr(vcpu); 716 test_ctr(vcpu); 717 718 test_id_reg(vcpu, SYS_MPIDR_EL1); 719 ksft_test_result_pass("%s\n", __func__); 720 } 721 722 static void test_vcpu_non_ftr_id_regs(struct kvm_vcpu *vcpu) 723 { 724 test_id_reg(vcpu, SYS_MIDR_EL1); 725 test_id_reg(vcpu, SYS_REVIDR_EL1); 726 test_id_reg(vcpu, SYS_AIDR_EL1); 727 728 ksft_test_result_pass("%s\n", __func__); 729 } 730 731 static void test_assert_id_reg_unchanged(struct kvm_vcpu *vcpu, uint32_t encoding) 732 { 733 size_t idx = encoding_to_range_idx(encoding); 734 uint64_t observed; 735 736 observed = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding)); 737 TEST_ASSERT_EQ(test_reg_vals[idx], observed); 738 } 739 740 static void test_reset_preserves_id_regs(struct kvm_vcpu *vcpu) 741 { 742 /* 743 * Calls KVM_ARM_VCPU_INIT behind the scenes, which will do an 744 * architectural reset of the vCPU. 745 */ 746 aarch64_vcpu_setup(vcpu, NULL); 747 748 for (int i = 0; i < ARRAY_SIZE(test_regs); i++) 749 test_assert_id_reg_unchanged(vcpu, test_regs[i].reg); 750 751 test_assert_id_reg_unchanged(vcpu, SYS_MPIDR_EL1); 752 test_assert_id_reg_unchanged(vcpu, SYS_CLIDR_EL1); 753 test_assert_id_reg_unchanged(vcpu, SYS_CTR_EL0); 754 test_assert_id_reg_unchanged(vcpu, SYS_MIDR_EL1); 755 test_assert_id_reg_unchanged(vcpu, SYS_REVIDR_EL1); 756 test_assert_id_reg_unchanged(vcpu, SYS_AIDR_EL1); 757 758 ksft_test_result_pass("%s\n", __func__); 759 } 760 761 int main(void) 762 { 763 struct kvm_vcpu *vcpu; 764 struct kvm_vm *vm; 765 bool aarch64_only; 766 uint64_t val, el0; 767 int test_cnt, i, j; 768 769 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES)); 770 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_WRITABLE_IMP_ID_REGS)); 771 772 test_wants_mte(); 773 774 vm = vm_create(1); 775 vm_enable_cap(vm, KVM_CAP_ARM_WRITABLE_IMP_ID_REGS, 0); 776 vcpu = vm_vcpu_add(vm, 0, guest_code); 777 kvm_arch_vm_finalize_vcpus(vm); 778 779 /* Check for AARCH64 only system */ 780 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1)); 781 el0 = FIELD_GET(ID_AA64PFR0_EL1_EL0, val); 782 aarch64_only = (el0 == ID_AA64PFR0_EL1_EL0_IMP); 783 784 ksft_print_header(); 785 786 test_cnt = 3 + MPAM_IDREG_TEST + MTE_IDREG_TEST; 787 for (i = 0; i < ARRAY_SIZE(test_regs); i++) 788 for (j = 0; test_regs[i].ftr_bits[j].type != FTR_END; j++) 789 test_cnt++; 790 791 ksft_set_plan(test_cnt); 792 793 test_vm_ftr_id_regs(vcpu, aarch64_only); 794 test_vcpu_ftr_id_regs(vcpu); 795 test_vcpu_non_ftr_id_regs(vcpu); 796 test_user_set_mpam_reg(vcpu); 797 test_user_set_mte_reg(vcpu); 798 799 test_guest_reg_read(vcpu); 800 801 test_reset_preserves_id_regs(vcpu); 802 803 kvm_vm_free(vm); 804 805 ksft_finished(); 806 } 807