1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * set_id_regs - Test for setting ID register from usersapce. 4 * 5 * Copyright (c) 2023 Google LLC. 6 * 7 * 8 * Test that KVM supports setting ID registers from userspace and handles the 9 * feature set correctly. 10 */ 11 12 #include <stdint.h> 13 #include "kvm_util.h" 14 #include "processor.h" 15 #include "test_util.h" 16 #include <linux/bitfield.h> 17 18 enum ftr_type { 19 FTR_EXACT, /* Use a predefined safe value */ 20 FTR_LOWER_SAFE, /* Smaller value is safe */ 21 FTR_HIGHER_SAFE, /* Bigger value is safe */ 22 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */ 23 FTR_END, /* Mark the last ftr bits */ 24 }; 25 26 #define FTR_SIGNED true /* Value should be treated as signed */ 27 #define FTR_UNSIGNED false /* Value should be treated as unsigned */ 28 29 struct reg_ftr_bits { 30 char *name; 31 bool sign; 32 enum ftr_type type; 33 uint8_t shift; 34 uint64_t mask; 35 /* 36 * For FTR_EXACT, safe_val is used as the exact safe value. 37 * For FTR_LOWER_SAFE, safe_val is used as the minimal safe value. 38 */ 39 int64_t safe_val; 40 }; 41 42 struct test_feature_reg { 43 uint32_t reg; 44 const struct reg_ftr_bits *ftr_bits; 45 }; 46 47 #define __REG_FTR_BITS(NAME, SIGNED, TYPE, SHIFT, MASK, SAFE_VAL) \ 48 { \ 49 .name = #NAME, \ 50 .sign = SIGNED, \ 51 .type = TYPE, \ 52 .shift = SHIFT, \ 53 .mask = MASK, \ 54 .safe_val = SAFE_VAL, \ 55 } 56 57 #define REG_FTR_BITS(type, reg, field, safe_val) \ 58 __REG_FTR_BITS(reg##_##field, FTR_UNSIGNED, type, reg##_##field##_SHIFT, \ 59 reg##_##field##_MASK, safe_val) 60 61 #define S_REG_FTR_BITS(type, reg, field, safe_val) \ 62 __REG_FTR_BITS(reg##_##field, FTR_SIGNED, type, reg##_##field##_SHIFT, \ 63 reg##_##field##_MASK, safe_val) 64 65 #define REG_FTR_END \ 66 { \ 67 .type = FTR_END, \ 68 } 69 70 static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = { 71 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0), 72 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, ID_AA64DFR0_EL1_DebugVer_IMP), 73 REG_FTR_END, 74 }; 75 76 static const struct reg_ftr_bits ftr_id_dfr0_el1[] = { 77 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, PerfMon, ID_DFR0_EL1_PerfMon_PMUv3), 78 REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, CopDbg, ID_DFR0_EL1_CopDbg_Armv8), 79 REG_FTR_END, 80 }; 81 82 static const struct reg_ftr_bits ftr_id_aa64isar0_el1[] = { 83 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RNDR, 0), 84 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TLB, 0), 85 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TS, 0), 86 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, FHM, 0), 87 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, DP, 0), 88 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM4, 0), 89 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM3, 0), 90 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA3, 0), 91 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RDM, 0), 92 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TME, 0), 93 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, ATOMIC, 0), 94 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, CRC32, 0), 95 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA2, 0), 96 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA1, 0), 97 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, AES, 0), 98 REG_FTR_END, 99 }; 100 101 static const struct reg_ftr_bits ftr_id_aa64isar1_el1[] = { 102 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LS64, 0), 103 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, XS, 0), 104 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, I8MM, 0), 105 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DGH, 0), 106 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, BF16, 0), 107 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SPECRES, 0), 108 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SB, 0), 109 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FRINTTS, 0), 110 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LRCPC, 0), 111 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FCMA, 0), 112 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, JSCVT, 0), 113 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DPB, 0), 114 REG_FTR_END, 115 }; 116 117 static const struct reg_ftr_bits ftr_id_aa64isar2_el1[] = { 118 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, BC, 0), 119 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, RPRES, 0), 120 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, WFxT, 0), 121 REG_FTR_END, 122 }; 123 124 static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = { 125 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV3, 0), 126 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV2, 0), 127 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, DIT, 0), 128 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, SEL2, 0), 129 REG_FTR_BITS(FTR_EXACT, ID_AA64PFR0_EL1, GIC, 0), 130 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL3, 0), 131 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL2, 0), 132 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL1, 0), 133 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL0, 0), 134 REG_FTR_END, 135 }; 136 137 static const struct reg_ftr_bits ftr_id_aa64mmfr0_el1[] = { 138 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ECV, 0), 139 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, EXS, 0), 140 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN4, 0), 141 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN64, 0), 142 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN16, 0), 143 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGENDEL0, 0), 144 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, SNSMEM, 0), 145 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGEND, 0), 146 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ASIDBITS, 0), 147 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, PARANGE, 0), 148 REG_FTR_END, 149 }; 150 151 static const struct reg_ftr_bits ftr_id_aa64mmfr1_el1[] = { 152 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, TIDCP1, 0), 153 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, AFP, 0), 154 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, ETS, 0), 155 REG_FTR_BITS(FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1, SpecSEI, 0), 156 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, PAN, 0), 157 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, LO, 0), 158 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HPDS, 0), 159 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HAFDBS, 0), 160 REG_FTR_END, 161 }; 162 163 static const struct reg_ftr_bits ftr_id_aa64mmfr2_el1[] = { 164 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, E0PD, 0), 165 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, BBM, 0), 166 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, TTL, 0), 167 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, AT, 0), 168 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, ST, 0), 169 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, VARange, 0), 170 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, IESB, 0), 171 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, LSM, 0), 172 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, UAO, 0), 173 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, CnP, 0), 174 REG_FTR_END, 175 }; 176 177 static const struct reg_ftr_bits ftr_id_aa64zfr0_el1[] = { 178 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F64MM, 0), 179 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F32MM, 0), 180 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, I8MM, 0), 181 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SM4, 0), 182 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SHA3, 0), 183 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BF16, 0), 184 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BitPerm, 0), 185 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, AES, 0), 186 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SVEver, 0), 187 REG_FTR_END, 188 }; 189 190 #define TEST_REG(id, table) \ 191 { \ 192 .reg = id, \ 193 .ftr_bits = &((table)[0]), \ 194 } 195 196 static struct test_feature_reg test_regs[] = { 197 TEST_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0_el1), 198 TEST_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0_el1), 199 TEST_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0_el1), 200 TEST_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1_el1), 201 TEST_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2_el1), 202 TEST_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0_el1), 203 TEST_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0_el1), 204 TEST_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1), 205 TEST_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1), 206 TEST_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0_el1), 207 }; 208 209 #define GUEST_REG_SYNC(id) GUEST_SYNC_ARGS(0, id, read_sysreg_s(id), 0, 0); 210 211 static void guest_code(void) 212 { 213 GUEST_REG_SYNC(SYS_ID_AA64DFR0_EL1); 214 GUEST_REG_SYNC(SYS_ID_DFR0_EL1); 215 GUEST_REG_SYNC(SYS_ID_AA64ISAR0_EL1); 216 GUEST_REG_SYNC(SYS_ID_AA64ISAR1_EL1); 217 GUEST_REG_SYNC(SYS_ID_AA64ISAR2_EL1); 218 GUEST_REG_SYNC(SYS_ID_AA64PFR0_EL1); 219 GUEST_REG_SYNC(SYS_ID_AA64MMFR0_EL1); 220 GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1); 221 GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1); 222 GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1); 223 GUEST_REG_SYNC(SYS_CTR_EL0); 224 225 GUEST_DONE(); 226 } 227 228 /* Return a safe value to a given ftr_bits an ftr value */ 229 uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr) 230 { 231 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0); 232 233 if (ftr_bits->sign == FTR_UNSIGNED) { 234 switch (ftr_bits->type) { 235 case FTR_EXACT: 236 ftr = ftr_bits->safe_val; 237 break; 238 case FTR_LOWER_SAFE: 239 if (ftr > ftr_bits->safe_val) 240 ftr--; 241 break; 242 case FTR_HIGHER_SAFE: 243 if (ftr < ftr_max) 244 ftr++; 245 break; 246 case FTR_HIGHER_OR_ZERO_SAFE: 247 if (ftr == ftr_max) 248 ftr = 0; 249 else if (ftr != 0) 250 ftr++; 251 break; 252 default: 253 break; 254 } 255 } else if (ftr != ftr_max) { 256 switch (ftr_bits->type) { 257 case FTR_EXACT: 258 ftr = ftr_bits->safe_val; 259 break; 260 case FTR_LOWER_SAFE: 261 if (ftr > ftr_bits->safe_val) 262 ftr--; 263 break; 264 case FTR_HIGHER_SAFE: 265 if (ftr < ftr_max - 1) 266 ftr++; 267 break; 268 case FTR_HIGHER_OR_ZERO_SAFE: 269 if (ftr != 0 && ftr != ftr_max - 1) 270 ftr++; 271 break; 272 default: 273 break; 274 } 275 } 276 277 return ftr; 278 } 279 280 /* Return an invalid value to a given ftr_bits an ftr value */ 281 uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr) 282 { 283 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0); 284 285 if (ftr_bits->sign == FTR_UNSIGNED) { 286 switch (ftr_bits->type) { 287 case FTR_EXACT: 288 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1); 289 break; 290 case FTR_LOWER_SAFE: 291 ftr++; 292 break; 293 case FTR_HIGHER_SAFE: 294 ftr--; 295 break; 296 case FTR_HIGHER_OR_ZERO_SAFE: 297 if (ftr == 0) 298 ftr = ftr_max; 299 else 300 ftr--; 301 break; 302 default: 303 break; 304 } 305 } else if (ftr != ftr_max) { 306 switch (ftr_bits->type) { 307 case FTR_EXACT: 308 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1); 309 break; 310 case FTR_LOWER_SAFE: 311 ftr++; 312 break; 313 case FTR_HIGHER_SAFE: 314 ftr--; 315 break; 316 case FTR_HIGHER_OR_ZERO_SAFE: 317 if (ftr == 0) 318 ftr = ftr_max - 1; 319 else 320 ftr--; 321 break; 322 default: 323 break; 324 } 325 } else { 326 ftr = 0; 327 } 328 329 return ftr; 330 } 331 332 static uint64_t test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg, 333 const struct reg_ftr_bits *ftr_bits) 334 { 335 uint8_t shift = ftr_bits->shift; 336 uint64_t mask = ftr_bits->mask; 337 uint64_t val, new_val, ftr; 338 339 vcpu_get_reg(vcpu, reg, &val); 340 ftr = (val & mask) >> shift; 341 342 ftr = get_safe_value(ftr_bits, ftr); 343 344 ftr <<= shift; 345 val &= ~mask; 346 val |= ftr; 347 348 vcpu_set_reg(vcpu, reg, val); 349 vcpu_get_reg(vcpu, reg, &new_val); 350 TEST_ASSERT_EQ(new_val, val); 351 352 return new_val; 353 } 354 355 static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg, 356 const struct reg_ftr_bits *ftr_bits) 357 { 358 uint8_t shift = ftr_bits->shift; 359 uint64_t mask = ftr_bits->mask; 360 uint64_t val, old_val, ftr; 361 int r; 362 363 vcpu_get_reg(vcpu, reg, &val); 364 ftr = (val & mask) >> shift; 365 366 ftr = get_invalid_value(ftr_bits, ftr); 367 368 old_val = val; 369 ftr <<= shift; 370 val &= ~mask; 371 val |= ftr; 372 373 r = __vcpu_set_reg(vcpu, reg, val); 374 TEST_ASSERT(r < 0 && errno == EINVAL, 375 "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno); 376 377 vcpu_get_reg(vcpu, reg, &val); 378 TEST_ASSERT_EQ(val, old_val); 379 } 380 381 static uint64_t test_reg_vals[KVM_ARM_FEATURE_ID_RANGE_SIZE]; 382 383 #define encoding_to_range_idx(encoding) \ 384 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(encoding), sys_reg_Op1(encoding), \ 385 sys_reg_CRn(encoding), sys_reg_CRm(encoding), \ 386 sys_reg_Op2(encoding)) 387 388 389 static void test_vm_ftr_id_regs(struct kvm_vcpu *vcpu, bool aarch64_only) 390 { 391 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE]; 392 struct reg_mask_range range = { 393 .addr = (__u64)masks, 394 }; 395 int ret; 396 397 /* KVM should return error when reserved field is not zero */ 398 range.reserved[0] = 1; 399 ret = __vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range); 400 TEST_ASSERT(ret, "KVM doesn't check invalid parameters."); 401 402 /* Get writable masks for feature ID registers */ 403 memset(range.reserved, 0, sizeof(range.reserved)); 404 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range); 405 406 for (int i = 0; i < ARRAY_SIZE(test_regs); i++) { 407 const struct reg_ftr_bits *ftr_bits = test_regs[i].ftr_bits; 408 uint32_t reg_id = test_regs[i].reg; 409 uint64_t reg = KVM_ARM64_SYS_REG(reg_id); 410 int idx; 411 412 /* Get the index to masks array for the idreg */ 413 idx = encoding_to_range_idx(reg_id); 414 415 for (int j = 0; ftr_bits[j].type != FTR_END; j++) { 416 /* Skip aarch32 reg on aarch64 only system, since they are RAZ/WI. */ 417 if (aarch64_only && sys_reg_CRm(reg_id) < 4) { 418 ksft_test_result_skip("%s on AARCH64 only system\n", 419 ftr_bits[j].name); 420 continue; 421 } 422 423 /* Make sure the feature field is writable */ 424 TEST_ASSERT_EQ(masks[idx] & ftr_bits[j].mask, ftr_bits[j].mask); 425 426 test_reg_set_fail(vcpu, reg, &ftr_bits[j]); 427 428 test_reg_vals[idx] = test_reg_set_success(vcpu, reg, 429 &ftr_bits[j]); 430 431 ksft_test_result_pass("%s\n", ftr_bits[j].name); 432 } 433 } 434 } 435 436 static void test_guest_reg_read(struct kvm_vcpu *vcpu) 437 { 438 bool done = false; 439 struct ucall uc; 440 441 while (!done) { 442 vcpu_run(vcpu); 443 444 switch (get_ucall(vcpu, &uc)) { 445 case UCALL_ABORT: 446 REPORT_GUEST_ASSERT(uc); 447 break; 448 case UCALL_SYNC: 449 /* Make sure the written values are seen by guest */ 450 TEST_ASSERT_EQ(test_reg_vals[encoding_to_range_idx(uc.args[2])], 451 uc.args[3]); 452 break; 453 case UCALL_DONE: 454 done = true; 455 break; 456 default: 457 TEST_FAIL("Unexpected ucall: %lu", uc.cmd); 458 } 459 } 460 } 461 462 /* Politely lifted from arch/arm64/include/asm/cache.h */ 463 /* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */ 464 #define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) 465 #define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) 466 #define CLIDR_CTYPE(clidr, level) \ 467 (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) 468 469 static void test_clidr(struct kvm_vcpu *vcpu) 470 { 471 uint64_t clidr; 472 int level; 473 474 vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1), &clidr); 475 476 /* find the first empty level in the cache hierarchy */ 477 for (level = 1; level < 7; level++) { 478 if (!CLIDR_CTYPE(clidr, level)) 479 break; 480 } 481 482 /* 483 * If you have a mind-boggling 7 levels of cache, congratulations, you 484 * get to fix this. 485 */ 486 TEST_ASSERT(level <= 7, "can't find an empty level in cache hierarchy"); 487 488 /* stick in a unified cache level */ 489 clidr |= BIT(2) << CLIDR_CTYPE_SHIFT(level); 490 491 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1), clidr); 492 test_reg_vals[encoding_to_range_idx(SYS_CLIDR_EL1)] = clidr; 493 } 494 495 static void test_ctr(struct kvm_vcpu *vcpu) 496 { 497 u64 ctr; 498 499 vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0), &ctr); 500 ctr &= ~CTR_EL0_DIC_MASK; 501 if (ctr & CTR_EL0_IminLine_MASK) 502 ctr--; 503 504 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0), ctr); 505 test_reg_vals[encoding_to_range_idx(SYS_CTR_EL0)] = ctr; 506 } 507 508 static void test_vcpu_ftr_id_regs(struct kvm_vcpu *vcpu) 509 { 510 u64 val; 511 512 test_clidr(vcpu); 513 test_ctr(vcpu); 514 515 vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1), &val); 516 val++; 517 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1), val); 518 519 test_reg_vals[encoding_to_range_idx(SYS_MPIDR_EL1)] = val; 520 ksft_test_result_pass("%s\n", __func__); 521 } 522 523 static void test_assert_id_reg_unchanged(struct kvm_vcpu *vcpu, uint32_t encoding) 524 { 525 size_t idx = encoding_to_range_idx(encoding); 526 uint64_t observed; 527 528 vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding), &observed); 529 TEST_ASSERT_EQ(test_reg_vals[idx], observed); 530 } 531 532 static void test_reset_preserves_id_regs(struct kvm_vcpu *vcpu) 533 { 534 /* 535 * Calls KVM_ARM_VCPU_INIT behind the scenes, which will do an 536 * architectural reset of the vCPU. 537 */ 538 aarch64_vcpu_setup(vcpu, NULL); 539 540 for (int i = 0; i < ARRAY_SIZE(test_regs); i++) 541 test_assert_id_reg_unchanged(vcpu, test_regs[i].reg); 542 543 test_assert_id_reg_unchanged(vcpu, SYS_MPIDR_EL1); 544 test_assert_id_reg_unchanged(vcpu, SYS_CLIDR_EL1); 545 test_assert_id_reg_unchanged(vcpu, SYS_CTR_EL0); 546 547 ksft_test_result_pass("%s\n", __func__); 548 } 549 550 int main(void) 551 { 552 struct kvm_vcpu *vcpu; 553 struct kvm_vm *vm; 554 bool aarch64_only; 555 uint64_t val, el0; 556 int test_cnt; 557 558 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES)); 559 560 vm = vm_create_with_one_vcpu(&vcpu, guest_code); 561 562 /* Check for AARCH64 only system */ 563 vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), &val); 564 el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val); 565 aarch64_only = (el0 == ID_AA64PFR0_EL1_ELx_64BIT_ONLY); 566 567 ksft_print_header(); 568 569 test_cnt = ARRAY_SIZE(ftr_id_aa64dfr0_el1) + ARRAY_SIZE(ftr_id_dfr0_el1) + 570 ARRAY_SIZE(ftr_id_aa64isar0_el1) + ARRAY_SIZE(ftr_id_aa64isar1_el1) + 571 ARRAY_SIZE(ftr_id_aa64isar2_el1) + ARRAY_SIZE(ftr_id_aa64pfr0_el1) + 572 ARRAY_SIZE(ftr_id_aa64mmfr0_el1) + ARRAY_SIZE(ftr_id_aa64mmfr1_el1) + 573 ARRAY_SIZE(ftr_id_aa64mmfr2_el1) + ARRAY_SIZE(ftr_id_aa64zfr0_el1) - 574 ARRAY_SIZE(test_regs) + 2; 575 576 ksft_set_plan(test_cnt); 577 578 test_vm_ftr_id_regs(vcpu, aarch64_only); 579 test_vcpu_ftr_id_regs(vcpu); 580 581 test_guest_reg_read(vcpu); 582 583 test_reset_preserves_id_regs(vcpu); 584 585 kvm_vm_free(vm); 586 587 ksft_finished(); 588 } 589