1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright(c) 2021 Intel Corporation. All rights reserved. 3 4 #include <linux/platform_device.h> 5 #include <linux/mod_devicetable.h> 6 #include <linux/vmalloc.h> 7 #include <linux/module.h> 8 #include <linux/delay.h> 9 #include <linux/sizes.h> 10 #include <linux/bits.h> 11 #include <asm/unaligned.h> 12 #include <crypto/sha2.h> 13 #include <cxlmem.h> 14 15 #include "trace.h" 16 17 #define LSA_SIZE SZ_128K 18 #define FW_SIZE SZ_64M 19 #define FW_SLOTS 3 20 #define DEV_SIZE SZ_2G 21 #define EFFECT(x) (1U << x) 22 23 #define MOCK_INJECT_DEV_MAX 8 24 #define MOCK_INJECT_TEST_MAX 128 25 26 static unsigned int poison_inject_dev_max = MOCK_INJECT_DEV_MAX; 27 28 enum cxl_command_effects { 29 CONF_CHANGE_COLD_RESET = 0, 30 CONF_CHANGE_IMMEDIATE, 31 DATA_CHANGE_IMMEDIATE, 32 POLICY_CHANGE_IMMEDIATE, 33 LOG_CHANGE_IMMEDIATE, 34 SECURITY_CHANGE_IMMEDIATE, 35 BACKGROUND_OP, 36 SECONDARY_MBOX_SUPPORTED, 37 }; 38 39 #define CXL_CMD_EFFECT_NONE cpu_to_le16(0) 40 41 static struct cxl_cel_entry mock_cel[] = { 42 { 43 .opcode = cpu_to_le16(CXL_MBOX_OP_GET_SUPPORTED_LOGS), 44 .effect = CXL_CMD_EFFECT_NONE, 45 }, 46 { 47 .opcode = cpu_to_le16(CXL_MBOX_OP_IDENTIFY), 48 .effect = CXL_CMD_EFFECT_NONE, 49 }, 50 { 51 .opcode = cpu_to_le16(CXL_MBOX_OP_GET_LSA), 52 .effect = CXL_CMD_EFFECT_NONE, 53 }, 54 { 55 .opcode = cpu_to_le16(CXL_MBOX_OP_GET_PARTITION_INFO), 56 .effect = CXL_CMD_EFFECT_NONE, 57 }, 58 { 59 .opcode = cpu_to_le16(CXL_MBOX_OP_SET_LSA), 60 .effect = cpu_to_le16(EFFECT(CONF_CHANGE_IMMEDIATE) | 61 EFFECT(DATA_CHANGE_IMMEDIATE)), 62 }, 63 { 64 .opcode = cpu_to_le16(CXL_MBOX_OP_GET_HEALTH_INFO), 65 .effect = CXL_CMD_EFFECT_NONE, 66 }, 67 { 68 .opcode = cpu_to_le16(CXL_MBOX_OP_GET_POISON), 69 .effect = CXL_CMD_EFFECT_NONE, 70 }, 71 { 72 .opcode = cpu_to_le16(CXL_MBOX_OP_INJECT_POISON), 73 .effect = cpu_to_le16(EFFECT(DATA_CHANGE_IMMEDIATE)), 74 }, 75 { 76 .opcode = cpu_to_le16(CXL_MBOX_OP_CLEAR_POISON), 77 .effect = cpu_to_le16(EFFECT(DATA_CHANGE_IMMEDIATE)), 78 }, 79 { 80 .opcode = cpu_to_le16(CXL_MBOX_OP_GET_FW_INFO), 81 .effect = CXL_CMD_EFFECT_NONE, 82 }, 83 { 84 .opcode = cpu_to_le16(CXL_MBOX_OP_TRANSFER_FW), 85 .effect = cpu_to_le16(EFFECT(CONF_CHANGE_COLD_RESET) | 86 EFFECT(BACKGROUND_OP)), 87 }, 88 { 89 .opcode = cpu_to_le16(CXL_MBOX_OP_ACTIVATE_FW), 90 .effect = cpu_to_le16(EFFECT(CONF_CHANGE_COLD_RESET) | 91 EFFECT(CONF_CHANGE_IMMEDIATE)), 92 }, 93 { 94 .opcode = cpu_to_le16(CXL_MBOX_OP_SANITIZE), 95 .effect = cpu_to_le16(EFFECT(DATA_CHANGE_IMMEDIATE) | 96 EFFECT(SECURITY_CHANGE_IMMEDIATE) | 97 EFFECT(BACKGROUND_OP)), 98 }, 99 }; 100 101 /* See CXL 2.0 Table 181 Get Health Info Output Payload */ 102 struct cxl_mbox_health_info { 103 u8 health_status; 104 u8 media_status; 105 u8 ext_status; 106 u8 life_used; 107 __le16 temperature; 108 __le32 dirty_shutdowns; 109 __le32 volatile_errors; 110 __le32 pmem_errors; 111 } __packed; 112 113 static struct { 114 struct cxl_mbox_get_supported_logs gsl; 115 struct cxl_gsl_entry entry; 116 } mock_gsl_payload = { 117 .gsl = { 118 .entries = cpu_to_le16(1), 119 }, 120 .entry = { 121 .uuid = DEFINE_CXL_CEL_UUID, 122 .size = cpu_to_le32(sizeof(mock_cel)), 123 }, 124 }; 125 126 #define PASS_TRY_LIMIT 3 127 128 #define CXL_TEST_EVENT_CNT_MAX 15 129 130 /* Set a number of events to return at a time for simulation. */ 131 #define CXL_TEST_EVENT_RET_MAX 4 132 133 struct mock_event_log { 134 u16 clear_idx; 135 u16 cur_idx; 136 u16 nr_events; 137 u16 nr_overflow; 138 u16 overflow_reset; 139 struct cxl_event_record_raw *events[CXL_TEST_EVENT_CNT_MAX]; 140 }; 141 142 struct mock_event_store { 143 struct mock_event_log mock_logs[CXL_EVENT_TYPE_MAX]; 144 u32 ev_status; 145 }; 146 147 struct cxl_mockmem_data { 148 void *lsa; 149 void *fw; 150 int fw_slot; 151 int fw_staged; 152 size_t fw_size; 153 u32 security_state; 154 u8 user_pass[NVDIMM_PASSPHRASE_LEN]; 155 u8 master_pass[NVDIMM_PASSPHRASE_LEN]; 156 int user_limit; 157 int master_limit; 158 struct mock_event_store mes; 159 struct cxl_memdev_state *mds; 160 u8 event_buf[SZ_4K]; 161 u64 timestamp; 162 unsigned long sanitize_timeout; 163 }; 164 165 static struct mock_event_log *event_find_log(struct device *dev, int log_type) 166 { 167 struct cxl_mockmem_data *mdata = dev_get_drvdata(dev); 168 169 if (log_type >= CXL_EVENT_TYPE_MAX) 170 return NULL; 171 return &mdata->mes.mock_logs[log_type]; 172 } 173 174 static struct cxl_event_record_raw *event_get_current(struct mock_event_log *log) 175 { 176 return log->events[log->cur_idx]; 177 } 178 179 static void event_reset_log(struct mock_event_log *log) 180 { 181 log->cur_idx = 0; 182 log->clear_idx = 0; 183 log->nr_overflow = log->overflow_reset; 184 } 185 186 /* Handle can never be 0 use 1 based indexing for handle */ 187 static u16 event_get_clear_handle(struct mock_event_log *log) 188 { 189 return log->clear_idx + 1; 190 } 191 192 /* Handle can never be 0 use 1 based indexing for handle */ 193 static __le16 event_get_cur_event_handle(struct mock_event_log *log) 194 { 195 u16 cur_handle = log->cur_idx + 1; 196 197 return cpu_to_le16(cur_handle); 198 } 199 200 static bool event_log_empty(struct mock_event_log *log) 201 { 202 return log->cur_idx == log->nr_events; 203 } 204 205 static void mes_add_event(struct mock_event_store *mes, 206 enum cxl_event_log_type log_type, 207 struct cxl_event_record_raw *event) 208 { 209 struct mock_event_log *log; 210 211 if (WARN_ON(log_type >= CXL_EVENT_TYPE_MAX)) 212 return; 213 214 log = &mes->mock_logs[log_type]; 215 216 if ((log->nr_events + 1) > CXL_TEST_EVENT_CNT_MAX) { 217 log->nr_overflow++; 218 log->overflow_reset = log->nr_overflow; 219 return; 220 } 221 222 log->events[log->nr_events] = event; 223 log->nr_events++; 224 } 225 226 /* 227 * Vary the number of events returned to simulate events occuring while the 228 * logs are being read. 229 */ 230 static int ret_limit = 0; 231 232 static int mock_get_event(struct device *dev, struct cxl_mbox_cmd *cmd) 233 { 234 struct cxl_get_event_payload *pl; 235 struct mock_event_log *log; 236 u16 nr_overflow; 237 u8 log_type; 238 int i; 239 240 if (cmd->size_in != sizeof(log_type)) 241 return -EINVAL; 242 243 ret_limit = (ret_limit + 1) % CXL_TEST_EVENT_RET_MAX; 244 if (!ret_limit) 245 ret_limit = 1; 246 247 if (cmd->size_out < struct_size(pl, records, ret_limit)) 248 return -EINVAL; 249 250 log_type = *((u8 *)cmd->payload_in); 251 if (log_type >= CXL_EVENT_TYPE_MAX) 252 return -EINVAL; 253 254 memset(cmd->payload_out, 0, struct_size(pl, records, 0)); 255 256 log = event_find_log(dev, log_type); 257 if (!log || event_log_empty(log)) 258 return 0; 259 260 pl = cmd->payload_out; 261 262 for (i = 0; i < ret_limit && !event_log_empty(log); i++) { 263 memcpy(&pl->records[i], event_get_current(log), 264 sizeof(pl->records[i])); 265 pl->records[i].event.generic.hdr.handle = 266 event_get_cur_event_handle(log); 267 log->cur_idx++; 268 } 269 270 cmd->size_out = struct_size(pl, records, i); 271 pl->record_count = cpu_to_le16(i); 272 if (!event_log_empty(log)) 273 pl->flags |= CXL_GET_EVENT_FLAG_MORE_RECORDS; 274 275 if (log->nr_overflow) { 276 u64 ns; 277 278 pl->flags |= CXL_GET_EVENT_FLAG_OVERFLOW; 279 pl->overflow_err_count = cpu_to_le16(nr_overflow); 280 ns = ktime_get_real_ns(); 281 ns -= 5000000000; /* 5s ago */ 282 pl->first_overflow_timestamp = cpu_to_le64(ns); 283 ns = ktime_get_real_ns(); 284 ns -= 1000000000; /* 1s ago */ 285 pl->last_overflow_timestamp = cpu_to_le64(ns); 286 } 287 288 return 0; 289 } 290 291 static int mock_clear_event(struct device *dev, struct cxl_mbox_cmd *cmd) 292 { 293 struct cxl_mbox_clear_event_payload *pl = cmd->payload_in; 294 struct mock_event_log *log; 295 u8 log_type = pl->event_log; 296 u16 handle; 297 int nr; 298 299 if (log_type >= CXL_EVENT_TYPE_MAX) 300 return -EINVAL; 301 302 log = event_find_log(dev, log_type); 303 if (!log) 304 return 0; /* No mock data in this log */ 305 306 /* 307 * This check is technically not invalid per the specification AFAICS. 308 * (The host could 'guess' handles and clear them in order). 309 * However, this is not good behavior for the host so test it. 310 */ 311 if (log->clear_idx + pl->nr_recs > log->cur_idx) { 312 dev_err(dev, 313 "Attempting to clear more events than returned!\n"); 314 return -EINVAL; 315 } 316 317 /* Check handle order prior to clearing events */ 318 for (nr = 0, handle = event_get_clear_handle(log); 319 nr < pl->nr_recs; 320 nr++, handle++) { 321 if (handle != le16_to_cpu(pl->handles[nr])) { 322 dev_err(dev, "Clearing events out of order\n"); 323 return -EINVAL; 324 } 325 } 326 327 if (log->nr_overflow) 328 log->nr_overflow = 0; 329 330 /* Clear events */ 331 log->clear_idx += pl->nr_recs; 332 return 0; 333 } 334 335 static void cxl_mock_event_trigger(struct device *dev) 336 { 337 struct cxl_mockmem_data *mdata = dev_get_drvdata(dev); 338 struct mock_event_store *mes = &mdata->mes; 339 int i; 340 341 for (i = CXL_EVENT_TYPE_INFO; i < CXL_EVENT_TYPE_MAX; i++) { 342 struct mock_event_log *log; 343 344 log = event_find_log(dev, i); 345 if (log) 346 event_reset_log(log); 347 } 348 349 cxl_mem_get_event_records(mdata->mds, mes->ev_status); 350 } 351 352 struct cxl_event_record_raw maint_needed = { 353 .id = UUID_INIT(0xBA5EBA11, 0xABCD, 0xEFEB, 354 0xa5, 0x5a, 0xa5, 0x5a, 0xa5, 0xa5, 0x5a, 0xa5), 355 .event.generic = { 356 .hdr = { 357 .length = sizeof(struct cxl_event_record_raw), 358 .flags[0] = CXL_EVENT_RECORD_FLAG_MAINT_NEEDED, 359 /* .handle = Set dynamically */ 360 .related_handle = cpu_to_le16(0xa5b6), 361 }, 362 .data = { 0xDE, 0xAD, 0xBE, 0xEF }, 363 }, 364 }; 365 366 struct cxl_event_record_raw hardware_replace = { 367 .id = UUID_INIT(0xABCDEFEB, 0xBA11, 0xBA5E, 368 0xa5, 0x5a, 0xa5, 0x5a, 0xa5, 0xa5, 0x5a, 0xa5), 369 .event.generic = { 370 .hdr = { 371 .length = sizeof(struct cxl_event_record_raw), 372 .flags[0] = CXL_EVENT_RECORD_FLAG_HW_REPLACE, 373 /* .handle = Set dynamically */ 374 .related_handle = cpu_to_le16(0xb6a5), 375 }, 376 .data = { 0xDE, 0xAD, 0xBE, 0xEF }, 377 }, 378 }; 379 380 struct cxl_test_gen_media { 381 uuid_t id; 382 struct cxl_event_gen_media rec; 383 } __packed; 384 385 struct cxl_test_gen_media gen_media = { 386 .id = CXL_EVENT_GEN_MEDIA_UUID, 387 .rec = { 388 .hdr = { 389 .length = sizeof(struct cxl_test_gen_media), 390 .flags[0] = CXL_EVENT_RECORD_FLAG_PERMANENT, 391 /* .handle = Set dynamically */ 392 .related_handle = cpu_to_le16(0), 393 }, 394 .phys_addr = cpu_to_le64(0x2000), 395 .descriptor = CXL_GMER_EVT_DESC_UNCORECTABLE_EVENT, 396 .type = CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR, 397 .transaction_type = CXL_GMER_TRANS_HOST_WRITE, 398 /* .validity_flags = <set below> */ 399 .channel = 1, 400 .rank = 30 401 }, 402 }; 403 404 struct cxl_test_dram { 405 uuid_t id; 406 struct cxl_event_dram rec; 407 } __packed; 408 409 struct cxl_test_dram dram = { 410 .id = CXL_EVENT_DRAM_UUID, 411 .rec = { 412 .hdr = { 413 .length = sizeof(struct cxl_test_dram), 414 .flags[0] = CXL_EVENT_RECORD_FLAG_PERF_DEGRADED, 415 /* .handle = Set dynamically */ 416 .related_handle = cpu_to_le16(0), 417 }, 418 .phys_addr = cpu_to_le64(0x8000), 419 .descriptor = CXL_GMER_EVT_DESC_THRESHOLD_EVENT, 420 .type = CXL_GMER_MEM_EVT_TYPE_INV_ADDR, 421 .transaction_type = CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB, 422 /* .validity_flags = <set below> */ 423 .channel = 1, 424 .bank_group = 5, 425 .bank = 2, 426 .column = {0xDE, 0xAD}, 427 }, 428 }; 429 430 struct cxl_test_mem_module { 431 uuid_t id; 432 struct cxl_event_mem_module rec; 433 } __packed; 434 435 struct cxl_test_mem_module mem_module = { 436 .id = CXL_EVENT_MEM_MODULE_UUID, 437 .rec = { 438 .hdr = { 439 .length = sizeof(struct cxl_test_mem_module), 440 /* .handle = Set dynamically */ 441 .related_handle = cpu_to_le16(0), 442 }, 443 .event_type = CXL_MMER_TEMP_CHANGE, 444 .info = { 445 .health_status = CXL_DHI_HS_PERFORMANCE_DEGRADED, 446 .media_status = CXL_DHI_MS_ALL_DATA_LOST, 447 .add_status = (CXL_DHI_AS_CRITICAL << 2) | 448 (CXL_DHI_AS_WARNING << 4) | 449 (CXL_DHI_AS_WARNING << 5), 450 .device_temp = { 0xDE, 0xAD}, 451 .dirty_shutdown_cnt = { 0xde, 0xad, 0xbe, 0xef }, 452 .cor_vol_err_cnt = { 0xde, 0xad, 0xbe, 0xef }, 453 .cor_per_err_cnt = { 0xde, 0xad, 0xbe, 0xef }, 454 } 455 }, 456 }; 457 458 static int mock_set_timestamp(struct cxl_dev_state *cxlds, 459 struct cxl_mbox_cmd *cmd) 460 { 461 struct cxl_mockmem_data *mdata = dev_get_drvdata(cxlds->dev); 462 struct cxl_mbox_set_timestamp_in *ts = cmd->payload_in; 463 464 if (cmd->size_in != sizeof(*ts)) 465 return -EINVAL; 466 467 if (cmd->size_out != 0) 468 return -EINVAL; 469 470 mdata->timestamp = le64_to_cpu(ts->timestamp); 471 return 0; 472 } 473 474 static void cxl_mock_add_event_logs(struct mock_event_store *mes) 475 { 476 put_unaligned_le16(CXL_GMER_VALID_CHANNEL | CXL_GMER_VALID_RANK, 477 &gen_media.rec.validity_flags); 478 479 put_unaligned_le16(CXL_DER_VALID_CHANNEL | CXL_DER_VALID_BANK_GROUP | 480 CXL_DER_VALID_BANK | CXL_DER_VALID_COLUMN, 481 &dram.rec.validity_flags); 482 483 mes_add_event(mes, CXL_EVENT_TYPE_INFO, &maint_needed); 484 mes_add_event(mes, CXL_EVENT_TYPE_INFO, 485 (struct cxl_event_record_raw *)&gen_media); 486 mes_add_event(mes, CXL_EVENT_TYPE_INFO, 487 (struct cxl_event_record_raw *)&mem_module); 488 mes->ev_status |= CXLDEV_EVENT_STATUS_INFO; 489 490 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &maint_needed); 491 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 492 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, 493 (struct cxl_event_record_raw *)&dram); 494 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, 495 (struct cxl_event_record_raw *)&gen_media); 496 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, 497 (struct cxl_event_record_raw *)&mem_module); 498 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 499 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, 500 (struct cxl_event_record_raw *)&dram); 501 /* Overflow this log */ 502 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 503 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 504 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 505 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 506 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 507 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 508 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 509 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 510 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 511 mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace); 512 mes->ev_status |= CXLDEV_EVENT_STATUS_FAIL; 513 514 mes_add_event(mes, CXL_EVENT_TYPE_FATAL, &hardware_replace); 515 mes_add_event(mes, CXL_EVENT_TYPE_FATAL, 516 (struct cxl_event_record_raw *)&dram); 517 mes->ev_status |= CXLDEV_EVENT_STATUS_FATAL; 518 } 519 520 static int mock_gsl(struct cxl_mbox_cmd *cmd) 521 { 522 if (cmd->size_out < sizeof(mock_gsl_payload)) 523 return -EINVAL; 524 525 memcpy(cmd->payload_out, &mock_gsl_payload, sizeof(mock_gsl_payload)); 526 cmd->size_out = sizeof(mock_gsl_payload); 527 528 return 0; 529 } 530 531 static int mock_get_log(struct cxl_memdev_state *mds, struct cxl_mbox_cmd *cmd) 532 { 533 struct cxl_mbox_get_log *gl = cmd->payload_in; 534 u32 offset = le32_to_cpu(gl->offset); 535 u32 length = le32_to_cpu(gl->length); 536 uuid_t uuid = DEFINE_CXL_CEL_UUID; 537 void *data = &mock_cel; 538 539 if (cmd->size_in < sizeof(*gl)) 540 return -EINVAL; 541 if (length > mds->payload_size) 542 return -EINVAL; 543 if (offset + length > sizeof(mock_cel)) 544 return -EINVAL; 545 if (!uuid_equal(&gl->uuid, &uuid)) 546 return -EINVAL; 547 if (length > cmd->size_out) 548 return -EINVAL; 549 550 memcpy(cmd->payload_out, data + offset, length); 551 552 return 0; 553 } 554 555 static int mock_rcd_id(struct cxl_mbox_cmd *cmd) 556 { 557 struct cxl_mbox_identify id = { 558 .fw_revision = { "mock fw v1 " }, 559 .total_capacity = 560 cpu_to_le64(DEV_SIZE / CXL_CAPACITY_MULTIPLIER), 561 .volatile_capacity = 562 cpu_to_le64(DEV_SIZE / CXL_CAPACITY_MULTIPLIER), 563 }; 564 565 if (cmd->size_out < sizeof(id)) 566 return -EINVAL; 567 568 memcpy(cmd->payload_out, &id, sizeof(id)); 569 570 return 0; 571 } 572 573 static int mock_id(struct cxl_mbox_cmd *cmd) 574 { 575 struct cxl_mbox_identify id = { 576 .fw_revision = { "mock fw v1 " }, 577 .lsa_size = cpu_to_le32(LSA_SIZE), 578 .partition_align = 579 cpu_to_le64(SZ_256M / CXL_CAPACITY_MULTIPLIER), 580 .total_capacity = 581 cpu_to_le64(DEV_SIZE / CXL_CAPACITY_MULTIPLIER), 582 .inject_poison_limit = cpu_to_le16(MOCK_INJECT_TEST_MAX), 583 }; 584 585 put_unaligned_le24(CXL_POISON_LIST_MAX, id.poison_list_max_mer); 586 587 if (cmd->size_out < sizeof(id)) 588 return -EINVAL; 589 590 memcpy(cmd->payload_out, &id, sizeof(id)); 591 592 return 0; 593 } 594 595 static int mock_partition_info(struct cxl_mbox_cmd *cmd) 596 { 597 struct cxl_mbox_get_partition_info pi = { 598 .active_volatile_cap = 599 cpu_to_le64(DEV_SIZE / 2 / CXL_CAPACITY_MULTIPLIER), 600 .active_persistent_cap = 601 cpu_to_le64(DEV_SIZE / 2 / CXL_CAPACITY_MULTIPLIER), 602 }; 603 604 if (cmd->size_out < sizeof(pi)) 605 return -EINVAL; 606 607 memcpy(cmd->payload_out, &pi, sizeof(pi)); 608 609 return 0; 610 } 611 612 void cxl_mockmem_sanitize_work(struct work_struct *work) 613 { 614 struct cxl_memdev_state *mds = 615 container_of(work, typeof(*mds), security.poll_dwork.work); 616 617 mutex_lock(&mds->mbox_mutex); 618 if (mds->security.sanitize_node) 619 sysfs_notify_dirent(mds->security.sanitize_node); 620 mds->security.sanitize_active = false; 621 mutex_unlock(&mds->mbox_mutex); 622 623 dev_dbg(mds->cxlds.dev, "sanitize complete\n"); 624 } 625 626 static int mock_sanitize(struct cxl_mockmem_data *mdata, 627 struct cxl_mbox_cmd *cmd) 628 { 629 struct cxl_memdev_state *mds = mdata->mds; 630 int rc = 0; 631 632 if (cmd->size_in != 0) 633 return -EINVAL; 634 635 if (cmd->size_out != 0) 636 return -EINVAL; 637 638 if (mdata->security_state & CXL_PMEM_SEC_STATE_USER_PASS_SET) { 639 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 640 return -ENXIO; 641 } 642 if (mdata->security_state & CXL_PMEM_SEC_STATE_LOCKED) { 643 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 644 return -ENXIO; 645 } 646 647 mutex_lock(&mds->mbox_mutex); 648 if (schedule_delayed_work(&mds->security.poll_dwork, 649 msecs_to_jiffies(mdata->sanitize_timeout))) { 650 mds->security.sanitize_active = true; 651 dev_dbg(mds->cxlds.dev, "sanitize issued\n"); 652 } else 653 rc = -EBUSY; 654 mutex_unlock(&mds->mbox_mutex); 655 656 return rc; 657 } 658 659 static int mock_secure_erase(struct cxl_mockmem_data *mdata, 660 struct cxl_mbox_cmd *cmd) 661 { 662 if (cmd->size_in != 0) 663 return -EINVAL; 664 665 if (cmd->size_out != 0) 666 return -EINVAL; 667 668 if (mdata->security_state & CXL_PMEM_SEC_STATE_USER_PASS_SET) { 669 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 670 return -ENXIO; 671 } 672 673 if (mdata->security_state & CXL_PMEM_SEC_STATE_LOCKED) { 674 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 675 return -ENXIO; 676 } 677 678 return 0; 679 } 680 681 static int mock_get_security_state(struct cxl_mockmem_data *mdata, 682 struct cxl_mbox_cmd *cmd) 683 { 684 if (cmd->size_in) 685 return -EINVAL; 686 687 if (cmd->size_out != sizeof(u32)) 688 return -EINVAL; 689 690 memcpy(cmd->payload_out, &mdata->security_state, sizeof(u32)); 691 692 return 0; 693 } 694 695 static void master_plimit_check(struct cxl_mockmem_data *mdata) 696 { 697 if (mdata->master_limit == PASS_TRY_LIMIT) 698 return; 699 mdata->master_limit++; 700 if (mdata->master_limit == PASS_TRY_LIMIT) 701 mdata->security_state |= CXL_PMEM_SEC_STATE_MASTER_PLIMIT; 702 } 703 704 static void user_plimit_check(struct cxl_mockmem_data *mdata) 705 { 706 if (mdata->user_limit == PASS_TRY_LIMIT) 707 return; 708 mdata->user_limit++; 709 if (mdata->user_limit == PASS_TRY_LIMIT) 710 mdata->security_state |= CXL_PMEM_SEC_STATE_USER_PLIMIT; 711 } 712 713 static int mock_set_passphrase(struct cxl_mockmem_data *mdata, 714 struct cxl_mbox_cmd *cmd) 715 { 716 struct cxl_set_pass *set_pass; 717 718 if (cmd->size_in != sizeof(*set_pass)) 719 return -EINVAL; 720 721 if (cmd->size_out != 0) 722 return -EINVAL; 723 724 if (mdata->security_state & CXL_PMEM_SEC_STATE_FROZEN) { 725 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 726 return -ENXIO; 727 } 728 729 set_pass = cmd->payload_in; 730 switch (set_pass->type) { 731 case CXL_PMEM_SEC_PASS_MASTER: 732 if (mdata->security_state & CXL_PMEM_SEC_STATE_MASTER_PLIMIT) { 733 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 734 return -ENXIO; 735 } 736 /* 737 * CXL spec rev3.0 8.2.9.8.6.2, The master pasphrase shall only be set in 738 * the security disabled state when the user passphrase is not set. 739 */ 740 if (mdata->security_state & CXL_PMEM_SEC_STATE_USER_PASS_SET) { 741 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 742 return -ENXIO; 743 } 744 if (memcmp(mdata->master_pass, set_pass->old_pass, NVDIMM_PASSPHRASE_LEN)) { 745 master_plimit_check(mdata); 746 cmd->return_code = CXL_MBOX_CMD_RC_PASSPHRASE; 747 return -ENXIO; 748 } 749 memcpy(mdata->master_pass, set_pass->new_pass, NVDIMM_PASSPHRASE_LEN); 750 mdata->security_state |= CXL_PMEM_SEC_STATE_MASTER_PASS_SET; 751 return 0; 752 753 case CXL_PMEM_SEC_PASS_USER: 754 if (mdata->security_state & CXL_PMEM_SEC_STATE_USER_PLIMIT) { 755 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 756 return -ENXIO; 757 } 758 if (memcmp(mdata->user_pass, set_pass->old_pass, NVDIMM_PASSPHRASE_LEN)) { 759 user_plimit_check(mdata); 760 cmd->return_code = CXL_MBOX_CMD_RC_PASSPHRASE; 761 return -ENXIO; 762 } 763 memcpy(mdata->user_pass, set_pass->new_pass, NVDIMM_PASSPHRASE_LEN); 764 mdata->security_state |= CXL_PMEM_SEC_STATE_USER_PASS_SET; 765 return 0; 766 767 default: 768 cmd->return_code = CXL_MBOX_CMD_RC_INPUT; 769 } 770 return -EINVAL; 771 } 772 773 static int mock_disable_passphrase(struct cxl_mockmem_data *mdata, 774 struct cxl_mbox_cmd *cmd) 775 { 776 struct cxl_disable_pass *dis_pass; 777 778 if (cmd->size_in != sizeof(*dis_pass)) 779 return -EINVAL; 780 781 if (cmd->size_out != 0) 782 return -EINVAL; 783 784 if (mdata->security_state & CXL_PMEM_SEC_STATE_FROZEN) { 785 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 786 return -ENXIO; 787 } 788 789 dis_pass = cmd->payload_in; 790 switch (dis_pass->type) { 791 case CXL_PMEM_SEC_PASS_MASTER: 792 if (mdata->security_state & CXL_PMEM_SEC_STATE_MASTER_PLIMIT) { 793 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 794 return -ENXIO; 795 } 796 797 if (!(mdata->security_state & CXL_PMEM_SEC_STATE_MASTER_PASS_SET)) { 798 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 799 return -ENXIO; 800 } 801 802 if (memcmp(dis_pass->pass, mdata->master_pass, NVDIMM_PASSPHRASE_LEN)) { 803 master_plimit_check(mdata); 804 cmd->return_code = CXL_MBOX_CMD_RC_PASSPHRASE; 805 return -ENXIO; 806 } 807 808 mdata->master_limit = 0; 809 memset(mdata->master_pass, 0, NVDIMM_PASSPHRASE_LEN); 810 mdata->security_state &= ~CXL_PMEM_SEC_STATE_MASTER_PASS_SET; 811 return 0; 812 813 case CXL_PMEM_SEC_PASS_USER: 814 if (mdata->security_state & CXL_PMEM_SEC_STATE_USER_PLIMIT) { 815 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 816 return -ENXIO; 817 } 818 819 if (!(mdata->security_state & CXL_PMEM_SEC_STATE_USER_PASS_SET)) { 820 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 821 return -ENXIO; 822 } 823 824 if (memcmp(dis_pass->pass, mdata->user_pass, NVDIMM_PASSPHRASE_LEN)) { 825 user_plimit_check(mdata); 826 cmd->return_code = CXL_MBOX_CMD_RC_PASSPHRASE; 827 return -ENXIO; 828 } 829 830 mdata->user_limit = 0; 831 memset(mdata->user_pass, 0, NVDIMM_PASSPHRASE_LEN); 832 mdata->security_state &= ~(CXL_PMEM_SEC_STATE_USER_PASS_SET | 833 CXL_PMEM_SEC_STATE_LOCKED); 834 return 0; 835 836 default: 837 cmd->return_code = CXL_MBOX_CMD_RC_INPUT; 838 return -EINVAL; 839 } 840 841 return 0; 842 } 843 844 static int mock_freeze_security(struct cxl_mockmem_data *mdata, 845 struct cxl_mbox_cmd *cmd) 846 { 847 if (cmd->size_in != 0) 848 return -EINVAL; 849 850 if (cmd->size_out != 0) 851 return -EINVAL; 852 853 if (mdata->security_state & CXL_PMEM_SEC_STATE_FROZEN) 854 return 0; 855 856 mdata->security_state |= CXL_PMEM_SEC_STATE_FROZEN; 857 return 0; 858 } 859 860 static int mock_unlock_security(struct cxl_mockmem_data *mdata, 861 struct cxl_mbox_cmd *cmd) 862 { 863 if (cmd->size_in != NVDIMM_PASSPHRASE_LEN) 864 return -EINVAL; 865 866 if (cmd->size_out != 0) 867 return -EINVAL; 868 869 if (mdata->security_state & CXL_PMEM_SEC_STATE_FROZEN) { 870 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 871 return -ENXIO; 872 } 873 874 if (!(mdata->security_state & CXL_PMEM_SEC_STATE_USER_PASS_SET)) { 875 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 876 return -ENXIO; 877 } 878 879 if (mdata->security_state & CXL_PMEM_SEC_STATE_USER_PLIMIT) { 880 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 881 return -ENXIO; 882 } 883 884 if (!(mdata->security_state & CXL_PMEM_SEC_STATE_LOCKED)) { 885 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 886 return -ENXIO; 887 } 888 889 if (memcmp(cmd->payload_in, mdata->user_pass, NVDIMM_PASSPHRASE_LEN)) { 890 if (++mdata->user_limit == PASS_TRY_LIMIT) 891 mdata->security_state |= CXL_PMEM_SEC_STATE_USER_PLIMIT; 892 cmd->return_code = CXL_MBOX_CMD_RC_PASSPHRASE; 893 return -ENXIO; 894 } 895 896 mdata->user_limit = 0; 897 mdata->security_state &= ~CXL_PMEM_SEC_STATE_LOCKED; 898 return 0; 899 } 900 901 static int mock_passphrase_secure_erase(struct cxl_mockmem_data *mdata, 902 struct cxl_mbox_cmd *cmd) 903 { 904 struct cxl_pass_erase *erase; 905 906 if (cmd->size_in != sizeof(*erase)) 907 return -EINVAL; 908 909 if (cmd->size_out != 0) 910 return -EINVAL; 911 912 erase = cmd->payload_in; 913 if (mdata->security_state & CXL_PMEM_SEC_STATE_FROZEN) { 914 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 915 return -ENXIO; 916 } 917 918 if (mdata->security_state & CXL_PMEM_SEC_STATE_USER_PLIMIT && 919 erase->type == CXL_PMEM_SEC_PASS_USER) { 920 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 921 return -ENXIO; 922 } 923 924 if (mdata->security_state & CXL_PMEM_SEC_STATE_MASTER_PLIMIT && 925 erase->type == CXL_PMEM_SEC_PASS_MASTER) { 926 cmd->return_code = CXL_MBOX_CMD_RC_SECURITY; 927 return -ENXIO; 928 } 929 930 switch (erase->type) { 931 case CXL_PMEM_SEC_PASS_MASTER: 932 /* 933 * The spec does not clearly define the behavior of the scenario 934 * where a master passphrase is passed in while the master 935 * passphrase is not set and user passphrase is not set. The 936 * code will take the assumption that it will behave the same 937 * as a CXL secure erase command without passphrase (0x4401). 938 */ 939 if (mdata->security_state & CXL_PMEM_SEC_STATE_MASTER_PASS_SET) { 940 if (memcmp(mdata->master_pass, erase->pass, 941 NVDIMM_PASSPHRASE_LEN)) { 942 master_plimit_check(mdata); 943 cmd->return_code = CXL_MBOX_CMD_RC_PASSPHRASE; 944 return -ENXIO; 945 } 946 mdata->master_limit = 0; 947 mdata->user_limit = 0; 948 mdata->security_state &= ~CXL_PMEM_SEC_STATE_USER_PASS_SET; 949 memset(mdata->user_pass, 0, NVDIMM_PASSPHRASE_LEN); 950 mdata->security_state &= ~CXL_PMEM_SEC_STATE_LOCKED; 951 } else { 952 /* 953 * CXL rev3 8.2.9.8.6.3 Disable Passphrase 954 * When master passphrase is disabled, the device shall 955 * return Invalid Input for the Passphrase Secure Erase 956 * command with master passphrase. 957 */ 958 return -EINVAL; 959 } 960 /* Scramble encryption keys so that data is effectively erased */ 961 break; 962 case CXL_PMEM_SEC_PASS_USER: 963 /* 964 * The spec does not clearly define the behavior of the scenario 965 * where a user passphrase is passed in while the user 966 * passphrase is not set. The code will take the assumption that 967 * it will behave the same as a CXL secure erase command without 968 * passphrase (0x4401). 969 */ 970 if (mdata->security_state & CXL_PMEM_SEC_STATE_USER_PASS_SET) { 971 if (memcmp(mdata->user_pass, erase->pass, 972 NVDIMM_PASSPHRASE_LEN)) { 973 user_plimit_check(mdata); 974 cmd->return_code = CXL_MBOX_CMD_RC_PASSPHRASE; 975 return -ENXIO; 976 } 977 mdata->user_limit = 0; 978 mdata->security_state &= ~CXL_PMEM_SEC_STATE_USER_PASS_SET; 979 memset(mdata->user_pass, 0, NVDIMM_PASSPHRASE_LEN); 980 } 981 982 /* 983 * CXL rev3 Table 8-118 984 * If user passphrase is not set or supported by device, current 985 * passphrase value is ignored. Will make the assumption that 986 * the operation will proceed as secure erase w/o passphrase 987 * since spec is not explicit. 988 */ 989 990 /* Scramble encryption keys so that data is effectively erased */ 991 break; 992 default: 993 return -EINVAL; 994 } 995 996 return 0; 997 } 998 999 static int mock_get_lsa(struct cxl_mockmem_data *mdata, 1000 struct cxl_mbox_cmd *cmd) 1001 { 1002 struct cxl_mbox_get_lsa *get_lsa = cmd->payload_in; 1003 void *lsa = mdata->lsa; 1004 u32 offset, length; 1005 1006 if (sizeof(*get_lsa) > cmd->size_in) 1007 return -EINVAL; 1008 offset = le32_to_cpu(get_lsa->offset); 1009 length = le32_to_cpu(get_lsa->length); 1010 if (offset + length > LSA_SIZE) 1011 return -EINVAL; 1012 if (length > cmd->size_out) 1013 return -EINVAL; 1014 1015 memcpy(cmd->payload_out, lsa + offset, length); 1016 return 0; 1017 } 1018 1019 static int mock_set_lsa(struct cxl_mockmem_data *mdata, 1020 struct cxl_mbox_cmd *cmd) 1021 { 1022 struct cxl_mbox_set_lsa *set_lsa = cmd->payload_in; 1023 void *lsa = mdata->lsa; 1024 u32 offset, length; 1025 1026 if (sizeof(*set_lsa) > cmd->size_in) 1027 return -EINVAL; 1028 offset = le32_to_cpu(set_lsa->offset); 1029 length = cmd->size_in - sizeof(*set_lsa); 1030 if (offset + length > LSA_SIZE) 1031 return -EINVAL; 1032 1033 memcpy(lsa + offset, &set_lsa->data[0], length); 1034 return 0; 1035 } 1036 1037 static int mock_health_info(struct cxl_mbox_cmd *cmd) 1038 { 1039 struct cxl_mbox_health_info health_info = { 1040 /* set flags for maint needed, perf degraded, hw replacement */ 1041 .health_status = 0x7, 1042 /* set media status to "All Data Lost" */ 1043 .media_status = 0x3, 1044 /* 1045 * set ext_status flags for: 1046 * ext_life_used: normal, 1047 * ext_temperature: critical, 1048 * ext_corrected_volatile: warning, 1049 * ext_corrected_persistent: normal, 1050 */ 1051 .ext_status = 0x18, 1052 .life_used = 15, 1053 .temperature = cpu_to_le16(25), 1054 .dirty_shutdowns = cpu_to_le32(10), 1055 .volatile_errors = cpu_to_le32(20), 1056 .pmem_errors = cpu_to_le32(30), 1057 }; 1058 1059 if (cmd->size_out < sizeof(health_info)) 1060 return -EINVAL; 1061 1062 memcpy(cmd->payload_out, &health_info, sizeof(health_info)); 1063 return 0; 1064 } 1065 1066 static struct mock_poison { 1067 struct cxl_dev_state *cxlds; 1068 u64 dpa; 1069 } mock_poison_list[MOCK_INJECT_TEST_MAX]; 1070 1071 static struct cxl_mbox_poison_out * 1072 cxl_get_injected_po(struct cxl_dev_state *cxlds, u64 offset, u64 length) 1073 { 1074 struct cxl_mbox_poison_out *po; 1075 int nr_records = 0; 1076 u64 dpa; 1077 1078 po = kzalloc(struct_size(po, record, poison_inject_dev_max), GFP_KERNEL); 1079 if (!po) 1080 return NULL; 1081 1082 for (int i = 0; i < MOCK_INJECT_TEST_MAX; i++) { 1083 if (mock_poison_list[i].cxlds != cxlds) 1084 continue; 1085 if (mock_poison_list[i].dpa < offset || 1086 mock_poison_list[i].dpa > offset + length - 1) 1087 continue; 1088 1089 dpa = mock_poison_list[i].dpa + CXL_POISON_SOURCE_INJECTED; 1090 po->record[nr_records].address = cpu_to_le64(dpa); 1091 po->record[nr_records].length = cpu_to_le32(1); 1092 nr_records++; 1093 if (nr_records == poison_inject_dev_max) 1094 break; 1095 } 1096 1097 /* Always return count, even when zero */ 1098 po->count = cpu_to_le16(nr_records); 1099 1100 return po; 1101 } 1102 1103 static int mock_get_poison(struct cxl_dev_state *cxlds, 1104 struct cxl_mbox_cmd *cmd) 1105 { 1106 struct cxl_mbox_poison_in *pi = cmd->payload_in; 1107 struct cxl_mbox_poison_out *po; 1108 u64 offset = le64_to_cpu(pi->offset); 1109 u64 length = le64_to_cpu(pi->length); 1110 int nr_records; 1111 1112 po = cxl_get_injected_po(cxlds, offset, length); 1113 if (!po) 1114 return -ENOMEM; 1115 nr_records = le16_to_cpu(po->count); 1116 memcpy(cmd->payload_out, po, struct_size(po, record, nr_records)); 1117 cmd->size_out = struct_size(po, record, nr_records); 1118 kfree(po); 1119 1120 return 0; 1121 } 1122 1123 static bool mock_poison_dev_max_injected(struct cxl_dev_state *cxlds) 1124 { 1125 int count = 0; 1126 1127 for (int i = 0; i < MOCK_INJECT_TEST_MAX; i++) { 1128 if (mock_poison_list[i].cxlds == cxlds) 1129 count++; 1130 } 1131 return (count >= poison_inject_dev_max); 1132 } 1133 1134 static bool mock_poison_add(struct cxl_dev_state *cxlds, u64 dpa) 1135 { 1136 if (mock_poison_dev_max_injected(cxlds)) { 1137 dev_dbg(cxlds->dev, 1138 "Device poison injection limit has been reached: %d\n", 1139 MOCK_INJECT_DEV_MAX); 1140 return false; 1141 } 1142 1143 for (int i = 0; i < MOCK_INJECT_TEST_MAX; i++) { 1144 if (!mock_poison_list[i].cxlds) { 1145 mock_poison_list[i].cxlds = cxlds; 1146 mock_poison_list[i].dpa = dpa; 1147 return true; 1148 } 1149 } 1150 dev_dbg(cxlds->dev, 1151 "Mock test poison injection limit has been reached: %d\n", 1152 MOCK_INJECT_TEST_MAX); 1153 1154 return false; 1155 } 1156 1157 static bool mock_poison_found(struct cxl_dev_state *cxlds, u64 dpa) 1158 { 1159 for (int i = 0; i < MOCK_INJECT_TEST_MAX; i++) { 1160 if (mock_poison_list[i].cxlds == cxlds && 1161 mock_poison_list[i].dpa == dpa) 1162 return true; 1163 } 1164 return false; 1165 } 1166 1167 static int mock_inject_poison(struct cxl_dev_state *cxlds, 1168 struct cxl_mbox_cmd *cmd) 1169 { 1170 struct cxl_mbox_inject_poison *pi = cmd->payload_in; 1171 u64 dpa = le64_to_cpu(pi->address); 1172 1173 if (mock_poison_found(cxlds, dpa)) { 1174 /* Not an error to inject poison if already poisoned */ 1175 dev_dbg(cxlds->dev, "DPA: 0x%llx already poisoned\n", dpa); 1176 return 0; 1177 } 1178 if (!mock_poison_add(cxlds, dpa)) 1179 return -ENXIO; 1180 1181 return 0; 1182 } 1183 1184 static bool mock_poison_del(struct cxl_dev_state *cxlds, u64 dpa) 1185 { 1186 for (int i = 0; i < MOCK_INJECT_TEST_MAX; i++) { 1187 if (mock_poison_list[i].cxlds == cxlds && 1188 mock_poison_list[i].dpa == dpa) { 1189 mock_poison_list[i].cxlds = NULL; 1190 return true; 1191 } 1192 } 1193 return false; 1194 } 1195 1196 static int mock_clear_poison(struct cxl_dev_state *cxlds, 1197 struct cxl_mbox_cmd *cmd) 1198 { 1199 struct cxl_mbox_clear_poison *pi = cmd->payload_in; 1200 u64 dpa = le64_to_cpu(pi->address); 1201 1202 /* 1203 * A real CXL device will write pi->write_data to the address 1204 * being cleared. In this mock, just delete this address from 1205 * the mock poison list. 1206 */ 1207 if (!mock_poison_del(cxlds, dpa)) 1208 dev_dbg(cxlds->dev, "DPA: 0x%llx not in poison list\n", dpa); 1209 1210 return 0; 1211 } 1212 1213 static bool mock_poison_list_empty(void) 1214 { 1215 for (int i = 0; i < MOCK_INJECT_TEST_MAX; i++) { 1216 if (mock_poison_list[i].cxlds) 1217 return false; 1218 } 1219 return true; 1220 } 1221 1222 static ssize_t poison_inject_max_show(struct device_driver *drv, char *buf) 1223 { 1224 return sysfs_emit(buf, "%u\n", poison_inject_dev_max); 1225 } 1226 1227 static ssize_t poison_inject_max_store(struct device_driver *drv, 1228 const char *buf, size_t len) 1229 { 1230 int val; 1231 1232 if (kstrtoint(buf, 0, &val) < 0) 1233 return -EINVAL; 1234 1235 if (!mock_poison_list_empty()) 1236 return -EBUSY; 1237 1238 if (val <= MOCK_INJECT_TEST_MAX) 1239 poison_inject_dev_max = val; 1240 else 1241 return -EINVAL; 1242 1243 return len; 1244 } 1245 1246 static DRIVER_ATTR_RW(poison_inject_max); 1247 1248 static struct attribute *cxl_mock_mem_core_attrs[] = { 1249 &driver_attr_poison_inject_max.attr, 1250 NULL 1251 }; 1252 ATTRIBUTE_GROUPS(cxl_mock_mem_core); 1253 1254 static int mock_fw_info(struct cxl_mockmem_data *mdata, 1255 struct cxl_mbox_cmd *cmd) 1256 { 1257 struct cxl_mbox_get_fw_info fw_info = { 1258 .num_slots = FW_SLOTS, 1259 .slot_info = (mdata->fw_slot & 0x7) | 1260 ((mdata->fw_staged & 0x7) << 3), 1261 .activation_cap = 0, 1262 }; 1263 1264 strcpy(fw_info.slot_1_revision, "cxl_test_fw_001"); 1265 strcpy(fw_info.slot_2_revision, "cxl_test_fw_002"); 1266 strcpy(fw_info.slot_3_revision, "cxl_test_fw_003"); 1267 strcpy(fw_info.slot_4_revision, ""); 1268 1269 if (cmd->size_out < sizeof(fw_info)) 1270 return -EINVAL; 1271 1272 memcpy(cmd->payload_out, &fw_info, sizeof(fw_info)); 1273 return 0; 1274 } 1275 1276 static int mock_transfer_fw(struct cxl_mockmem_data *mdata, 1277 struct cxl_mbox_cmd *cmd) 1278 { 1279 struct cxl_mbox_transfer_fw *transfer = cmd->payload_in; 1280 void *fw = mdata->fw; 1281 size_t offset, length; 1282 1283 offset = le32_to_cpu(transfer->offset) * CXL_FW_TRANSFER_ALIGNMENT; 1284 length = cmd->size_in - sizeof(*transfer); 1285 if (offset + length > FW_SIZE) 1286 return -EINVAL; 1287 1288 switch (transfer->action) { 1289 case CXL_FW_TRANSFER_ACTION_FULL: 1290 if (offset != 0) 1291 return -EINVAL; 1292 fallthrough; 1293 case CXL_FW_TRANSFER_ACTION_END: 1294 if (transfer->slot == 0 || transfer->slot > FW_SLOTS) 1295 return -EINVAL; 1296 mdata->fw_size = offset + length; 1297 break; 1298 case CXL_FW_TRANSFER_ACTION_INITIATE: 1299 case CXL_FW_TRANSFER_ACTION_CONTINUE: 1300 break; 1301 case CXL_FW_TRANSFER_ACTION_ABORT: 1302 return 0; 1303 default: 1304 return -EINVAL; 1305 } 1306 1307 memcpy(fw + offset, transfer->data, length); 1308 usleep_range(1500, 2000); 1309 return 0; 1310 } 1311 1312 static int mock_activate_fw(struct cxl_mockmem_data *mdata, 1313 struct cxl_mbox_cmd *cmd) 1314 { 1315 struct cxl_mbox_activate_fw *activate = cmd->payload_in; 1316 1317 if (activate->slot == 0 || activate->slot > FW_SLOTS) 1318 return -EINVAL; 1319 1320 switch (activate->action) { 1321 case CXL_FW_ACTIVATE_ONLINE: 1322 mdata->fw_slot = activate->slot; 1323 mdata->fw_staged = 0; 1324 return 0; 1325 case CXL_FW_ACTIVATE_OFFLINE: 1326 mdata->fw_staged = activate->slot; 1327 return 0; 1328 } 1329 1330 return -EINVAL; 1331 } 1332 1333 static int cxl_mock_mbox_send(struct cxl_memdev_state *mds, 1334 struct cxl_mbox_cmd *cmd) 1335 { 1336 struct cxl_dev_state *cxlds = &mds->cxlds; 1337 struct device *dev = cxlds->dev; 1338 struct cxl_mockmem_data *mdata = dev_get_drvdata(dev); 1339 int rc = -EIO; 1340 1341 switch (cmd->opcode) { 1342 case CXL_MBOX_OP_SET_TIMESTAMP: 1343 rc = mock_set_timestamp(cxlds, cmd); 1344 break; 1345 case CXL_MBOX_OP_GET_SUPPORTED_LOGS: 1346 rc = mock_gsl(cmd); 1347 break; 1348 case CXL_MBOX_OP_GET_LOG: 1349 rc = mock_get_log(mds, cmd); 1350 break; 1351 case CXL_MBOX_OP_IDENTIFY: 1352 if (cxlds->rcd) 1353 rc = mock_rcd_id(cmd); 1354 else 1355 rc = mock_id(cmd); 1356 break; 1357 case CXL_MBOX_OP_GET_LSA: 1358 rc = mock_get_lsa(mdata, cmd); 1359 break; 1360 case CXL_MBOX_OP_GET_PARTITION_INFO: 1361 rc = mock_partition_info(cmd); 1362 break; 1363 case CXL_MBOX_OP_GET_EVENT_RECORD: 1364 rc = mock_get_event(dev, cmd); 1365 break; 1366 case CXL_MBOX_OP_CLEAR_EVENT_RECORD: 1367 rc = mock_clear_event(dev, cmd); 1368 break; 1369 case CXL_MBOX_OP_SET_LSA: 1370 rc = mock_set_lsa(mdata, cmd); 1371 break; 1372 case CXL_MBOX_OP_GET_HEALTH_INFO: 1373 rc = mock_health_info(cmd); 1374 break; 1375 case CXL_MBOX_OP_SANITIZE: 1376 rc = mock_sanitize(mdata, cmd); 1377 break; 1378 case CXL_MBOX_OP_SECURE_ERASE: 1379 rc = mock_secure_erase(mdata, cmd); 1380 break; 1381 case CXL_MBOX_OP_GET_SECURITY_STATE: 1382 rc = mock_get_security_state(mdata, cmd); 1383 break; 1384 case CXL_MBOX_OP_SET_PASSPHRASE: 1385 rc = mock_set_passphrase(mdata, cmd); 1386 break; 1387 case CXL_MBOX_OP_DISABLE_PASSPHRASE: 1388 rc = mock_disable_passphrase(mdata, cmd); 1389 break; 1390 case CXL_MBOX_OP_FREEZE_SECURITY: 1391 rc = mock_freeze_security(mdata, cmd); 1392 break; 1393 case CXL_MBOX_OP_UNLOCK: 1394 rc = mock_unlock_security(mdata, cmd); 1395 break; 1396 case CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE: 1397 rc = mock_passphrase_secure_erase(mdata, cmd); 1398 break; 1399 case CXL_MBOX_OP_GET_POISON: 1400 rc = mock_get_poison(cxlds, cmd); 1401 break; 1402 case CXL_MBOX_OP_INJECT_POISON: 1403 rc = mock_inject_poison(cxlds, cmd); 1404 break; 1405 case CXL_MBOX_OP_CLEAR_POISON: 1406 rc = mock_clear_poison(cxlds, cmd); 1407 break; 1408 case CXL_MBOX_OP_GET_FW_INFO: 1409 rc = mock_fw_info(mdata, cmd); 1410 break; 1411 case CXL_MBOX_OP_TRANSFER_FW: 1412 rc = mock_transfer_fw(mdata, cmd); 1413 break; 1414 case CXL_MBOX_OP_ACTIVATE_FW: 1415 rc = mock_activate_fw(mdata, cmd); 1416 break; 1417 default: 1418 break; 1419 } 1420 1421 dev_dbg(dev, "opcode: %#x sz_in: %zd sz_out: %zd rc: %d\n", cmd->opcode, 1422 cmd->size_in, cmd->size_out, rc); 1423 1424 return rc; 1425 } 1426 1427 static void label_area_release(void *lsa) 1428 { 1429 vfree(lsa); 1430 } 1431 1432 static void fw_buf_release(void *buf) 1433 { 1434 vfree(buf); 1435 } 1436 1437 static bool is_rcd(struct platform_device *pdev) 1438 { 1439 const struct platform_device_id *id = platform_get_device_id(pdev); 1440 1441 return !!id->driver_data; 1442 } 1443 1444 static ssize_t event_trigger_store(struct device *dev, 1445 struct device_attribute *attr, 1446 const char *buf, size_t count) 1447 { 1448 cxl_mock_event_trigger(dev); 1449 return count; 1450 } 1451 static DEVICE_ATTR_WO(event_trigger); 1452 1453 static int cxl_mock_mem_probe(struct platform_device *pdev) 1454 { 1455 struct device *dev = &pdev->dev; 1456 struct cxl_memdev *cxlmd; 1457 struct cxl_memdev_state *mds; 1458 struct cxl_dev_state *cxlds; 1459 struct cxl_mockmem_data *mdata; 1460 int rc; 1461 1462 mdata = devm_kzalloc(dev, sizeof(*mdata), GFP_KERNEL); 1463 if (!mdata) 1464 return -ENOMEM; 1465 dev_set_drvdata(dev, mdata); 1466 1467 mdata->lsa = vmalloc(LSA_SIZE); 1468 if (!mdata->lsa) 1469 return -ENOMEM; 1470 mdata->fw = vmalloc(FW_SIZE); 1471 if (!mdata->fw) 1472 return -ENOMEM; 1473 mdata->fw_slot = 2; 1474 1475 rc = devm_add_action_or_reset(dev, label_area_release, mdata->lsa); 1476 if (rc) 1477 return rc; 1478 1479 rc = devm_add_action_or_reset(dev, fw_buf_release, mdata->fw); 1480 if (rc) 1481 return rc; 1482 1483 mds = cxl_memdev_state_create(dev); 1484 if (IS_ERR(mds)) 1485 return PTR_ERR(mds); 1486 1487 mdata->mds = mds; 1488 mds->mbox_send = cxl_mock_mbox_send; 1489 mds->payload_size = SZ_4K; 1490 mds->event.buf = (struct cxl_get_event_payload *) mdata->event_buf; 1491 INIT_DELAYED_WORK(&mds->security.poll_dwork, cxl_mockmem_sanitize_work); 1492 1493 cxlds = &mds->cxlds; 1494 cxlds->serial = pdev->id; 1495 if (is_rcd(pdev)) 1496 cxlds->rcd = true; 1497 1498 rc = cxl_enumerate_cmds(mds); 1499 if (rc) 1500 return rc; 1501 1502 rc = cxl_poison_state_init(mds); 1503 if (rc) 1504 return rc; 1505 1506 rc = cxl_set_timestamp(mds); 1507 if (rc) 1508 return rc; 1509 1510 cxlds->media_ready = true; 1511 rc = cxl_dev_state_identify(mds); 1512 if (rc) 1513 return rc; 1514 1515 rc = cxl_mem_create_range_info(mds); 1516 if (rc) 1517 return rc; 1518 1519 cxl_mock_add_event_logs(&mdata->mes); 1520 1521 cxlmd = devm_cxl_add_memdev(&pdev->dev, cxlds); 1522 if (IS_ERR(cxlmd)) 1523 return PTR_ERR(cxlmd); 1524 1525 rc = devm_cxl_setup_fw_upload(&pdev->dev, mds); 1526 if (rc) 1527 return rc; 1528 1529 rc = devm_cxl_sanitize_setup_notifier(&pdev->dev, cxlmd); 1530 if (rc) 1531 return rc; 1532 1533 cxl_mem_get_event_records(mds, CXLDEV_EVENT_STATUS_ALL); 1534 1535 return 0; 1536 } 1537 1538 static ssize_t security_lock_show(struct device *dev, 1539 struct device_attribute *attr, char *buf) 1540 { 1541 struct cxl_mockmem_data *mdata = dev_get_drvdata(dev); 1542 1543 return sysfs_emit(buf, "%u\n", 1544 !!(mdata->security_state & CXL_PMEM_SEC_STATE_LOCKED)); 1545 } 1546 1547 static ssize_t security_lock_store(struct device *dev, struct device_attribute *attr, 1548 const char *buf, size_t count) 1549 { 1550 struct cxl_mockmem_data *mdata = dev_get_drvdata(dev); 1551 u32 mask = CXL_PMEM_SEC_STATE_FROZEN | CXL_PMEM_SEC_STATE_USER_PLIMIT | 1552 CXL_PMEM_SEC_STATE_MASTER_PLIMIT; 1553 int val; 1554 1555 if (kstrtoint(buf, 0, &val) < 0) 1556 return -EINVAL; 1557 1558 if (val == 1) { 1559 if (!(mdata->security_state & CXL_PMEM_SEC_STATE_USER_PASS_SET)) 1560 return -ENXIO; 1561 mdata->security_state |= CXL_PMEM_SEC_STATE_LOCKED; 1562 mdata->security_state &= ~mask; 1563 } else { 1564 return -EINVAL; 1565 } 1566 return count; 1567 } 1568 1569 static DEVICE_ATTR_RW(security_lock); 1570 1571 static ssize_t fw_buf_checksum_show(struct device *dev, 1572 struct device_attribute *attr, char *buf) 1573 { 1574 struct cxl_mockmem_data *mdata = dev_get_drvdata(dev); 1575 u8 hash[SHA256_DIGEST_SIZE]; 1576 unsigned char *hstr, *hptr; 1577 struct sha256_state sctx; 1578 ssize_t written = 0; 1579 int i; 1580 1581 sha256_init(&sctx); 1582 sha256_update(&sctx, mdata->fw, mdata->fw_size); 1583 sha256_final(&sctx, hash); 1584 1585 hstr = kzalloc((SHA256_DIGEST_SIZE * 2) + 1, GFP_KERNEL); 1586 if (!hstr) 1587 return -ENOMEM; 1588 1589 hptr = hstr; 1590 for (i = 0; i < SHA256_DIGEST_SIZE; i++) 1591 hptr += sprintf(hptr, "%02x", hash[i]); 1592 1593 written = sysfs_emit(buf, "%s\n", hstr); 1594 1595 kfree(hstr); 1596 return written; 1597 } 1598 1599 static DEVICE_ATTR_RO(fw_buf_checksum); 1600 1601 static ssize_t sanitize_timeout_show(struct device *dev, 1602 struct device_attribute *attr, char *buf) 1603 { 1604 struct cxl_mockmem_data *mdata = dev_get_drvdata(dev); 1605 1606 return sysfs_emit(buf, "%lu\n", mdata->sanitize_timeout); 1607 } 1608 1609 static ssize_t sanitize_timeout_store(struct device *dev, 1610 struct device_attribute *attr, 1611 const char *buf, size_t count) 1612 { 1613 struct cxl_mockmem_data *mdata = dev_get_drvdata(dev); 1614 unsigned long val; 1615 int rc; 1616 1617 rc = kstrtoul(buf, 0, &val); 1618 if (rc) 1619 return rc; 1620 1621 mdata->sanitize_timeout = val; 1622 1623 return count; 1624 } 1625 1626 static DEVICE_ATTR_RW(sanitize_timeout); 1627 1628 static struct attribute *cxl_mock_mem_attrs[] = { 1629 &dev_attr_security_lock.attr, 1630 &dev_attr_event_trigger.attr, 1631 &dev_attr_fw_buf_checksum.attr, 1632 &dev_attr_sanitize_timeout.attr, 1633 NULL 1634 }; 1635 ATTRIBUTE_GROUPS(cxl_mock_mem); 1636 1637 static const struct platform_device_id cxl_mock_mem_ids[] = { 1638 { .name = "cxl_mem", 0 }, 1639 { .name = "cxl_rcd", 1 }, 1640 { }, 1641 }; 1642 MODULE_DEVICE_TABLE(platform, cxl_mock_mem_ids); 1643 1644 static struct platform_driver cxl_mock_mem_driver = { 1645 .probe = cxl_mock_mem_probe, 1646 .id_table = cxl_mock_mem_ids, 1647 .driver = { 1648 .name = KBUILD_MODNAME, 1649 .dev_groups = cxl_mock_mem_groups, 1650 .groups = cxl_mock_mem_core_groups, 1651 }, 1652 }; 1653 1654 module_platform_driver(cxl_mock_mem_driver); 1655 MODULE_LICENSE("GPL v2"); 1656 MODULE_IMPORT_NS(CXL); 1657