1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * turbostat -- show CPU frequency and C-state residency 4 * on modern Intel and AMD processors. 5 * 6 * Copyright (c) 2023 Intel Corporation. 7 * Len Brown <len.brown@intel.com> 8 */ 9 10 #define _GNU_SOURCE 11 #include MSRHEADER 12 #include INTEL_FAMILY_HEADER 13 #include <stdarg.h> 14 #include <stdio.h> 15 #include <err.h> 16 #include <unistd.h> 17 #include <sys/types.h> 18 #include <sys/wait.h> 19 #include <sys/stat.h> 20 #include <sys/select.h> 21 #include <sys/resource.h> 22 #include <fcntl.h> 23 #include <signal.h> 24 #include <sys/time.h> 25 #include <stdlib.h> 26 #include <getopt.h> 27 #include <dirent.h> 28 #include <string.h> 29 #include <ctype.h> 30 #include <sched.h> 31 #include <time.h> 32 #include <cpuid.h> 33 #include <sys/capability.h> 34 #include <errno.h> 35 #include <math.h> 36 #include <linux/perf_event.h> 37 #include <asm/unistd.h> 38 #include <stdbool.h> 39 40 #define UNUSED(x) (void)(x) 41 42 /* 43 * This list matches the column headers, except 44 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time 45 * 2. Core and CPU are moved to the end, we can't have strings that contain them 46 * matching on them for --show and --hide. 47 */ 48 49 /* 50 * buffer size used by sscanf() for added column names 51 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters 52 */ 53 #define NAME_BYTES 20 54 #define PATH_BYTES 128 55 56 enum counter_scope { SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE }; 57 enum counter_type { COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC }; 58 enum counter_format { FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT }; 59 60 struct msr_counter { 61 unsigned int msr_num; 62 char name[NAME_BYTES]; 63 char path[PATH_BYTES]; 64 unsigned int width; 65 enum counter_type type; 66 enum counter_format format; 67 struct msr_counter *next; 68 unsigned int flags; 69 #define FLAGS_HIDE (1 << 0) 70 #define FLAGS_SHOW (1 << 1) 71 #define SYSFS_PERCPU (1 << 1) 72 }; 73 74 struct msr_counter bic[] = { 75 { 0x0, "usec", "", 0, 0, 0, NULL, 0 }, 76 { 0x0, "Time_Of_Day_Seconds", "", 0, 0, 0, NULL, 0 }, 77 { 0x0, "Package", "", 0, 0, 0, NULL, 0 }, 78 { 0x0, "Node", "", 0, 0, 0, NULL, 0 }, 79 { 0x0, "Avg_MHz", "", 0, 0, 0, NULL, 0 }, 80 { 0x0, "Busy%", "", 0, 0, 0, NULL, 0 }, 81 { 0x0, "Bzy_MHz", "", 0, 0, 0, NULL, 0 }, 82 { 0x0, "TSC_MHz", "", 0, 0, 0, NULL, 0 }, 83 { 0x0, "IRQ", "", 0, 0, 0, NULL, 0 }, 84 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL, 0 }, 85 { 0x0, "sysfs", "", 0, 0, 0, NULL, 0 }, 86 { 0x0, "CPU%c1", "", 0, 0, 0, NULL, 0 }, 87 { 0x0, "CPU%c3", "", 0, 0, 0, NULL, 0 }, 88 { 0x0, "CPU%c6", "", 0, 0, 0, NULL, 0 }, 89 { 0x0, "CPU%c7", "", 0, 0, 0, NULL, 0 }, 90 { 0x0, "ThreadC", "", 0, 0, 0, NULL, 0 }, 91 { 0x0, "CoreTmp", "", 0, 0, 0, NULL, 0 }, 92 { 0x0, "CoreCnt", "", 0, 0, 0, NULL, 0 }, 93 { 0x0, "PkgTmp", "", 0, 0, 0, NULL, 0 }, 94 { 0x0, "GFX%rc6", "", 0, 0, 0, NULL, 0 }, 95 { 0x0, "GFXMHz", "", 0, 0, 0, NULL, 0 }, 96 { 0x0, "Pkg%pc2", "", 0, 0, 0, NULL, 0 }, 97 { 0x0, "Pkg%pc3", "", 0, 0, 0, NULL, 0 }, 98 { 0x0, "Pkg%pc6", "", 0, 0, 0, NULL, 0 }, 99 { 0x0, "Pkg%pc7", "", 0, 0, 0, NULL, 0 }, 100 { 0x0, "Pkg%pc8", "", 0, 0, 0, NULL, 0 }, 101 { 0x0, "Pkg%pc9", "", 0, 0, 0, NULL, 0 }, 102 { 0x0, "Pk%pc10", "", 0, 0, 0, NULL, 0 }, 103 { 0x0, "CPU%LPI", "", 0, 0, 0, NULL, 0 }, 104 { 0x0, "SYS%LPI", "", 0, 0, 0, NULL, 0 }, 105 { 0x0, "PkgWatt", "", 0, 0, 0, NULL, 0 }, 106 { 0x0, "CorWatt", "", 0, 0, 0, NULL, 0 }, 107 { 0x0, "GFXWatt", "", 0, 0, 0, NULL, 0 }, 108 { 0x0, "PkgCnt", "", 0, 0, 0, NULL, 0 }, 109 { 0x0, "RAMWatt", "", 0, 0, 0, NULL, 0 }, 110 { 0x0, "PKG_%", "", 0, 0, 0, NULL, 0 }, 111 { 0x0, "RAM_%", "", 0, 0, 0, NULL, 0 }, 112 { 0x0, "Pkg_J", "", 0, 0, 0, NULL, 0 }, 113 { 0x0, "Cor_J", "", 0, 0, 0, NULL, 0 }, 114 { 0x0, "GFX_J", "", 0, 0, 0, NULL, 0 }, 115 { 0x0, "RAM_J", "", 0, 0, 0, NULL, 0 }, 116 { 0x0, "Mod%c6", "", 0, 0, 0, NULL, 0 }, 117 { 0x0, "Totl%C0", "", 0, 0, 0, NULL, 0 }, 118 { 0x0, "Any%C0", "", 0, 0, 0, NULL, 0 }, 119 { 0x0, "GFX%C0", "", 0, 0, 0, NULL, 0 }, 120 { 0x0, "CPUGFX%", "", 0, 0, 0, NULL, 0 }, 121 { 0x0, "Core", "", 0, 0, 0, NULL, 0 }, 122 { 0x0, "CPU", "", 0, 0, 0, NULL, 0 }, 123 { 0x0, "APIC", "", 0, 0, 0, NULL, 0 }, 124 { 0x0, "X2APIC", "", 0, 0, 0, NULL, 0 }, 125 { 0x0, "Die", "", 0, 0, 0, NULL, 0 }, 126 { 0x0, "GFXAMHz", "", 0, 0, 0, NULL, 0 }, 127 { 0x0, "IPC", "", 0, 0, 0, NULL, 0 }, 128 { 0x0, "CoreThr", "", 0, 0, 0, NULL, 0 }, 129 { 0x0, "UncMHz", "", 0, 0, 0, NULL, 0 }, 130 }; 131 132 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter)) 133 #define BIC_USEC (1ULL << 0) 134 #define BIC_TOD (1ULL << 1) 135 #define BIC_Package (1ULL << 2) 136 #define BIC_Node (1ULL << 3) 137 #define BIC_Avg_MHz (1ULL << 4) 138 #define BIC_Busy (1ULL << 5) 139 #define BIC_Bzy_MHz (1ULL << 6) 140 #define BIC_TSC_MHz (1ULL << 7) 141 #define BIC_IRQ (1ULL << 8) 142 #define BIC_SMI (1ULL << 9) 143 #define BIC_sysfs (1ULL << 10) 144 #define BIC_CPU_c1 (1ULL << 11) 145 #define BIC_CPU_c3 (1ULL << 12) 146 #define BIC_CPU_c6 (1ULL << 13) 147 #define BIC_CPU_c7 (1ULL << 14) 148 #define BIC_ThreadC (1ULL << 15) 149 #define BIC_CoreTmp (1ULL << 16) 150 #define BIC_CoreCnt (1ULL << 17) 151 #define BIC_PkgTmp (1ULL << 18) 152 #define BIC_GFX_rc6 (1ULL << 19) 153 #define BIC_GFXMHz (1ULL << 20) 154 #define BIC_Pkgpc2 (1ULL << 21) 155 #define BIC_Pkgpc3 (1ULL << 22) 156 #define BIC_Pkgpc6 (1ULL << 23) 157 #define BIC_Pkgpc7 (1ULL << 24) 158 #define BIC_Pkgpc8 (1ULL << 25) 159 #define BIC_Pkgpc9 (1ULL << 26) 160 #define BIC_Pkgpc10 (1ULL << 27) 161 #define BIC_CPU_LPI (1ULL << 28) 162 #define BIC_SYS_LPI (1ULL << 29) 163 #define BIC_PkgWatt (1ULL << 30) 164 #define BIC_CorWatt (1ULL << 31) 165 #define BIC_GFXWatt (1ULL << 32) 166 #define BIC_PkgCnt (1ULL << 33) 167 #define BIC_RAMWatt (1ULL << 34) 168 #define BIC_PKG__ (1ULL << 35) 169 #define BIC_RAM__ (1ULL << 36) 170 #define BIC_Pkg_J (1ULL << 37) 171 #define BIC_Cor_J (1ULL << 38) 172 #define BIC_GFX_J (1ULL << 39) 173 #define BIC_RAM_J (1ULL << 40) 174 #define BIC_Mod_c6 (1ULL << 41) 175 #define BIC_Totl_c0 (1ULL << 42) 176 #define BIC_Any_c0 (1ULL << 43) 177 #define BIC_GFX_c0 (1ULL << 44) 178 #define BIC_CPUGFX (1ULL << 45) 179 #define BIC_Core (1ULL << 46) 180 #define BIC_CPU (1ULL << 47) 181 #define BIC_APIC (1ULL << 48) 182 #define BIC_X2APIC (1ULL << 49) 183 #define BIC_Die (1ULL << 50) 184 #define BIC_GFXACTMHz (1ULL << 51) 185 #define BIC_IPC (1ULL << 52) 186 #define BIC_CORE_THROT_CNT (1ULL << 53) 187 #define BIC_UNCORE_MHZ (1ULL << 54) 188 189 #define BIC_TOPOLOGY (BIC_Package | BIC_Node | BIC_CoreCnt | BIC_PkgCnt | BIC_Core | BIC_CPU | BIC_Die ) 190 #define BIC_THERMAL_PWR ( BIC_CoreTmp | BIC_PkgTmp | BIC_PkgWatt | BIC_CorWatt | BIC_GFXWatt | BIC_RAMWatt | BIC_PKG__ | BIC_RAM__) 191 #define BIC_FREQUENCY ( BIC_Avg_MHz | BIC_Busy | BIC_Bzy_MHz | BIC_TSC_MHz | BIC_GFXMHz | BIC_GFXACTMHz | BIC_UNCORE_MHZ) 192 #define BIC_IDLE ( BIC_sysfs | BIC_CPU_c1 | BIC_CPU_c3 | BIC_CPU_c6 | BIC_CPU_c7 | BIC_GFX_rc6 | BIC_Pkgpc2 | BIC_Pkgpc3 | BIC_Pkgpc6 | BIC_Pkgpc7 | BIC_Pkgpc8 | BIC_Pkgpc9 | BIC_Pkgpc10 | BIC_CPU_LPI | BIC_SYS_LPI | BIC_Mod_c6 | BIC_Totl_c0 | BIC_Any_c0 | BIC_GFX_c0 | BIC_CPUGFX) 193 #define BIC_OTHER ( BIC_IRQ | BIC_SMI | BIC_ThreadC | BIC_CoreTmp | BIC_IPC) 194 195 #define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC) 196 197 unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT); 198 unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC; 199 200 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME) 201 #define DO_BIC_READ(COUNTER_NAME) (bic_present & COUNTER_NAME) 202 #define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME) 203 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT) 204 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT) 205 #define BIC_IS_ENABLED(COUNTER_BIT) (bic_enabled & COUNTER_BIT) 206 207 char *proc_stat = "/proc/stat"; 208 FILE *outf; 209 int *fd_percpu; 210 int *fd_instr_count_percpu; 211 struct timeval interval_tv = { 5, 0 }; 212 struct timespec interval_ts = { 5, 0 }; 213 214 unsigned int num_iterations; 215 unsigned int header_iterations; 216 unsigned int debug; 217 unsigned int quiet; 218 unsigned int shown; 219 unsigned int sums_need_wide_columns; 220 unsigned int rapl_joules; 221 unsigned int summary_only; 222 unsigned int list_header_only; 223 unsigned int dump_only; 224 unsigned int has_aperf; 225 unsigned int has_epb; 226 unsigned int has_turbo; 227 unsigned int is_hybrid; 228 unsigned int units = 1000000; /* MHz etc */ 229 unsigned int genuine_intel; 230 unsigned int authentic_amd; 231 unsigned int hygon_genuine; 232 unsigned int max_level, max_extended_level; 233 unsigned int has_invariant_tsc; 234 unsigned int aperf_mperf_multiplier = 1; 235 double bclk; 236 double base_hz; 237 unsigned int has_base_hz; 238 double tsc_tweak = 1.0; 239 unsigned int show_pkg_only; 240 unsigned int show_core_only; 241 char *output_buffer, *outp; 242 unsigned int do_dts; 243 unsigned int do_ptm; 244 unsigned int do_ipc; 245 unsigned long long gfx_cur_rc6_ms; 246 unsigned long long cpuidle_cur_cpu_lpi_us; 247 unsigned long long cpuidle_cur_sys_lpi_us; 248 unsigned int gfx_cur_mhz; 249 unsigned int gfx_act_mhz; 250 unsigned int tj_max; 251 unsigned int tj_max_override; 252 double rapl_power_units, rapl_time_units; 253 double rapl_dram_energy_units, rapl_energy_units; 254 double rapl_joule_counter_range; 255 unsigned int crystal_hz; 256 unsigned long long tsc_hz; 257 int base_cpu; 258 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ 259 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ 260 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ 261 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ 262 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ 263 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ 264 unsigned int first_counter_read = 1; 265 int ignore_stdin; 266 267 int get_msr(int cpu, off_t offset, unsigned long long *msr); 268 269 /* Model specific support Start */ 270 271 /* List of features that may diverge among different platforms */ 272 struct platform_features { 273 bool has_msr_misc_feature_control; /* MSR_MISC_FEATURE_CONTROL */ 274 bool has_msr_misc_pwr_mgmt; /* MSR_MISC_PWR_MGMT */ 275 bool has_nhm_msrs; /* MSR_PLATFORM_INFO, MSR_IA32_TEMPERATURE_TARGET, MSR_SMI_COUNT, MSR_PKG_CST_CONFIG_CONTROL, MSR_IA32_POWER_CTL, TRL MSRs */ 276 bool has_config_tdp; /* MSR_CONFIG_TDP_NOMINAL/LEVEL_1/LEVEL_2/CONTROL, MSR_TURBO_ACTIVATION_RATIO */ 277 int bclk_freq; /* CPU base clock */ 278 int crystal_freq; /* Crystal clock to use when not available from CPUID.15 */ 279 int supported_cstates; /* Core cstates and Package cstates supported */ 280 int cst_limit; /* MSR_PKG_CST_CONFIG_CONTROL */ 281 bool has_cst_auto_convension; /* AUTOMATIC_CSTATE_CONVERSION bit in MSR_PKG_CST_CONFIG_CONTROL */ 282 bool has_irtl_msrs; /* MSR_PKGC3/PKGC6/PKGC7/PKGC8/PKGC9/PKGC10_IRTL */ 283 bool has_msr_core_c1_res; /* MSR_CORE_C1_RES */ 284 bool has_msr_module_c6_res_ms; /* MSR_MODULE_C6_RES_MS */ 285 bool has_msr_c6_demotion_policy_config; /* MSR_CC6_DEMOTION_POLICY_CONFIG/MSR_MC6_DEMOTION_POLICY_CONFIG */ 286 bool has_msr_atom_pkg_c6_residency; /* MSR_ATOM_PKG_C6_RESIDENCY */ 287 bool has_msr_knl_core_c6_residency; /* MSR_KNL_CORE_C6_RESIDENCY */ 288 bool has_ext_cst_msrs; /* MSR_PKG_WEIGHTED_CORE_C0_RES/MSR_PKG_ANY_CORE_C0_RES/MSR_PKG_ANY_GFXE_C0_RES/MSR_PKG_BOTH_CORE_GFXE_C0_RES */ 289 bool has_cst_prewake_bit; /* Cstate prewake bit in MSR_IA32_POWER_CTL */ 290 int trl_msrs; /* MSR_TURBO_RATIO_LIMIT/LIMIT1/LIMIT2/SECONDARY, Atom TRL MSRs */ 291 int plr_msrs; /* MSR_CORE/GFX/RING_PERF_LIMIT_REASONS */ 292 int rapl_msrs; /* RAPL PKG/DRAM/CORE/GFX MSRs, AMD RAPL MSRs */ 293 bool has_per_core_rapl; /* Indicates cores energy collection is per-core, not per-package. AMD specific for now */ 294 bool has_rapl_divisor; /* Divisor for Energy unit raw value from MSR_RAPL_POWER_UNIT */ 295 bool has_fixed_rapl_unit; /* Fixed Energy Unit used for DRAM RAPL Domain */ 296 int rapl_quirk_tdp; /* Hardcoded TDP value when cannot be retrieved from hardware */ 297 int tcc_offset_bits; /* TCC Offset bits in MSR_IA32_TEMPERATURE_TARGET */ 298 bool enable_tsc_tweak; /* Use CPU Base freq instead of TSC freq for aperf/mperf counter */ 299 bool need_perf_multiplier; /* mperf/aperf multiplier */ 300 }; 301 302 struct platform_data { 303 unsigned int model; 304 const struct platform_features *features; 305 }; 306 307 /* For BCLK */ 308 enum bclk_freq { 309 BCLK_100MHZ = 1, 310 BCLK_133MHZ, 311 BCLK_SLV, 312 }; 313 314 #define SLM_BCLK_FREQS 5 315 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0 }; 316 317 double slm_bclk(void) 318 { 319 unsigned long long msr = 3; 320 unsigned int i; 321 double freq; 322 323 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) 324 fprintf(outf, "SLM BCLK: unknown\n"); 325 326 i = msr & 0xf; 327 if (i >= SLM_BCLK_FREQS) { 328 fprintf(outf, "SLM BCLK[%d] invalid\n", i); 329 i = 3; 330 } 331 freq = slm_freq_table[i]; 332 333 if (!quiet) 334 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); 335 336 return freq; 337 } 338 339 /* For Package cstate limit */ 340 enum package_cstate_limit { 341 CST_LIMIT_NHM = 1, 342 CST_LIMIT_SNB, 343 CST_LIMIT_HSW, 344 CST_LIMIT_SKX, 345 CST_LIMIT_ICX, 346 CST_LIMIT_SLV, 347 CST_LIMIT_AMT, 348 CST_LIMIT_KNL, 349 CST_LIMIT_GMT, 350 }; 351 352 /* For Turbo Ratio Limit MSRs */ 353 enum turbo_ratio_limit_msrs { 354 TRL_BASE = BIT(0), 355 TRL_LIMIT1 = BIT(1), 356 TRL_LIMIT2 = BIT(2), 357 TRL_ATOM = BIT(3), 358 TRL_KNL = BIT(4), 359 TRL_CORECOUNT = BIT(5), 360 }; 361 362 /* For Perf Limit Reason MSRs */ 363 enum perf_limit_reason_msrs { 364 PLR_CORE = BIT(0), 365 PLR_GFX = BIT(1), 366 PLR_RING = BIT(2), 367 }; 368 369 /* For RAPL MSRs */ 370 enum rapl_msrs { 371 RAPL_PKG_POWER_LIMIT = BIT(0), /* 0x610 MSR_PKG_POWER_LIMIT */ 372 RAPL_PKG_ENERGY_STATUS = BIT(1), /* 0x611 MSR_PKG_ENERGY_STATUS */ 373 RAPL_PKG_PERF_STATUS = BIT(2), /* 0x613 MSR_PKG_PERF_STATUS */ 374 RAPL_PKG_POWER_INFO = BIT(3), /* 0x614 MSR_PKG_POWER_INFO */ 375 RAPL_DRAM_POWER_LIMIT = BIT(4), /* 0x618 MSR_DRAM_POWER_LIMIT */ 376 RAPL_DRAM_ENERGY_STATUS = BIT(5), /* 0x619 MSR_DRAM_ENERGY_STATUS */ 377 RAPL_DRAM_PERF_STATUS = BIT(6), /* 0x61b MSR_DRAM_PERF_STATUS */ 378 RAPL_DRAM_POWER_INFO = BIT(7), /* 0x61c MSR_DRAM_POWER_INFO */ 379 RAPL_CORE_POWER_LIMIT = BIT(8), /* 0x638 MSR_PP0_POWER_LIMIT */ 380 RAPL_CORE_ENERGY_STATUS = BIT(9), /* 0x639 MSR_PP0_ENERGY_STATUS */ 381 RAPL_CORE_POLICY = BIT(10), /* 0x63a MSR_PP0_POLICY */ 382 RAPL_GFX_POWER_LIMIT = BIT(11), /* 0x640 MSR_PP1_POWER_LIMIT */ 383 RAPL_GFX_ENERGY_STATUS = BIT(12), /* 0x641 MSR_PP1_ENERGY_STATUS */ 384 RAPL_GFX_POLICY = BIT(13), /* 0x642 MSR_PP1_POLICY */ 385 RAPL_AMD_PWR_UNIT = BIT(14), /* 0xc0010299 MSR_AMD_RAPL_POWER_UNIT */ 386 RAPL_AMD_CORE_ENERGY_STAT = BIT(15), /* 0xc001029a MSR_AMD_CORE_ENERGY_STATUS */ 387 RAPL_AMD_PKG_ENERGY_STAT = BIT(16), /* 0xc001029b MSR_AMD_PKG_ENERGY_STATUS */ 388 }; 389 390 #define RAPL_PKG (RAPL_PKG_ENERGY_STATUS | RAPL_PKG_POWER_LIMIT) 391 #define RAPL_DRAM (RAPL_DRAM_ENERGY_STATUS | RAPL_DRAM_POWER_LIMIT) 392 #define RAPL_CORE (RAPL_CORE_ENERGY_STATUS | RAPL_CORE_POWER_LIMIT) 393 #define RAPL_GFX (RAPL_GFX_POWER_LIMIT | RAPL_GFX_ENERGY_STATUS) 394 395 #define RAPL_PKG_ALL (RAPL_PKG | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO) 396 #define RAPL_DRAM_ALL (RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_DRAM_POWER_INFO) 397 #define RAPL_CORE_ALL (RAPL_CORE | RAPL_CORE_POLICY) 398 #define RAPL_GFX_ALL (RAPL_GFX | RAPL_GFX_POLIGY) 399 400 #define RAPL_AMD_F17H (RAPL_AMD_PWR_UNIT | RAPL_AMD_CORE_ENERGY_STAT | RAPL_AMD_PKG_ENERGY_STAT) 401 402 /* For Cstates */ 403 enum cstates { 404 CC1 = BIT(0), 405 CC3 = BIT(1), 406 CC6 = BIT(2), 407 CC7 = BIT(3), 408 PC2 = BIT(4), 409 PC3 = BIT(5), 410 PC6 = BIT(6), 411 PC7 = BIT(7), 412 PC8 = BIT(8), 413 PC9 = BIT(9), 414 PC10 = BIT(10), 415 }; 416 417 static const struct platform_features nhm_features = { 418 .has_msr_misc_pwr_mgmt = 1, 419 .has_nhm_msrs = 1, 420 .bclk_freq = BCLK_133MHZ, 421 .supported_cstates = CC1 | CC3 | CC6 | PC3 | PC6, 422 .cst_limit = CST_LIMIT_NHM, 423 .trl_msrs = TRL_BASE, 424 }; 425 426 static const struct platform_features nhx_features = { 427 .has_msr_misc_pwr_mgmt = 1, 428 .has_nhm_msrs = 1, 429 .bclk_freq = BCLK_133MHZ, 430 .supported_cstates = CC1 | CC3 | CC6 | PC3 | PC6, 431 .cst_limit = CST_LIMIT_NHM, 432 }; 433 434 static const struct platform_features snb_features = { 435 .has_msr_misc_feature_control = 1, 436 .has_msr_misc_pwr_mgmt = 1, 437 .has_nhm_msrs = 1, 438 .bclk_freq = BCLK_100MHZ, 439 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7, 440 .cst_limit = CST_LIMIT_SNB, 441 .has_irtl_msrs = 1, 442 .trl_msrs = TRL_BASE, 443 .rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO, 444 }; 445 446 static const struct platform_features snx_features = { 447 .has_msr_misc_feature_control = 1, 448 .has_msr_misc_pwr_mgmt = 1, 449 .has_nhm_msrs = 1, 450 .bclk_freq = BCLK_100MHZ, 451 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7, 452 .cst_limit = CST_LIMIT_SNB, 453 .has_irtl_msrs = 1, 454 .trl_msrs = TRL_BASE, 455 .rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM_ALL, 456 }; 457 458 static const struct platform_features ivb_features = { 459 .has_msr_misc_feature_control = 1, 460 .has_msr_misc_pwr_mgmt = 1, 461 .has_nhm_msrs = 1, 462 .has_config_tdp = 1, 463 .bclk_freq = BCLK_100MHZ, 464 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7, 465 .cst_limit = CST_LIMIT_SNB, 466 .has_irtl_msrs = 1, 467 .trl_msrs = TRL_BASE, 468 .rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO, 469 }; 470 471 static const struct platform_features ivx_features = { 472 .has_msr_misc_feature_control = 1, 473 .has_msr_misc_pwr_mgmt = 1, 474 .has_nhm_msrs = 1, 475 .bclk_freq = BCLK_100MHZ, 476 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7, 477 .cst_limit = CST_LIMIT_SNB, 478 .has_irtl_msrs = 1, 479 .trl_msrs = TRL_BASE | TRL_LIMIT1, 480 .rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM_ALL, 481 }; 482 483 static const struct platform_features hsw_features = { 484 .has_msr_misc_feature_control = 1, 485 .has_msr_misc_pwr_mgmt = 1, 486 .has_nhm_msrs = 1, 487 .has_config_tdp = 1, 488 .bclk_freq = BCLK_100MHZ, 489 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7, 490 .cst_limit = CST_LIMIT_HSW, 491 .has_irtl_msrs = 1, 492 .trl_msrs = TRL_BASE, 493 .plr_msrs = PLR_CORE | PLR_GFX | PLR_RING, 494 .rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO, 495 }; 496 497 static const struct platform_features hsx_features = { 498 .has_msr_misc_feature_control = 1, 499 .has_msr_misc_pwr_mgmt = 1, 500 .has_nhm_msrs = 1, 501 .has_config_tdp = 1, 502 .bclk_freq = BCLK_100MHZ, 503 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7, 504 .cst_limit = CST_LIMIT_HSW, 505 .has_irtl_msrs = 1, 506 .trl_msrs = TRL_BASE | TRL_LIMIT1 | TRL_LIMIT2, 507 .plr_msrs = PLR_CORE | PLR_RING, 508 .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL, 509 .has_fixed_rapl_unit = 1, 510 }; 511 512 static const struct platform_features hswl_features = { 513 .has_msr_misc_feature_control = 1, 514 .has_msr_misc_pwr_mgmt = 1, 515 .has_nhm_msrs = 1, 516 .has_config_tdp = 1, 517 .bclk_freq = BCLK_100MHZ, 518 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7 | PC8 | PC9 | PC10, 519 .cst_limit = CST_LIMIT_HSW, 520 .has_irtl_msrs = 1, 521 .trl_msrs = TRL_BASE, 522 .plr_msrs = PLR_CORE | PLR_GFX | PLR_RING, 523 .rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO, 524 }; 525 526 static const struct platform_features hswg_features = { 527 .has_msr_misc_feature_control = 1, 528 .has_msr_misc_pwr_mgmt = 1, 529 .has_nhm_msrs = 1, 530 .has_config_tdp = 1, 531 .bclk_freq = BCLK_100MHZ, 532 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7, 533 .cst_limit = CST_LIMIT_HSW, 534 .has_irtl_msrs = 1, 535 .trl_msrs = TRL_BASE, 536 .plr_msrs = PLR_CORE | PLR_GFX | PLR_RING, 537 .rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO, 538 }; 539 540 static const struct platform_features bdw_features = { 541 .has_msr_misc_feature_control = 1, 542 .has_msr_misc_pwr_mgmt = 1, 543 .has_nhm_msrs = 1, 544 .has_config_tdp = 1, 545 .bclk_freq = BCLK_100MHZ, 546 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7 | PC8 | PC9 | PC10, 547 .cst_limit = CST_LIMIT_HSW, 548 .has_irtl_msrs = 1, 549 .trl_msrs = TRL_BASE, 550 .rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO, 551 }; 552 553 static const struct platform_features bdwg_features = { 554 .has_msr_misc_feature_control = 1, 555 .has_msr_misc_pwr_mgmt = 1, 556 .has_nhm_msrs = 1, 557 .has_config_tdp = 1, 558 .bclk_freq = BCLK_100MHZ, 559 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7, 560 .cst_limit = CST_LIMIT_HSW, 561 .has_irtl_msrs = 1, 562 .trl_msrs = TRL_BASE, 563 .rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO, 564 }; 565 566 static const struct platform_features bdx_features = { 567 .has_msr_misc_feature_control = 1, 568 .has_msr_misc_pwr_mgmt = 1, 569 .has_nhm_msrs = 1, 570 .has_config_tdp = 1, 571 .bclk_freq = BCLK_100MHZ, 572 .supported_cstates = CC1 | CC3 | CC6 | PC2 | PC3 | PC6, 573 .cst_limit = CST_LIMIT_HSW, 574 .has_irtl_msrs = 1, 575 .has_cst_auto_convension = 1, 576 .trl_msrs = TRL_BASE, 577 .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL, 578 .has_fixed_rapl_unit = 1, 579 }; 580 581 static const struct platform_features skl_features = { 582 .has_msr_misc_feature_control = 1, 583 .has_msr_misc_pwr_mgmt = 1, 584 .has_nhm_msrs = 1, 585 .has_config_tdp = 1, 586 .bclk_freq = BCLK_100MHZ, 587 .crystal_freq = 24000000, 588 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7 | PC8 | PC9 | PC10, 589 .cst_limit = CST_LIMIT_HSW, 590 .has_irtl_msrs = 1, 591 .has_ext_cst_msrs = 1, 592 .trl_msrs = TRL_BASE, 593 .tcc_offset_bits = 6, 594 .rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_GFX, 595 .enable_tsc_tweak = 1, 596 }; 597 598 static const struct platform_features cnl_features = { 599 .has_msr_misc_feature_control = 1, 600 .has_msr_misc_pwr_mgmt = 1, 601 .has_nhm_msrs = 1, 602 .has_config_tdp = 1, 603 .bclk_freq = BCLK_100MHZ, 604 .supported_cstates = CC1 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7 | PC8 | PC9 | PC10, 605 .cst_limit = CST_LIMIT_HSW, 606 .has_irtl_msrs = 1, 607 .has_msr_core_c1_res = 1, 608 .has_ext_cst_msrs = 1, 609 .trl_msrs = TRL_BASE, 610 .tcc_offset_bits = 6, 611 .rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_GFX, 612 .enable_tsc_tweak = 1, 613 }; 614 615 static const struct platform_features adl_features = { 616 .has_msr_misc_feature_control = 1, 617 .has_msr_misc_pwr_mgmt = 1, 618 .has_nhm_msrs = 1, 619 .has_config_tdp = 1, 620 .bclk_freq = BCLK_100MHZ, 621 .supported_cstates = CC1 | CC6 | CC7 | PC2 | PC3 | PC6 | PC8 | PC10, 622 .cst_limit = CST_LIMIT_HSW, 623 .has_irtl_msrs = 1, 624 .has_msr_core_c1_res = 1, 625 .has_ext_cst_msrs = 1, 626 .trl_msrs = TRL_BASE, 627 .tcc_offset_bits = 6, 628 .rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_GFX, 629 .enable_tsc_tweak = 1, 630 }; 631 632 static const struct platform_features skx_features = { 633 .has_msr_misc_feature_control = 1, 634 .has_msr_misc_pwr_mgmt = 1, 635 .has_nhm_msrs = 1, 636 .has_config_tdp = 1, 637 .bclk_freq = BCLK_100MHZ, 638 .supported_cstates = CC1 | CC6 | PC2 | PC6, 639 .cst_limit = CST_LIMIT_SKX, 640 .has_irtl_msrs = 1, 641 .has_cst_auto_convension = 1, 642 .trl_msrs = TRL_BASE | TRL_CORECOUNT, 643 .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL, 644 .has_fixed_rapl_unit = 1, 645 }; 646 647 static const struct platform_features icx_features = { 648 .has_msr_misc_feature_control = 1, 649 .has_msr_misc_pwr_mgmt = 1, 650 .has_nhm_msrs = 1, 651 .has_config_tdp = 1, 652 .bclk_freq = BCLK_100MHZ, 653 .supported_cstates = CC1 | CC6 | PC2 | PC6, 654 .cst_limit = CST_LIMIT_ICX, 655 .has_irtl_msrs = 1, 656 .has_cst_prewake_bit = 1, 657 .trl_msrs = TRL_BASE | TRL_CORECOUNT, 658 .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL, 659 .has_fixed_rapl_unit = 1, 660 }; 661 662 static const struct platform_features spr_features = { 663 .has_msr_misc_feature_control = 1, 664 .has_msr_misc_pwr_mgmt = 1, 665 .has_nhm_msrs = 1, 666 .has_config_tdp = 1, 667 .bclk_freq = BCLK_100MHZ, 668 .supported_cstates = CC1 | CC6 | PC2 | PC6, 669 .cst_limit = CST_LIMIT_SKX, 670 .has_msr_core_c1_res = 1, 671 .has_irtl_msrs = 1, 672 .has_cst_prewake_bit = 1, 673 .trl_msrs = TRL_BASE | TRL_CORECOUNT, 674 .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL, 675 }; 676 677 static const struct platform_features srf_features = { 678 .has_msr_misc_feature_control = 1, 679 .has_msr_misc_pwr_mgmt = 1, 680 .has_nhm_msrs = 1, 681 .has_config_tdp = 1, 682 .bclk_freq = BCLK_100MHZ, 683 .supported_cstates = CC1 | CC6 | PC2 | PC6, 684 .cst_limit = CST_LIMIT_SKX, 685 .has_msr_core_c1_res = 1, 686 .has_msr_module_c6_res_ms = 1, 687 .has_irtl_msrs = 1, 688 .has_cst_prewake_bit = 1, 689 .trl_msrs = TRL_BASE | TRL_CORECOUNT, 690 .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL, 691 }; 692 693 static const struct platform_features grr_features = { 694 .has_msr_misc_feature_control = 1, 695 .has_msr_misc_pwr_mgmt = 1, 696 .has_nhm_msrs = 1, 697 .has_config_tdp = 1, 698 .bclk_freq = BCLK_100MHZ, 699 .supported_cstates = CC1 | CC6, 700 .cst_limit = CST_LIMIT_SKX, 701 .has_msr_core_c1_res = 1, 702 .has_msr_module_c6_res_ms = 1, 703 .has_irtl_msrs = 1, 704 .has_cst_prewake_bit = 1, 705 .trl_msrs = TRL_BASE | TRL_CORECOUNT, 706 .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL, 707 }; 708 709 static const struct platform_features slv_features = { 710 .has_nhm_msrs = 1, 711 .bclk_freq = BCLK_SLV, 712 .supported_cstates = CC1 | CC6 | PC6, 713 .cst_limit = CST_LIMIT_SLV, 714 .has_msr_core_c1_res = 1, 715 .has_msr_module_c6_res_ms = 1, 716 .has_msr_c6_demotion_policy_config = 1, 717 .has_msr_atom_pkg_c6_residency = 1, 718 .trl_msrs = TRL_ATOM, 719 .rapl_msrs = RAPL_PKG | RAPL_CORE, 720 .has_rapl_divisor = 1, 721 .rapl_quirk_tdp = 30, 722 }; 723 724 static const struct platform_features slvd_features = { 725 .has_msr_misc_pwr_mgmt = 1, 726 .has_nhm_msrs = 1, 727 .bclk_freq = BCLK_SLV, 728 .supported_cstates = CC1 | CC6 | PC3 | PC6, 729 .cst_limit = CST_LIMIT_SLV, 730 .has_msr_atom_pkg_c6_residency = 1, 731 .trl_msrs = TRL_BASE, 732 .rapl_msrs = RAPL_PKG | RAPL_CORE, 733 .rapl_quirk_tdp = 30, 734 }; 735 736 static const struct platform_features amt_features = { 737 .has_nhm_msrs = 1, 738 .bclk_freq = BCLK_133MHZ, 739 .supported_cstates = CC1 | CC3 | CC6 | PC3 | PC6, 740 .cst_limit = CST_LIMIT_AMT, 741 .trl_msrs = TRL_BASE, 742 }; 743 744 static const struct platform_features gmt_features = { 745 .has_msr_misc_pwr_mgmt = 1, 746 .has_nhm_msrs = 1, 747 .bclk_freq = BCLK_100MHZ, 748 .crystal_freq = 19200000, 749 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7 | PC8 | PC9 | PC10, 750 .cst_limit = CST_LIMIT_GMT, 751 .has_irtl_msrs = 1, 752 .trl_msrs = TRL_BASE | TRL_CORECOUNT, 753 .rapl_msrs = RAPL_PKG | RAPL_PKG_POWER_INFO, 754 }; 755 756 static const struct platform_features gmtd_features = { 757 .has_msr_misc_pwr_mgmt = 1, 758 .has_nhm_msrs = 1, 759 .bclk_freq = BCLK_100MHZ, 760 .crystal_freq = 25000000, 761 .supported_cstates = CC1 | CC6 | PC2 | PC6, 762 .cst_limit = CST_LIMIT_GMT, 763 .has_irtl_msrs = 1, 764 .has_msr_core_c1_res = 1, 765 .trl_msrs = TRL_BASE | TRL_CORECOUNT, 766 .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL | RAPL_CORE_ENERGY_STATUS, 767 }; 768 769 static const struct platform_features gmtp_features = { 770 .has_msr_misc_pwr_mgmt = 1, 771 .has_nhm_msrs = 1, 772 .bclk_freq = BCLK_100MHZ, 773 .crystal_freq = 19200000, 774 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7 | PC8 | PC9 | PC10, 775 .cst_limit = CST_LIMIT_GMT, 776 .has_irtl_msrs = 1, 777 .trl_msrs = TRL_BASE, 778 .rapl_msrs = RAPL_PKG | RAPL_PKG_POWER_INFO, 779 }; 780 781 static const struct platform_features tmt_features = { 782 .has_msr_misc_pwr_mgmt = 1, 783 .has_nhm_msrs = 1, 784 .bclk_freq = BCLK_100MHZ, 785 .supported_cstates = CC1 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7 | PC8 | PC9 | PC10, 786 .cst_limit = CST_LIMIT_GMT, 787 .has_irtl_msrs = 1, 788 .trl_msrs = TRL_BASE, 789 .rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_GFX, 790 .enable_tsc_tweak = 1, 791 }; 792 793 static const struct platform_features tmtd_features = { 794 .has_msr_misc_pwr_mgmt = 1, 795 .has_nhm_msrs = 1, 796 .bclk_freq = BCLK_100MHZ, 797 .supported_cstates = CC1 | CC6, 798 .cst_limit = CST_LIMIT_GMT, 799 .has_irtl_msrs = 1, 800 .trl_msrs = TRL_BASE | TRL_CORECOUNT, 801 .rapl_msrs = RAPL_PKG_ALL, 802 }; 803 804 static const struct platform_features knl_features = { 805 .has_msr_misc_pwr_mgmt = 1, 806 .has_nhm_msrs = 1, 807 .has_config_tdp = 1, 808 .bclk_freq = BCLK_100MHZ, 809 .supported_cstates = CC1 | CC6 | PC3 | PC6, 810 .cst_limit = CST_LIMIT_KNL, 811 .has_msr_knl_core_c6_residency = 1, 812 .trl_msrs = TRL_KNL, 813 .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL, 814 .has_fixed_rapl_unit = 1, 815 .need_perf_multiplier = 1, 816 }; 817 818 static const struct platform_features default_features = { 819 }; 820 821 static const struct platform_features amd_features_with_rapl = { 822 .rapl_msrs = RAPL_AMD_F17H, 823 .has_per_core_rapl = 1, 824 .rapl_quirk_tdp = 280, /* This is the max stock TDP of HEDT/Server Fam17h+ chips */ 825 }; 826 827 static const struct platform_data turbostat_pdata[] = { 828 { INTEL_FAM6_NEHALEM, &nhm_features }, 829 { INTEL_FAM6_NEHALEM_G, &nhm_features }, 830 { INTEL_FAM6_NEHALEM_EP, &nhm_features }, 831 { INTEL_FAM6_NEHALEM_EX, &nhx_features }, 832 { INTEL_FAM6_WESTMERE, &nhm_features }, 833 { INTEL_FAM6_WESTMERE_EP, &nhm_features }, 834 { INTEL_FAM6_WESTMERE_EX, &nhx_features }, 835 { INTEL_FAM6_SANDYBRIDGE, &snb_features }, 836 { INTEL_FAM6_SANDYBRIDGE_X, &snx_features }, 837 { INTEL_FAM6_IVYBRIDGE, &ivb_features }, 838 { INTEL_FAM6_IVYBRIDGE_X, &ivx_features }, 839 { INTEL_FAM6_HASWELL, &hsw_features }, 840 { INTEL_FAM6_HASWELL_X, &hsx_features }, 841 { INTEL_FAM6_HASWELL_L, &hswl_features }, 842 { INTEL_FAM6_HASWELL_G, &hswg_features }, 843 { INTEL_FAM6_BROADWELL, &bdw_features }, 844 { INTEL_FAM6_BROADWELL_G, &bdwg_features }, 845 { INTEL_FAM6_BROADWELL_X, &bdx_features }, 846 { INTEL_FAM6_BROADWELL_D, &bdx_features }, 847 { INTEL_FAM6_SKYLAKE_L, &skl_features }, 848 { INTEL_FAM6_SKYLAKE, &skl_features }, 849 { INTEL_FAM6_SKYLAKE_X, &skx_features }, 850 { INTEL_FAM6_KABYLAKE_L, &skl_features }, 851 { INTEL_FAM6_KABYLAKE, &skl_features }, 852 { INTEL_FAM6_COMETLAKE, &skl_features }, 853 { INTEL_FAM6_COMETLAKE_L, &skl_features }, 854 { INTEL_FAM6_CANNONLAKE_L, &cnl_features }, 855 { INTEL_FAM6_ICELAKE_X, &icx_features }, 856 { INTEL_FAM6_ICELAKE_D, &icx_features }, 857 { INTEL_FAM6_ICELAKE_L, &cnl_features }, 858 { INTEL_FAM6_ICELAKE_NNPI, &cnl_features }, 859 { INTEL_FAM6_ROCKETLAKE, &cnl_features }, 860 { INTEL_FAM6_TIGERLAKE_L, &cnl_features }, 861 { INTEL_FAM6_TIGERLAKE, &cnl_features }, 862 { INTEL_FAM6_SAPPHIRERAPIDS_X, &spr_features }, 863 { INTEL_FAM6_EMERALDRAPIDS_X, &spr_features }, 864 { INTEL_FAM6_GRANITERAPIDS_X, &spr_features }, 865 { INTEL_FAM6_LAKEFIELD, &cnl_features }, 866 { INTEL_FAM6_ALDERLAKE, &adl_features }, 867 { INTEL_FAM6_ALDERLAKE_L, &adl_features }, 868 { INTEL_FAM6_RAPTORLAKE, &adl_features }, 869 { INTEL_FAM6_RAPTORLAKE_P, &adl_features }, 870 { INTEL_FAM6_RAPTORLAKE_S, &adl_features }, 871 { INTEL_FAM6_METEORLAKE, &cnl_features }, 872 { INTEL_FAM6_METEORLAKE_L, &cnl_features }, 873 { INTEL_FAM6_ARROWLAKE, &cnl_features }, 874 { INTEL_FAM6_LUNARLAKE_M, &cnl_features }, 875 { INTEL_FAM6_ATOM_SILVERMONT, &slv_features }, 876 { INTEL_FAM6_ATOM_SILVERMONT_D, &slvd_features }, 877 { INTEL_FAM6_ATOM_AIRMONT, &amt_features }, 878 { INTEL_FAM6_ATOM_GOLDMONT, &gmt_features }, 879 { INTEL_FAM6_ATOM_GOLDMONT_D, &gmtd_features }, 880 { INTEL_FAM6_ATOM_GOLDMONT_PLUS, &gmtp_features }, 881 { INTEL_FAM6_ATOM_TREMONT_D, &tmtd_features }, 882 { INTEL_FAM6_ATOM_TREMONT, &tmt_features }, 883 { INTEL_FAM6_ATOM_TREMONT_L, &tmt_features }, 884 { INTEL_FAM6_ATOM_GRACEMONT, &adl_features }, 885 { INTEL_FAM6_ATOM_CRESTMONT_X, &srf_features }, 886 { INTEL_FAM6_ATOM_CRESTMONT, &grr_features }, 887 { INTEL_FAM6_XEON_PHI_KNL, &knl_features }, 888 { INTEL_FAM6_XEON_PHI_KNM, &knl_features }, 889 /* 890 * Missing support for 891 * INTEL_FAM6_ICELAKE 892 * INTEL_FAM6_ATOM_SILVERMONT_MID 893 * INTEL_FAM6_ATOM_AIRMONT_MID 894 * INTEL_FAM6_ATOM_AIRMONT_NP 895 */ 896 { 0, NULL }, 897 }; 898 899 static const struct platform_features *platform; 900 901 void probe_platform_features(unsigned int family, unsigned int model) 902 { 903 int i; 904 905 platform = &default_features; 906 907 if (authentic_amd || hygon_genuine) { 908 if (max_extended_level >= 0x80000007) { 909 unsigned int eax, ebx, ecx, edx; 910 911 __cpuid(0x80000007, eax, ebx, ecx, edx); 912 /* RAPL (Fam 17h+) */ 913 if ((edx & (1 << 14)) && family >= 0x17) 914 platform = &amd_features_with_rapl; 915 } 916 return; 917 } 918 919 if (!genuine_intel || family != 6) 920 return; 921 922 for (i = 0; turbostat_pdata[i].features; i++) { 923 if (turbostat_pdata[i].model == model) { 924 platform = turbostat_pdata[i].features; 925 return; 926 } 927 } 928 } 929 930 /* Model specific support End */ 931 932 #define TJMAX_DEFAULT 100 933 934 /* MSRs that are not yet in the kernel-provided header. */ 935 #define MSR_RAPL_PWR_UNIT 0xc0010299 936 #define MSR_CORE_ENERGY_STAT 0xc001029a 937 #define MSR_PKG_ENERGY_STAT 0xc001029b 938 939 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 940 941 int backwards_count; 942 char *progname; 943 944 #define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */ 945 cpu_set_t *cpu_present_set, *cpu_effective_set, *cpu_allowed_set, *cpu_affinity_set, *cpu_subset; 946 size_t cpu_present_setsize, cpu_effective_setsize, cpu_allowed_setsize, cpu_affinity_setsize, cpu_subset_size; 947 #define MAX_ADDED_COUNTERS 8 948 #define MAX_ADDED_THREAD_COUNTERS 24 949 #define BITMASK_SIZE 32 950 951 struct thread_data { 952 struct timeval tv_begin; 953 struct timeval tv_end; 954 struct timeval tv_delta; 955 unsigned long long tsc; 956 unsigned long long aperf; 957 unsigned long long mperf; 958 unsigned long long c1; 959 unsigned long long instr_count; 960 unsigned long long irq_count; 961 unsigned int smi_count; 962 unsigned int cpu_id; 963 unsigned int apic_id; 964 unsigned int x2apic_id; 965 unsigned int flags; 966 bool is_atom; 967 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS]; 968 } *thread_even, *thread_odd; 969 970 struct core_data { 971 int base_cpu; 972 unsigned long long c3; 973 unsigned long long c6; 974 unsigned long long c7; 975 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */ 976 unsigned int core_temp_c; 977 unsigned int core_energy; /* MSR_CORE_ENERGY_STAT */ 978 unsigned int core_id; 979 unsigned long long core_throt_cnt; 980 unsigned long long counter[MAX_ADDED_COUNTERS]; 981 } *core_even, *core_odd; 982 983 struct pkg_data { 984 int base_cpu; 985 unsigned long long pc2; 986 unsigned long long pc3; 987 unsigned long long pc6; 988 unsigned long long pc7; 989 unsigned long long pc8; 990 unsigned long long pc9; 991 unsigned long long pc10; 992 unsigned long long cpu_lpi; 993 unsigned long long sys_lpi; 994 unsigned long long pkg_wtd_core_c0; 995 unsigned long long pkg_any_core_c0; 996 unsigned long long pkg_any_gfxe_c0; 997 unsigned long long pkg_both_core_gfxe_c0; 998 long long gfx_rc6_ms; 999 unsigned int gfx_mhz; 1000 unsigned int gfx_act_mhz; 1001 unsigned int package_id; 1002 unsigned long long energy_pkg; /* MSR_PKG_ENERGY_STATUS */ 1003 unsigned long long energy_dram; /* MSR_DRAM_ENERGY_STATUS */ 1004 unsigned long long energy_cores; /* MSR_PP0_ENERGY_STATUS */ 1005 unsigned long long energy_gfx; /* MSR_PP1_ENERGY_STATUS */ 1006 unsigned long long rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ 1007 unsigned long long rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ 1008 unsigned int pkg_temp_c; 1009 unsigned int uncore_mhz; 1010 unsigned long long counter[MAX_ADDED_COUNTERS]; 1011 } *package_even, *package_odd; 1012 1013 #define ODD_COUNTERS thread_odd, core_odd, package_odd 1014 #define EVEN_COUNTERS thread_even, core_even, package_even 1015 1016 #define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \ 1017 ((thread_base) + \ 1018 ((pkg_no) * \ 1019 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \ 1020 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \ 1021 ((core_no) * topo.threads_per_core) + \ 1022 (thread_no)) 1023 1024 #define GET_CORE(core_base, core_no, node_no, pkg_no) \ 1025 ((core_base) + \ 1026 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \ 1027 ((node_no) * topo.cores_per_node) + \ 1028 (core_no)) 1029 1030 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) 1031 1032 /* 1033 * The accumulated sum of MSR is defined as a monotonic 1034 * increasing MSR, it will be accumulated periodically, 1035 * despite its register's bit width. 1036 */ 1037 enum { 1038 IDX_PKG_ENERGY, 1039 IDX_DRAM_ENERGY, 1040 IDX_PP0_ENERGY, 1041 IDX_PP1_ENERGY, 1042 IDX_PKG_PERF, 1043 IDX_DRAM_PERF, 1044 IDX_COUNT, 1045 }; 1046 1047 int get_msr_sum(int cpu, off_t offset, unsigned long long *msr); 1048 1049 struct msr_sum_array { 1050 /* get_msr_sum() = sum + (get_msr() - last) */ 1051 struct { 1052 /*The accumulated MSR value is updated by the timer */ 1053 unsigned long long sum; 1054 /*The MSR footprint recorded in last timer */ 1055 unsigned long long last; 1056 } entries[IDX_COUNT]; 1057 }; 1058 1059 /* The percpu MSR sum array.*/ 1060 struct msr_sum_array *per_cpu_msr_sum; 1061 1062 off_t idx_to_offset(int idx) 1063 { 1064 off_t offset; 1065 1066 switch (idx) { 1067 case IDX_PKG_ENERGY: 1068 if (platform->rapl_msrs & RAPL_AMD_F17H) 1069 offset = MSR_PKG_ENERGY_STAT; 1070 else 1071 offset = MSR_PKG_ENERGY_STATUS; 1072 break; 1073 case IDX_DRAM_ENERGY: 1074 offset = MSR_DRAM_ENERGY_STATUS; 1075 break; 1076 case IDX_PP0_ENERGY: 1077 offset = MSR_PP0_ENERGY_STATUS; 1078 break; 1079 case IDX_PP1_ENERGY: 1080 offset = MSR_PP1_ENERGY_STATUS; 1081 break; 1082 case IDX_PKG_PERF: 1083 offset = MSR_PKG_PERF_STATUS; 1084 break; 1085 case IDX_DRAM_PERF: 1086 offset = MSR_DRAM_PERF_STATUS; 1087 break; 1088 default: 1089 offset = -1; 1090 } 1091 return offset; 1092 } 1093 1094 int offset_to_idx(off_t offset) 1095 { 1096 int idx; 1097 1098 switch (offset) { 1099 case MSR_PKG_ENERGY_STATUS: 1100 case MSR_PKG_ENERGY_STAT: 1101 idx = IDX_PKG_ENERGY; 1102 break; 1103 case MSR_DRAM_ENERGY_STATUS: 1104 idx = IDX_DRAM_ENERGY; 1105 break; 1106 case MSR_PP0_ENERGY_STATUS: 1107 idx = IDX_PP0_ENERGY; 1108 break; 1109 case MSR_PP1_ENERGY_STATUS: 1110 idx = IDX_PP1_ENERGY; 1111 break; 1112 case MSR_PKG_PERF_STATUS: 1113 idx = IDX_PKG_PERF; 1114 break; 1115 case MSR_DRAM_PERF_STATUS: 1116 idx = IDX_DRAM_PERF; 1117 break; 1118 default: 1119 idx = -1; 1120 } 1121 return idx; 1122 } 1123 1124 int idx_valid(int idx) 1125 { 1126 switch (idx) { 1127 case IDX_PKG_ENERGY: 1128 return platform->rapl_msrs & (RAPL_PKG | RAPL_AMD_F17H); 1129 case IDX_DRAM_ENERGY: 1130 return platform->rapl_msrs & RAPL_DRAM; 1131 case IDX_PP0_ENERGY: 1132 return platform->rapl_msrs & RAPL_CORE_ENERGY_STATUS; 1133 case IDX_PP1_ENERGY: 1134 return platform->rapl_msrs & RAPL_GFX; 1135 case IDX_PKG_PERF: 1136 return platform->rapl_msrs & RAPL_PKG_PERF_STATUS; 1137 case IDX_DRAM_PERF: 1138 return platform->rapl_msrs & RAPL_DRAM_PERF_STATUS; 1139 default: 1140 return 0; 1141 } 1142 } 1143 1144 struct sys_counters { 1145 unsigned int added_thread_counters; 1146 unsigned int added_core_counters; 1147 unsigned int added_package_counters; 1148 struct msr_counter *tp; 1149 struct msr_counter *cp; 1150 struct msr_counter *pp; 1151 } sys; 1152 1153 struct system_summary { 1154 struct thread_data threads; 1155 struct core_data cores; 1156 struct pkg_data packages; 1157 } average; 1158 1159 struct cpu_topology { 1160 int physical_package_id; 1161 int die_id; 1162 int logical_cpu_id; 1163 int physical_node_id; 1164 int logical_node_id; /* 0-based count within the package */ 1165 int physical_core_id; 1166 int thread_id; 1167 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */ 1168 } *cpus; 1169 1170 struct topo_params { 1171 int num_packages; 1172 int num_die; 1173 int num_cpus; 1174 int num_cores; 1175 int allowed_packages; 1176 int allowed_cpus; 1177 int allowed_cores; 1178 int max_cpu_num; 1179 int max_node_num; 1180 int nodes_per_pkg; 1181 int cores_per_node; 1182 int threads_per_core; 1183 } topo; 1184 1185 struct timeval tv_even, tv_odd, tv_delta; 1186 1187 int *irq_column_2_cpu; /* /proc/interrupts column numbers */ 1188 int *irqs_per_cpu; /* indexed by cpu_num */ 1189 1190 void setup_all_buffers(bool startup); 1191 1192 char *sys_lpi_file; 1193 char *sys_lpi_file_sysfs = "/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us"; 1194 char *sys_lpi_file_debugfs = "/sys/kernel/debug/pmc_core/slp_s0_residency_usec"; 1195 1196 int cpu_is_not_present(int cpu) 1197 { 1198 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); 1199 } 1200 1201 int cpu_is_not_allowed(int cpu) 1202 { 1203 return !CPU_ISSET_S(cpu, cpu_allowed_setsize, cpu_allowed_set); 1204 } 1205 1206 /* 1207 * run func(thread, core, package) in topology order 1208 * skip non-present cpus 1209 */ 1210 1211 int for_all_cpus(int (func) (struct thread_data *, struct core_data *, struct pkg_data *), 1212 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) 1213 { 1214 int retval, pkg_no, core_no, thread_no, node_no; 1215 1216 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 1217 for (node_no = 0; node_no < topo.nodes_per_pkg; node_no++) { 1218 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) { 1219 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) { 1220 struct thread_data *t; 1221 struct core_data *c; 1222 struct pkg_data *p; 1223 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no); 1224 1225 if (cpu_is_not_allowed(t->cpu_id)) 1226 continue; 1227 1228 c = GET_CORE(core_base, core_no, node_no, pkg_no); 1229 p = GET_PKG(pkg_base, pkg_no); 1230 1231 retval = func(t, c, p); 1232 if (retval) 1233 return retval; 1234 } 1235 } 1236 } 1237 } 1238 return 0; 1239 } 1240 1241 int is_cpu_first_thread_in_core(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1242 { 1243 UNUSED(p); 1244 1245 return ((int)t->cpu_id == c->base_cpu || c->base_cpu < 0); 1246 } 1247 1248 int is_cpu_first_core_in_package(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1249 { 1250 UNUSED(c); 1251 1252 return ((int)t->cpu_id == p->base_cpu || p->base_cpu < 0); 1253 } 1254 1255 int is_cpu_first_thread_in_package(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1256 { 1257 return is_cpu_first_thread_in_core(t, c, p) && is_cpu_first_core_in_package(t, c, p); 1258 } 1259 1260 int cpu_migrate(int cpu) 1261 { 1262 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 1263 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); 1264 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) 1265 return -1; 1266 else 1267 return 0; 1268 } 1269 1270 int get_msr_fd(int cpu) 1271 { 1272 char pathname[32]; 1273 int fd; 1274 1275 fd = fd_percpu[cpu]; 1276 1277 if (fd) 1278 return fd; 1279 1280 sprintf(pathname, "/dev/cpu/%d/msr", cpu); 1281 fd = open(pathname, O_RDONLY); 1282 if (fd < 0) 1283 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); 1284 1285 fd_percpu[cpu] = fd; 1286 1287 return fd; 1288 } 1289 1290 static long perf_event_open(struct perf_event_attr *hw_event, pid_t pid, int cpu, int group_fd, unsigned long flags) 1291 { 1292 return syscall(__NR_perf_event_open, hw_event, pid, cpu, group_fd, flags); 1293 } 1294 1295 static int perf_instr_count_open(int cpu_num) 1296 { 1297 struct perf_event_attr pea; 1298 int fd; 1299 1300 memset(&pea, 0, sizeof(struct perf_event_attr)); 1301 pea.type = PERF_TYPE_HARDWARE; 1302 pea.size = sizeof(struct perf_event_attr); 1303 pea.config = PERF_COUNT_HW_INSTRUCTIONS; 1304 1305 /* counter for cpu_num, including user + kernel and all processes */ 1306 fd = perf_event_open(&pea, -1, cpu_num, -1, 0); 1307 if (fd == -1) { 1308 warnx("capget(CAP_PERFMON) failed, try \"# setcap cap_sys_admin=ep %s\"", progname); 1309 BIC_NOT_PRESENT(BIC_IPC); 1310 } 1311 1312 return fd; 1313 } 1314 1315 int get_instr_count_fd(int cpu) 1316 { 1317 if (fd_instr_count_percpu[cpu]) 1318 return fd_instr_count_percpu[cpu]; 1319 1320 fd_instr_count_percpu[cpu] = perf_instr_count_open(cpu); 1321 1322 return fd_instr_count_percpu[cpu]; 1323 } 1324 1325 int get_msr(int cpu, off_t offset, unsigned long long *msr) 1326 { 1327 ssize_t retval; 1328 1329 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); 1330 1331 if (retval != sizeof *msr) 1332 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset); 1333 1334 return 0; 1335 } 1336 1337 #define MAX_DEFERRED 16 1338 char *deferred_add_names[MAX_DEFERRED]; 1339 char *deferred_skip_names[MAX_DEFERRED]; 1340 int deferred_add_index; 1341 int deferred_skip_index; 1342 1343 /* 1344 * HIDE_LIST - hide this list of counters, show the rest [default] 1345 * SHOW_LIST - show this list of counters, hide the rest 1346 */ 1347 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST; 1348 1349 void help(void) 1350 { 1351 fprintf(outf, 1352 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" 1353 "\n" 1354 "Turbostat forks the specified COMMAND and prints statistics\n" 1355 "when COMMAND completes.\n" 1356 "If no COMMAND is specified, turbostat wakes every 5-seconds\n" 1357 "to print statistics, until interrupted.\n" 1358 " -a, --add add a counter\n" 1359 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n" 1360 " -c, --cpu cpu-set limit output to summary plus cpu-set:\n" 1361 " {core | package | j,k,l..m,n-p }\n" 1362 " -d, --debug displays usec, Time_Of_Day_Seconds and more debugging\n" 1363 " -D, --Dump displays the raw counter values\n" 1364 " -e, --enable [all | column]\n" 1365 " shows all or the specified disabled column\n" 1366 " -H, --hide [column|column,column,...]\n" 1367 " hide the specified column(s)\n" 1368 " -i, --interval sec.subsec\n" 1369 " Override default 5-second measurement interval\n" 1370 " -J, --Joules displays energy in Joules instead of Watts\n" 1371 " -l, --list list column headers only\n" 1372 " -n, --num_iterations num\n" 1373 " number of the measurement iterations\n" 1374 " -N, --header_iterations num\n" 1375 " print header every num iterations\n" 1376 " -o, --out file\n" 1377 " create or truncate \"file\" for all output\n" 1378 " -q, --quiet skip decoding system configuration header\n" 1379 " -s, --show [column|column,column,...]\n" 1380 " show only the specified column(s)\n" 1381 " -S, --Summary\n" 1382 " limits output to 1-line system summary per interval\n" 1383 " -T, --TCC temperature\n" 1384 " sets the Thermal Control Circuit temperature in\n" 1385 " degrees Celsius\n" 1386 " -h, --help print this help message\n" 1387 " -v, --version print version information\n" "\n" "For more help, run \"man turbostat\"\n"); 1388 } 1389 1390 /* 1391 * bic_lookup 1392 * for all the strings in comma separate name_list, 1393 * set the approprate bit in return value. 1394 */ 1395 unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode) 1396 { 1397 unsigned int i; 1398 unsigned long long retval = 0; 1399 1400 while (name_list) { 1401 char *comma; 1402 1403 comma = strchr(name_list, ','); 1404 1405 if (comma) 1406 *comma = '\0'; 1407 1408 for (i = 0; i < MAX_BIC; ++i) { 1409 if (!strcmp(name_list, bic[i].name)) { 1410 retval |= (1ULL << i); 1411 break; 1412 } 1413 if (!strcmp(name_list, "all")) { 1414 retval |= ~0; 1415 break; 1416 } else if (!strcmp(name_list, "topology")) { 1417 retval |= BIC_TOPOLOGY; 1418 break; 1419 } else if (!strcmp(name_list, "power")) { 1420 retval |= BIC_THERMAL_PWR; 1421 break; 1422 } else if (!strcmp(name_list, "idle")) { 1423 retval |= BIC_IDLE; 1424 break; 1425 } else if (!strcmp(name_list, "frequency")) { 1426 retval |= BIC_FREQUENCY; 1427 break; 1428 } else if (!strcmp(name_list, "other")) { 1429 retval |= BIC_OTHER; 1430 break; 1431 } 1432 1433 } 1434 if (i == MAX_BIC) { 1435 if (mode == SHOW_LIST) { 1436 deferred_add_names[deferred_add_index++] = name_list; 1437 if (deferred_add_index >= MAX_DEFERRED) { 1438 fprintf(stderr, "More than max %d un-recognized --add options '%s'\n", 1439 MAX_DEFERRED, name_list); 1440 help(); 1441 exit(1); 1442 } 1443 } else { 1444 deferred_skip_names[deferred_skip_index++] = name_list; 1445 if (debug) 1446 fprintf(stderr, "deferred \"%s\"\n", name_list); 1447 if (deferred_skip_index >= MAX_DEFERRED) { 1448 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n", 1449 MAX_DEFERRED, name_list); 1450 help(); 1451 exit(1); 1452 } 1453 } 1454 } 1455 1456 name_list = comma; 1457 if (name_list) 1458 name_list++; 1459 1460 } 1461 return retval; 1462 } 1463 1464 void print_header(char *delim) 1465 { 1466 struct msr_counter *mp; 1467 int printed = 0; 1468 1469 if (DO_BIC(BIC_USEC)) 1470 outp += sprintf(outp, "%susec", (printed++ ? delim : "")); 1471 if (DO_BIC(BIC_TOD)) 1472 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : "")); 1473 if (DO_BIC(BIC_Package)) 1474 outp += sprintf(outp, "%sPackage", (printed++ ? delim : "")); 1475 if (DO_BIC(BIC_Die)) 1476 outp += sprintf(outp, "%sDie", (printed++ ? delim : "")); 1477 if (DO_BIC(BIC_Node)) 1478 outp += sprintf(outp, "%sNode", (printed++ ? delim : "")); 1479 if (DO_BIC(BIC_Core)) 1480 outp += sprintf(outp, "%sCore", (printed++ ? delim : "")); 1481 if (DO_BIC(BIC_CPU)) 1482 outp += sprintf(outp, "%sCPU", (printed++ ? delim : "")); 1483 if (DO_BIC(BIC_APIC)) 1484 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : "")); 1485 if (DO_BIC(BIC_X2APIC)) 1486 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : "")); 1487 if (DO_BIC(BIC_Avg_MHz)) 1488 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : "")); 1489 if (DO_BIC(BIC_Busy)) 1490 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : "")); 1491 if (DO_BIC(BIC_Bzy_MHz)) 1492 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : "")); 1493 if (DO_BIC(BIC_TSC_MHz)) 1494 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : "")); 1495 1496 if (DO_BIC(BIC_IPC)) 1497 outp += sprintf(outp, "%sIPC", (printed++ ? delim : "")); 1498 1499 if (DO_BIC(BIC_IRQ)) { 1500 if (sums_need_wide_columns) 1501 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : "")); 1502 else 1503 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : "")); 1504 } 1505 1506 if (DO_BIC(BIC_SMI)) 1507 outp += sprintf(outp, "%sSMI", (printed++ ? delim : "")); 1508 1509 for (mp = sys.tp; mp; mp = mp->next) { 1510 1511 if (mp->format == FORMAT_RAW) { 1512 if (mp->width == 64) 1513 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name); 1514 else 1515 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name); 1516 } else { 1517 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1518 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name); 1519 else 1520 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name); 1521 } 1522 } 1523 1524 if (DO_BIC(BIC_CPU_c1)) 1525 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : "")); 1526 if (DO_BIC(BIC_CPU_c3)) 1527 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : "")); 1528 if (DO_BIC(BIC_CPU_c6)) 1529 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : "")); 1530 if (DO_BIC(BIC_CPU_c7)) 1531 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : "")); 1532 1533 if (DO_BIC(BIC_Mod_c6)) 1534 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : "")); 1535 1536 if (DO_BIC(BIC_CoreTmp)) 1537 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : "")); 1538 1539 if (DO_BIC(BIC_CORE_THROT_CNT)) 1540 outp += sprintf(outp, "%sCoreThr", (printed++ ? delim : "")); 1541 1542 if (platform->rapl_msrs && !rapl_joules) { 1543 if (DO_BIC(BIC_CorWatt) && platform->has_per_core_rapl) 1544 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 1545 } else if (platform->rapl_msrs && rapl_joules) { 1546 if (DO_BIC(BIC_Cor_J) && platform->has_per_core_rapl) 1547 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 1548 } 1549 1550 for (mp = sys.cp; mp; mp = mp->next) { 1551 if (mp->format == FORMAT_RAW) { 1552 if (mp->width == 64) 1553 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 1554 else 1555 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 1556 } else { 1557 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1558 outp += sprintf(outp, "%s%8s", delim, mp->name); 1559 else 1560 outp += sprintf(outp, "%s%s", delim, mp->name); 1561 } 1562 } 1563 1564 if (DO_BIC(BIC_PkgTmp)) 1565 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : "")); 1566 1567 if (DO_BIC(BIC_GFX_rc6)) 1568 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : "")); 1569 1570 if (DO_BIC(BIC_GFXMHz)) 1571 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : "")); 1572 1573 if (DO_BIC(BIC_GFXACTMHz)) 1574 outp += sprintf(outp, "%sGFXAMHz", (printed++ ? delim : "")); 1575 1576 if (DO_BIC(BIC_Totl_c0)) 1577 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : "")); 1578 if (DO_BIC(BIC_Any_c0)) 1579 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : "")); 1580 if (DO_BIC(BIC_GFX_c0)) 1581 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : "")); 1582 if (DO_BIC(BIC_CPUGFX)) 1583 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : "")); 1584 1585 if (DO_BIC(BIC_Pkgpc2)) 1586 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : "")); 1587 if (DO_BIC(BIC_Pkgpc3)) 1588 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : "")); 1589 if (DO_BIC(BIC_Pkgpc6)) 1590 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : "")); 1591 if (DO_BIC(BIC_Pkgpc7)) 1592 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : "")); 1593 if (DO_BIC(BIC_Pkgpc8)) 1594 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : "")); 1595 if (DO_BIC(BIC_Pkgpc9)) 1596 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : "")); 1597 if (DO_BIC(BIC_Pkgpc10)) 1598 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : "")); 1599 if (DO_BIC(BIC_CPU_LPI)) 1600 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : "")); 1601 if (DO_BIC(BIC_SYS_LPI)) 1602 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : "")); 1603 1604 if (platform->rapl_msrs && !rapl_joules) { 1605 if (DO_BIC(BIC_PkgWatt)) 1606 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : "")); 1607 if (DO_BIC(BIC_CorWatt) && !platform->has_per_core_rapl) 1608 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 1609 if (DO_BIC(BIC_GFXWatt)) 1610 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : "")); 1611 if (DO_BIC(BIC_RAMWatt)) 1612 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : "")); 1613 if (DO_BIC(BIC_PKG__)) 1614 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 1615 if (DO_BIC(BIC_RAM__)) 1616 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 1617 } else if (platform->rapl_msrs && rapl_joules) { 1618 if (DO_BIC(BIC_Pkg_J)) 1619 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : "")); 1620 if (DO_BIC(BIC_Cor_J) && !platform->has_per_core_rapl) 1621 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 1622 if (DO_BIC(BIC_GFX_J)) 1623 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : "")); 1624 if (DO_BIC(BIC_RAM_J)) 1625 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : "")); 1626 if (DO_BIC(BIC_PKG__)) 1627 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 1628 if (DO_BIC(BIC_RAM__)) 1629 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 1630 } 1631 if (DO_BIC(BIC_UNCORE_MHZ)) 1632 outp += sprintf(outp, "%sUncMHz", (printed++ ? delim : "")); 1633 1634 for (mp = sys.pp; mp; mp = mp->next) { 1635 if (mp->format == FORMAT_RAW) { 1636 if (mp->width == 64) 1637 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 1638 else 1639 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 1640 } else { 1641 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1642 outp += sprintf(outp, "%s%8s", delim, mp->name); 1643 else 1644 outp += sprintf(outp, "%s%s", delim, mp->name); 1645 } 1646 } 1647 1648 outp += sprintf(outp, "\n"); 1649 } 1650 1651 int dump_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1652 { 1653 int i; 1654 struct msr_counter *mp; 1655 1656 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); 1657 1658 if (t) { 1659 outp += sprintf(outp, "CPU: %d flags 0x%x\n", t->cpu_id, t->flags); 1660 outp += sprintf(outp, "TSC: %016llX\n", t->tsc); 1661 outp += sprintf(outp, "aperf: %016llX\n", t->aperf); 1662 outp += sprintf(outp, "mperf: %016llX\n", t->mperf); 1663 outp += sprintf(outp, "c1: %016llX\n", t->c1); 1664 1665 if (DO_BIC(BIC_IPC)) 1666 outp += sprintf(outp, "IPC: %lld\n", t->instr_count); 1667 1668 if (DO_BIC(BIC_IRQ)) 1669 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count); 1670 if (DO_BIC(BIC_SMI)) 1671 outp += sprintf(outp, "SMI: %d\n", t->smi_count); 1672 1673 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1674 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, t->counter[i]); 1675 } 1676 } 1677 1678 if (c) { 1679 outp += sprintf(outp, "core: %d\n", c->core_id); 1680 outp += sprintf(outp, "c3: %016llX\n", c->c3); 1681 outp += sprintf(outp, "c6: %016llX\n", c->c6); 1682 outp += sprintf(outp, "c7: %016llX\n", c->c7); 1683 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); 1684 outp += sprintf(outp, "cpu_throt_count: %016llX\n", c->core_throt_cnt); 1685 outp += sprintf(outp, "Joules: %0X\n", c->core_energy); 1686 1687 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1688 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, c->counter[i]); 1689 } 1690 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us); 1691 } 1692 1693 if (p) { 1694 outp += sprintf(outp, "package: %d\n", p->package_id); 1695 1696 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); 1697 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); 1698 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); 1699 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); 1700 1701 outp += sprintf(outp, "pc2: %016llX\n", p->pc2); 1702 if (DO_BIC(BIC_Pkgpc3)) 1703 outp += sprintf(outp, "pc3: %016llX\n", p->pc3); 1704 if (DO_BIC(BIC_Pkgpc6)) 1705 outp += sprintf(outp, "pc6: %016llX\n", p->pc6); 1706 if (DO_BIC(BIC_Pkgpc7)) 1707 outp += sprintf(outp, "pc7: %016llX\n", p->pc7); 1708 outp += sprintf(outp, "pc8: %016llX\n", p->pc8); 1709 outp += sprintf(outp, "pc9: %016llX\n", p->pc9); 1710 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 1711 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi); 1712 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi); 1713 outp += sprintf(outp, "Joules PKG: %0llX\n", p->energy_pkg); 1714 outp += sprintf(outp, "Joules COR: %0llX\n", p->energy_cores); 1715 outp += sprintf(outp, "Joules GFX: %0llX\n", p->energy_gfx); 1716 outp += sprintf(outp, "Joules RAM: %0llX\n", p->energy_dram); 1717 outp += sprintf(outp, "Throttle PKG: %0llX\n", p->rapl_pkg_perf_status); 1718 outp += sprintf(outp, "Throttle RAM: %0llX\n", p->rapl_dram_perf_status); 1719 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); 1720 1721 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1722 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, p->counter[i]); 1723 } 1724 } 1725 1726 outp += sprintf(outp, "\n"); 1727 1728 return 0; 1729 } 1730 1731 /* 1732 * column formatting convention & formats 1733 */ 1734 int format_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1735 { 1736 double interval_float, tsc; 1737 char *fmt8; 1738 int i; 1739 struct msr_counter *mp; 1740 char *delim = "\t"; 1741 int printed = 0; 1742 1743 /* if showing only 1st thread in core and this isn't one, bail out */ 1744 if (show_core_only && !is_cpu_first_thread_in_core(t, c, p)) 1745 return 0; 1746 1747 /* if showing only 1st thread in pkg and this isn't one, bail out */ 1748 if (show_pkg_only && !is_cpu_first_core_in_package(t, c, p)) 1749 return 0; 1750 1751 /*if not summary line and --cpu is used */ 1752 if ((t != &average.threads) && (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset))) 1753 return 0; 1754 1755 if (DO_BIC(BIC_USEC)) { 1756 /* on each row, print how many usec each timestamp took to gather */ 1757 struct timeval tv; 1758 1759 timersub(&t->tv_end, &t->tv_begin, &tv); 1760 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec); 1761 } 1762 1763 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */ 1764 if (DO_BIC(BIC_TOD)) 1765 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec); 1766 1767 interval_float = t->tv_delta.tv_sec + t->tv_delta.tv_usec / 1000000.0; 1768 1769 tsc = t->tsc * tsc_tweak; 1770 1771 /* topo columns, print blanks on 1st (average) line */ 1772 if (t == &average.threads) { 1773 if (DO_BIC(BIC_Package)) 1774 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1775 if (DO_BIC(BIC_Die)) 1776 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1777 if (DO_BIC(BIC_Node)) 1778 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1779 if (DO_BIC(BIC_Core)) 1780 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1781 if (DO_BIC(BIC_CPU)) 1782 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1783 if (DO_BIC(BIC_APIC)) 1784 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1785 if (DO_BIC(BIC_X2APIC)) 1786 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1787 } else { 1788 if (DO_BIC(BIC_Package)) { 1789 if (p) 1790 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id); 1791 else 1792 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1793 } 1794 if (DO_BIC(BIC_Die)) { 1795 if (c) 1796 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), cpus[t->cpu_id].die_id); 1797 else 1798 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1799 } 1800 if (DO_BIC(BIC_Node)) { 1801 if (t) 1802 outp += sprintf(outp, "%s%d", 1803 (printed++ ? delim : ""), cpus[t->cpu_id].physical_node_id); 1804 else 1805 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1806 } 1807 if (DO_BIC(BIC_Core)) { 1808 if (c) 1809 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id); 1810 else 1811 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1812 } 1813 if (DO_BIC(BIC_CPU)) 1814 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id); 1815 if (DO_BIC(BIC_APIC)) 1816 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id); 1817 if (DO_BIC(BIC_X2APIC)) 1818 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id); 1819 } 1820 1821 if (DO_BIC(BIC_Avg_MHz)) 1822 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 / units * t->aperf / interval_float); 1823 1824 if (DO_BIC(BIC_Busy)) 1825 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf / tsc); 1826 1827 if (DO_BIC(BIC_Bzy_MHz)) { 1828 if (has_base_hz) 1829 outp += 1830 sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf); 1831 else 1832 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1833 tsc / units * t->aperf / t->mperf / interval_float); 1834 } 1835 1836 if (DO_BIC(BIC_TSC_MHz)) 1837 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc / units / interval_float); 1838 1839 if (DO_BIC(BIC_IPC)) 1840 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1.0 * t->instr_count / t->aperf); 1841 1842 /* IRQ */ 1843 if (DO_BIC(BIC_IRQ)) { 1844 if (sums_need_wide_columns) 1845 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count); 1846 else 1847 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count); 1848 } 1849 1850 /* SMI */ 1851 if (DO_BIC(BIC_SMI)) 1852 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count); 1853 1854 /* Added counters */ 1855 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1856 if (mp->format == FORMAT_RAW) { 1857 if (mp->width == 32) 1858 outp += 1859 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)t->counter[i]); 1860 else 1861 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]); 1862 } else if (mp->format == FORMAT_DELTA) { 1863 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1864 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]); 1865 else 1866 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]); 1867 } else if (mp->format == FORMAT_PERCENT) { 1868 if (mp->type == COUNTER_USEC) 1869 outp += 1870 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1871 t->counter[i] / interval_float / 10000); 1872 else 1873 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i] / tsc); 1874 } 1875 } 1876 1877 /* C1 */ 1878 if (DO_BIC(BIC_CPU_c1)) 1879 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1 / tsc); 1880 1881 /* print per-core data only for 1st thread in core */ 1882 if (!is_cpu_first_thread_in_core(t, c, p)) 1883 goto done; 1884 1885 if (DO_BIC(BIC_CPU_c3)) 1886 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3 / tsc); 1887 if (DO_BIC(BIC_CPU_c6)) 1888 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6 / tsc); 1889 if (DO_BIC(BIC_CPU_c7)) 1890 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7 / tsc); 1891 1892 /* Mod%c6 */ 1893 if (DO_BIC(BIC_Mod_c6)) 1894 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc); 1895 1896 if (DO_BIC(BIC_CoreTmp)) 1897 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c); 1898 1899 /* Core throttle count */ 1900 if (DO_BIC(BIC_CORE_THROT_CNT)) 1901 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->core_throt_cnt); 1902 1903 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1904 if (mp->format == FORMAT_RAW) { 1905 if (mp->width == 32) 1906 outp += 1907 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)c->counter[i]); 1908 else 1909 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]); 1910 } else if (mp->format == FORMAT_DELTA) { 1911 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1912 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]); 1913 else 1914 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]); 1915 } else if (mp->format == FORMAT_PERCENT) { 1916 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i] / tsc); 1917 } 1918 } 1919 1920 fmt8 = "%s%.2f"; 1921 1922 if (DO_BIC(BIC_CorWatt) && platform->has_per_core_rapl) 1923 outp += 1924 sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units / interval_float); 1925 if (DO_BIC(BIC_Cor_J) && platform->has_per_core_rapl) 1926 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units); 1927 1928 /* print per-package data only for 1st core in package */ 1929 if (!is_cpu_first_core_in_package(t, c, p)) 1930 goto done; 1931 1932 /* PkgTmp */ 1933 if (DO_BIC(BIC_PkgTmp)) 1934 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c); 1935 1936 /* GFXrc6 */ 1937 if (DO_BIC(BIC_GFX_rc6)) { 1938 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */ 1939 outp += sprintf(outp, "%s**.**", (printed++ ? delim : "")); 1940 } else { 1941 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1942 p->gfx_rc6_ms / 10.0 / interval_float); 1943 } 1944 } 1945 1946 /* GFXMHz */ 1947 if (DO_BIC(BIC_GFXMHz)) 1948 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz); 1949 1950 /* GFXACTMHz */ 1951 if (DO_BIC(BIC_GFXACTMHz)) 1952 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_act_mhz); 1953 1954 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ 1955 if (DO_BIC(BIC_Totl_c0)) 1956 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0 / tsc); 1957 if (DO_BIC(BIC_Any_c0)) 1958 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0 / tsc); 1959 if (DO_BIC(BIC_GFX_c0)) 1960 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0 / tsc); 1961 if (DO_BIC(BIC_CPUGFX)) 1962 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0 / tsc); 1963 1964 if (DO_BIC(BIC_Pkgpc2)) 1965 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2 / tsc); 1966 if (DO_BIC(BIC_Pkgpc3)) 1967 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3 / tsc); 1968 if (DO_BIC(BIC_Pkgpc6)) 1969 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6 / tsc); 1970 if (DO_BIC(BIC_Pkgpc7)) 1971 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7 / tsc); 1972 if (DO_BIC(BIC_Pkgpc8)) 1973 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8 / tsc); 1974 if (DO_BIC(BIC_Pkgpc9)) 1975 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9 / tsc); 1976 if (DO_BIC(BIC_Pkgpc10)) 1977 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10 / tsc); 1978 1979 if (DO_BIC(BIC_CPU_LPI)) 1980 outp += 1981 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float); 1982 if (DO_BIC(BIC_SYS_LPI)) 1983 outp += 1984 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float); 1985 1986 if (DO_BIC(BIC_PkgWatt)) 1987 outp += 1988 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float); 1989 1990 if (DO_BIC(BIC_CorWatt) && !platform->has_per_core_rapl) 1991 outp += 1992 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float); 1993 if (DO_BIC(BIC_GFXWatt)) 1994 outp += 1995 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float); 1996 if (DO_BIC(BIC_RAMWatt)) 1997 outp += 1998 sprintf(outp, fmt8, (printed++ ? delim : ""), 1999 p->energy_dram * rapl_dram_energy_units / interval_float); 2000 if (DO_BIC(BIC_Pkg_J)) 2001 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units); 2002 if (DO_BIC(BIC_Cor_J) && !platform->has_per_core_rapl) 2003 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units); 2004 if (DO_BIC(BIC_GFX_J)) 2005 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units); 2006 if (DO_BIC(BIC_RAM_J)) 2007 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units); 2008 if (DO_BIC(BIC_PKG__)) 2009 outp += 2010 sprintf(outp, fmt8, (printed++ ? delim : ""), 2011 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 2012 if (DO_BIC(BIC_RAM__)) 2013 outp += 2014 sprintf(outp, fmt8, (printed++ ? delim : ""), 2015 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 2016 /* UncMHz */ 2017 if (DO_BIC(BIC_UNCORE_MHZ)) 2018 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->uncore_mhz); 2019 2020 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 2021 if (mp->format == FORMAT_RAW) { 2022 if (mp->width == 32) 2023 outp += 2024 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)p->counter[i]); 2025 else 2026 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]); 2027 } else if (mp->format == FORMAT_DELTA) { 2028 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 2029 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]); 2030 else 2031 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]); 2032 } else if (mp->format == FORMAT_PERCENT) { 2033 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i] / tsc); 2034 } 2035 } 2036 2037 done: 2038 if (*(outp - 1) != '\n') 2039 outp += sprintf(outp, "\n"); 2040 2041 return 0; 2042 } 2043 2044 void flush_output_stdout(void) 2045 { 2046 FILE *filep; 2047 2048 if (outf == stderr) 2049 filep = stdout; 2050 else 2051 filep = outf; 2052 2053 fputs(output_buffer, filep); 2054 fflush(filep); 2055 2056 outp = output_buffer; 2057 } 2058 2059 void flush_output_stderr(void) 2060 { 2061 fputs(output_buffer, outf); 2062 fflush(outf); 2063 outp = output_buffer; 2064 } 2065 2066 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2067 { 2068 static int count; 2069 2070 if ((!count || (header_iterations && !(count % header_iterations))) || !summary_only) 2071 print_header("\t"); 2072 2073 format_counters(&average.threads, &average.cores, &average.packages); 2074 2075 count++; 2076 2077 if (summary_only) 2078 return; 2079 2080 for_all_cpus(format_counters, t, c, p); 2081 } 2082 2083 #define DELTA_WRAP32(new, old) \ 2084 old = ((((unsigned long long)new << 32) - ((unsigned long long)old << 32)) >> 32); 2085 2086 int delta_package(struct pkg_data *new, struct pkg_data *old) 2087 { 2088 int i; 2089 struct msr_counter *mp; 2090 2091 if (DO_BIC(BIC_Totl_c0)) 2092 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; 2093 if (DO_BIC(BIC_Any_c0)) 2094 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; 2095 if (DO_BIC(BIC_GFX_c0)) 2096 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; 2097 if (DO_BIC(BIC_CPUGFX)) 2098 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; 2099 2100 old->pc2 = new->pc2 - old->pc2; 2101 if (DO_BIC(BIC_Pkgpc3)) 2102 old->pc3 = new->pc3 - old->pc3; 2103 if (DO_BIC(BIC_Pkgpc6)) 2104 old->pc6 = new->pc6 - old->pc6; 2105 if (DO_BIC(BIC_Pkgpc7)) 2106 old->pc7 = new->pc7 - old->pc7; 2107 old->pc8 = new->pc8 - old->pc8; 2108 old->pc9 = new->pc9 - old->pc9; 2109 old->pc10 = new->pc10 - old->pc10; 2110 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi; 2111 old->sys_lpi = new->sys_lpi - old->sys_lpi; 2112 old->pkg_temp_c = new->pkg_temp_c; 2113 2114 /* flag an error when rc6 counter resets/wraps */ 2115 if (old->gfx_rc6_ms > new->gfx_rc6_ms) 2116 old->gfx_rc6_ms = -1; 2117 else 2118 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; 2119 2120 old->uncore_mhz = new->uncore_mhz; 2121 old->gfx_mhz = new->gfx_mhz; 2122 old->gfx_act_mhz = new->gfx_act_mhz; 2123 2124 old->energy_pkg = new->energy_pkg - old->energy_pkg; 2125 old->energy_cores = new->energy_cores - old->energy_cores; 2126 old->energy_gfx = new->energy_gfx - old->energy_gfx; 2127 old->energy_dram = new->energy_dram - old->energy_dram; 2128 old->rapl_pkg_perf_status = new->rapl_pkg_perf_status - old->rapl_pkg_perf_status; 2129 old->rapl_dram_perf_status = new->rapl_dram_perf_status - old->rapl_dram_perf_status; 2130 2131 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 2132 if (mp->format == FORMAT_RAW) 2133 old->counter[i] = new->counter[i]; 2134 else 2135 old->counter[i] = new->counter[i] - old->counter[i]; 2136 } 2137 2138 return 0; 2139 } 2140 2141 void delta_core(struct core_data *new, struct core_data *old) 2142 { 2143 int i; 2144 struct msr_counter *mp; 2145 2146 old->c3 = new->c3 - old->c3; 2147 old->c6 = new->c6 - old->c6; 2148 old->c7 = new->c7 - old->c7; 2149 old->core_temp_c = new->core_temp_c; 2150 old->core_throt_cnt = new->core_throt_cnt; 2151 old->mc6_us = new->mc6_us - old->mc6_us; 2152 2153 DELTA_WRAP32(new->core_energy, old->core_energy); 2154 2155 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 2156 if (mp->format == FORMAT_RAW) 2157 old->counter[i] = new->counter[i]; 2158 else 2159 old->counter[i] = new->counter[i] - old->counter[i]; 2160 } 2161 } 2162 2163 int soft_c1_residency_display(int bic) 2164 { 2165 if (!DO_BIC(BIC_CPU_c1) || platform->has_msr_core_c1_res) 2166 return 0; 2167 2168 return DO_BIC_READ(bic); 2169 } 2170 2171 /* 2172 * old = new - old 2173 */ 2174 int delta_thread(struct thread_data *new, struct thread_data *old, struct core_data *core_delta) 2175 { 2176 int i; 2177 struct msr_counter *mp; 2178 2179 /* we run cpuid just the 1st time, copy the results */ 2180 if (DO_BIC(BIC_APIC)) 2181 new->apic_id = old->apic_id; 2182 if (DO_BIC(BIC_X2APIC)) 2183 new->x2apic_id = old->x2apic_id; 2184 2185 /* 2186 * the timestamps from start of measurement interval are in "old" 2187 * the timestamp from end of measurement interval are in "new" 2188 * over-write old w/ new so we can print end of interval values 2189 */ 2190 2191 timersub(&new->tv_begin, &old->tv_begin, &old->tv_delta); 2192 old->tv_begin = new->tv_begin; 2193 old->tv_end = new->tv_end; 2194 2195 old->tsc = new->tsc - old->tsc; 2196 2197 /* check for TSC < 1 Mcycles over interval */ 2198 if (old->tsc < (1000 * 1000)) 2199 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" 2200 "You can disable all c-states by booting with \"idle=poll\"\n" 2201 "or just the deep ones with \"processor.max_cstate=1\""); 2202 2203 old->c1 = new->c1 - old->c1; 2204 2205 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || DO_BIC(BIC_IPC) 2206 || soft_c1_residency_display(BIC_Avg_MHz)) { 2207 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { 2208 old->aperf = new->aperf - old->aperf; 2209 old->mperf = new->mperf - old->mperf; 2210 } else { 2211 return -1; 2212 } 2213 } 2214 2215 if (platform->has_msr_core_c1_res) { 2216 /* 2217 * Some models have a dedicated C1 residency MSR, 2218 * which should be more accurate than the derivation below. 2219 */ 2220 } else { 2221 /* 2222 * As counter collection is not atomic, 2223 * it is possible for mperf's non-halted cycles + idle states 2224 * to exceed TSC's all cycles: show c1 = 0% in that case. 2225 */ 2226 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak)) 2227 old->c1 = 0; 2228 else { 2229 /* normal case, derive c1 */ 2230 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3 2231 - core_delta->c6 - core_delta->c7; 2232 } 2233 } 2234 2235 if (old->mperf == 0) { 2236 if (debug > 1) 2237 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); 2238 old->mperf = 1; /* divide by 0 protection */ 2239 } 2240 2241 if (DO_BIC(BIC_IPC)) 2242 old->instr_count = new->instr_count - old->instr_count; 2243 2244 if (DO_BIC(BIC_IRQ)) 2245 old->irq_count = new->irq_count - old->irq_count; 2246 2247 if (DO_BIC(BIC_SMI)) 2248 old->smi_count = new->smi_count - old->smi_count; 2249 2250 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 2251 if (mp->format == FORMAT_RAW) 2252 old->counter[i] = new->counter[i]; 2253 else 2254 old->counter[i] = new->counter[i] - old->counter[i]; 2255 } 2256 return 0; 2257 } 2258 2259 int delta_cpu(struct thread_data *t, struct core_data *c, 2260 struct pkg_data *p, struct thread_data *t2, struct core_data *c2, struct pkg_data *p2) 2261 { 2262 int retval = 0; 2263 2264 /* calculate core delta only for 1st thread in core */ 2265 if (is_cpu_first_thread_in_core(t, c, p)) 2266 delta_core(c, c2); 2267 2268 /* always calculate thread delta */ 2269 retval = delta_thread(t, t2, c2); /* c2 is core delta */ 2270 if (retval) 2271 return retval; 2272 2273 /* calculate package delta only for 1st core in package */ 2274 if (is_cpu_first_core_in_package(t, c, p)) 2275 retval = delta_package(p, p2); 2276 2277 return retval; 2278 } 2279 2280 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2281 { 2282 int i; 2283 struct msr_counter *mp; 2284 2285 t->tv_begin.tv_sec = 0; 2286 t->tv_begin.tv_usec = 0; 2287 t->tv_end.tv_sec = 0; 2288 t->tv_end.tv_usec = 0; 2289 t->tv_delta.tv_sec = 0; 2290 t->tv_delta.tv_usec = 0; 2291 2292 t->tsc = 0; 2293 t->aperf = 0; 2294 t->mperf = 0; 2295 t->c1 = 0; 2296 2297 t->instr_count = 0; 2298 2299 t->irq_count = 0; 2300 t->smi_count = 0; 2301 2302 c->c3 = 0; 2303 c->c6 = 0; 2304 c->c7 = 0; 2305 c->mc6_us = 0; 2306 c->core_temp_c = 0; 2307 c->core_energy = 0; 2308 c->core_throt_cnt = 0; 2309 2310 p->pkg_wtd_core_c0 = 0; 2311 p->pkg_any_core_c0 = 0; 2312 p->pkg_any_gfxe_c0 = 0; 2313 p->pkg_both_core_gfxe_c0 = 0; 2314 2315 p->pc2 = 0; 2316 if (DO_BIC(BIC_Pkgpc3)) 2317 p->pc3 = 0; 2318 if (DO_BIC(BIC_Pkgpc6)) 2319 p->pc6 = 0; 2320 if (DO_BIC(BIC_Pkgpc7)) 2321 p->pc7 = 0; 2322 p->pc8 = 0; 2323 p->pc9 = 0; 2324 p->pc10 = 0; 2325 p->cpu_lpi = 0; 2326 p->sys_lpi = 0; 2327 2328 p->energy_pkg = 0; 2329 p->energy_dram = 0; 2330 p->energy_cores = 0; 2331 p->energy_gfx = 0; 2332 p->rapl_pkg_perf_status = 0; 2333 p->rapl_dram_perf_status = 0; 2334 p->pkg_temp_c = 0; 2335 2336 p->gfx_rc6_ms = 0; 2337 p->uncore_mhz = 0; 2338 p->gfx_mhz = 0; 2339 p->gfx_act_mhz = 0; 2340 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) 2341 t->counter[i] = 0; 2342 2343 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) 2344 c->counter[i] = 0; 2345 2346 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) 2347 p->counter[i] = 0; 2348 } 2349 2350 int sum_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2351 { 2352 int i; 2353 struct msr_counter *mp; 2354 2355 /* copy un-changing apic_id's */ 2356 if (DO_BIC(BIC_APIC)) 2357 average.threads.apic_id = t->apic_id; 2358 if (DO_BIC(BIC_X2APIC)) 2359 average.threads.x2apic_id = t->x2apic_id; 2360 2361 /* remember first tv_begin */ 2362 if (average.threads.tv_begin.tv_sec == 0) 2363 average.threads.tv_begin = t->tv_begin; 2364 2365 /* remember last tv_end */ 2366 average.threads.tv_end = t->tv_end; 2367 2368 average.threads.tsc += t->tsc; 2369 average.threads.aperf += t->aperf; 2370 average.threads.mperf += t->mperf; 2371 average.threads.c1 += t->c1; 2372 2373 average.threads.instr_count += t->instr_count; 2374 2375 average.threads.irq_count += t->irq_count; 2376 average.threads.smi_count += t->smi_count; 2377 2378 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 2379 if (mp->format == FORMAT_RAW) 2380 continue; 2381 average.threads.counter[i] += t->counter[i]; 2382 } 2383 2384 /* sum per-core values only for 1st thread in core */ 2385 if (!is_cpu_first_thread_in_core(t, c, p)) 2386 return 0; 2387 2388 average.cores.c3 += c->c3; 2389 average.cores.c6 += c->c6; 2390 average.cores.c7 += c->c7; 2391 average.cores.mc6_us += c->mc6_us; 2392 2393 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); 2394 average.cores.core_throt_cnt = MAX(average.cores.core_throt_cnt, c->core_throt_cnt); 2395 2396 average.cores.core_energy += c->core_energy; 2397 2398 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 2399 if (mp->format == FORMAT_RAW) 2400 continue; 2401 average.cores.counter[i] += c->counter[i]; 2402 } 2403 2404 /* sum per-pkg values only for 1st core in pkg */ 2405 if (!is_cpu_first_core_in_package(t, c, p)) 2406 return 0; 2407 2408 if (DO_BIC(BIC_Totl_c0)) 2409 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; 2410 if (DO_BIC(BIC_Any_c0)) 2411 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; 2412 if (DO_BIC(BIC_GFX_c0)) 2413 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; 2414 if (DO_BIC(BIC_CPUGFX)) 2415 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; 2416 2417 average.packages.pc2 += p->pc2; 2418 if (DO_BIC(BIC_Pkgpc3)) 2419 average.packages.pc3 += p->pc3; 2420 if (DO_BIC(BIC_Pkgpc6)) 2421 average.packages.pc6 += p->pc6; 2422 if (DO_BIC(BIC_Pkgpc7)) 2423 average.packages.pc7 += p->pc7; 2424 average.packages.pc8 += p->pc8; 2425 average.packages.pc9 += p->pc9; 2426 average.packages.pc10 += p->pc10; 2427 2428 average.packages.cpu_lpi = p->cpu_lpi; 2429 average.packages.sys_lpi = p->sys_lpi; 2430 2431 average.packages.energy_pkg += p->energy_pkg; 2432 average.packages.energy_dram += p->energy_dram; 2433 average.packages.energy_cores += p->energy_cores; 2434 average.packages.energy_gfx += p->energy_gfx; 2435 2436 average.packages.gfx_rc6_ms = p->gfx_rc6_ms; 2437 average.packages.uncore_mhz = p->uncore_mhz; 2438 average.packages.gfx_mhz = p->gfx_mhz; 2439 average.packages.gfx_act_mhz = p->gfx_act_mhz; 2440 2441 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); 2442 2443 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; 2444 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; 2445 2446 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 2447 if (mp->format == FORMAT_RAW) 2448 continue; 2449 average.packages.counter[i] += p->counter[i]; 2450 } 2451 return 0; 2452 } 2453 2454 /* 2455 * sum the counters for all cpus in the system 2456 * compute the weighted average 2457 */ 2458 void compute_average(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2459 { 2460 int i; 2461 struct msr_counter *mp; 2462 2463 clear_counters(&average.threads, &average.cores, &average.packages); 2464 2465 for_all_cpus(sum_counters, t, c, p); 2466 2467 /* Use the global time delta for the average. */ 2468 average.threads.tv_delta = tv_delta; 2469 2470 average.threads.tsc /= topo.allowed_cpus; 2471 average.threads.aperf /= topo.allowed_cpus; 2472 average.threads.mperf /= topo.allowed_cpus; 2473 average.threads.instr_count /= topo.allowed_cpus; 2474 average.threads.c1 /= topo.allowed_cpus; 2475 2476 if (average.threads.irq_count > 9999999) 2477 sums_need_wide_columns = 1; 2478 2479 average.cores.c3 /= topo.allowed_cores; 2480 average.cores.c6 /= topo.allowed_cores; 2481 average.cores.c7 /= topo.allowed_cores; 2482 average.cores.mc6_us /= topo.allowed_cores; 2483 2484 if (DO_BIC(BIC_Totl_c0)) 2485 average.packages.pkg_wtd_core_c0 /= topo.allowed_packages; 2486 if (DO_BIC(BIC_Any_c0)) 2487 average.packages.pkg_any_core_c0 /= topo.allowed_packages; 2488 if (DO_BIC(BIC_GFX_c0)) 2489 average.packages.pkg_any_gfxe_c0 /= topo.allowed_packages; 2490 if (DO_BIC(BIC_CPUGFX)) 2491 average.packages.pkg_both_core_gfxe_c0 /= topo.allowed_packages; 2492 2493 average.packages.pc2 /= topo.allowed_packages; 2494 if (DO_BIC(BIC_Pkgpc3)) 2495 average.packages.pc3 /= topo.allowed_packages; 2496 if (DO_BIC(BIC_Pkgpc6)) 2497 average.packages.pc6 /= topo.allowed_packages; 2498 if (DO_BIC(BIC_Pkgpc7)) 2499 average.packages.pc7 /= topo.allowed_packages; 2500 2501 average.packages.pc8 /= topo.allowed_packages; 2502 average.packages.pc9 /= topo.allowed_packages; 2503 average.packages.pc10 /= topo.allowed_packages; 2504 2505 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 2506 if (mp->format == FORMAT_RAW) 2507 continue; 2508 if (mp->type == COUNTER_ITEMS) { 2509 if (average.threads.counter[i] > 9999999) 2510 sums_need_wide_columns = 1; 2511 continue; 2512 } 2513 average.threads.counter[i] /= topo.allowed_cpus; 2514 } 2515 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 2516 if (mp->format == FORMAT_RAW) 2517 continue; 2518 if (mp->type == COUNTER_ITEMS) { 2519 if (average.cores.counter[i] > 9999999) 2520 sums_need_wide_columns = 1; 2521 } 2522 average.cores.counter[i] /= topo.allowed_cores; 2523 } 2524 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 2525 if (mp->format == FORMAT_RAW) 2526 continue; 2527 if (mp->type == COUNTER_ITEMS) { 2528 if (average.packages.counter[i] > 9999999) 2529 sums_need_wide_columns = 1; 2530 } 2531 average.packages.counter[i] /= topo.allowed_packages; 2532 } 2533 } 2534 2535 static unsigned long long rdtsc(void) 2536 { 2537 unsigned int low, high; 2538 2539 asm volatile ("rdtsc":"=a" (low), "=d"(high)); 2540 2541 return low | ((unsigned long long)high) << 32; 2542 } 2543 2544 /* 2545 * Open a file, and exit on failure 2546 */ 2547 FILE *fopen_or_die(const char *path, const char *mode) 2548 { 2549 FILE *filep = fopen(path, mode); 2550 2551 if (!filep) 2552 err(1, "%s: open failed", path); 2553 return filep; 2554 } 2555 2556 /* 2557 * snapshot_sysfs_counter() 2558 * 2559 * return snapshot of given counter 2560 */ 2561 unsigned long long snapshot_sysfs_counter(char *path) 2562 { 2563 FILE *fp; 2564 int retval; 2565 unsigned long long counter; 2566 2567 fp = fopen_or_die(path, "r"); 2568 2569 retval = fscanf(fp, "%lld", &counter); 2570 if (retval != 1) 2571 err(1, "snapshot_sysfs_counter(%s)", path); 2572 2573 fclose(fp); 2574 2575 return counter; 2576 } 2577 2578 int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp) 2579 { 2580 if (mp->msr_num != 0) { 2581 if (get_msr(cpu, mp->msr_num, counterp)) 2582 return -1; 2583 } else { 2584 char path[128 + PATH_BYTES]; 2585 2586 if (mp->flags & SYSFS_PERCPU) { 2587 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s", cpu, mp->path); 2588 2589 *counterp = snapshot_sysfs_counter(path); 2590 } else { 2591 *counterp = snapshot_sysfs_counter(mp->path); 2592 } 2593 } 2594 2595 return 0; 2596 } 2597 2598 unsigned long long get_uncore_mhz(int package, int die) 2599 { 2600 char path[128]; 2601 2602 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/current_freq_khz", package, 2603 die); 2604 2605 return (snapshot_sysfs_counter(path) / 1000); 2606 } 2607 2608 int get_epb(int cpu) 2609 { 2610 char path[128 + PATH_BYTES]; 2611 unsigned long long msr; 2612 int ret, epb = -1; 2613 FILE *fp; 2614 2615 sprintf(path, "/sys/devices/system/cpu/cpu%d/power/energy_perf_bias", cpu); 2616 2617 fp = fopen(path, "r"); 2618 if (!fp) 2619 goto msr_fallback; 2620 2621 ret = fscanf(fp, "%d", &epb); 2622 if (ret != 1) 2623 err(1, "%s(%s)", __func__, path); 2624 2625 fclose(fp); 2626 2627 return epb; 2628 2629 msr_fallback: 2630 get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr); 2631 2632 return msr & 0xf; 2633 } 2634 2635 void get_apic_id(struct thread_data *t) 2636 { 2637 unsigned int eax, ebx, ecx, edx; 2638 2639 if (DO_BIC(BIC_APIC)) { 2640 eax = ebx = ecx = edx = 0; 2641 __cpuid(1, eax, ebx, ecx, edx); 2642 2643 t->apic_id = (ebx >> 24) & 0xff; 2644 } 2645 2646 if (!DO_BIC(BIC_X2APIC)) 2647 return; 2648 2649 if (authentic_amd || hygon_genuine) { 2650 unsigned int topology_extensions; 2651 2652 if (max_extended_level < 0x8000001e) 2653 return; 2654 2655 eax = ebx = ecx = edx = 0; 2656 __cpuid(0x80000001, eax, ebx, ecx, edx); 2657 topology_extensions = ecx & (1 << 22); 2658 2659 if (topology_extensions == 0) 2660 return; 2661 2662 eax = ebx = ecx = edx = 0; 2663 __cpuid(0x8000001e, eax, ebx, ecx, edx); 2664 2665 t->x2apic_id = eax; 2666 return; 2667 } 2668 2669 if (!genuine_intel) 2670 return; 2671 2672 if (max_level < 0xb) 2673 return; 2674 2675 ecx = 0; 2676 __cpuid(0xb, eax, ebx, ecx, edx); 2677 t->x2apic_id = edx; 2678 2679 if (debug && (t->apic_id != (t->x2apic_id & 0xff))) 2680 fprintf(outf, "cpu%d: BIOS BUG: apic 0x%x x2apic 0x%x\n", t->cpu_id, t->apic_id, t->x2apic_id); 2681 } 2682 2683 int get_core_throt_cnt(int cpu, unsigned long long *cnt) 2684 { 2685 char path[128 + PATH_BYTES]; 2686 unsigned long long tmp; 2687 FILE *fp; 2688 int ret; 2689 2690 sprintf(path, "/sys/devices/system/cpu/cpu%d/thermal_throttle/core_throttle_count", cpu); 2691 fp = fopen(path, "r"); 2692 if (!fp) 2693 return -1; 2694 ret = fscanf(fp, "%lld", &tmp); 2695 fclose(fp); 2696 if (ret != 1) 2697 return -1; 2698 *cnt = tmp; 2699 2700 return 0; 2701 } 2702 2703 /* 2704 * get_counters(...) 2705 * migrate to cpu 2706 * acquire and record local counters for that cpu 2707 */ 2708 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2709 { 2710 int cpu = t->cpu_id; 2711 unsigned long long msr; 2712 int aperf_mperf_retry_count = 0; 2713 struct msr_counter *mp; 2714 int i; 2715 2716 if (cpu_migrate(cpu)) { 2717 fprintf(outf, "get_counters: Could not migrate to CPU %d\n", cpu); 2718 return -1; 2719 } 2720 2721 gettimeofday(&t->tv_begin, (struct timezone *)NULL); 2722 2723 if (first_counter_read) 2724 get_apic_id(t); 2725 retry: 2726 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 2727 2728 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || DO_BIC(BIC_IPC) 2729 || soft_c1_residency_display(BIC_Avg_MHz)) { 2730 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; 2731 2732 /* 2733 * The TSC, APERF and MPERF must be read together for 2734 * APERF/MPERF and MPERF/TSC to give accurate results. 2735 * 2736 * Unfortunately, APERF and MPERF are read by 2737 * individual system call, so delays may occur 2738 * between them. If the time to read them 2739 * varies by a large amount, we re-read them. 2740 */ 2741 2742 /* 2743 * This initial dummy APERF read has been seen to 2744 * reduce jitter in the subsequent reads. 2745 */ 2746 2747 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 2748 return -3; 2749 2750 t->tsc = rdtsc(); /* re-read close to APERF */ 2751 2752 tsc_before = t->tsc; 2753 2754 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 2755 return -3; 2756 2757 tsc_between = rdtsc(); 2758 2759 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) 2760 return -4; 2761 2762 tsc_after = rdtsc(); 2763 2764 aperf_time = tsc_between - tsc_before; 2765 mperf_time = tsc_after - tsc_between; 2766 2767 /* 2768 * If the system call latency to read APERF and MPERF 2769 * differ by more than 2x, then try again. 2770 */ 2771 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { 2772 aperf_mperf_retry_count++; 2773 if (aperf_mperf_retry_count < 5) 2774 goto retry; 2775 else 2776 warnx("cpu%d jitter %lld %lld", cpu, aperf_time, mperf_time); 2777 } 2778 aperf_mperf_retry_count = 0; 2779 2780 t->aperf = t->aperf * aperf_mperf_multiplier; 2781 t->mperf = t->mperf * aperf_mperf_multiplier; 2782 } 2783 2784 if (DO_BIC(BIC_IPC)) 2785 if (read(get_instr_count_fd(cpu), &t->instr_count, sizeof(long long)) != sizeof(long long)) 2786 return -4; 2787 2788 if (DO_BIC(BIC_IRQ)) 2789 t->irq_count = irqs_per_cpu[cpu]; 2790 if (DO_BIC(BIC_SMI)) { 2791 if (get_msr(cpu, MSR_SMI_COUNT, &msr)) 2792 return -5; 2793 t->smi_count = msr & 0xFFFFFFFF; 2794 } 2795 if (DO_BIC(BIC_CPU_c1) && platform->has_msr_core_c1_res) { 2796 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) 2797 return -6; 2798 } 2799 2800 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 2801 if (get_mp(cpu, mp, &t->counter[i])) 2802 return -10; 2803 } 2804 2805 /* collect core counters only for 1st thread in core */ 2806 if (!is_cpu_first_thread_in_core(t, c, p)) 2807 goto done; 2808 2809 if (DO_BIC(BIC_CPU_c3) || soft_c1_residency_display(BIC_CPU_c3)) { 2810 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) 2811 return -6; 2812 } 2813 2814 if ((DO_BIC(BIC_CPU_c6) || soft_c1_residency_display(BIC_CPU_c6)) && !platform->has_msr_knl_core_c6_residency) { 2815 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) 2816 return -7; 2817 } else if (platform->has_msr_knl_core_c6_residency && soft_c1_residency_display(BIC_CPU_c6)) { 2818 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) 2819 return -7; 2820 } 2821 2822 if (DO_BIC(BIC_CPU_c7) || soft_c1_residency_display(BIC_CPU_c7)) { 2823 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 2824 return -8; 2825 else if (t->is_atom) { 2826 /* 2827 * For Atom CPUs that has core cstate deeper than c6, 2828 * MSR_CORE_C6_RESIDENCY returns residency of cc6 and deeper. 2829 * Minus CC7 (and deeper cstates) residency to get 2830 * accturate cc6 residency. 2831 */ 2832 c->c6 -= c->c7; 2833 } 2834 } 2835 2836 if (DO_BIC(BIC_Mod_c6)) 2837 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us)) 2838 return -8; 2839 2840 if (DO_BIC(BIC_CoreTmp)) { 2841 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 2842 return -9; 2843 c->core_temp_c = tj_max - ((msr >> 16) & 0x7F); 2844 } 2845 2846 if (DO_BIC(BIC_CORE_THROT_CNT)) 2847 get_core_throt_cnt(cpu, &c->core_throt_cnt); 2848 2849 if (platform->rapl_msrs & RAPL_AMD_F17H) { 2850 if (get_msr(cpu, MSR_CORE_ENERGY_STAT, &msr)) 2851 return -14; 2852 c->core_energy = msr & 0xFFFFFFFF; 2853 } 2854 2855 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 2856 if (get_mp(cpu, mp, &c->counter[i])) 2857 return -10; 2858 } 2859 2860 /* collect package counters only for 1st core in package */ 2861 if (!is_cpu_first_core_in_package(t, c, p)) 2862 goto done; 2863 2864 if (DO_BIC(BIC_Totl_c0)) { 2865 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) 2866 return -10; 2867 } 2868 if (DO_BIC(BIC_Any_c0)) { 2869 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) 2870 return -11; 2871 } 2872 if (DO_BIC(BIC_GFX_c0)) { 2873 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) 2874 return -12; 2875 } 2876 if (DO_BIC(BIC_CPUGFX)) { 2877 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) 2878 return -13; 2879 } 2880 if (DO_BIC(BIC_Pkgpc3)) 2881 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) 2882 return -9; 2883 if (DO_BIC(BIC_Pkgpc6)) { 2884 if (platform->has_msr_atom_pkg_c6_residency) { 2885 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6)) 2886 return -10; 2887 } else { 2888 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) 2889 return -10; 2890 } 2891 } 2892 2893 if (DO_BIC(BIC_Pkgpc2)) 2894 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) 2895 return -11; 2896 if (DO_BIC(BIC_Pkgpc7)) 2897 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) 2898 return -12; 2899 if (DO_BIC(BIC_Pkgpc8)) 2900 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) 2901 return -13; 2902 if (DO_BIC(BIC_Pkgpc9)) 2903 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) 2904 return -13; 2905 if (DO_BIC(BIC_Pkgpc10)) 2906 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) 2907 return -13; 2908 2909 if (DO_BIC(BIC_CPU_LPI)) 2910 p->cpu_lpi = cpuidle_cur_cpu_lpi_us; 2911 if (DO_BIC(BIC_SYS_LPI)) 2912 p->sys_lpi = cpuidle_cur_sys_lpi_us; 2913 2914 if (platform->rapl_msrs & RAPL_PKG) { 2915 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STATUS, &msr)) 2916 return -13; 2917 p->energy_pkg = msr; 2918 } 2919 if (platform->rapl_msrs & RAPL_CORE_ENERGY_STATUS) { 2920 if (get_msr_sum(cpu, MSR_PP0_ENERGY_STATUS, &msr)) 2921 return -14; 2922 p->energy_cores = msr; 2923 } 2924 if (platform->rapl_msrs & RAPL_DRAM) { 2925 if (get_msr_sum(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) 2926 return -15; 2927 p->energy_dram = msr; 2928 } 2929 if (platform->rapl_msrs & RAPL_GFX) { 2930 if (get_msr_sum(cpu, MSR_PP1_ENERGY_STATUS, &msr)) 2931 return -16; 2932 p->energy_gfx = msr; 2933 } 2934 if (platform->rapl_msrs & RAPL_PKG_PERF_STATUS) { 2935 if (get_msr_sum(cpu, MSR_PKG_PERF_STATUS, &msr)) 2936 return -16; 2937 p->rapl_pkg_perf_status = msr; 2938 } 2939 if (platform->rapl_msrs & RAPL_DRAM_PERF_STATUS) { 2940 if (get_msr_sum(cpu, MSR_DRAM_PERF_STATUS, &msr)) 2941 return -16; 2942 p->rapl_dram_perf_status = msr; 2943 } 2944 if (platform->rapl_msrs & RAPL_AMD_F17H) { 2945 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STAT, &msr)) 2946 return -13; 2947 p->energy_pkg = msr; 2948 } 2949 if (DO_BIC(BIC_PkgTmp)) { 2950 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 2951 return -17; 2952 p->pkg_temp_c = tj_max - ((msr >> 16) & 0x7F); 2953 } 2954 2955 if (DO_BIC(BIC_GFX_rc6)) 2956 p->gfx_rc6_ms = gfx_cur_rc6_ms; 2957 2958 /* n.b. assume die0 uncore frequency applies to whole package */ 2959 if (DO_BIC(BIC_UNCORE_MHZ)) 2960 p->uncore_mhz = get_uncore_mhz(p->package_id, 0); 2961 2962 if (DO_BIC(BIC_GFXMHz)) 2963 p->gfx_mhz = gfx_cur_mhz; 2964 2965 if (DO_BIC(BIC_GFXACTMHz)) 2966 p->gfx_act_mhz = gfx_act_mhz; 2967 2968 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 2969 if (get_mp(cpu, mp, &p->counter[i])) 2970 return -10; 2971 } 2972 done: 2973 gettimeofday(&t->tv_end, (struct timezone *)NULL); 2974 2975 return 0; 2976 } 2977 2978 /* 2979 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: 2980 * If you change the values, note they are used both in comparisons 2981 * (>= PCL__7) and to index pkg_cstate_limit_strings[]. 2982 */ 2983 2984 #define PCLUKN 0 /* Unknown */ 2985 #define PCLRSV 1 /* Reserved */ 2986 #define PCL__0 2 /* PC0 */ 2987 #define PCL__1 3 /* PC1 */ 2988 #define PCL__2 4 /* PC2 */ 2989 #define PCL__3 5 /* PC3 */ 2990 #define PCL__4 6 /* PC4 */ 2991 #define PCL__6 7 /* PC6 */ 2992 #define PCL_6N 8 /* PC6 No Retention */ 2993 #define PCL_6R 9 /* PC6 Retention */ 2994 #define PCL__7 10 /* PC7 */ 2995 #define PCL_7S 11 /* PC7 Shrink */ 2996 #define PCL__8 12 /* PC8 */ 2997 #define PCL__9 13 /* PC9 */ 2998 #define PCL_10 14 /* PC10 */ 2999 #define PCLUNL 15 /* Unlimited */ 3000 3001 int pkg_cstate_limit = PCLUKN; 3002 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", 3003 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "pc10", "unlimited" 3004 }; 3005 3006 int nhm_pkg_cstate_limits[16] = 3007 { PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 3008 PCLRSV, PCLRSV 3009 }; 3010 3011 int snb_pkg_cstate_limits[16] = 3012 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 3013 PCLRSV, PCLRSV 3014 }; 3015 3016 int hsw_pkg_cstate_limits[16] = 3017 { PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 3018 PCLRSV, PCLRSV 3019 }; 3020 3021 int slv_pkg_cstate_limits[16] = 3022 { PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 3023 PCL__6, PCL__7 3024 }; 3025 3026 int amt_pkg_cstate_limits[16] = 3027 { PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 3028 PCLRSV, PCLRSV 3029 }; 3030 3031 int phi_pkg_cstate_limits[16] = 3032 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 3033 PCLRSV, PCLRSV 3034 }; 3035 3036 int glm_pkg_cstate_limits[16] = 3037 { PCLUNL, PCL__1, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCL_10, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 3038 PCLRSV, PCLRSV 3039 }; 3040 3041 int skx_pkg_cstate_limits[16] = 3042 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 3043 PCLRSV, PCLRSV 3044 }; 3045 3046 int icx_pkg_cstate_limits[16] = 3047 { PCL__0, PCL__2, PCL__6, PCL__6, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 3048 PCLRSV, PCLRSV 3049 }; 3050 3051 void probe_cst_limit(void) 3052 { 3053 unsigned long long msr; 3054 int *pkg_cstate_limits; 3055 3056 if (!platform->has_nhm_msrs) 3057 return; 3058 3059 switch (platform->cst_limit) { 3060 case CST_LIMIT_NHM: 3061 pkg_cstate_limits = nhm_pkg_cstate_limits; 3062 break; 3063 case CST_LIMIT_SNB: 3064 pkg_cstate_limits = snb_pkg_cstate_limits; 3065 break; 3066 case CST_LIMIT_HSW: 3067 pkg_cstate_limits = hsw_pkg_cstate_limits; 3068 break; 3069 case CST_LIMIT_SKX: 3070 pkg_cstate_limits = skx_pkg_cstate_limits; 3071 break; 3072 case CST_LIMIT_ICX: 3073 pkg_cstate_limits = icx_pkg_cstate_limits; 3074 break; 3075 case CST_LIMIT_SLV: 3076 pkg_cstate_limits = slv_pkg_cstate_limits; 3077 break; 3078 case CST_LIMIT_AMT: 3079 pkg_cstate_limits = amt_pkg_cstate_limits; 3080 break; 3081 case CST_LIMIT_KNL: 3082 pkg_cstate_limits = phi_pkg_cstate_limits; 3083 break; 3084 case CST_LIMIT_GMT: 3085 pkg_cstate_limits = glm_pkg_cstate_limits; 3086 break; 3087 default: 3088 return; 3089 } 3090 3091 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 3092 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; 3093 } 3094 3095 static void dump_platform_info(void) 3096 { 3097 unsigned long long msr; 3098 unsigned int ratio; 3099 3100 if (!platform->has_nhm_msrs) 3101 return; 3102 3103 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 3104 3105 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 3106 3107 ratio = (msr >> 40) & 0xFF; 3108 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", ratio, bclk, ratio * bclk); 3109 3110 ratio = (msr >> 8) & 0xFF; 3111 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk); 3112 } 3113 3114 static void dump_power_ctl(void) 3115 { 3116 unsigned long long msr; 3117 3118 if (!platform->has_nhm_msrs) 3119 return; 3120 3121 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); 3122 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", 3123 base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); 3124 3125 /* C-state Pre-wake Disable (CSTATE_PREWAKE_DISABLE) */ 3126 if (platform->has_cst_prewake_bit) 3127 fprintf(outf, "C-state Pre-wake: %sabled\n", msr & 0x40000000 ? "DIS" : "EN"); 3128 3129 return; 3130 } 3131 3132 static void dump_turbo_ratio_limit2(void) 3133 { 3134 unsigned long long msr; 3135 unsigned int ratio; 3136 3137 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); 3138 3139 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); 3140 3141 ratio = (msr >> 8) & 0xFF; 3142 if (ratio) 3143 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", ratio, bclk, ratio * bclk); 3144 3145 ratio = (msr >> 0) & 0xFF; 3146 if (ratio) 3147 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", ratio, bclk, ratio * bclk); 3148 return; 3149 } 3150 3151 static void dump_turbo_ratio_limit1(void) 3152 { 3153 unsigned long long msr; 3154 unsigned int ratio; 3155 3156 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); 3157 3158 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); 3159 3160 ratio = (msr >> 56) & 0xFF; 3161 if (ratio) 3162 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", ratio, bclk, ratio * bclk); 3163 3164 ratio = (msr >> 48) & 0xFF; 3165 if (ratio) 3166 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", ratio, bclk, ratio * bclk); 3167 3168 ratio = (msr >> 40) & 0xFF; 3169 if (ratio) 3170 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", ratio, bclk, ratio * bclk); 3171 3172 ratio = (msr >> 32) & 0xFF; 3173 if (ratio) 3174 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", ratio, bclk, ratio * bclk); 3175 3176 ratio = (msr >> 24) & 0xFF; 3177 if (ratio) 3178 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", ratio, bclk, ratio * bclk); 3179 3180 ratio = (msr >> 16) & 0xFF; 3181 if (ratio) 3182 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", ratio, bclk, ratio * bclk); 3183 3184 ratio = (msr >> 8) & 0xFF; 3185 if (ratio) 3186 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", ratio, bclk, ratio * bclk); 3187 3188 ratio = (msr >> 0) & 0xFF; 3189 if (ratio) 3190 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", ratio, bclk, ratio * bclk); 3191 return; 3192 } 3193 3194 static void dump_turbo_ratio_limits(int trl_msr_offset) 3195 { 3196 unsigned long long msr, core_counts; 3197 int shift; 3198 3199 get_msr(base_cpu, trl_msr_offset, &msr); 3200 fprintf(outf, "cpu%d: MSR_%sTURBO_RATIO_LIMIT: 0x%08llx\n", 3201 base_cpu, trl_msr_offset == MSR_SECONDARY_TURBO_RATIO_LIMIT ? "SECONDARY_" : "", msr); 3202 3203 if (platform->trl_msrs & TRL_CORECOUNT) { 3204 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts); 3205 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts); 3206 } else { 3207 core_counts = 0x0807060504030201; 3208 } 3209 3210 for (shift = 56; shift >= 0; shift -= 8) { 3211 unsigned int ratio, group_size; 3212 3213 ratio = (msr >> shift) & 0xFF; 3214 group_size = (core_counts >> shift) & 0xFF; 3215 if (ratio) 3216 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 3217 ratio, bclk, ratio * bclk, group_size); 3218 } 3219 3220 return; 3221 } 3222 3223 static void dump_atom_turbo_ratio_limits(void) 3224 { 3225 unsigned long long msr; 3226 unsigned int ratio; 3227 3228 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr); 3229 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 3230 3231 ratio = (msr >> 0) & 0x3F; 3232 if (ratio) 3233 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", ratio, bclk, ratio * bclk); 3234 3235 ratio = (msr >> 8) & 0x3F; 3236 if (ratio) 3237 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", ratio, bclk, ratio * bclk); 3238 3239 ratio = (msr >> 16) & 0x3F; 3240 if (ratio) 3241 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk); 3242 3243 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr); 3244 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 3245 3246 ratio = (msr >> 24) & 0x3F; 3247 if (ratio) 3248 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", ratio, bclk, ratio * bclk); 3249 3250 ratio = (msr >> 16) & 0x3F; 3251 if (ratio) 3252 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", ratio, bclk, ratio * bclk); 3253 3254 ratio = (msr >> 8) & 0x3F; 3255 if (ratio) 3256 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", ratio, bclk, ratio * bclk); 3257 3258 ratio = (msr >> 0) & 0x3F; 3259 if (ratio) 3260 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", ratio, bclk, ratio * bclk); 3261 } 3262 3263 static void dump_knl_turbo_ratio_limits(void) 3264 { 3265 const unsigned int buckets_no = 7; 3266 3267 unsigned long long msr; 3268 int delta_cores, delta_ratio; 3269 int i, b_nr; 3270 unsigned int cores[buckets_no]; 3271 unsigned int ratio[buckets_no]; 3272 3273 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 3274 3275 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 3276 3277 /* 3278 * Turbo encoding in KNL is as follows: 3279 * [0] -- Reserved 3280 * [7:1] -- Base value of number of active cores of bucket 1. 3281 * [15:8] -- Base value of freq ratio of bucket 1. 3282 * [20:16] -- +ve delta of number of active cores of bucket 2. 3283 * i.e. active cores of bucket 2 = 3284 * active cores of bucket 1 + delta 3285 * [23:21] -- Negative delta of freq ratio of bucket 2. 3286 * i.e. freq ratio of bucket 2 = 3287 * freq ratio of bucket 1 - delta 3288 * [28:24]-- +ve delta of number of active cores of bucket 3. 3289 * [31:29]-- -ve delta of freq ratio of bucket 3. 3290 * [36:32]-- +ve delta of number of active cores of bucket 4. 3291 * [39:37]-- -ve delta of freq ratio of bucket 4. 3292 * [44:40]-- +ve delta of number of active cores of bucket 5. 3293 * [47:45]-- -ve delta of freq ratio of bucket 5. 3294 * [52:48]-- +ve delta of number of active cores of bucket 6. 3295 * [55:53]-- -ve delta of freq ratio of bucket 6. 3296 * [60:56]-- +ve delta of number of active cores of bucket 7. 3297 * [63:61]-- -ve delta of freq ratio of bucket 7. 3298 */ 3299 3300 b_nr = 0; 3301 cores[b_nr] = (msr & 0xFF) >> 1; 3302 ratio[b_nr] = (msr >> 8) & 0xFF; 3303 3304 for (i = 16; i < 64; i += 8) { 3305 delta_cores = (msr >> i) & 0x1F; 3306 delta_ratio = (msr >> (i + 5)) & 0x7; 3307 3308 cores[b_nr + 1] = cores[b_nr] + delta_cores; 3309 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; 3310 b_nr++; 3311 } 3312 3313 for (i = buckets_no - 1; i >= 0; i--) 3314 if (i > 0 ? ratio[i] != ratio[i - 1] : 1) 3315 fprintf(outf, 3316 "%d * %.1f = %.1f MHz max turbo %d active cores\n", 3317 ratio[i], bclk, ratio[i] * bclk, cores[i]); 3318 } 3319 3320 static void dump_cst_cfg(void) 3321 { 3322 unsigned long long msr; 3323 3324 if (!platform->has_nhm_msrs) 3325 return; 3326 3327 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 3328 3329 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr); 3330 3331 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)", 3332 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", 3333 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", 3334 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", 3335 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", 3336 (msr & (1 << 15)) ? "" : "UN", (unsigned int)msr & 0xF, pkg_cstate_limit_strings[pkg_cstate_limit]); 3337 3338 #define AUTOMATIC_CSTATE_CONVERSION (1UL << 16) 3339 if (platform->has_cst_auto_convension) { 3340 fprintf(outf, ", automatic c-state conversion=%s", (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off"); 3341 } 3342 3343 fprintf(outf, ")\n"); 3344 3345 return; 3346 } 3347 3348 static void dump_config_tdp(void) 3349 { 3350 unsigned long long msr; 3351 3352 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); 3353 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); 3354 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); 3355 3356 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); 3357 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); 3358 if (msr) { 3359 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 3360 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 3361 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 3362 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); 3363 } 3364 fprintf(outf, ")\n"); 3365 3366 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); 3367 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); 3368 if (msr) { 3369 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 3370 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 3371 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 3372 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); 3373 } 3374 fprintf(outf, ")\n"); 3375 3376 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); 3377 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); 3378 if ((msr) & 0x3) 3379 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); 3380 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 3381 fprintf(outf, ")\n"); 3382 3383 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); 3384 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); 3385 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); 3386 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 3387 fprintf(outf, ")\n"); 3388 } 3389 3390 unsigned int irtl_time_units[] = { 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; 3391 3392 void print_irtl(void) 3393 { 3394 unsigned long long msr; 3395 3396 if (!platform->has_irtl_msrs) 3397 return; 3398 3399 if (platform->supported_cstates & PC3) { 3400 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr); 3401 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr); 3402 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 3403 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 3404 } 3405 3406 if (platform->supported_cstates & PC6) { 3407 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr); 3408 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr); 3409 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 3410 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 3411 } 3412 3413 if (platform->supported_cstates & PC7) { 3414 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr); 3415 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr); 3416 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 3417 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 3418 } 3419 3420 if (platform->supported_cstates & PC8) { 3421 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr); 3422 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr); 3423 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 3424 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 3425 } 3426 3427 if (platform->supported_cstates & PC9) { 3428 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr); 3429 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr); 3430 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 3431 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 3432 } 3433 3434 if (platform->supported_cstates & PC10) { 3435 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr); 3436 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr); 3437 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 3438 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 3439 } 3440 } 3441 3442 void free_fd_percpu(void) 3443 { 3444 int i; 3445 3446 for (i = 0; i < topo.max_cpu_num + 1; ++i) { 3447 if (fd_percpu[i] != 0) 3448 close(fd_percpu[i]); 3449 } 3450 3451 free(fd_percpu); 3452 } 3453 3454 void free_all_buffers(void) 3455 { 3456 int i; 3457 3458 CPU_FREE(cpu_present_set); 3459 cpu_present_set = NULL; 3460 cpu_present_setsize = 0; 3461 3462 CPU_FREE(cpu_effective_set); 3463 cpu_effective_set = NULL; 3464 cpu_effective_setsize = 0; 3465 3466 CPU_FREE(cpu_allowed_set); 3467 cpu_allowed_set = NULL; 3468 cpu_allowed_setsize = 0; 3469 3470 CPU_FREE(cpu_affinity_set); 3471 cpu_affinity_set = NULL; 3472 cpu_affinity_setsize = 0; 3473 3474 free(thread_even); 3475 free(core_even); 3476 free(package_even); 3477 3478 thread_even = NULL; 3479 core_even = NULL; 3480 package_even = NULL; 3481 3482 free(thread_odd); 3483 free(core_odd); 3484 free(package_odd); 3485 3486 thread_odd = NULL; 3487 core_odd = NULL; 3488 package_odd = NULL; 3489 3490 free(output_buffer); 3491 output_buffer = NULL; 3492 outp = NULL; 3493 3494 free_fd_percpu(); 3495 3496 free(irq_column_2_cpu); 3497 free(irqs_per_cpu); 3498 3499 for (i = 0; i <= topo.max_cpu_num; ++i) { 3500 if (cpus[i].put_ids) 3501 CPU_FREE(cpus[i].put_ids); 3502 } 3503 free(cpus); 3504 } 3505 3506 /* 3507 * Parse a file containing a single int. 3508 * Return 0 if file can not be opened 3509 * Exit if file can be opened, but can not be parsed 3510 */ 3511 int parse_int_file(const char *fmt, ...) 3512 { 3513 va_list args; 3514 char path[PATH_MAX]; 3515 FILE *filep; 3516 int value; 3517 3518 va_start(args, fmt); 3519 vsnprintf(path, sizeof(path), fmt, args); 3520 va_end(args); 3521 filep = fopen(path, "r"); 3522 if (!filep) 3523 return 0; 3524 if (fscanf(filep, "%d", &value) != 1) 3525 err(1, "%s: failed to parse number from file", path); 3526 fclose(filep); 3527 return value; 3528 } 3529 3530 /* 3531 * cpu_is_first_core_in_package(cpu) 3532 * return 1 if given CPU is 1st core in package 3533 */ 3534 int cpu_is_first_core_in_package(int cpu) 3535 { 3536 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); 3537 } 3538 3539 int get_physical_package_id(int cpu) 3540 { 3541 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); 3542 } 3543 3544 int get_die_id(int cpu) 3545 { 3546 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/die_id", cpu); 3547 } 3548 3549 int get_core_id(int cpu) 3550 { 3551 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); 3552 } 3553 3554 void set_node_data(void) 3555 { 3556 int pkg, node, lnode, cpu, cpux; 3557 int cpu_count; 3558 3559 /* initialize logical_node_id */ 3560 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) 3561 cpus[cpu].logical_node_id = -1; 3562 3563 cpu_count = 0; 3564 for (pkg = 0; pkg < topo.num_packages; pkg++) { 3565 lnode = 0; 3566 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) { 3567 if (cpus[cpu].physical_package_id != pkg) 3568 continue; 3569 /* find a cpu with an unset logical_node_id */ 3570 if (cpus[cpu].logical_node_id != -1) 3571 continue; 3572 cpus[cpu].logical_node_id = lnode; 3573 node = cpus[cpu].physical_node_id; 3574 cpu_count++; 3575 /* 3576 * find all matching cpus on this pkg and set 3577 * the logical_node_id 3578 */ 3579 for (cpux = cpu; cpux <= topo.max_cpu_num; cpux++) { 3580 if ((cpus[cpux].physical_package_id == pkg) && (cpus[cpux].physical_node_id == node)) { 3581 cpus[cpux].logical_node_id = lnode; 3582 cpu_count++; 3583 } 3584 } 3585 lnode++; 3586 if (lnode > topo.nodes_per_pkg) 3587 topo.nodes_per_pkg = lnode; 3588 } 3589 if (cpu_count >= topo.max_cpu_num) 3590 break; 3591 } 3592 } 3593 3594 int get_physical_node_id(struct cpu_topology *thiscpu) 3595 { 3596 char path[80]; 3597 FILE *filep; 3598 int i; 3599 int cpu = thiscpu->logical_cpu_id; 3600 3601 for (i = 0; i <= topo.max_cpu_num; i++) { 3602 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist", cpu, i); 3603 filep = fopen(path, "r"); 3604 if (!filep) 3605 continue; 3606 fclose(filep); 3607 return i; 3608 } 3609 return -1; 3610 } 3611 3612 static int parse_cpu_str(char *cpu_str, cpu_set_t *cpu_set, int cpu_set_size) 3613 { 3614 unsigned int start, end; 3615 char *next = cpu_str; 3616 3617 while (next && *next) { 3618 3619 if (*next == '-') /* no negative cpu numbers */ 3620 return 1; 3621 3622 start = strtoul(next, &next, 10); 3623 3624 if (start >= CPU_SUBSET_MAXCPUS) 3625 return 1; 3626 CPU_SET_S(start, cpu_set_size, cpu_set); 3627 3628 if (*next == '\0' || *next == '\n') 3629 break; 3630 3631 if (*next == ',') { 3632 next += 1; 3633 continue; 3634 } 3635 3636 if (*next == '-') { 3637 next += 1; /* start range */ 3638 } else if (*next == '.') { 3639 next += 1; 3640 if (*next == '.') 3641 next += 1; /* start range */ 3642 else 3643 return 1; 3644 } 3645 3646 end = strtoul(next, &next, 10); 3647 if (end <= start) 3648 return 1; 3649 3650 while (++start <= end) { 3651 if (start >= CPU_SUBSET_MAXCPUS) 3652 return 1; 3653 CPU_SET_S(start, cpu_set_size, cpu_set); 3654 } 3655 3656 if (*next == ',') 3657 next += 1; 3658 else if (*next != '\0' && *next != '\n') 3659 return 1; 3660 } 3661 3662 return 0; 3663 } 3664 3665 int get_thread_siblings(struct cpu_topology *thiscpu) 3666 { 3667 char path[80], character; 3668 FILE *filep; 3669 unsigned long map; 3670 int so, shift, sib_core; 3671 int cpu = thiscpu->logical_cpu_id; 3672 int offset = topo.max_cpu_num + 1; 3673 size_t size; 3674 int thread_id = 0; 3675 3676 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1)); 3677 if (thiscpu->thread_id < 0) 3678 thiscpu->thread_id = thread_id++; 3679 if (!thiscpu->put_ids) 3680 return -1; 3681 3682 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 3683 CPU_ZERO_S(size, thiscpu->put_ids); 3684 3685 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu); 3686 filep = fopen(path, "r"); 3687 3688 if (!filep) { 3689 warnx("%s: open failed", path); 3690 return -1; 3691 } 3692 do { 3693 offset -= BITMASK_SIZE; 3694 if (fscanf(filep, "%lx%c", &map, &character) != 2) 3695 err(1, "%s: failed to parse file", path); 3696 for (shift = 0; shift < BITMASK_SIZE; shift++) { 3697 if ((map >> shift) & 0x1) { 3698 so = shift + offset; 3699 sib_core = get_core_id(so); 3700 if (sib_core == thiscpu->physical_core_id) { 3701 CPU_SET_S(so, size, thiscpu->put_ids); 3702 if ((so != cpu) && (cpus[so].thread_id < 0)) 3703 cpus[so].thread_id = thread_id++; 3704 } 3705 } 3706 } 3707 } while (character == ','); 3708 fclose(filep); 3709 3710 return CPU_COUNT_S(size, thiscpu->put_ids); 3711 } 3712 3713 /* 3714 * run func(thread, core, package) in topology order 3715 * skip non-present cpus 3716 */ 3717 3718 int for_all_cpus_2(int (func) (struct thread_data *, struct core_data *, 3719 struct pkg_data *, struct thread_data *, struct core_data *, 3720 struct pkg_data *), struct thread_data *thread_base, 3721 struct core_data *core_base, struct pkg_data *pkg_base, 3722 struct thread_data *thread_base2, struct core_data *core_base2, struct pkg_data *pkg_base2) 3723 { 3724 int retval, pkg_no, node_no, core_no, thread_no; 3725 3726 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 3727 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) { 3728 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) { 3729 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) { 3730 struct thread_data *t, *t2; 3731 struct core_data *c, *c2; 3732 struct pkg_data *p, *p2; 3733 3734 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no); 3735 3736 if (cpu_is_not_allowed(t->cpu_id)) 3737 continue; 3738 3739 t2 = GET_THREAD(thread_base2, thread_no, core_no, node_no, pkg_no); 3740 3741 c = GET_CORE(core_base, core_no, node_no, pkg_no); 3742 c2 = GET_CORE(core_base2, core_no, node_no, pkg_no); 3743 3744 p = GET_PKG(pkg_base, pkg_no); 3745 p2 = GET_PKG(pkg_base2, pkg_no); 3746 3747 retval = func(t, c, p, t2, c2, p2); 3748 if (retval) 3749 return retval; 3750 } 3751 } 3752 } 3753 } 3754 return 0; 3755 } 3756 3757 /* 3758 * run func(cpu) on every cpu in /proc/stat 3759 * return max_cpu number 3760 */ 3761 int for_all_proc_cpus(int (func) (int)) 3762 { 3763 FILE *fp; 3764 int cpu_num; 3765 int retval; 3766 3767 fp = fopen_or_die(proc_stat, "r"); 3768 3769 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); 3770 if (retval != 0) 3771 err(1, "%s: failed to parse format", proc_stat); 3772 3773 while (1) { 3774 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); 3775 if (retval != 1) 3776 break; 3777 3778 retval = func(cpu_num); 3779 if (retval) { 3780 fclose(fp); 3781 return (retval); 3782 } 3783 } 3784 fclose(fp); 3785 return 0; 3786 } 3787 3788 #define PATH_EFFECTIVE_CPUS "/sys/fs/cgroup/cpuset.cpus.effective" 3789 3790 static char cpu_effective_str[1024]; 3791 3792 static int update_effective_str(bool startup) 3793 { 3794 FILE *fp; 3795 char *pos; 3796 char buf[1024]; 3797 int ret; 3798 3799 if (cpu_effective_str[0] == '\0' && !startup) 3800 return 0; 3801 3802 fp = fopen(PATH_EFFECTIVE_CPUS, "r"); 3803 if (!fp) 3804 return 0; 3805 3806 pos = fgets(buf, 1024, fp); 3807 if (!pos) 3808 err(1, "%s: file read failed\n", PATH_EFFECTIVE_CPUS); 3809 3810 fclose(fp); 3811 3812 ret = strncmp(cpu_effective_str, buf, 1024); 3813 if (!ret) 3814 return 0; 3815 3816 strncpy(cpu_effective_str, buf, 1024); 3817 return 1; 3818 } 3819 3820 static void update_effective_set(bool startup) 3821 { 3822 update_effective_str(startup); 3823 3824 if (parse_cpu_str(cpu_effective_str, cpu_effective_set, cpu_effective_setsize)) 3825 err(1, "%s: cpu str malformat %s\n", PATH_EFFECTIVE_CPUS, cpu_effective_str); 3826 } 3827 3828 void re_initialize(void) 3829 { 3830 free_all_buffers(); 3831 setup_all_buffers(false); 3832 fprintf(outf, "turbostat: re-initialized with num_cpus %d, allowed_cpus %d\n", topo.num_cpus, topo.allowed_cpus); 3833 } 3834 3835 void set_max_cpu_num(void) 3836 { 3837 FILE *filep; 3838 int base_cpu; 3839 unsigned long dummy; 3840 char pathname[64]; 3841 3842 base_cpu = sched_getcpu(); 3843 if (base_cpu < 0) 3844 err(1, "cannot find calling cpu ID"); 3845 sprintf(pathname, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", base_cpu); 3846 3847 filep = fopen_or_die(pathname, "r"); 3848 topo.max_cpu_num = 0; 3849 while (fscanf(filep, "%lx,", &dummy) == 1) 3850 topo.max_cpu_num += BITMASK_SIZE; 3851 fclose(filep); 3852 topo.max_cpu_num--; /* 0 based */ 3853 } 3854 3855 /* 3856 * count_cpus() 3857 * remember the last one seen, it will be the max 3858 */ 3859 int count_cpus(int cpu) 3860 { 3861 UNUSED(cpu); 3862 3863 topo.num_cpus++; 3864 return 0; 3865 } 3866 3867 int mark_cpu_present(int cpu) 3868 { 3869 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); 3870 return 0; 3871 } 3872 3873 int init_thread_id(int cpu) 3874 { 3875 cpus[cpu].thread_id = -1; 3876 return 0; 3877 } 3878 3879 /* 3880 * snapshot_proc_interrupts() 3881 * 3882 * read and record summary of /proc/interrupts 3883 * 3884 * return 1 if config change requires a restart, else return 0 3885 */ 3886 int snapshot_proc_interrupts(void) 3887 { 3888 static FILE *fp; 3889 int column, retval; 3890 3891 if (fp == NULL) 3892 fp = fopen_or_die("/proc/interrupts", "r"); 3893 else 3894 rewind(fp); 3895 3896 /* read 1st line of /proc/interrupts to get cpu* name for each column */ 3897 for (column = 0; column < topo.num_cpus; ++column) { 3898 int cpu_number; 3899 3900 retval = fscanf(fp, " CPU%d", &cpu_number); 3901 if (retval != 1) 3902 break; 3903 3904 if (cpu_number > topo.max_cpu_num) { 3905 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); 3906 return 1; 3907 } 3908 3909 irq_column_2_cpu[column] = cpu_number; 3910 irqs_per_cpu[cpu_number] = 0; 3911 } 3912 3913 /* read /proc/interrupt count lines and sum up irqs per cpu */ 3914 while (1) { 3915 int column; 3916 char buf[64]; 3917 3918 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ 3919 if (retval != 1) 3920 break; 3921 3922 /* read the count per cpu */ 3923 for (column = 0; column < topo.num_cpus; ++column) { 3924 3925 int cpu_number, irq_count; 3926 3927 retval = fscanf(fp, " %d", &irq_count); 3928 if (retval != 1) 3929 break; 3930 3931 cpu_number = irq_column_2_cpu[column]; 3932 irqs_per_cpu[cpu_number] += irq_count; 3933 3934 } 3935 3936 while (getc(fp) != '\n') ; /* flush interrupt description */ 3937 3938 } 3939 return 0; 3940 } 3941 3942 /* 3943 * snapshot_gfx_rc6_ms() 3944 * 3945 * record snapshot of 3946 * /sys/class/drm/card0/power/rc6_residency_ms 3947 * 3948 * return 1 if config change requires a restart, else return 0 3949 */ 3950 int snapshot_gfx_rc6_ms(void) 3951 { 3952 FILE *fp; 3953 int retval; 3954 3955 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); 3956 3957 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); 3958 if (retval != 1) 3959 err(1, "GFX rc6"); 3960 3961 fclose(fp); 3962 3963 return 0; 3964 } 3965 3966 /* 3967 * snapshot_gfx_mhz() 3968 * 3969 * fall back to /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz 3970 * when /sys/class/drm/card0/gt_cur_freq_mhz is not available. 3971 * 3972 * return 1 if config change requires a restart, else return 0 3973 */ 3974 int snapshot_gfx_mhz(void) 3975 { 3976 static FILE *fp; 3977 int retval; 3978 3979 if (fp == NULL) { 3980 fp = fopen("/sys/class/drm/card0/gt_cur_freq_mhz", "r"); 3981 if (!fp) 3982 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); 3983 } else { 3984 rewind(fp); 3985 fflush(fp); 3986 } 3987 3988 retval = fscanf(fp, "%d", &gfx_cur_mhz); 3989 if (retval != 1) 3990 err(1, "GFX MHz"); 3991 3992 return 0; 3993 } 3994 3995 /* 3996 * snapshot_gfx_cur_mhz() 3997 * 3998 * fall back to /sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz 3999 * when /sys/class/drm/card0/gt_act_freq_mhz is not available. 4000 * 4001 * return 1 if config change requires a restart, else return 0 4002 */ 4003 int snapshot_gfx_act_mhz(void) 4004 { 4005 static FILE *fp; 4006 int retval; 4007 4008 if (fp == NULL) { 4009 fp = fopen("/sys/class/drm/card0/gt_act_freq_mhz", "r"); 4010 if (!fp) 4011 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", "r"); 4012 } else { 4013 rewind(fp); 4014 fflush(fp); 4015 } 4016 4017 retval = fscanf(fp, "%d", &gfx_act_mhz); 4018 if (retval != 1) 4019 err(1, "GFX ACT MHz"); 4020 4021 return 0; 4022 } 4023 4024 /* 4025 * snapshot_cpu_lpi() 4026 * 4027 * record snapshot of 4028 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us 4029 */ 4030 int snapshot_cpu_lpi_us(void) 4031 { 4032 FILE *fp; 4033 int retval; 4034 4035 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r"); 4036 4037 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us); 4038 if (retval != 1) { 4039 fprintf(stderr, "Disabling Low Power Idle CPU output\n"); 4040 BIC_NOT_PRESENT(BIC_CPU_LPI); 4041 fclose(fp); 4042 return -1; 4043 } 4044 4045 fclose(fp); 4046 4047 return 0; 4048 } 4049 4050 /* 4051 * snapshot_sys_lpi() 4052 * 4053 * record snapshot of sys_lpi_file 4054 */ 4055 int snapshot_sys_lpi_us(void) 4056 { 4057 FILE *fp; 4058 int retval; 4059 4060 fp = fopen_or_die(sys_lpi_file, "r"); 4061 4062 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us); 4063 if (retval != 1) { 4064 fprintf(stderr, "Disabling Low Power Idle System output\n"); 4065 BIC_NOT_PRESENT(BIC_SYS_LPI); 4066 fclose(fp); 4067 return -1; 4068 } 4069 fclose(fp); 4070 4071 return 0; 4072 } 4073 4074 /* 4075 * snapshot /proc and /sys files 4076 * 4077 * return 1 if configuration restart needed, else return 0 4078 */ 4079 int snapshot_proc_sysfs_files(void) 4080 { 4081 if (DO_BIC(BIC_IRQ)) 4082 if (snapshot_proc_interrupts()) 4083 return 1; 4084 4085 if (DO_BIC(BIC_GFX_rc6)) 4086 snapshot_gfx_rc6_ms(); 4087 4088 if (DO_BIC(BIC_GFXMHz)) 4089 snapshot_gfx_mhz(); 4090 4091 if (DO_BIC(BIC_GFXACTMHz)) 4092 snapshot_gfx_act_mhz(); 4093 4094 if (DO_BIC(BIC_CPU_LPI)) 4095 snapshot_cpu_lpi_us(); 4096 4097 if (DO_BIC(BIC_SYS_LPI)) 4098 snapshot_sys_lpi_us(); 4099 4100 return 0; 4101 } 4102 4103 int exit_requested; 4104 4105 static void signal_handler(int signal) 4106 { 4107 switch (signal) { 4108 case SIGINT: 4109 exit_requested = 1; 4110 if (debug) 4111 fprintf(stderr, " SIGINT\n"); 4112 break; 4113 case SIGUSR1: 4114 if (debug > 1) 4115 fprintf(stderr, "SIGUSR1\n"); 4116 break; 4117 } 4118 } 4119 4120 void setup_signal_handler(void) 4121 { 4122 struct sigaction sa; 4123 4124 memset(&sa, 0, sizeof(sa)); 4125 4126 sa.sa_handler = &signal_handler; 4127 4128 if (sigaction(SIGINT, &sa, NULL) < 0) 4129 err(1, "sigaction SIGINT"); 4130 if (sigaction(SIGUSR1, &sa, NULL) < 0) 4131 err(1, "sigaction SIGUSR1"); 4132 } 4133 4134 void do_sleep(void) 4135 { 4136 struct timeval tout; 4137 struct timespec rest; 4138 fd_set readfds; 4139 int retval; 4140 4141 FD_ZERO(&readfds); 4142 FD_SET(0, &readfds); 4143 4144 if (ignore_stdin) { 4145 nanosleep(&interval_ts, NULL); 4146 return; 4147 } 4148 4149 tout = interval_tv; 4150 retval = select(1, &readfds, NULL, NULL, &tout); 4151 4152 if (retval == 1) { 4153 switch (getc(stdin)) { 4154 case 'q': 4155 exit_requested = 1; 4156 break; 4157 case EOF: 4158 /* 4159 * 'stdin' is a pipe closed on the other end. There 4160 * won't be any further input. 4161 */ 4162 ignore_stdin = 1; 4163 /* Sleep the rest of the time */ 4164 rest.tv_sec = (tout.tv_sec + tout.tv_usec / 1000000); 4165 rest.tv_nsec = (tout.tv_usec % 1000000) * 1000; 4166 nanosleep(&rest, NULL); 4167 } 4168 } 4169 } 4170 4171 int get_msr_sum(int cpu, off_t offset, unsigned long long *msr) 4172 { 4173 int ret, idx; 4174 unsigned long long msr_cur, msr_last; 4175 4176 if (!per_cpu_msr_sum) 4177 return 1; 4178 4179 idx = offset_to_idx(offset); 4180 if (idx < 0) 4181 return idx; 4182 /* get_msr_sum() = sum + (get_msr() - last) */ 4183 ret = get_msr(cpu, offset, &msr_cur); 4184 if (ret) 4185 return ret; 4186 msr_last = per_cpu_msr_sum[cpu].entries[idx].last; 4187 DELTA_WRAP32(msr_cur, msr_last); 4188 *msr = msr_last + per_cpu_msr_sum[cpu].entries[idx].sum; 4189 4190 return 0; 4191 } 4192 4193 timer_t timerid; 4194 4195 /* Timer callback, update the sum of MSRs periodically. */ 4196 static int update_msr_sum(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4197 { 4198 int i, ret; 4199 int cpu = t->cpu_id; 4200 4201 UNUSED(c); 4202 UNUSED(p); 4203 4204 for (i = IDX_PKG_ENERGY; i < IDX_COUNT; i++) { 4205 unsigned long long msr_cur, msr_last; 4206 off_t offset; 4207 4208 if (!idx_valid(i)) 4209 continue; 4210 offset = idx_to_offset(i); 4211 if (offset < 0) 4212 continue; 4213 ret = get_msr(cpu, offset, &msr_cur); 4214 if (ret) { 4215 fprintf(outf, "Can not update msr(0x%llx)\n", (unsigned long long)offset); 4216 continue; 4217 } 4218 4219 msr_last = per_cpu_msr_sum[cpu].entries[i].last; 4220 per_cpu_msr_sum[cpu].entries[i].last = msr_cur & 0xffffffff; 4221 4222 DELTA_WRAP32(msr_cur, msr_last); 4223 per_cpu_msr_sum[cpu].entries[i].sum += msr_last; 4224 } 4225 return 0; 4226 } 4227 4228 static void msr_record_handler(union sigval v) 4229 { 4230 UNUSED(v); 4231 4232 for_all_cpus(update_msr_sum, EVEN_COUNTERS); 4233 } 4234 4235 void msr_sum_record(void) 4236 { 4237 struct itimerspec its; 4238 struct sigevent sev; 4239 4240 per_cpu_msr_sum = calloc(topo.max_cpu_num + 1, sizeof(struct msr_sum_array)); 4241 if (!per_cpu_msr_sum) { 4242 fprintf(outf, "Can not allocate memory for long time MSR.\n"); 4243 return; 4244 } 4245 /* 4246 * Signal handler might be restricted, so use thread notifier instead. 4247 */ 4248 memset(&sev, 0, sizeof(struct sigevent)); 4249 sev.sigev_notify = SIGEV_THREAD; 4250 sev.sigev_notify_function = msr_record_handler; 4251 4252 sev.sigev_value.sival_ptr = &timerid; 4253 if (timer_create(CLOCK_REALTIME, &sev, &timerid) == -1) { 4254 fprintf(outf, "Can not create timer.\n"); 4255 goto release_msr; 4256 } 4257 4258 its.it_value.tv_sec = 0; 4259 its.it_value.tv_nsec = 1; 4260 /* 4261 * A wraparound time has been calculated early. 4262 * Some sources state that the peak power for a 4263 * microprocessor is usually 1.5 times the TDP rating, 4264 * use 2 * TDP for safety. 4265 */ 4266 its.it_interval.tv_sec = rapl_joule_counter_range / 2; 4267 its.it_interval.tv_nsec = 0; 4268 4269 if (timer_settime(timerid, 0, &its, NULL) == -1) { 4270 fprintf(outf, "Can not set timer.\n"); 4271 goto release_timer; 4272 } 4273 return; 4274 4275 release_timer: 4276 timer_delete(timerid); 4277 release_msr: 4278 free(per_cpu_msr_sum); 4279 } 4280 4281 /* 4282 * set_my_sched_priority(pri) 4283 * return previous 4284 */ 4285 int set_my_sched_priority(int priority) 4286 { 4287 int retval; 4288 int original_priority; 4289 4290 errno = 0; 4291 original_priority = getpriority(PRIO_PROCESS, 0); 4292 if (errno && (original_priority == -1)) 4293 err(errno, "getpriority"); 4294 4295 retval = setpriority(PRIO_PROCESS, 0, priority); 4296 if (retval) 4297 errx(retval, "capget(CAP_SYS_NICE) failed,try \"# setcap cap_sys_nice=ep %s\"", progname); 4298 4299 errno = 0; 4300 retval = getpriority(PRIO_PROCESS, 0); 4301 if (retval != priority) 4302 err(retval, "getpriority(%d) != setpriority(%d)", retval, priority); 4303 4304 return original_priority; 4305 } 4306 4307 void turbostat_loop() 4308 { 4309 int retval; 4310 int restarted = 0; 4311 unsigned int done_iters = 0; 4312 4313 setup_signal_handler(); 4314 4315 /* 4316 * elevate own priority for interval mode 4317 */ 4318 set_my_sched_priority(-20); 4319 4320 restart: 4321 restarted++; 4322 4323 snapshot_proc_sysfs_files(); 4324 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 4325 first_counter_read = 0; 4326 if (retval < -1) { 4327 exit(retval); 4328 } else if (retval == -1) { 4329 if (restarted > 10) { 4330 exit(retval); 4331 } 4332 re_initialize(); 4333 goto restart; 4334 } 4335 restarted = 0; 4336 done_iters = 0; 4337 gettimeofday(&tv_even, (struct timezone *)NULL); 4338 4339 while (1) { 4340 if (for_all_proc_cpus(cpu_is_not_present)) { 4341 re_initialize(); 4342 goto restart; 4343 } 4344 if (update_effective_str(false)) { 4345 re_initialize(); 4346 goto restart; 4347 } 4348 do_sleep(); 4349 if (snapshot_proc_sysfs_files()) 4350 goto restart; 4351 retval = for_all_cpus(get_counters, ODD_COUNTERS); 4352 if (retval < -1) { 4353 exit(retval); 4354 } else if (retval == -1) { 4355 re_initialize(); 4356 goto restart; 4357 } 4358 gettimeofday(&tv_odd, (struct timezone *)NULL); 4359 timersub(&tv_odd, &tv_even, &tv_delta); 4360 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) { 4361 re_initialize(); 4362 goto restart; 4363 } 4364 compute_average(EVEN_COUNTERS); 4365 format_all_counters(EVEN_COUNTERS); 4366 flush_output_stdout(); 4367 if (exit_requested) 4368 break; 4369 if (num_iterations && ++done_iters >= num_iterations) 4370 break; 4371 do_sleep(); 4372 if (snapshot_proc_sysfs_files()) 4373 goto restart; 4374 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 4375 if (retval < -1) { 4376 exit(retval); 4377 } else if (retval == -1) { 4378 re_initialize(); 4379 goto restart; 4380 } 4381 gettimeofday(&tv_even, (struct timezone *)NULL); 4382 timersub(&tv_even, &tv_odd, &tv_delta); 4383 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) { 4384 re_initialize(); 4385 goto restart; 4386 } 4387 compute_average(ODD_COUNTERS); 4388 format_all_counters(ODD_COUNTERS); 4389 flush_output_stdout(); 4390 if (exit_requested) 4391 break; 4392 if (num_iterations && ++done_iters >= num_iterations) 4393 break; 4394 } 4395 } 4396 4397 void check_dev_msr() 4398 { 4399 struct stat sb; 4400 char pathname[32]; 4401 4402 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 4403 if (stat(pathname, &sb)) 4404 if (system("/sbin/modprobe msr > /dev/null 2>&1")) 4405 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); 4406 } 4407 4408 /* 4409 * check for CAP_SYS_RAWIO 4410 * return 0 on success 4411 * return 1 on fail 4412 */ 4413 int check_for_cap_sys_rawio(void) 4414 { 4415 cap_t caps; 4416 cap_flag_value_t cap_flag_value; 4417 4418 caps = cap_get_proc(); 4419 if (caps == NULL) 4420 err(-6, "cap_get_proc\n"); 4421 4422 if (cap_get_flag(caps, CAP_SYS_RAWIO, CAP_EFFECTIVE, &cap_flag_value)) 4423 err(-6, "cap_get\n"); 4424 4425 if (cap_flag_value != CAP_SET) { 4426 warnx("capget(CAP_SYS_RAWIO) failed," " try \"# setcap cap_sys_rawio=ep %s\"", progname); 4427 return 1; 4428 } 4429 4430 if (cap_free(caps) == -1) 4431 err(-6, "cap_free\n"); 4432 4433 return 0; 4434 } 4435 4436 void check_permissions(void) 4437 { 4438 int do_exit = 0; 4439 char pathname[32]; 4440 4441 /* check for CAP_SYS_RAWIO */ 4442 do_exit += check_for_cap_sys_rawio(); 4443 4444 /* test file permissions */ 4445 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 4446 if (euidaccess(pathname, R_OK)) { 4447 do_exit++; 4448 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); 4449 } 4450 4451 /* if all else fails, thell them to be root */ 4452 if (do_exit) 4453 if (getuid() != 0) 4454 warnx("... or simply run as root"); 4455 4456 if (do_exit) 4457 exit(-6); 4458 } 4459 4460 void probe_bclk(void) 4461 { 4462 unsigned long long msr; 4463 unsigned int base_ratio; 4464 4465 if (!platform->has_nhm_msrs) 4466 return; 4467 4468 if (platform->bclk_freq == BCLK_100MHZ) 4469 bclk = 100.00; 4470 else if (platform->bclk_freq == BCLK_133MHZ) 4471 bclk = 133.33; 4472 else if (platform->bclk_freq == BCLK_SLV) 4473 bclk = slm_bclk(); 4474 else 4475 return; 4476 4477 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 4478 base_ratio = (msr >> 8) & 0xFF; 4479 4480 base_hz = base_ratio * bclk * 1000000; 4481 has_base_hz = 1; 4482 4483 if (platform->enable_tsc_tweak) 4484 tsc_tweak = base_hz / tsc_hz; 4485 } 4486 4487 static void remove_underbar(char *s) 4488 { 4489 char *to = s; 4490 4491 while (*s) { 4492 if (*s != '_') 4493 *to++ = *s; 4494 s++; 4495 } 4496 4497 *to = 0; 4498 } 4499 4500 static void dump_turbo_ratio_info(void) 4501 { 4502 if (!has_turbo) 4503 return; 4504 4505 if (!platform->has_nhm_msrs) 4506 return; 4507 4508 if (platform->trl_msrs & TRL_LIMIT2) 4509 dump_turbo_ratio_limit2(); 4510 4511 if (platform->trl_msrs & TRL_LIMIT1) 4512 dump_turbo_ratio_limit1(); 4513 4514 if (platform->trl_msrs & TRL_BASE) { 4515 dump_turbo_ratio_limits(MSR_TURBO_RATIO_LIMIT); 4516 4517 if (is_hybrid) 4518 dump_turbo_ratio_limits(MSR_SECONDARY_TURBO_RATIO_LIMIT); 4519 } 4520 4521 if (platform->trl_msrs & TRL_ATOM) 4522 dump_atom_turbo_ratio_limits(); 4523 4524 if (platform->trl_msrs & TRL_KNL) 4525 dump_knl_turbo_ratio_limits(); 4526 4527 if (platform->has_config_tdp) 4528 dump_config_tdp(); 4529 } 4530 4531 static int read_sysfs_int(char *path) 4532 { 4533 FILE *input; 4534 int retval = -1; 4535 4536 input = fopen(path, "r"); 4537 if (input == NULL) { 4538 if (debug) 4539 fprintf(outf, "NSFOD %s\n", path); 4540 return (-1); 4541 } 4542 if (fscanf(input, "%d", &retval) != 1) 4543 err(1, "%s: failed to read int from file", path); 4544 fclose(input); 4545 4546 return (retval); 4547 } 4548 4549 static void dump_sysfs_file(char *path) 4550 { 4551 FILE *input; 4552 char cpuidle_buf[64]; 4553 4554 input = fopen(path, "r"); 4555 if (input == NULL) { 4556 if (debug) 4557 fprintf(outf, "NSFOD %s\n", path); 4558 return; 4559 } 4560 if (!fgets(cpuidle_buf, sizeof(cpuidle_buf), input)) 4561 err(1, "%s: failed to read file", path); 4562 fclose(input); 4563 4564 fprintf(outf, "%s: %s", strrchr(path, '/') + 1, cpuidle_buf); 4565 } 4566 4567 static void probe_intel_uncore_frequency(void) 4568 { 4569 int i, j; 4570 char path[128]; 4571 4572 if (!genuine_intel) 4573 return; 4574 4575 if (access("/sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00", R_OK)) 4576 return; 4577 4578 /* Cluster level sysfs not supported yet. */ 4579 if (!access("/sys/devices/system/cpu/intel_uncore_frequency/uncore00", R_OK)) 4580 return; 4581 4582 if (!access("/sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00/current_freq_khz", R_OK)) 4583 BIC_PRESENT(BIC_UNCORE_MHZ); 4584 4585 if (quiet) 4586 return; 4587 4588 for (i = 0; i < topo.num_packages; ++i) { 4589 for (j = 0; j < topo.num_die; ++j) { 4590 int k, l; 4591 4592 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/min_freq_khz", 4593 i, j); 4594 k = read_sysfs_int(path); 4595 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/max_freq_khz", 4596 i, j); 4597 l = read_sysfs_int(path); 4598 fprintf(outf, "Uncore Frequency pkg%d die%d: %d - %d MHz ", i, j, k / 1000, l / 1000); 4599 4600 sprintf(path, 4601 "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/initial_min_freq_khz", 4602 i, j); 4603 k = read_sysfs_int(path); 4604 sprintf(path, 4605 "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/initial_max_freq_khz", 4606 i, j); 4607 l = read_sysfs_int(path); 4608 fprintf(outf, "(%d - %d MHz)\n", k / 1000, l / 1000); 4609 } 4610 } 4611 } 4612 4613 static void probe_graphics(void) 4614 { 4615 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK)) 4616 BIC_PRESENT(BIC_GFX_rc6); 4617 4618 if (!access("/sys/class/drm/card0/gt_cur_freq_mhz", R_OK) || 4619 !access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK)) 4620 BIC_PRESENT(BIC_GFXMHz); 4621 4622 if (!access("/sys/class/drm/card0/gt_act_freq_mhz", R_OK) || 4623 !access("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", R_OK)) 4624 BIC_PRESENT(BIC_GFXACTMHz); 4625 } 4626 4627 static void dump_sysfs_cstate_config(void) 4628 { 4629 char path[64]; 4630 char name_buf[16]; 4631 char desc[64]; 4632 FILE *input; 4633 int state; 4634 char *sp; 4635 4636 if (access("/sys/devices/system/cpu/cpuidle", R_OK)) { 4637 fprintf(outf, "cpuidle not loaded\n"); 4638 return; 4639 } 4640 4641 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_driver"); 4642 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor"); 4643 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor_ro"); 4644 4645 for (state = 0; state < 10; ++state) { 4646 4647 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state); 4648 input = fopen(path, "r"); 4649 if (input == NULL) 4650 continue; 4651 if (!fgets(name_buf, sizeof(name_buf), input)) 4652 err(1, "%s: failed to read file", path); 4653 4654 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 4655 sp = strchr(name_buf, '-'); 4656 if (!sp) 4657 sp = strchrnul(name_buf, '\n'); 4658 *sp = '\0'; 4659 fclose(input); 4660 4661 remove_underbar(name_buf); 4662 4663 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc", base_cpu, state); 4664 input = fopen(path, "r"); 4665 if (input == NULL) 4666 continue; 4667 if (!fgets(desc, sizeof(desc), input)) 4668 err(1, "%s: failed to read file", path); 4669 4670 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc); 4671 fclose(input); 4672 } 4673 } 4674 4675 static void dump_sysfs_pstate_config(void) 4676 { 4677 char path[64]; 4678 char driver_buf[64]; 4679 char governor_buf[64]; 4680 FILE *input; 4681 int turbo; 4682 4683 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver", base_cpu); 4684 input = fopen(path, "r"); 4685 if (input == NULL) { 4686 fprintf(outf, "NSFOD %s\n", path); 4687 return; 4688 } 4689 if (!fgets(driver_buf, sizeof(driver_buf), input)) 4690 err(1, "%s: failed to read file", path); 4691 fclose(input); 4692 4693 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor", base_cpu); 4694 input = fopen(path, "r"); 4695 if (input == NULL) { 4696 fprintf(outf, "NSFOD %s\n", path); 4697 return; 4698 } 4699 if (!fgets(governor_buf, sizeof(governor_buf), input)) 4700 err(1, "%s: failed to read file", path); 4701 fclose(input); 4702 4703 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf); 4704 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf); 4705 4706 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost"); 4707 input = fopen(path, "r"); 4708 if (input != NULL) { 4709 if (fscanf(input, "%d", &turbo) != 1) 4710 err(1, "%s: failed to parse number from file", path); 4711 fprintf(outf, "cpufreq boost: %d\n", turbo); 4712 fclose(input); 4713 } 4714 4715 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo"); 4716 input = fopen(path, "r"); 4717 if (input != NULL) { 4718 if (fscanf(input, "%d", &turbo) != 1) 4719 err(1, "%s: failed to parse number from file", path); 4720 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo); 4721 fclose(input); 4722 } 4723 } 4724 4725 /* 4726 * print_epb() 4727 * Decode the ENERGY_PERF_BIAS MSR 4728 */ 4729 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4730 { 4731 char *epb_string; 4732 int cpu, epb; 4733 4734 UNUSED(c); 4735 UNUSED(p); 4736 4737 if (!has_epb) 4738 return 0; 4739 4740 cpu = t->cpu_id; 4741 4742 /* EPB is per-package */ 4743 if (!is_cpu_first_thread_in_package(t, c, p)) 4744 return 0; 4745 4746 if (cpu_migrate(cpu)) { 4747 fprintf(outf, "print_epb: Could not migrate to CPU %d\n", cpu); 4748 return -1; 4749 } 4750 4751 epb = get_epb(cpu); 4752 if (epb < 0) 4753 return 0; 4754 4755 switch (epb) { 4756 case ENERGY_PERF_BIAS_PERFORMANCE: 4757 epb_string = "performance"; 4758 break; 4759 case ENERGY_PERF_BIAS_NORMAL: 4760 epb_string = "balanced"; 4761 break; 4762 case ENERGY_PERF_BIAS_POWERSAVE: 4763 epb_string = "powersave"; 4764 break; 4765 default: 4766 epb_string = "custom"; 4767 break; 4768 } 4769 fprintf(outf, "cpu%d: EPB: %d (%s)\n", cpu, epb, epb_string); 4770 4771 return 0; 4772 } 4773 4774 /* 4775 * print_hwp() 4776 * Decode the MSR_HWP_CAPABILITIES 4777 */ 4778 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4779 { 4780 unsigned long long msr; 4781 int cpu; 4782 4783 UNUSED(c); 4784 UNUSED(p); 4785 4786 if (!has_hwp) 4787 return 0; 4788 4789 cpu = t->cpu_id; 4790 4791 /* MSR_HWP_CAPABILITIES is per-package */ 4792 if (!is_cpu_first_thread_in_package(t, c, p)) 4793 return 0; 4794 4795 if (cpu_migrate(cpu)) { 4796 fprintf(outf, "print_hwp: Could not migrate to CPU %d\n", cpu); 4797 return -1; 4798 } 4799 4800 if (get_msr(cpu, MSR_PM_ENABLE, &msr)) 4801 return 0; 4802 4803 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", cpu, msr, (msr & (1 << 0)) ? "" : "No-"); 4804 4805 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ 4806 if ((msr & (1 << 0)) == 0) 4807 return 0; 4808 4809 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) 4810 return 0; 4811 4812 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " 4813 "(high %d guar %d eff %d low %d)\n", 4814 cpu, msr, 4815 (unsigned int)HWP_HIGHEST_PERF(msr), 4816 (unsigned int)HWP_GUARANTEED_PERF(msr), 4817 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), (unsigned int)HWP_LOWEST_PERF(msr)); 4818 4819 if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) 4820 return 0; 4821 4822 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " 4823 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n", 4824 cpu, msr, 4825 (unsigned int)(((msr) >> 0) & 0xff), 4826 (unsigned int)(((msr) >> 8) & 0xff), 4827 (unsigned int)(((msr) >> 16) & 0xff), 4828 (unsigned int)(((msr) >> 24) & 0xff), 4829 (unsigned int)(((msr) >> 32) & 0xff3), (unsigned int)(((msr) >> 42) & 0x1)); 4830 4831 if (has_hwp_pkg) { 4832 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) 4833 return 0; 4834 4835 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " 4836 "(min %d max %d des %d epp 0x%x window 0x%x)\n", 4837 cpu, msr, 4838 (unsigned int)(((msr) >> 0) & 0xff), 4839 (unsigned int)(((msr) >> 8) & 0xff), 4840 (unsigned int)(((msr) >> 16) & 0xff), 4841 (unsigned int)(((msr) >> 24) & 0xff), (unsigned int)(((msr) >> 32) & 0xff3)); 4842 } 4843 if (has_hwp_notify) { 4844 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) 4845 return 0; 4846 4847 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " 4848 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", 4849 cpu, msr, ((msr) & 0x1) ? "EN" : "Dis", ((msr) & 0x2) ? "EN" : "Dis"); 4850 } 4851 if (get_msr(cpu, MSR_HWP_STATUS, &msr)) 4852 return 0; 4853 4854 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " 4855 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", 4856 cpu, msr, ((msr) & 0x1) ? "" : "No-", ((msr) & 0x4) ? "" : "No-"); 4857 4858 return 0; 4859 } 4860 4861 /* 4862 * print_perf_limit() 4863 */ 4864 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4865 { 4866 unsigned long long msr; 4867 int cpu; 4868 4869 UNUSED(c); 4870 UNUSED(p); 4871 4872 cpu = t->cpu_id; 4873 4874 /* per-package */ 4875 if (!is_cpu_first_thread_in_package(t, c, p)) 4876 return 0; 4877 4878 if (cpu_migrate(cpu)) { 4879 fprintf(outf, "print_perf_limit: Could not migrate to CPU %d\n", cpu); 4880 return -1; 4881 } 4882 4883 if (platform->plr_msrs & PLR_CORE) { 4884 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); 4885 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4886 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", 4887 (msr & 1 << 15) ? "bit15, " : "", 4888 (msr & 1 << 14) ? "bit14, " : "", 4889 (msr & 1 << 13) ? "Transitions, " : "", 4890 (msr & 1 << 12) ? "MultiCoreTurbo, " : "", 4891 (msr & 1 << 11) ? "PkgPwrL2, " : "", 4892 (msr & 1 << 10) ? "PkgPwrL1, " : "", 4893 (msr & 1 << 9) ? "CorePwr, " : "", 4894 (msr & 1 << 8) ? "Amps, " : "", 4895 (msr & 1 << 6) ? "VR-Therm, " : "", 4896 (msr & 1 << 5) ? "Auto-HWP, " : "", 4897 (msr & 1 << 4) ? "Graphics, " : "", 4898 (msr & 1 << 2) ? "bit2, " : "", 4899 (msr & 1 << 1) ? "ThermStatus, " : "", (msr & 1 << 0) ? "PROCHOT, " : ""); 4900 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 4901 (msr & 1 << 31) ? "bit31, " : "", 4902 (msr & 1 << 30) ? "bit30, " : "", 4903 (msr & 1 << 29) ? "Transitions, " : "", 4904 (msr & 1 << 28) ? "MultiCoreTurbo, " : "", 4905 (msr & 1 << 27) ? "PkgPwrL2, " : "", 4906 (msr & 1 << 26) ? "PkgPwrL1, " : "", 4907 (msr & 1 << 25) ? "CorePwr, " : "", 4908 (msr & 1 << 24) ? "Amps, " : "", 4909 (msr & 1 << 22) ? "VR-Therm, " : "", 4910 (msr & 1 << 21) ? "Auto-HWP, " : "", 4911 (msr & 1 << 20) ? "Graphics, " : "", 4912 (msr & 1 << 18) ? "bit18, " : "", 4913 (msr & 1 << 17) ? "ThermStatus, " : "", (msr & 1 << 16) ? "PROCHOT, " : ""); 4914 4915 } 4916 if (platform->plr_msrs & PLR_GFX) { 4917 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); 4918 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4919 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", 4920 (msr & 1 << 0) ? "PROCHOT, " : "", 4921 (msr & 1 << 1) ? "ThermStatus, " : "", 4922 (msr & 1 << 4) ? "Graphics, " : "", 4923 (msr & 1 << 6) ? "VR-Therm, " : "", 4924 (msr & 1 << 8) ? "Amps, " : "", 4925 (msr & 1 << 9) ? "GFXPwr, " : "", 4926 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : ""); 4927 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", 4928 (msr & 1 << 16) ? "PROCHOT, " : "", 4929 (msr & 1 << 17) ? "ThermStatus, " : "", 4930 (msr & 1 << 20) ? "Graphics, " : "", 4931 (msr & 1 << 22) ? "VR-Therm, " : "", 4932 (msr & 1 << 24) ? "Amps, " : "", 4933 (msr & 1 << 25) ? "GFXPwr, " : "", 4934 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : ""); 4935 } 4936 if (platform->plr_msrs & PLR_RING) { 4937 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); 4938 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4939 fprintf(outf, " (Active: %s%s%s%s%s%s)", 4940 (msr & 1 << 0) ? "PROCHOT, " : "", 4941 (msr & 1 << 1) ? "ThermStatus, " : "", 4942 (msr & 1 << 6) ? "VR-Therm, " : "", 4943 (msr & 1 << 8) ? "Amps, " : "", 4944 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : ""); 4945 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", 4946 (msr & 1 << 16) ? "PROCHOT, " : "", 4947 (msr & 1 << 17) ? "ThermStatus, " : "", 4948 (msr & 1 << 22) ? "VR-Therm, " : "", 4949 (msr & 1 << 24) ? "Amps, " : "", 4950 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : ""); 4951 } 4952 return 0; 4953 } 4954 4955 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ 4956 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ 4957 4958 double get_quirk_tdp(void) 4959 { 4960 if (platform->rapl_quirk_tdp) 4961 return platform->rapl_quirk_tdp; 4962 4963 return 135.0; 4964 } 4965 4966 double get_tdp_intel(void) 4967 { 4968 unsigned long long msr; 4969 4970 if (platform->rapl_msrs & RAPL_PKG_POWER_INFO) 4971 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) 4972 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; 4973 return get_quirk_tdp(); 4974 } 4975 4976 double get_tdp_amd(void) 4977 { 4978 return get_quirk_tdp(); 4979 } 4980 4981 void rapl_probe_intel(void) 4982 { 4983 unsigned long long msr; 4984 unsigned int time_unit; 4985 double tdp; 4986 4987 if (rapl_joules) { 4988 if (platform->rapl_msrs & RAPL_PKG_ENERGY_STATUS) 4989 BIC_PRESENT(BIC_Pkg_J); 4990 if (platform->rapl_msrs & RAPL_CORE_ENERGY_STATUS) 4991 BIC_PRESENT(BIC_Cor_J); 4992 if (platform->rapl_msrs & RAPL_DRAM_ENERGY_STATUS) 4993 BIC_PRESENT(BIC_RAM_J); 4994 if (platform->rapl_msrs & RAPL_GFX_ENERGY_STATUS) 4995 BIC_PRESENT(BIC_GFX_J); 4996 } else { 4997 if (platform->rapl_msrs & RAPL_PKG_ENERGY_STATUS) 4998 BIC_PRESENT(BIC_PkgWatt); 4999 if (platform->rapl_msrs & RAPL_CORE_ENERGY_STATUS) 5000 BIC_PRESENT(BIC_CorWatt); 5001 if (platform->rapl_msrs & RAPL_DRAM_ENERGY_STATUS) 5002 BIC_PRESENT(BIC_RAMWatt); 5003 if (platform->rapl_msrs & RAPL_GFX_ENERGY_STATUS) 5004 BIC_PRESENT(BIC_GFXWatt); 5005 } 5006 5007 if (platform->rapl_msrs & RAPL_PKG_PERF_STATUS) 5008 BIC_PRESENT(BIC_PKG__); 5009 if (platform->rapl_msrs & RAPL_DRAM_PERF_STATUS) 5010 BIC_PRESENT(BIC_RAM__); 5011 5012 /* units on package 0, verify later other packages match */ 5013 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) 5014 return; 5015 5016 rapl_power_units = 1.0 / (1 << (msr & 0xF)); 5017 if (platform->has_rapl_divisor) 5018 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; 5019 else 5020 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 5021 5022 if (platform->has_fixed_rapl_unit) 5023 rapl_dram_energy_units = (15.3 / 1000000); 5024 else 5025 rapl_dram_energy_units = rapl_energy_units; 5026 5027 time_unit = msr >> 16 & 0xF; 5028 if (time_unit == 0) 5029 time_unit = 0xA; 5030 5031 rapl_time_units = 1.0 / (1 << (time_unit)); 5032 5033 tdp = get_tdp_intel(); 5034 5035 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 5036 if (!quiet) 5037 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 5038 } 5039 5040 void rapl_probe_amd(void) 5041 { 5042 unsigned long long msr; 5043 double tdp; 5044 5045 if (rapl_joules) { 5046 BIC_PRESENT(BIC_Pkg_J); 5047 BIC_PRESENT(BIC_Cor_J); 5048 } else { 5049 BIC_PRESENT(BIC_PkgWatt); 5050 BIC_PRESENT(BIC_CorWatt); 5051 } 5052 5053 if (get_msr(base_cpu, MSR_RAPL_PWR_UNIT, &msr)) 5054 return; 5055 5056 rapl_time_units = ldexp(1.0, -(msr >> 16 & 0xf)); 5057 rapl_energy_units = ldexp(1.0, -(msr >> 8 & 0x1f)); 5058 rapl_power_units = ldexp(1.0, -(msr & 0xf)); 5059 5060 tdp = get_tdp_amd(); 5061 5062 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 5063 if (!quiet) 5064 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 5065 } 5066 5067 void print_power_limit_msr(int cpu, unsigned long long msr, char *label) 5068 { 5069 fprintf(outf, "cpu%d: %s: %sabled (%0.3f Watts, %f sec, clamp %sabled)\n", 5070 cpu, label, 5071 ((msr >> 15) & 1) ? "EN" : "DIS", 5072 ((msr >> 0) & 0x7FFF) * rapl_power_units, 5073 (1.0 + (((msr >> 22) & 0x3) / 4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, 5074 (((msr >> 16) & 1) ? "EN" : "DIS")); 5075 5076 return; 5077 } 5078 5079 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 5080 { 5081 unsigned long long msr; 5082 const char *msr_name; 5083 int cpu; 5084 5085 UNUSED(c); 5086 UNUSED(p); 5087 5088 if (!platform->rapl_msrs) 5089 return 0; 5090 5091 /* RAPL counters are per package, so print only for 1st thread/package */ 5092 if (!is_cpu_first_thread_in_package(t, c, p)) 5093 return 0; 5094 5095 cpu = t->cpu_id; 5096 if (cpu_migrate(cpu)) { 5097 fprintf(outf, "print_rapl: Could not migrate to CPU %d\n", cpu); 5098 return -1; 5099 } 5100 5101 if (platform->rapl_msrs & RAPL_AMD_F17H) { 5102 msr_name = "MSR_RAPL_PWR_UNIT"; 5103 if (get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr)) 5104 return -1; 5105 } else { 5106 msr_name = "MSR_RAPL_POWER_UNIT"; 5107 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) 5108 return -1; 5109 } 5110 5111 fprintf(outf, "cpu%d: %s: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr_name, msr, 5112 rapl_power_units, rapl_energy_units, rapl_time_units); 5113 5114 if (platform->rapl_msrs & RAPL_PKG_POWER_INFO) { 5115 5116 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) 5117 return -5; 5118 5119 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 5120 cpu, msr, 5121 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 5122 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 5123 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 5124 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 5125 5126 } 5127 if (platform->rapl_msrs & RAPL_PKG) { 5128 5129 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) 5130 return -9; 5131 5132 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", 5133 cpu, msr, (msr >> 63) & 1 ? "" : "UN"); 5134 5135 print_power_limit_msr(cpu, msr, "PKG Limit #1"); 5136 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%0.3f Watts, %f* sec, clamp %sabled)\n", 5137 cpu, 5138 ((msr >> 47) & 1) ? "EN" : "DIS", 5139 ((msr >> 32) & 0x7FFF) * rapl_power_units, 5140 (1.0 + (((msr >> 54) & 0x3) / 4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, 5141 ((msr >> 48) & 1) ? "EN" : "DIS"); 5142 5143 if (get_msr(cpu, MSR_VR_CURRENT_CONFIG, &msr)) 5144 return -9; 5145 5146 fprintf(outf, "cpu%d: MSR_VR_CURRENT_CONFIG: 0x%08llx\n", cpu, msr); 5147 fprintf(outf, "cpu%d: PKG Limit #4: %f Watts (%slocked)\n", 5148 cpu, ((msr >> 0) & 0x1FFF) * rapl_power_units, (msr >> 31) & 1 ? "" : "UN"); 5149 } 5150 5151 if (platform->rapl_msrs & RAPL_DRAM_POWER_INFO) { 5152 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) 5153 return -6; 5154 5155 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 5156 cpu, msr, 5157 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 5158 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 5159 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 5160 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 5161 } 5162 if (platform->rapl_msrs & RAPL_DRAM) { 5163 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) 5164 return -9; 5165 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", 5166 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 5167 5168 print_power_limit_msr(cpu, msr, "DRAM Limit"); 5169 } 5170 if (platform->rapl_msrs & RAPL_CORE_POLICY) { 5171 if (get_msr(cpu, MSR_PP0_POLICY, &msr)) 5172 return -7; 5173 5174 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); 5175 } 5176 if (platform->rapl_msrs & RAPL_CORE_POWER_LIMIT) { 5177 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) 5178 return -9; 5179 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", 5180 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 5181 print_power_limit_msr(cpu, msr, "Cores Limit"); 5182 } 5183 if (platform->rapl_msrs & RAPL_GFX) { 5184 if (get_msr(cpu, MSR_PP1_POLICY, &msr)) 5185 return -8; 5186 5187 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); 5188 5189 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) 5190 return -9; 5191 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", 5192 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 5193 print_power_limit_msr(cpu, msr, "GFX Limit"); 5194 } 5195 return 0; 5196 } 5197 5198 /* 5199 * probe_rapl() 5200 * 5201 * sets rapl_power_units, rapl_energy_units, rapl_time_units 5202 */ 5203 void probe_rapl(void) 5204 { 5205 if (!platform->rapl_msrs) 5206 return; 5207 5208 if (genuine_intel) 5209 rapl_probe_intel(); 5210 if (authentic_amd || hygon_genuine) 5211 rapl_probe_amd(); 5212 5213 if (quiet) 5214 return; 5215 5216 for_all_cpus(print_rapl, ODD_COUNTERS); 5217 } 5218 5219 /* 5220 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where 5221 * the Thermal Control Circuit (TCC) activates. 5222 * This is usually equal to tjMax. 5223 * 5224 * Older processors do not have this MSR, so there we guess, 5225 * but also allow cmdline over-ride with -T. 5226 * 5227 * Several MSR temperature values are in units of degrees-C 5228 * below this value, including the Digital Thermal Sensor (DTS), 5229 * Package Thermal Management Sensor (PTM), and thermal event thresholds. 5230 */ 5231 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 5232 { 5233 unsigned long long msr; 5234 unsigned int tcc_default, tcc_offset; 5235 int cpu; 5236 5237 UNUSED(c); 5238 UNUSED(p); 5239 5240 /* tj_max is used only for dts or ptm */ 5241 if (!(do_dts || do_ptm)) 5242 return 0; 5243 5244 /* this is a per-package concept */ 5245 if (!is_cpu_first_thread_in_package(t, c, p)) 5246 return 0; 5247 5248 cpu = t->cpu_id; 5249 if (cpu_migrate(cpu)) { 5250 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 5251 return -1; 5252 } 5253 5254 if (tj_max_override != 0) { 5255 tj_max = tj_max_override; 5256 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", cpu, tj_max); 5257 return 0; 5258 } 5259 5260 /* Temperature Target MSR is Nehalem and newer only */ 5261 if (!platform->has_nhm_msrs) 5262 goto guess; 5263 5264 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) 5265 goto guess; 5266 5267 tcc_default = (msr >> 16) & 0xFF; 5268 5269 if (!quiet) { 5270 int bits = platform->tcc_offset_bits; 5271 unsigned long long enabled = 0; 5272 5273 if (bits && !get_msr(base_cpu, MSR_PLATFORM_INFO, &enabled)) 5274 enabled = (enabled >> 30) & 1; 5275 5276 if (bits && enabled) { 5277 tcc_offset = (msr >> 24) & GENMASK(bits - 1, 0); 5278 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n", 5279 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset); 5280 } else { 5281 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", cpu, msr, tcc_default); 5282 } 5283 } 5284 5285 if (!tcc_default) 5286 goto guess; 5287 5288 tj_max = tcc_default; 5289 5290 return 0; 5291 5292 guess: 5293 tj_max = TJMAX_DEFAULT; 5294 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", cpu, tj_max); 5295 5296 return 0; 5297 } 5298 5299 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 5300 { 5301 unsigned long long msr; 5302 unsigned int dts, dts2; 5303 int cpu; 5304 5305 UNUSED(c); 5306 UNUSED(p); 5307 5308 if (!(do_dts || do_ptm)) 5309 return 0; 5310 5311 cpu = t->cpu_id; 5312 5313 /* DTS is per-core, no need to print for each thread */ 5314 if (!is_cpu_first_thread_in_core(t, c, p)) 5315 return 0; 5316 5317 if (cpu_migrate(cpu)) { 5318 fprintf(outf, "print_thermal: Could not migrate to CPU %d\n", cpu); 5319 return -1; 5320 } 5321 5322 if (do_ptm && is_cpu_first_core_in_package(t, c, p)) { 5323 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 5324 return 0; 5325 5326 dts = (msr >> 16) & 0x7F; 5327 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", cpu, msr, tj_max - dts); 5328 5329 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) 5330 return 0; 5331 5332 dts = (msr >> 16) & 0x7F; 5333 dts2 = (msr >> 8) & 0x7F; 5334 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 5335 cpu, msr, tj_max - dts, tj_max - dts2); 5336 } 5337 5338 if (do_dts && debug) { 5339 unsigned int resolution; 5340 5341 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 5342 return 0; 5343 5344 dts = (msr >> 16) & 0x7F; 5345 resolution = (msr >> 27) & 0xF; 5346 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", 5347 cpu, msr, tj_max - dts, resolution); 5348 5349 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) 5350 return 0; 5351 5352 dts = (msr >> 16) & 0x7F; 5353 dts2 = (msr >> 8) & 0x7F; 5354 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 5355 cpu, msr, tj_max - dts, tj_max - dts2); 5356 } 5357 5358 return 0; 5359 } 5360 5361 void probe_thermal(void) 5362 { 5363 if (!access("/sys/devices/system/cpu/cpu0/thermal_throttle/core_throttle_count", R_OK)) 5364 BIC_PRESENT(BIC_CORE_THROT_CNT); 5365 else 5366 BIC_NOT_PRESENT(BIC_CORE_THROT_CNT); 5367 5368 for_all_cpus(set_temperature_target, ODD_COUNTERS); 5369 5370 if (quiet) 5371 return; 5372 5373 for_all_cpus(print_thermal, ODD_COUNTERS); 5374 } 5375 5376 int get_cpu_type(struct thread_data *t, struct core_data *c, struct pkg_data *p) 5377 { 5378 unsigned int eax, ebx, ecx, edx; 5379 5380 UNUSED(c); 5381 UNUSED(p); 5382 5383 if (!genuine_intel) 5384 return 0; 5385 5386 if (cpu_migrate(t->cpu_id)) { 5387 fprintf(outf, "Could not migrate to CPU %d\n", t->cpu_id); 5388 return -1; 5389 } 5390 5391 if (max_level < 0x1a) 5392 return 0; 5393 5394 __cpuid(0x1a, eax, ebx, ecx, edx); 5395 eax = (eax >> 24) & 0xFF; 5396 if (eax == 0x20) 5397 t->is_atom = true; 5398 return 0; 5399 } 5400 5401 void decode_feature_control_msr(void) 5402 { 5403 unsigned long long msr; 5404 5405 if (!get_msr(base_cpu, MSR_IA32_FEAT_CTL, &msr)) 5406 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", 5407 base_cpu, msr, msr & FEAT_CTL_LOCKED ? "" : "UN-", msr & (1 << 18) ? "SGX" : ""); 5408 } 5409 5410 void decode_misc_enable_msr(void) 5411 { 5412 unsigned long long msr; 5413 5414 if (!genuine_intel) 5415 return; 5416 5417 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) 5418 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n", 5419 base_cpu, msr, 5420 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-", 5421 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-", 5422 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-", 5423 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "", 5424 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : ""); 5425 } 5426 5427 void decode_misc_feature_control(void) 5428 { 5429 unsigned long long msr; 5430 5431 if (!platform->has_msr_misc_feature_control) 5432 return; 5433 5434 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr)) 5435 fprintf(outf, 5436 "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n", 5437 base_cpu, msr, msr & (0 << 0) ? "No-" : "", msr & (1 << 0) ? "No-" : "", 5438 msr & (2 << 0) ? "No-" : "", msr & (3 << 0) ? "No-" : ""); 5439 } 5440 5441 /* 5442 * Decode MSR_MISC_PWR_MGMT 5443 * 5444 * Decode the bits according to the Nehalem documentation 5445 * bit[0] seems to continue to have same meaning going forward 5446 * bit[1] less so... 5447 */ 5448 void decode_misc_pwr_mgmt_msr(void) 5449 { 5450 unsigned long long msr; 5451 5452 if (!platform->has_msr_misc_pwr_mgmt) 5453 return; 5454 5455 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) 5456 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n", 5457 base_cpu, msr, 5458 msr & (1 << 0) ? "DIS" : "EN", msr & (1 << 1) ? "EN" : "DIS", msr & (1 << 8) ? "EN" : "DIS"); 5459 } 5460 5461 /* 5462 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG 5463 * 5464 * This MSRs are present on Silvermont processors, 5465 * Intel Atom processor E3000 series (Baytrail), and friends. 5466 */ 5467 void decode_c6_demotion_policy_msr(void) 5468 { 5469 unsigned long long msr; 5470 5471 if (!platform->has_msr_c6_demotion_policy_config) 5472 return; 5473 5474 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr)) 5475 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n", 5476 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 5477 5478 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr)) 5479 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n", 5480 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 5481 } 5482 5483 void print_dev_latency(void) 5484 { 5485 char *path = "/dev/cpu_dma_latency"; 5486 int fd; 5487 int value; 5488 int retval; 5489 5490 fd = open(path, O_RDONLY); 5491 if (fd < 0) { 5492 warnx("capget(CAP_SYS_ADMIN) failed, try \"# setcap cap_sys_admin=ep %s\"", progname); 5493 return; 5494 } 5495 5496 retval = read(fd, (void *)&value, sizeof(int)); 5497 if (retval != sizeof(int)) { 5498 warn("read failed %s", path); 5499 close(fd); 5500 return; 5501 } 5502 fprintf(outf, "/dev/cpu_dma_latency: %d usec (%s)\n", value, value == 2000000000 ? "default" : "constrained"); 5503 5504 close(fd); 5505 } 5506 5507 /* 5508 * Linux-perf manages the HW instructions-retired counter 5509 * by enabling when requested, and hiding rollover 5510 */ 5511 void linux_perf_init(void) 5512 { 5513 if (!BIC_IS_ENABLED(BIC_IPC)) 5514 return; 5515 5516 if (access("/proc/sys/kernel/perf_event_paranoid", F_OK)) 5517 return; 5518 5519 fd_instr_count_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 5520 if (fd_instr_count_percpu == NULL) 5521 err(-1, "calloc fd_instr_count_percpu"); 5522 5523 BIC_PRESENT(BIC_IPC); 5524 } 5525 5526 void probe_cstates(void) 5527 { 5528 probe_cst_limit(); 5529 5530 if (platform->supported_cstates & CC1) 5531 BIC_PRESENT(BIC_CPU_c1); 5532 5533 if (platform->supported_cstates & CC3) 5534 BIC_PRESENT(BIC_CPU_c3); 5535 5536 if (platform->supported_cstates & CC6) 5537 BIC_PRESENT(BIC_CPU_c6); 5538 5539 if (platform->supported_cstates & CC7) 5540 BIC_PRESENT(BIC_CPU_c7); 5541 5542 if (platform->supported_cstates & PC2 && (pkg_cstate_limit >= PCL__2)) 5543 BIC_PRESENT(BIC_Pkgpc2); 5544 5545 if (platform->supported_cstates & PC3 && (pkg_cstate_limit >= PCL__3)) 5546 BIC_PRESENT(BIC_Pkgpc3); 5547 5548 if (platform->supported_cstates & PC6 && (pkg_cstate_limit >= PCL__6)) 5549 BIC_PRESENT(BIC_Pkgpc6); 5550 5551 if (platform->supported_cstates & PC7 && (pkg_cstate_limit >= PCL__7)) 5552 BIC_PRESENT(BIC_Pkgpc7); 5553 5554 if (platform->supported_cstates & PC8 && (pkg_cstate_limit >= PCL__8)) 5555 BIC_PRESENT(BIC_Pkgpc8); 5556 5557 if (platform->supported_cstates & PC9 && (pkg_cstate_limit >= PCL__9)) 5558 BIC_PRESENT(BIC_Pkgpc9); 5559 5560 if (platform->supported_cstates & PC10 && (pkg_cstate_limit >= PCL_10)) 5561 BIC_PRESENT(BIC_Pkgpc10); 5562 5563 if (platform->has_msr_module_c6_res_ms) 5564 BIC_PRESENT(BIC_Mod_c6); 5565 5566 if (platform->has_ext_cst_msrs) { 5567 BIC_PRESENT(BIC_Totl_c0); 5568 BIC_PRESENT(BIC_Any_c0); 5569 BIC_PRESENT(BIC_GFX_c0); 5570 BIC_PRESENT(BIC_CPUGFX); 5571 } 5572 5573 if (quiet) 5574 return; 5575 5576 dump_power_ctl(); 5577 dump_cst_cfg(); 5578 decode_c6_demotion_policy_msr(); 5579 print_dev_latency(); 5580 dump_sysfs_cstate_config(); 5581 print_irtl(); 5582 } 5583 5584 void probe_lpi(void) 5585 { 5586 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK)) 5587 BIC_PRESENT(BIC_CPU_LPI); 5588 else 5589 BIC_NOT_PRESENT(BIC_CPU_LPI); 5590 5591 if (!access(sys_lpi_file_sysfs, R_OK)) { 5592 sys_lpi_file = sys_lpi_file_sysfs; 5593 BIC_PRESENT(BIC_SYS_LPI); 5594 } else if (!access(sys_lpi_file_debugfs, R_OK)) { 5595 sys_lpi_file = sys_lpi_file_debugfs; 5596 BIC_PRESENT(BIC_SYS_LPI); 5597 } else { 5598 sys_lpi_file_sysfs = NULL; 5599 BIC_NOT_PRESENT(BIC_SYS_LPI); 5600 } 5601 5602 } 5603 5604 void probe_pstates(void) 5605 { 5606 probe_bclk(); 5607 5608 if (quiet) 5609 return; 5610 5611 dump_platform_info(); 5612 dump_turbo_ratio_info(); 5613 dump_sysfs_pstate_config(); 5614 decode_misc_pwr_mgmt_msr(); 5615 5616 for_all_cpus(print_hwp, ODD_COUNTERS); 5617 for_all_cpus(print_epb, ODD_COUNTERS); 5618 for_all_cpus(print_perf_limit, ODD_COUNTERS); 5619 } 5620 5621 void process_cpuid() 5622 { 5623 unsigned int eax, ebx, ecx, edx; 5624 unsigned int fms, family, model, stepping, ecx_flags, edx_flags; 5625 unsigned long long ucode_patch = 0; 5626 5627 eax = ebx = ecx = edx = 0; 5628 5629 __cpuid(0, max_level, ebx, ecx, edx); 5630 5631 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69) 5632 genuine_intel = 1; 5633 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) 5634 authentic_amd = 1; 5635 else if (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e) 5636 hygon_genuine = 1; 5637 5638 if (!quiet) 5639 fprintf(outf, "CPUID(0): %.4s%.4s%.4s 0x%x CPUID levels\n", 5640 (char *)&ebx, (char *)&edx, (char *)&ecx, max_level); 5641 5642 __cpuid(1, fms, ebx, ecx, edx); 5643 family = (fms >> 8) & 0xf; 5644 model = (fms >> 4) & 0xf; 5645 stepping = fms & 0xf; 5646 if (family == 0xf) 5647 family += (fms >> 20) & 0xff; 5648 if (family >= 6) 5649 model += ((fms >> 16) & 0xf) << 4; 5650 ecx_flags = ecx; 5651 edx_flags = edx; 5652 5653 if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch)) 5654 warnx("get_msr(UCODE)"); 5655 5656 /* 5657 * check max extended function levels of CPUID. 5658 * This is needed to check for invariant TSC. 5659 * This check is valid for both Intel and AMD. 5660 */ 5661 ebx = ecx = edx = 0; 5662 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); 5663 5664 if (!quiet) { 5665 fprintf(outf, "CPUID(1): family:model:stepping 0x%x:%x:%x (%d:%d:%d) microcode 0x%x\n", 5666 family, model, stepping, family, model, stepping, 5667 (unsigned int)((ucode_patch >> 32) & 0xFFFFFFFF)); 5668 fprintf(outf, "CPUID(0x80000000): max_extended_levels: 0x%x\n", max_extended_level); 5669 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n", 5670 ecx_flags & (1 << 0) ? "SSE3" : "-", 5671 ecx_flags & (1 << 3) ? "MONITOR" : "-", 5672 ecx_flags & (1 << 6) ? "SMX" : "-", 5673 ecx_flags & (1 << 7) ? "EIST" : "-", 5674 ecx_flags & (1 << 8) ? "TM2" : "-", 5675 edx_flags & (1 << 4) ? "TSC" : "-", 5676 edx_flags & (1 << 5) ? "MSR" : "-", 5677 edx_flags & (1 << 22) ? "ACPI-TM" : "-", 5678 edx_flags & (1 << 28) ? "HT" : "-", edx_flags & (1 << 29) ? "TM" : "-"); 5679 } 5680 5681 probe_platform_features(family, model); 5682 5683 if (!(edx_flags & (1 << 5))) 5684 errx(1, "CPUID: no MSR"); 5685 5686 if (max_extended_level >= 0x80000007) { 5687 5688 /* 5689 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 5690 * this check is valid for both Intel and AMD 5691 */ 5692 __cpuid(0x80000007, eax, ebx, ecx, edx); 5693 has_invariant_tsc = edx & (1 << 8); 5694 } 5695 5696 /* 5697 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 5698 * this check is valid for both Intel and AMD 5699 */ 5700 5701 __cpuid(0x6, eax, ebx, ecx, edx); 5702 has_aperf = ecx & (1 << 0); 5703 if (has_aperf) { 5704 BIC_PRESENT(BIC_Avg_MHz); 5705 BIC_PRESENT(BIC_Busy); 5706 BIC_PRESENT(BIC_Bzy_MHz); 5707 } 5708 do_dts = eax & (1 << 0); 5709 if (do_dts) 5710 BIC_PRESENT(BIC_CoreTmp); 5711 has_turbo = eax & (1 << 1); 5712 do_ptm = eax & (1 << 6); 5713 if (do_ptm) 5714 BIC_PRESENT(BIC_PkgTmp); 5715 has_hwp = eax & (1 << 7); 5716 has_hwp_notify = eax & (1 << 8); 5717 has_hwp_activity_window = eax & (1 << 9); 5718 has_hwp_epp = eax & (1 << 10); 5719 has_hwp_pkg = eax & (1 << 11); 5720 has_epb = ecx & (1 << 3); 5721 5722 if (!quiet) 5723 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, " 5724 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", 5725 has_aperf ? "" : "No-", 5726 has_turbo ? "" : "No-", 5727 do_dts ? "" : "No-", 5728 do_ptm ? "" : "No-", 5729 has_hwp ? "" : "No-", 5730 has_hwp_notify ? "" : "No-", 5731 has_hwp_activity_window ? "" : "No-", 5732 has_hwp_epp ? "" : "No-", has_hwp_pkg ? "" : "No-", has_epb ? "" : "No-"); 5733 5734 if (!quiet) 5735 decode_misc_enable_msr(); 5736 5737 if (max_level >= 0x7 && !quiet) { 5738 int has_sgx; 5739 5740 ecx = 0; 5741 5742 __cpuid_count(0x7, 0, eax, ebx, ecx, edx); 5743 5744 has_sgx = ebx & (1 << 2); 5745 5746 is_hybrid = edx & (1 << 15); 5747 5748 fprintf(outf, "CPUID(7): %sSGX %sHybrid\n", has_sgx ? "" : "No-", is_hybrid ? "" : "No-"); 5749 5750 if (has_sgx) 5751 decode_feature_control_msr(); 5752 } 5753 5754 if (max_level >= 0x15) { 5755 unsigned int eax_crystal; 5756 unsigned int ebx_tsc; 5757 5758 /* 5759 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz 5760 */ 5761 eax_crystal = ebx_tsc = crystal_hz = edx = 0; 5762 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); 5763 5764 if (ebx_tsc != 0) { 5765 if (!quiet && (ebx != 0)) 5766 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", 5767 eax_crystal, ebx_tsc, crystal_hz); 5768 5769 if (crystal_hz == 0) 5770 crystal_hz = platform->crystal_freq; 5771 5772 if (crystal_hz) { 5773 tsc_hz = (unsigned long long)crystal_hz *ebx_tsc / eax_crystal; 5774 if (!quiet) 5775 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", 5776 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); 5777 } 5778 } 5779 } 5780 if (max_level >= 0x16) { 5781 unsigned int base_mhz, max_mhz, bus_mhz, edx; 5782 5783 /* 5784 * CPUID 16H Base MHz, Max MHz, Bus MHz 5785 */ 5786 base_mhz = max_mhz = bus_mhz = edx = 0; 5787 5788 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); 5789 if (!quiet) 5790 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", 5791 base_mhz, max_mhz, bus_mhz); 5792 } 5793 5794 if (has_aperf) 5795 aperf_mperf_multiplier = platform->need_perf_multiplier ? 1024 : 1; 5796 5797 BIC_PRESENT(BIC_IRQ); 5798 BIC_PRESENT(BIC_TSC_MHz); 5799 } 5800 5801 void probe_pm_features(void) 5802 { 5803 probe_pstates(); 5804 5805 probe_cstates(); 5806 5807 probe_lpi(); 5808 5809 probe_intel_uncore_frequency(); 5810 5811 probe_graphics(); 5812 5813 probe_rapl(); 5814 5815 probe_thermal(); 5816 5817 if (platform->has_nhm_msrs) 5818 BIC_PRESENT(BIC_SMI); 5819 5820 if (!quiet) 5821 decode_misc_feature_control(); 5822 } 5823 5824 /* 5825 * in /dev/cpu/ return success for names that are numbers 5826 * ie. filter out ".", "..", "microcode". 5827 */ 5828 int dir_filter(const struct dirent *dirp) 5829 { 5830 if (isdigit(dirp->d_name[0])) 5831 return 1; 5832 else 5833 return 0; 5834 } 5835 5836 void topology_probe(bool startup) 5837 { 5838 int i; 5839 int max_core_id = 0; 5840 int max_package_id = 0; 5841 int max_die_id = 0; 5842 int max_siblings = 0; 5843 5844 /* Initialize num_cpus, max_cpu_num */ 5845 set_max_cpu_num(); 5846 topo.num_cpus = 0; 5847 for_all_proc_cpus(count_cpus); 5848 if (!summary_only && topo.num_cpus > 1) 5849 BIC_PRESENT(BIC_CPU); 5850 5851 if (debug > 1) 5852 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); 5853 5854 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); 5855 if (cpus == NULL) 5856 err(1, "calloc cpus"); 5857 5858 /* 5859 * Allocate and initialize cpu_present_set 5860 */ 5861 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); 5862 if (cpu_present_set == NULL) 5863 err(3, "CPU_ALLOC"); 5864 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 5865 CPU_ZERO_S(cpu_present_setsize, cpu_present_set); 5866 for_all_proc_cpus(mark_cpu_present); 5867 5868 /* 5869 * Allocate and initialize cpu_effective_set 5870 */ 5871 cpu_effective_set = CPU_ALLOC((topo.max_cpu_num + 1)); 5872 if (cpu_effective_set == NULL) 5873 err(3, "CPU_ALLOC"); 5874 cpu_effective_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 5875 CPU_ZERO_S(cpu_effective_setsize, cpu_effective_set); 5876 update_effective_set(startup); 5877 5878 /* 5879 * Allocate and initialize cpu_allowed_set 5880 */ 5881 cpu_allowed_set = CPU_ALLOC((topo.max_cpu_num + 1)); 5882 if (cpu_allowed_set == NULL) 5883 err(3, "CPU_ALLOC"); 5884 cpu_allowed_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 5885 CPU_ZERO_S(cpu_allowed_setsize, cpu_allowed_set); 5886 5887 /* 5888 * Validate and update cpu_allowed_set. 5889 * 5890 * Make sure all cpus in cpu_subset are also in cpu_present_set during startup. 5891 * Give a warning when cpus in cpu_subset become unavailable at runtime. 5892 * Give a warning when cpus are not effective because of cgroup setting. 5893 * 5894 * cpu_allowed_set is the intersection of cpu_present_set/cpu_effective_set/cpu_subset. 5895 */ 5896 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) { 5897 if (cpu_subset && !CPU_ISSET_S(i, cpu_subset_size, cpu_subset)) 5898 continue; 5899 5900 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set)) { 5901 if (cpu_subset) { 5902 /* cpus in cpu_subset must be in cpu_present_set during startup */ 5903 if (startup) 5904 err(1, "cpu%d not present", i); 5905 else 5906 fprintf(stderr, "cpu%d not present\n", i); 5907 } 5908 continue; 5909 } 5910 5911 if (CPU_COUNT_S(cpu_effective_setsize, cpu_effective_set)) { 5912 if (!CPU_ISSET_S(i, cpu_effective_setsize, cpu_effective_set)) { 5913 fprintf(stderr, "cpu%d not effective\n", i); 5914 continue; 5915 } 5916 } 5917 5918 CPU_SET_S(i, cpu_allowed_setsize, cpu_allowed_set); 5919 } 5920 5921 if (!CPU_COUNT_S(cpu_allowed_setsize, cpu_allowed_set)) 5922 err(-ENODEV, "No valid cpus found"); 5923 sched_setaffinity(0, cpu_allowed_setsize, cpu_allowed_set); 5924 5925 /* 5926 * Allocate and initialize cpu_affinity_set 5927 */ 5928 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); 5929 if (cpu_affinity_set == NULL) 5930 err(3, "CPU_ALLOC"); 5931 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 5932 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 5933 5934 for_all_proc_cpus(init_thread_id); 5935 5936 /* 5937 * For online cpus 5938 * find max_core_id, max_package_id 5939 */ 5940 for (i = 0; i <= topo.max_cpu_num; ++i) { 5941 int siblings; 5942 5943 if (cpu_is_not_present(i)) { 5944 if (debug > 1) 5945 fprintf(outf, "cpu%d NOT PRESENT\n", i); 5946 continue; 5947 } 5948 5949 cpus[i].logical_cpu_id = i; 5950 5951 /* get package information */ 5952 cpus[i].physical_package_id = get_physical_package_id(i); 5953 if (cpus[i].physical_package_id > max_package_id) 5954 max_package_id = cpus[i].physical_package_id; 5955 5956 /* get die information */ 5957 cpus[i].die_id = get_die_id(i); 5958 if (cpus[i].die_id > max_die_id) 5959 max_die_id = cpus[i].die_id; 5960 5961 /* get numa node information */ 5962 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]); 5963 if (cpus[i].physical_node_id > topo.max_node_num) 5964 topo.max_node_num = cpus[i].physical_node_id; 5965 5966 /* get core information */ 5967 cpus[i].physical_core_id = get_core_id(i); 5968 if (cpus[i].physical_core_id > max_core_id) 5969 max_core_id = cpus[i].physical_core_id; 5970 5971 /* get thread information */ 5972 siblings = get_thread_siblings(&cpus[i]); 5973 if (siblings > max_siblings) 5974 max_siblings = siblings; 5975 if (cpus[i].thread_id == 0) 5976 topo.num_cores++; 5977 } 5978 5979 topo.cores_per_node = max_core_id + 1; 5980 if (debug > 1) 5981 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", max_core_id, topo.cores_per_node); 5982 if (!summary_only && topo.cores_per_node > 1) 5983 BIC_PRESENT(BIC_Core); 5984 5985 topo.num_die = max_die_id + 1; 5986 if (debug > 1) 5987 fprintf(outf, "max_die_id %d, sizing for %d die\n", max_die_id, topo.num_die); 5988 if (!summary_only && topo.num_die > 1) 5989 BIC_PRESENT(BIC_Die); 5990 5991 topo.num_packages = max_package_id + 1; 5992 if (debug > 1) 5993 fprintf(outf, "max_package_id %d, sizing for %d packages\n", max_package_id, topo.num_packages); 5994 if (!summary_only && topo.num_packages > 1) 5995 BIC_PRESENT(BIC_Package); 5996 5997 set_node_data(); 5998 if (debug > 1) 5999 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg); 6000 if (!summary_only && topo.nodes_per_pkg > 1) 6001 BIC_PRESENT(BIC_Node); 6002 6003 topo.threads_per_core = max_siblings; 6004 if (debug > 1) 6005 fprintf(outf, "max_siblings %d\n", max_siblings); 6006 6007 if (debug < 1) 6008 return; 6009 6010 for (i = 0; i <= topo.max_cpu_num; ++i) { 6011 if (cpu_is_not_present(i)) 6012 continue; 6013 fprintf(outf, 6014 "cpu %d pkg %d die %d node %d lnode %d core %d thread %d\n", 6015 i, cpus[i].physical_package_id, cpus[i].die_id, 6016 cpus[i].physical_node_id, cpus[i].logical_node_id, cpus[i].physical_core_id, cpus[i].thread_id); 6017 } 6018 6019 } 6020 6021 void allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p) 6022 { 6023 int i; 6024 int num_cores = topo.cores_per_node * topo.nodes_per_pkg * topo.num_packages; 6025 int num_threads = topo.threads_per_core * num_cores; 6026 6027 *t = calloc(num_threads, sizeof(struct thread_data)); 6028 if (*t == NULL) 6029 goto error; 6030 6031 for (i = 0; i < num_threads; i++) 6032 (*t)[i].cpu_id = -1; 6033 6034 *c = calloc(num_cores, sizeof(struct core_data)); 6035 if (*c == NULL) 6036 goto error; 6037 6038 for (i = 0; i < num_cores; i++) { 6039 (*c)[i].core_id = -1; 6040 (*c)[i].base_cpu = -1; 6041 } 6042 6043 *p = calloc(topo.num_packages, sizeof(struct pkg_data)); 6044 if (*p == NULL) 6045 goto error; 6046 6047 for (i = 0; i < topo.num_packages; i++) { 6048 (*p)[i].package_id = i; 6049 (*p)[i].base_cpu = -1; 6050 } 6051 6052 return; 6053 error: 6054 err(1, "calloc counters"); 6055 } 6056 6057 /* 6058 * init_counter() 6059 * 6060 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE 6061 */ 6062 void init_counter(struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base, int cpu_id) 6063 { 6064 int pkg_id = cpus[cpu_id].physical_package_id; 6065 int node_id = cpus[cpu_id].logical_node_id; 6066 int core_id = cpus[cpu_id].physical_core_id; 6067 int thread_id = cpus[cpu_id].thread_id; 6068 struct thread_data *t; 6069 struct core_data *c; 6070 struct pkg_data *p; 6071 6072 /* Workaround for systems where physical_node_id==-1 6073 * and logical_node_id==(-1 - topo.num_cpus) 6074 */ 6075 if (node_id < 0) 6076 node_id = 0; 6077 6078 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id); 6079 c = GET_CORE(core_base, core_id, node_id, pkg_id); 6080 p = GET_PKG(pkg_base, pkg_id); 6081 6082 t->cpu_id = cpu_id; 6083 if (!cpu_is_not_allowed(cpu_id)) { 6084 if (c->base_cpu < 0) 6085 c->base_cpu = t->cpu_id; 6086 if (p->base_cpu < 0) 6087 p->base_cpu = t->cpu_id; 6088 } 6089 6090 c->core_id = core_id; 6091 p->package_id = pkg_id; 6092 } 6093 6094 int initialize_counters(int cpu_id) 6095 { 6096 init_counter(EVEN_COUNTERS, cpu_id); 6097 init_counter(ODD_COUNTERS, cpu_id); 6098 return 0; 6099 } 6100 6101 void allocate_output_buffer() 6102 { 6103 output_buffer = calloc(1, (1 + topo.num_cpus) * 2048); 6104 outp = output_buffer; 6105 if (outp == NULL) 6106 err(-1, "calloc output buffer"); 6107 } 6108 6109 void allocate_fd_percpu(void) 6110 { 6111 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 6112 if (fd_percpu == NULL) 6113 err(-1, "calloc fd_percpu"); 6114 } 6115 6116 void allocate_irq_buffers(void) 6117 { 6118 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); 6119 if (irq_column_2_cpu == NULL) 6120 err(-1, "calloc %d", topo.num_cpus); 6121 6122 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 6123 if (irqs_per_cpu == NULL) 6124 err(-1, "calloc %d", topo.max_cpu_num + 1); 6125 } 6126 6127 int update_topo(struct thread_data *t, struct core_data *c, struct pkg_data *p) 6128 { 6129 topo.allowed_cpus++; 6130 if ((int)t->cpu_id == c->base_cpu) 6131 topo.allowed_cores++; 6132 if ((int)t->cpu_id == p->base_cpu) 6133 topo.allowed_packages++; 6134 6135 return 0; 6136 } 6137 6138 void topology_update(void) 6139 { 6140 topo.allowed_cpus = 0; 6141 topo.allowed_cores = 0; 6142 topo.allowed_packages = 0; 6143 for_all_cpus(update_topo, ODD_COUNTERS); 6144 } 6145 void setup_all_buffers(bool startup) 6146 { 6147 topology_probe(startup); 6148 allocate_irq_buffers(); 6149 allocate_fd_percpu(); 6150 allocate_counters(&thread_even, &core_even, &package_even); 6151 allocate_counters(&thread_odd, &core_odd, &package_odd); 6152 allocate_output_buffer(); 6153 for_all_proc_cpus(initialize_counters); 6154 topology_update(); 6155 } 6156 6157 void set_base_cpu(void) 6158 { 6159 int i; 6160 6161 for (i = 0; i < topo.max_cpu_num + 1; ++i) { 6162 if (cpu_is_not_allowed(i)) 6163 continue; 6164 base_cpu = i; 6165 if (debug > 1) 6166 fprintf(outf, "base_cpu = %d\n", base_cpu); 6167 return; 6168 } 6169 err(-ENODEV, "No valid cpus found"); 6170 } 6171 6172 void turbostat_init() 6173 { 6174 setup_all_buffers(true); 6175 set_base_cpu(); 6176 check_dev_msr(); 6177 check_permissions(); 6178 process_cpuid(); 6179 probe_pm_features(); 6180 linux_perf_init(); 6181 6182 for_all_cpus(get_cpu_type, ODD_COUNTERS); 6183 for_all_cpus(get_cpu_type, EVEN_COUNTERS); 6184 6185 if (DO_BIC(BIC_IPC)) 6186 (void)get_instr_count_fd(base_cpu); 6187 } 6188 6189 int fork_it(char **argv) 6190 { 6191 pid_t child_pid; 6192 int status; 6193 6194 snapshot_proc_sysfs_files(); 6195 status = for_all_cpus(get_counters, EVEN_COUNTERS); 6196 first_counter_read = 0; 6197 if (status) 6198 exit(status); 6199 gettimeofday(&tv_even, (struct timezone *)NULL); 6200 6201 child_pid = fork(); 6202 if (!child_pid) { 6203 /* child */ 6204 execvp(argv[0], argv); 6205 err(errno, "exec %s", argv[0]); 6206 } else { 6207 6208 /* parent */ 6209 if (child_pid == -1) 6210 err(1, "fork"); 6211 6212 signal(SIGINT, SIG_IGN); 6213 signal(SIGQUIT, SIG_IGN); 6214 if (waitpid(child_pid, &status, 0) == -1) 6215 err(status, "waitpid"); 6216 6217 if (WIFEXITED(status)) 6218 status = WEXITSTATUS(status); 6219 } 6220 /* 6221 * n.b. fork_it() does not check for errors from for_all_cpus() 6222 * because re-starting is problematic when forking 6223 */ 6224 snapshot_proc_sysfs_files(); 6225 for_all_cpus(get_counters, ODD_COUNTERS); 6226 gettimeofday(&tv_odd, (struct timezone *)NULL); 6227 timersub(&tv_odd, &tv_even, &tv_delta); 6228 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) 6229 fprintf(outf, "%s: Counter reset detected\n", progname); 6230 else { 6231 compute_average(EVEN_COUNTERS); 6232 format_all_counters(EVEN_COUNTERS); 6233 } 6234 6235 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec / 1000000.0); 6236 6237 flush_output_stderr(); 6238 6239 return status; 6240 } 6241 6242 int get_and_dump_counters(void) 6243 { 6244 int status; 6245 6246 snapshot_proc_sysfs_files(); 6247 status = for_all_cpus(get_counters, ODD_COUNTERS); 6248 if (status) 6249 return status; 6250 6251 status = for_all_cpus(dump_counters, ODD_COUNTERS); 6252 if (status) 6253 return status; 6254 6255 flush_output_stdout(); 6256 6257 return status; 6258 } 6259 6260 void print_version() 6261 { 6262 fprintf(outf, "turbostat version 2023.11.07 - Len Brown <lenb@kernel.org>\n"); 6263 } 6264 6265 #define COMMAND_LINE_SIZE 2048 6266 6267 void print_bootcmd(void) 6268 { 6269 char bootcmd[COMMAND_LINE_SIZE]; 6270 FILE *fp; 6271 int ret; 6272 6273 memset(bootcmd, 0, COMMAND_LINE_SIZE); 6274 fp = fopen("/proc/cmdline", "r"); 6275 if (!fp) 6276 return; 6277 6278 ret = fread(bootcmd, sizeof(char), COMMAND_LINE_SIZE - 1, fp); 6279 if (ret) { 6280 bootcmd[ret] = '\0'; 6281 /* the last character is already '\n' */ 6282 fprintf(outf, "Kernel command line: %s", bootcmd); 6283 } 6284 6285 fclose(fp); 6286 } 6287 6288 int add_counter(unsigned int msr_num, char *path, char *name, 6289 unsigned int width, enum counter_scope scope, 6290 enum counter_type type, enum counter_format format, int flags) 6291 { 6292 struct msr_counter *msrp; 6293 6294 msrp = calloc(1, sizeof(struct msr_counter)); 6295 if (msrp == NULL) { 6296 perror("calloc"); 6297 exit(1); 6298 } 6299 6300 msrp->msr_num = msr_num; 6301 strncpy(msrp->name, name, NAME_BYTES - 1); 6302 if (path) 6303 strncpy(msrp->path, path, PATH_BYTES - 1); 6304 msrp->width = width; 6305 msrp->type = type; 6306 msrp->format = format; 6307 msrp->flags = flags; 6308 6309 switch (scope) { 6310 6311 case SCOPE_CPU: 6312 msrp->next = sys.tp; 6313 sys.tp = msrp; 6314 sys.added_thread_counters++; 6315 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) { 6316 fprintf(stderr, "exceeded max %d added thread counters\n", MAX_ADDED_COUNTERS); 6317 exit(-1); 6318 } 6319 break; 6320 6321 case SCOPE_CORE: 6322 msrp->next = sys.cp; 6323 sys.cp = msrp; 6324 sys.added_core_counters++; 6325 if (sys.added_core_counters > MAX_ADDED_COUNTERS) { 6326 fprintf(stderr, "exceeded max %d added core counters\n", MAX_ADDED_COUNTERS); 6327 exit(-1); 6328 } 6329 break; 6330 6331 case SCOPE_PACKAGE: 6332 msrp->next = sys.pp; 6333 sys.pp = msrp; 6334 sys.added_package_counters++; 6335 if (sys.added_package_counters > MAX_ADDED_COUNTERS) { 6336 fprintf(stderr, "exceeded max %d added package counters\n", MAX_ADDED_COUNTERS); 6337 exit(-1); 6338 } 6339 break; 6340 } 6341 6342 return 0; 6343 } 6344 6345 void parse_add_command(char *add_command) 6346 { 6347 int msr_num = 0; 6348 char *path = NULL; 6349 char name_buffer[NAME_BYTES] = ""; 6350 int width = 64; 6351 int fail = 0; 6352 enum counter_scope scope = SCOPE_CPU; 6353 enum counter_type type = COUNTER_CYCLES; 6354 enum counter_format format = FORMAT_DELTA; 6355 6356 while (add_command) { 6357 6358 if (sscanf(add_command, "msr0x%x", &msr_num) == 1) 6359 goto next; 6360 6361 if (sscanf(add_command, "msr%d", &msr_num) == 1) 6362 goto next; 6363 6364 if (*add_command == '/') { 6365 path = add_command; 6366 goto next; 6367 } 6368 6369 if (sscanf(add_command, "u%d", &width) == 1) { 6370 if ((width == 32) || (width == 64)) 6371 goto next; 6372 width = 64; 6373 } 6374 if (!strncmp(add_command, "cpu", strlen("cpu"))) { 6375 scope = SCOPE_CPU; 6376 goto next; 6377 } 6378 if (!strncmp(add_command, "core", strlen("core"))) { 6379 scope = SCOPE_CORE; 6380 goto next; 6381 } 6382 if (!strncmp(add_command, "package", strlen("package"))) { 6383 scope = SCOPE_PACKAGE; 6384 goto next; 6385 } 6386 if (!strncmp(add_command, "cycles", strlen("cycles"))) { 6387 type = COUNTER_CYCLES; 6388 goto next; 6389 } 6390 if (!strncmp(add_command, "seconds", strlen("seconds"))) { 6391 type = COUNTER_SECONDS; 6392 goto next; 6393 } 6394 if (!strncmp(add_command, "usec", strlen("usec"))) { 6395 type = COUNTER_USEC; 6396 goto next; 6397 } 6398 if (!strncmp(add_command, "raw", strlen("raw"))) { 6399 format = FORMAT_RAW; 6400 goto next; 6401 } 6402 if (!strncmp(add_command, "delta", strlen("delta"))) { 6403 format = FORMAT_DELTA; 6404 goto next; 6405 } 6406 if (!strncmp(add_command, "percent", strlen("percent"))) { 6407 format = FORMAT_PERCENT; 6408 goto next; 6409 } 6410 6411 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */ 6412 char *eos; 6413 6414 eos = strchr(name_buffer, ','); 6415 if (eos) 6416 *eos = '\0'; 6417 goto next; 6418 } 6419 6420 next: 6421 add_command = strchr(add_command, ','); 6422 if (add_command) { 6423 *add_command = '\0'; 6424 add_command++; 6425 } 6426 6427 } 6428 if ((msr_num == 0) && (path == NULL)) { 6429 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n"); 6430 fail++; 6431 } 6432 6433 /* generate default column header */ 6434 if (*name_buffer == '\0') { 6435 if (width == 32) 6436 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 6437 else 6438 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 6439 } 6440 6441 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0)) 6442 fail++; 6443 6444 if (fail) { 6445 help(); 6446 exit(1); 6447 } 6448 } 6449 6450 int is_deferred_add(char *name) 6451 { 6452 int i; 6453 6454 for (i = 0; i < deferred_add_index; ++i) 6455 if (!strcmp(name, deferred_add_names[i])) 6456 return 1; 6457 return 0; 6458 } 6459 6460 int is_deferred_skip(char *name) 6461 { 6462 int i; 6463 6464 for (i = 0; i < deferred_skip_index; ++i) 6465 if (!strcmp(name, deferred_skip_names[i])) 6466 return 1; 6467 return 0; 6468 } 6469 6470 void probe_sysfs(void) 6471 { 6472 char path[64]; 6473 char name_buf[16]; 6474 FILE *input; 6475 int state; 6476 char *sp; 6477 6478 for (state = 10; state >= 0; --state) { 6479 6480 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state); 6481 input = fopen(path, "r"); 6482 if (input == NULL) 6483 continue; 6484 if (!fgets(name_buf, sizeof(name_buf), input)) 6485 err(1, "%s: failed to read file", path); 6486 6487 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 6488 sp = strchr(name_buf, '-'); 6489 if (!sp) 6490 sp = strchrnul(name_buf, '\n'); 6491 *sp = '%'; 6492 *(sp + 1) = '\0'; 6493 6494 remove_underbar(name_buf); 6495 6496 fclose(input); 6497 6498 sprintf(path, "cpuidle/state%d/time", state); 6499 6500 if (!DO_BIC(BIC_sysfs) && !is_deferred_add(name_buf)) 6501 continue; 6502 6503 if (is_deferred_skip(name_buf)) 6504 continue; 6505 6506 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC, FORMAT_PERCENT, SYSFS_PERCPU); 6507 } 6508 6509 for (state = 10; state >= 0; --state) { 6510 6511 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state); 6512 input = fopen(path, "r"); 6513 if (input == NULL) 6514 continue; 6515 if (!fgets(name_buf, sizeof(name_buf), input)) 6516 err(1, "%s: failed to read file", path); 6517 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 6518 sp = strchr(name_buf, '-'); 6519 if (!sp) 6520 sp = strchrnul(name_buf, '\n'); 6521 *sp = '\0'; 6522 fclose(input); 6523 6524 remove_underbar(name_buf); 6525 6526 sprintf(path, "cpuidle/state%d/usage", state); 6527 6528 if (!DO_BIC(BIC_sysfs) && !is_deferred_add(name_buf)) 6529 continue; 6530 6531 if (is_deferred_skip(name_buf)) 6532 continue; 6533 6534 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS, FORMAT_DELTA, SYSFS_PERCPU); 6535 } 6536 6537 } 6538 6539 /* 6540 * parse cpuset with following syntax 6541 * 1,2,4..6,8-10 and set bits in cpu_subset 6542 */ 6543 void parse_cpu_command(char *optarg) 6544 { 6545 if (!strcmp(optarg, "core")) { 6546 if (cpu_subset) 6547 goto error; 6548 show_core_only++; 6549 return; 6550 } 6551 if (!strcmp(optarg, "package")) { 6552 if (cpu_subset) 6553 goto error; 6554 show_pkg_only++; 6555 return; 6556 } 6557 if (show_core_only || show_pkg_only) 6558 goto error; 6559 6560 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS); 6561 if (cpu_subset == NULL) 6562 err(3, "CPU_ALLOC"); 6563 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS); 6564 6565 CPU_ZERO_S(cpu_subset_size, cpu_subset); 6566 6567 if (parse_cpu_str(optarg, cpu_subset, cpu_subset_size)) 6568 goto error; 6569 6570 return; 6571 6572 error: 6573 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg); 6574 help(); 6575 exit(-1); 6576 } 6577 6578 void cmdline(int argc, char **argv) 6579 { 6580 int opt; 6581 int option_index = 0; 6582 static struct option long_options[] = { 6583 { "add", required_argument, 0, 'a' }, 6584 { "cpu", required_argument, 0, 'c' }, 6585 { "Dump", no_argument, 0, 'D' }, 6586 { "debug", no_argument, 0, 'd' }, /* internal, not documented */ 6587 { "enable", required_argument, 0, 'e' }, 6588 { "interval", required_argument, 0, 'i' }, 6589 { "IPC", no_argument, 0, 'I' }, 6590 { "num_iterations", required_argument, 0, 'n' }, 6591 { "header_iterations", required_argument, 0, 'N' }, 6592 { "help", no_argument, 0, 'h' }, 6593 { "hide", required_argument, 0, 'H' }, // meh, -h taken by --help 6594 { "Joules", no_argument, 0, 'J' }, 6595 { "list", no_argument, 0, 'l' }, 6596 { "out", required_argument, 0, 'o' }, 6597 { "quiet", no_argument, 0, 'q' }, 6598 { "show", required_argument, 0, 's' }, 6599 { "Summary", no_argument, 0, 'S' }, 6600 { "TCC", required_argument, 0, 'T' }, 6601 { "version", no_argument, 0, 'v' }, 6602 { 0, 0, 0, 0 } 6603 }; 6604 6605 progname = argv[0]; 6606 6607 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v", long_options, &option_index)) != -1) { 6608 switch (opt) { 6609 case 'a': 6610 parse_add_command(optarg); 6611 break; 6612 case 'c': 6613 parse_cpu_command(optarg); 6614 break; 6615 case 'D': 6616 dump_only++; 6617 break; 6618 case 'e': 6619 /* --enable specified counter */ 6620 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST); 6621 break; 6622 case 'd': 6623 debug++; 6624 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 6625 break; 6626 case 'H': 6627 /* 6628 * --hide: do not show those specified 6629 * multiple invocations simply clear more bits in enabled mask 6630 */ 6631 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST); 6632 break; 6633 case 'h': 6634 default: 6635 help(); 6636 exit(1); 6637 case 'i': 6638 { 6639 double interval = strtod(optarg, NULL); 6640 6641 if (interval < 0.001) { 6642 fprintf(outf, "interval %f seconds is too small\n", interval); 6643 exit(2); 6644 } 6645 6646 interval_tv.tv_sec = interval_ts.tv_sec = interval; 6647 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000; 6648 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; 6649 } 6650 break; 6651 case 'J': 6652 rapl_joules++; 6653 break; 6654 case 'l': 6655 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 6656 list_header_only++; 6657 quiet++; 6658 break; 6659 case 'o': 6660 outf = fopen_or_die(optarg, "w"); 6661 break; 6662 case 'q': 6663 quiet = 1; 6664 break; 6665 case 'n': 6666 num_iterations = strtod(optarg, NULL); 6667 6668 if (num_iterations <= 0) { 6669 fprintf(outf, "iterations %d should be positive number\n", num_iterations); 6670 exit(2); 6671 } 6672 break; 6673 case 'N': 6674 header_iterations = strtod(optarg, NULL); 6675 6676 if (header_iterations <= 0) { 6677 fprintf(outf, "iterations %d should be positive number\n", header_iterations); 6678 exit(2); 6679 } 6680 break; 6681 case 's': 6682 /* 6683 * --show: show only those specified 6684 * The 1st invocation will clear and replace the enabled mask 6685 * subsequent invocations can add to it. 6686 */ 6687 if (shown == 0) 6688 bic_enabled = bic_lookup(optarg, SHOW_LIST); 6689 else 6690 bic_enabled |= bic_lookup(optarg, SHOW_LIST); 6691 shown = 1; 6692 break; 6693 case 'S': 6694 summary_only++; 6695 break; 6696 case 'T': 6697 tj_max_override = atoi(optarg); 6698 break; 6699 case 'v': 6700 print_version(); 6701 exit(0); 6702 break; 6703 } 6704 } 6705 } 6706 6707 int main(int argc, char **argv) 6708 { 6709 int fd, ret; 6710 6711 fd = open("/sys/fs/cgroup/cgroup.procs", O_WRONLY); 6712 if (fd < 0) 6713 goto skip_cgroup_setting; 6714 6715 ret = write(fd, "0\n", 2); 6716 if (ret == -1) 6717 perror("Can't update cgroup\n"); 6718 6719 close(fd); 6720 6721 skip_cgroup_setting: 6722 outf = stderr; 6723 cmdline(argc, argv); 6724 6725 if (!quiet) { 6726 print_version(); 6727 print_bootcmd(); 6728 } 6729 6730 probe_sysfs(); 6731 6732 turbostat_init(); 6733 6734 msr_sum_record(); 6735 6736 /* dump counters and exit */ 6737 if (dump_only) 6738 return get_and_dump_counters(); 6739 6740 /* list header and exit */ 6741 if (list_header_only) { 6742 print_header(","); 6743 flush_output_stdout(); 6744 return 0; 6745 } 6746 6747 /* 6748 * if any params left, it must be a command to fork 6749 */ 6750 if (argc - optind) 6751 return fork_it(argv + optind); 6752 else 6753 turbostat_loop(); 6754 6755 return 0; 6756 } 6757