turbostat [ Options ] [ "-i interval_sec" ]
The -P option limits output to the 1st thread in each Package.
The -S option limits output to a 1-line System Summary for each interval.
The -v option increases verbosity.
The -s option prints the SMI counter, equivalent to "-c 0x34"
The -c MSR# option includes the delta of the specified 32-bit MSR counter.
The -C MSR# option includes the delta of the specified 64-bit MSR counter.
The -m MSR# option includes the the specified 32-bit MSR value.
The -M MSR# option includes the the specified 64-bit MSR value.
The -i interval_sec option prints statistics every \fiinterval_sec seconds. The default is 5 seconds.
The command parameter forks command and upon its exit, displays the statistics gathered since it was forked.
pk processor package number. cor processor core number. CPU Linux CPU (logical processor) number. Note that multiple CPUs per core indicate support for Intel(R) Hyper-Threading Technology. %c0 percent of the interval that the CPU retired instructions. GHz average clock rate while the CPU was in c0 state. TSC average GHz that the TSC ran during the entire interval. %c1, %c3, %c6, %c7 show the percentage residency in hardware core idle states. %pc2, %pc3, %pc6, %pc7 percentage residency in hardware package idle states.
[root@x980]# ./turbostat cor CPU %c0 GHz TSC %c1 %c3 %c6 %pc3 %pc6 0.09 1.62 3.38 1.83 0.32 97.76 1.26 83.61 0 0 0.15 1.62 3.38 10.23 0.05 89.56 1.26 83.61 0 6 0.05 1.62 3.38 10.34 1 2 0.03 1.62 3.38 0.07 0.05 99.86 1 8 0.03 1.62 3.38 0.06 2 4 0.21 1.62 3.38 0.10 1.49 98.21 2 10 0.02 1.62 3.38 0.29 8 1 0.04 1.62 3.38 0.04 0.08 99.84 8 7 0.01 1.62 3.38 0.06 9 3 0.53 1.62 3.38 0.10 0.20 99.17 9 9 0.02 1.62 3.38 0.60 10 5 0.01 1.62 3.38 0.02 0.04 99.92 10 11 0.02 1.62 3.38 0.02
[root@x980]# ./turbostat -s %c0 GHz TSC %c1 %c3 %c6 %pc3 %pc6 0.23 1.67 3.38 2.00 0.30 97.47 1.07 82.12 0.10 1.62 3.38 1.87 2.25 95.77 12.02 72.60 0.20 1.64 3.38 1.98 0.11 97.72 0.30 83.36 0.11 1.70 3.38 1.86 1.81 96.22 9.71 74.90
GenuineIntel 11 CPUID levels; family:model:stepping 0x6:2c:2 (6:44:2) 12 * 133 = 1600 MHz max efficiency 25 * 133 = 3333 MHz TSC frequency 26 * 133 = 3467 MHz max turbo 4 active cores 26 * 133 = 3467 MHz max turbo 3 active cores 27 * 133 = 3600 MHz max turbo 2 active cores 27 * 133 = 3600 MHz max turbo 1 active coresThe max efficiency frequency, a.k.a. Low Frequency Mode, is the frequency available at the minimum package voltage. The TSC frequency is the nominal maximum frequency of the processor if turbo-mode were not available. This frequency should be sustainable on all CPUs indefinitely, given nominal power and cooling. The remaining rows show what maximum turbo frequency is possible depending on the number of idle cores. Note that this information is not available on all processors.
[root@x980 lenb]# ./turbostat cat /dev/zero > /dev/null ^C cor CPU %c0 GHz TSC %c1 %c3 %c6 %pc3 %pc6 8.86 3.61 3.38 15.06 31.19 44.89 0.00 0.00 0 0 1.46 3.22 3.38 16.84 29.48 52.22 0.00 0.00 0 6 0.21 3.06 3.38 18.09 1 2 0.53 3.33 3.38 2.80 46.40 50.27 1 8 0.89 3.47 3.38 2.44 2 4 1.36 3.43 3.38 9.04 23.71 65.89 2 10 0.18 2.86 3.38 10.22 8 1 0.04 2.87 3.38 99.96 0.01 0.00 8 7 99.72 3.63 3.38 0.27 9 3 0.31 3.21 3.38 7.64 56.55 35.50 9 9 0.08 2.95 3.38 7.88 10 5 1.42 3.43 3.38 2.14 30.99 65.44 10 11 0.16 2.88 3.38 3.40Above the cycle soaker drives cpu7 up its 3.6 Ghz turbo limit while the other processors are generally in various states of idle. Note that cpu1 and cpu7 are HT siblings within core8. As cpu7 is very busy, it prevents its sibling, cpu1, from entering a c-state deeper than c1. Note that turbostat reports average GHz of 3.63, while the arithmetic average of the GHz column above is lower. This is a weighted average, where the weight is %c0. ie. it is the total number of un-halted cycles elapsed per time divided by the number of CPUs.
[root@x980 ~]# turbostat -m 0x34 cor CPU %c0 GHz TSC MSR 0x034 %c1 %c3 %c6 %pc3 %pc6 1.41 1.82 3.38 0x00000000 8.92 37.82 51.85 17.37 0.55 0 0 3.73 2.03 3.38 0x00000055 1.72 48.25 46.31 17.38 0.55 0 6 0.14 1.63 3.38 0x00000056 5.30 1 2 2.51 1.80 3.38 0x00000056 15.65 29.33 52.52 1 8 0.10 1.65 3.38 0x00000056 18.05 2 4 1.16 1.68 3.38 0x00000056 5.87 24.47 68.50 2 10 0.10 1.63 3.38 0x00000056 6.93 8 1 3.84 1.91 3.38 0x00000056 1.36 50.65 44.16 8 7 0.08 1.64 3.38 0x00000056 5.12 9 3 1.82 1.73 3.38 0x00000056 7.59 24.21 66.38 9 9 0.09 1.68 3.38 0x00000056 9.32 10 5 1.66 1.65 3.38 0x00000056 15.10 50.00 33.23 10 11 1.72 1.65 3.38 0x00000056 15.05 ^C [root@x980 ~]#
/dev/cpu/*/msr
Written by Len Brown <len.brown@intel.com>