1 // SPDX-License-Identifier: GPL-2.0 2 3 #include "../perf_regs.h" 4 #include "../../arch/riscv/include/perf_regs.h" 5 6 uint64_t __perf_reg_mask_riscv(bool intr __maybe_unused) 7 { 8 return PERF_REGS_MASK; 9 } 10 11 const char *__perf_reg_name_riscv(int id) 12 { 13 switch (id) { 14 case PERF_REG_RISCV_PC: 15 return "pc"; 16 case PERF_REG_RISCV_RA: 17 return "ra"; 18 case PERF_REG_RISCV_SP: 19 return "sp"; 20 case PERF_REG_RISCV_GP: 21 return "gp"; 22 case PERF_REG_RISCV_TP: 23 return "tp"; 24 case PERF_REG_RISCV_T0: 25 return "t0"; 26 case PERF_REG_RISCV_T1: 27 return "t1"; 28 case PERF_REG_RISCV_T2: 29 return "t2"; 30 case PERF_REG_RISCV_S0: 31 return "s0"; 32 case PERF_REG_RISCV_S1: 33 return "s1"; 34 case PERF_REG_RISCV_A0: 35 return "a0"; 36 case PERF_REG_RISCV_A1: 37 return "a1"; 38 case PERF_REG_RISCV_A2: 39 return "a2"; 40 case PERF_REG_RISCV_A3: 41 return "a3"; 42 case PERF_REG_RISCV_A4: 43 return "a4"; 44 case PERF_REG_RISCV_A5: 45 return "a5"; 46 case PERF_REG_RISCV_A6: 47 return "a6"; 48 case PERF_REG_RISCV_A7: 49 return "a7"; 50 case PERF_REG_RISCV_S2: 51 return "s2"; 52 case PERF_REG_RISCV_S3: 53 return "s3"; 54 case PERF_REG_RISCV_S4: 55 return "s4"; 56 case PERF_REG_RISCV_S5: 57 return "s5"; 58 case PERF_REG_RISCV_S6: 59 return "s6"; 60 case PERF_REG_RISCV_S7: 61 return "s7"; 62 case PERF_REG_RISCV_S8: 63 return "s8"; 64 case PERF_REG_RISCV_S9: 65 return "s9"; 66 case PERF_REG_RISCV_S10: 67 return "s10"; 68 case PERF_REG_RISCV_S11: 69 return "s11"; 70 case PERF_REG_RISCV_T3: 71 return "t3"; 72 case PERF_REG_RISCV_T4: 73 return "t4"; 74 case PERF_REG_RISCV_T5: 75 return "t5"; 76 case PERF_REG_RISCV_T6: 77 return "t6"; 78 default: 79 return NULL; 80 } 81 82 return NULL; 83 } 84 85 uint64_t __perf_reg_ip_riscv(void) 86 { 87 return PERF_REG_RISCV_PC; 88 } 89 90 uint64_t __perf_reg_sp_riscv(void) 91 { 92 return PERF_REG_RISCV_SP; 93 } 94