1 // SPDX-License-Identifier: GPL-2.0 2 3 #ifdef HAVE_PERF_REGS_SUPPORT 4 5 #include "../perf_regs.h" 6 #include "../../../arch/riscv/include/uapi/asm/perf_regs.h" 7 8 const char *__perf_reg_name_riscv(int id) 9 { 10 switch (id) { 11 case PERF_REG_RISCV_PC: 12 return "pc"; 13 case PERF_REG_RISCV_RA: 14 return "ra"; 15 case PERF_REG_RISCV_SP: 16 return "sp"; 17 case PERF_REG_RISCV_GP: 18 return "gp"; 19 case PERF_REG_RISCV_TP: 20 return "tp"; 21 case PERF_REG_RISCV_T0: 22 return "t0"; 23 case PERF_REG_RISCV_T1: 24 return "t1"; 25 case PERF_REG_RISCV_T2: 26 return "t2"; 27 case PERF_REG_RISCV_S0: 28 return "s0"; 29 case PERF_REG_RISCV_S1: 30 return "s1"; 31 case PERF_REG_RISCV_A0: 32 return "a0"; 33 case PERF_REG_RISCV_A1: 34 return "a1"; 35 case PERF_REG_RISCV_A2: 36 return "a2"; 37 case PERF_REG_RISCV_A3: 38 return "a3"; 39 case PERF_REG_RISCV_A4: 40 return "a4"; 41 case PERF_REG_RISCV_A5: 42 return "a5"; 43 case PERF_REG_RISCV_A6: 44 return "a6"; 45 case PERF_REG_RISCV_A7: 46 return "a7"; 47 case PERF_REG_RISCV_S2: 48 return "s2"; 49 case PERF_REG_RISCV_S3: 50 return "s3"; 51 case PERF_REG_RISCV_S4: 52 return "s4"; 53 case PERF_REG_RISCV_S5: 54 return "s5"; 55 case PERF_REG_RISCV_S6: 56 return "s6"; 57 case PERF_REG_RISCV_S7: 58 return "s7"; 59 case PERF_REG_RISCV_S8: 60 return "s8"; 61 case PERF_REG_RISCV_S9: 62 return "s9"; 63 case PERF_REG_RISCV_S10: 64 return "s10"; 65 case PERF_REG_RISCV_S11: 66 return "s11"; 67 case PERF_REG_RISCV_T3: 68 return "t3"; 69 case PERF_REG_RISCV_T4: 70 return "t4"; 71 case PERF_REG_RISCV_T5: 72 return "t5"; 73 case PERF_REG_RISCV_T6: 74 return "t6"; 75 default: 76 return NULL; 77 } 78 79 return NULL; 80 } 81 82 uint64_t __perf_reg_ip_riscv(void) 83 { 84 return PERF_REG_RISCV_PC; 85 } 86 87 uint64_t __perf_reg_sp_riscv(void) 88 { 89 return PERF_REG_RISCV_SP; 90 } 91 92 #endif 93