xref: /linux/tools/perf/util/mem-events.h (revision 36ec807b627b4c0a0a382f0ae48eac7187d14b2b)
1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2acbe613eSJiri Olsa #ifndef __PERF_MEM_EVENTS_H
3acbe613eSJiri Olsa #define __PERF_MEM_EVENTS_H
4acbe613eSJiri Olsa 
5acbe613eSJiri Olsa #include <stdbool.h>
6aadddd68SJiri Olsa #include <linux/types.h>
7acbe613eSJiri Olsa 
8acbe613eSJiri Olsa struct perf_mem_event {
9acbe613eSJiri Olsa 	bool		record;
1054fbad54SJiri Olsa 	bool		supported;
11abbdd79bSKan Liang 	bool		ldlat;
12abbdd79bSKan Liang 	u32		aux_event;
13ce1e22b0SJiri Olsa 	const char	*tag;
14acbe613eSJiri Olsa 	const char	*name;
15db95c2ceSKan Liang 	const char	*event_name;
16acbe613eSJiri Olsa };
17acbe613eSJiri Olsa 
18acbe613eSJiri Olsa enum {
19acbe613eSJiri Olsa 	PERF_MEM_EVENTS__LOAD,
20acbe613eSJiri Olsa 	PERF_MEM_EVENTS__STORE,
214ba2452cSLeo Yan 	PERF_MEM_EVENTS__LOAD_STORE,
22acbe613eSJiri Olsa 	PERF_MEM_EVENTS__MAX,
23acbe613eSJiri Olsa };
24acbe613eSJiri Olsa 
25*ad3003a6SIan Rogers struct evsel;
26*ad3003a6SIan Rogers struct mem_info;
27*ad3003a6SIan Rogers struct perf_pmu;
28*ad3003a6SIan Rogers 
29b0d745b3SJiri Olsa extern unsigned int perf_mem_events__loads_ldlat;
30bb65acdcSKan Liang extern struct perf_mem_event perf_mem_events[PERF_MEM_EVENTS__MAX];
31acbe613eSJiri Olsa 
32a30450e6SKan Liang int perf_pmu__mem_events_parse(struct perf_pmu *pmu, const char *str);
33a30450e6SKan Liang int perf_pmu__mem_events_init(struct perf_pmu *pmu);
34ce1e22b0SJiri Olsa 
35a30450e6SKan Liang struct perf_mem_event *perf_pmu__mem_events_ptr(struct perf_pmu *pmu, int i);
36a30450e6SKan Liang struct perf_pmu *perf_mem_events_find_pmu(void);
37821aca20SKan Liang int perf_pmu__mem_events_num_mem_pmus(struct perf_pmu *pmu);
382a57d408SKan Liang bool is_mem_loads_aux_event(struct evsel *leader);
390c877d75SJiri Olsa 
40a30450e6SKan Liang void perf_pmu__mem_events_list(struct perf_pmu *pmu);
4170f4b20dSKan Liang int perf_mem_events__record_args(const char **rec_argv, int *argv_nr);
42b027cc6fSIan Rogers 
43*ad3003a6SIan Rogers int perf_mem__tlb_scnprintf(char *out, size_t sz, const struct mem_info *mem_info);
44*ad3003a6SIan Rogers int perf_mem__lvl_scnprintf(char *out, size_t sz, const struct mem_info *mem_info);
45*ad3003a6SIan Rogers int perf_mem__snp_scnprintf(char *out, size_t sz, const struct mem_info *mem_info);
46*ad3003a6SIan Rogers int perf_mem__lck_scnprintf(char *out, size_t sz, const struct mem_info *mem_info);
47*ad3003a6SIan Rogers int perf_mem__blk_scnprintf(char *out, size_t sz, const struct mem_info *mem_info);
4869a77275SJiri Olsa 
49*ad3003a6SIan Rogers int perf_script__meminfo_scnprintf(char *bf, size_t size, const struct mem_info *mem_info);
50c19ac912SJiri Olsa 
51aadddd68SJiri Olsa struct c2c_stats {
52aadddd68SJiri Olsa 	u32	nr_entries;
53aadddd68SJiri Olsa 
54aadddd68SJiri Olsa 	u32	locks;               /* count of 'lock' transactions */
55aadddd68SJiri Olsa 	u32	store;               /* count of all stores in trace */
56aadddd68SJiri Olsa 	u32	st_uncache;          /* stores to uncacheable address */
57aadddd68SJiri Olsa 	u32	st_noadrs;           /* cacheable store with no address */
58aadddd68SJiri Olsa 	u32	st_l1hit;            /* count of stores that hit L1D */
59aadddd68SJiri Olsa 	u32	st_l1miss;           /* count of stores that miss L1D */
6098450637SLeo Yan 	u32	st_na;               /* count of stores with memory level is not available */
61aadddd68SJiri Olsa 	u32	load;                /* count of all loads in trace */
62aadddd68SJiri Olsa 	u32	ld_excl;             /* exclusive loads, rmt/lcl DRAM - snp none/miss */
63aadddd68SJiri Olsa 	u32	ld_shared;           /* shared loads, rmt/lcl DRAM - snp hit */
64aadddd68SJiri Olsa 	u32	ld_uncache;          /* loads to uncacheable address */
65aadddd68SJiri Olsa 	u32	ld_io;               /* loads to io address */
66aadddd68SJiri Olsa 	u32	ld_miss;             /* loads miss */
67aadddd68SJiri Olsa 	u32	ld_noadrs;           /* cacheable load with no address */
68aadddd68SJiri Olsa 	u32	ld_fbhit;            /* count of loads hitting Fill Buffer */
69aadddd68SJiri Olsa 	u32	ld_l1hit;            /* count of loads that hit L1D */
70aadddd68SJiri Olsa 	u32	ld_l2hit;            /* count of loads that hit L2D */
71aadddd68SJiri Olsa 	u32	ld_llchit;           /* count of loads that hit LLC */
72aadddd68SJiri Olsa 	u32	lcl_hitm;            /* count of loads with local HITM  */
73aadddd68SJiri Olsa 	u32	rmt_hitm;            /* count of loads with remote HITM */
74dba8ab93SJiri Olsa 	u32	tot_hitm;            /* count of loads with local and remote HITM */
75e843dec5SLeo Yan 	u32	lcl_peer;            /* count of loads with local peer cache */
76e843dec5SLeo Yan 	u32	rmt_peer;            /* count of loads with remote peer cache */
77e843dec5SLeo Yan 	u32	tot_peer;            /* count of loads with local and remote peer cache */
78aadddd68SJiri Olsa 	u32	rmt_hit;             /* count of loads with remote hit clean; */
79aadddd68SJiri Olsa 	u32	lcl_dram;            /* count of loads miss to local DRAM */
80aadddd68SJiri Olsa 	u32	rmt_dram;            /* count of loads miss to remote DRAM */
81d9d5d767SKan Liang 	u32	blk_data;            /* count of loads blocked by data */
82d9d5d767SKan Liang 	u32	blk_addr;            /* count of loads blocked by address conflict */
834d39c89fSIngo Molnar 	u32	nomap;               /* count of load/stores with no phys addrs */
84aadddd68SJiri Olsa 	u32	noparse;             /* count of unparsable data sources */
85aadddd68SJiri Olsa };
86aadddd68SJiri Olsa 
87aadddd68SJiri Olsa struct hist_entry;
88aadddd68SJiri Olsa int c2c_decode_stats(struct c2c_stats *stats, struct mem_info *mi);
890a9a24ccSJiri Olsa void c2c_add_stats(struct c2c_stats *stats, struct c2c_stats *add);
90aadddd68SJiri Olsa 
91acbe613eSJiri Olsa #endif /* __PERF_MEM_EVENTS_H */
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