1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_pt.c: Intel Processor Trace support 4 * Copyright (c) 2013-2015, Intel Corporation. 5 */ 6 7 #include <inttypes.h> 8 #include <stdio.h> 9 #include <stdbool.h> 10 #include <errno.h> 11 #include <linux/kernel.h> 12 #include <linux/string.h> 13 #include <linux/types.h> 14 #include <linux/zalloc.h> 15 16 #include "session.h" 17 #include "machine.h" 18 #include "memswap.h" 19 #include "sort.h" 20 #include "tool.h" 21 #include "event.h" 22 #include "evlist.h" 23 #include "evsel.h" 24 #include "map.h" 25 #include "color.h" 26 #include "thread.h" 27 #include "thread-stack.h" 28 #include "symbol.h" 29 #include "callchain.h" 30 #include "dso.h" 31 #include "debug.h" 32 #include "auxtrace.h" 33 #include "tsc.h" 34 #include "intel-pt.h" 35 #include "config.h" 36 #include "util/perf_api_probe.h" 37 #include "util/synthetic-events.h" 38 #include "time-utils.h" 39 40 #include "../arch/x86/include/uapi/asm/perf_regs.h" 41 42 #include "intel-pt-decoder/intel-pt-log.h" 43 #include "intel-pt-decoder/intel-pt-decoder.h" 44 #include "intel-pt-decoder/intel-pt-insn-decoder.h" 45 #include "intel-pt-decoder/intel-pt-pkt-decoder.h" 46 47 #define MAX_TIMESTAMP (~0ULL) 48 49 struct range { 50 u64 start; 51 u64 end; 52 }; 53 54 struct intel_pt { 55 struct auxtrace auxtrace; 56 struct auxtrace_queues queues; 57 struct auxtrace_heap heap; 58 u32 auxtrace_type; 59 struct perf_session *session; 60 struct machine *machine; 61 struct evsel *switch_evsel; 62 struct thread *unknown_thread; 63 bool timeless_decoding; 64 bool sampling_mode; 65 bool snapshot_mode; 66 bool per_cpu_mmaps; 67 bool have_tsc; 68 bool data_queued; 69 bool est_tsc; 70 bool sync_switch; 71 bool mispred_all; 72 bool use_thread_stack; 73 bool callstack; 74 unsigned int br_stack_sz; 75 unsigned int br_stack_sz_plus; 76 int have_sched_switch; 77 u32 pmu_type; 78 u64 kernel_start; 79 u64 switch_ip; 80 u64 ptss_ip; 81 82 struct perf_tsc_conversion tc; 83 bool cap_user_time_zero; 84 85 struct itrace_synth_opts synth_opts; 86 87 bool sample_instructions; 88 u64 instructions_sample_type; 89 u64 instructions_id; 90 91 bool sample_branches; 92 u32 branches_filter; 93 u64 branches_sample_type; 94 u64 branches_id; 95 96 bool sample_transactions; 97 u64 transactions_sample_type; 98 u64 transactions_id; 99 100 bool sample_ptwrites; 101 u64 ptwrites_sample_type; 102 u64 ptwrites_id; 103 104 bool sample_pwr_events; 105 u64 pwr_events_sample_type; 106 u64 mwait_id; 107 u64 pwre_id; 108 u64 exstop_id; 109 u64 pwrx_id; 110 u64 cbr_id; 111 u64 psb_id; 112 113 bool sample_pebs; 114 struct evsel *pebs_evsel; 115 116 u64 tsc_bit; 117 u64 mtc_bit; 118 u64 mtc_freq_bits; 119 u32 tsc_ctc_ratio_n; 120 u32 tsc_ctc_ratio_d; 121 u64 cyc_bit; 122 u64 noretcomp_bit; 123 unsigned max_non_turbo_ratio; 124 unsigned cbr2khz; 125 126 unsigned long num_events; 127 128 char *filter; 129 struct addr_filters filts; 130 131 struct range *time_ranges; 132 unsigned int range_cnt; 133 134 struct ip_callchain *chain; 135 struct branch_stack *br_stack; 136 }; 137 138 enum switch_state { 139 INTEL_PT_SS_NOT_TRACING, 140 INTEL_PT_SS_UNKNOWN, 141 INTEL_PT_SS_TRACING, 142 INTEL_PT_SS_EXPECTING_SWITCH_EVENT, 143 INTEL_PT_SS_EXPECTING_SWITCH_IP, 144 }; 145 146 struct intel_pt_queue { 147 struct intel_pt *pt; 148 unsigned int queue_nr; 149 struct auxtrace_buffer *buffer; 150 struct auxtrace_buffer *old_buffer; 151 void *decoder; 152 const struct intel_pt_state *state; 153 struct ip_callchain *chain; 154 struct branch_stack *last_branch; 155 union perf_event *event_buf; 156 bool on_heap; 157 bool stop; 158 bool step_through_buffers; 159 bool use_buffer_pid_tid; 160 bool sync_switch; 161 pid_t pid, tid; 162 int cpu; 163 int switch_state; 164 pid_t next_tid; 165 struct thread *thread; 166 struct machine *guest_machine; 167 struct thread *unknown_guest_thread; 168 pid_t guest_machine_pid; 169 bool exclude_kernel; 170 bool have_sample; 171 u64 time; 172 u64 timestamp; 173 u64 sel_timestamp; 174 bool sel_start; 175 unsigned int sel_idx; 176 u32 flags; 177 u16 insn_len; 178 u64 last_insn_cnt; 179 u64 ipc_insn_cnt; 180 u64 ipc_cyc_cnt; 181 u64 last_in_insn_cnt; 182 u64 last_in_cyc_cnt; 183 u64 last_br_insn_cnt; 184 u64 last_br_cyc_cnt; 185 unsigned int cbr_seen; 186 char insn[INTEL_PT_INSN_BUF_SZ]; 187 }; 188 189 static void intel_pt_dump(struct intel_pt *pt __maybe_unused, 190 unsigned char *buf, size_t len) 191 { 192 struct intel_pt_pkt packet; 193 size_t pos = 0; 194 int ret, pkt_len, i; 195 char desc[INTEL_PT_PKT_DESC_MAX]; 196 const char *color = PERF_COLOR_BLUE; 197 enum intel_pt_pkt_ctx ctx = INTEL_PT_NO_CTX; 198 199 color_fprintf(stdout, color, 200 ". ... Intel Processor Trace data: size %zu bytes\n", 201 len); 202 203 while (len) { 204 ret = intel_pt_get_packet(buf, len, &packet, &ctx); 205 if (ret > 0) 206 pkt_len = ret; 207 else 208 pkt_len = 1; 209 printf("."); 210 color_fprintf(stdout, color, " %08x: ", pos); 211 for (i = 0; i < pkt_len; i++) 212 color_fprintf(stdout, color, " %02x", buf[i]); 213 for (; i < 16; i++) 214 color_fprintf(stdout, color, " "); 215 if (ret > 0) { 216 ret = intel_pt_pkt_desc(&packet, desc, 217 INTEL_PT_PKT_DESC_MAX); 218 if (ret > 0) 219 color_fprintf(stdout, color, " %s\n", desc); 220 } else { 221 color_fprintf(stdout, color, " Bad packet!\n"); 222 } 223 pos += pkt_len; 224 buf += pkt_len; 225 len -= pkt_len; 226 } 227 } 228 229 static void intel_pt_dump_event(struct intel_pt *pt, unsigned char *buf, 230 size_t len) 231 { 232 printf(".\n"); 233 intel_pt_dump(pt, buf, len); 234 } 235 236 static void intel_pt_log_event(union perf_event *event) 237 { 238 FILE *f = intel_pt_log_fp(); 239 240 if (!intel_pt_enable_logging || !f) 241 return; 242 243 perf_event__fprintf(event, NULL, f); 244 } 245 246 static void intel_pt_dump_sample(struct perf_session *session, 247 struct perf_sample *sample) 248 { 249 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 250 auxtrace); 251 252 printf("\n"); 253 intel_pt_dump(pt, sample->aux_sample.data, sample->aux_sample.size); 254 } 255 256 static bool intel_pt_log_events(struct intel_pt *pt, u64 tm) 257 { 258 struct perf_time_interval *range = pt->synth_opts.ptime_range; 259 int n = pt->synth_opts.range_num; 260 261 if (pt->synth_opts.log_plus_flags & AUXTRACE_LOG_FLG_ALL_PERF_EVTS) 262 return true; 263 264 if (pt->synth_opts.log_minus_flags & AUXTRACE_LOG_FLG_ALL_PERF_EVTS) 265 return false; 266 267 /* perf_time__ranges_skip_sample does not work if time is zero */ 268 if (!tm) 269 tm = 1; 270 271 return !n || !perf_time__ranges_skip_sample(range, n, tm); 272 } 273 274 static int intel_pt_do_fix_overlap(struct intel_pt *pt, struct auxtrace_buffer *a, 275 struct auxtrace_buffer *b) 276 { 277 bool consecutive = false; 278 void *start; 279 280 start = intel_pt_find_overlap(a->data, a->size, b->data, b->size, 281 pt->have_tsc, &consecutive); 282 if (!start) 283 return -EINVAL; 284 b->use_size = b->data + b->size - start; 285 b->use_data = start; 286 if (b->use_size && consecutive) 287 b->consecutive = true; 288 return 0; 289 } 290 291 static int intel_pt_get_buffer(struct intel_pt_queue *ptq, 292 struct auxtrace_buffer *buffer, 293 struct auxtrace_buffer *old_buffer, 294 struct intel_pt_buffer *b) 295 { 296 bool might_overlap; 297 298 if (!buffer->data) { 299 int fd = perf_data__fd(ptq->pt->session->data); 300 301 buffer->data = auxtrace_buffer__get_data(buffer, fd); 302 if (!buffer->data) 303 return -ENOMEM; 304 } 305 306 might_overlap = ptq->pt->snapshot_mode || ptq->pt->sampling_mode; 307 if (might_overlap && !buffer->consecutive && old_buffer && 308 intel_pt_do_fix_overlap(ptq->pt, old_buffer, buffer)) 309 return -ENOMEM; 310 311 if (buffer->use_data) { 312 b->len = buffer->use_size; 313 b->buf = buffer->use_data; 314 } else { 315 b->len = buffer->size; 316 b->buf = buffer->data; 317 } 318 b->ref_timestamp = buffer->reference; 319 320 if (!old_buffer || (might_overlap && !buffer->consecutive)) { 321 b->consecutive = false; 322 b->trace_nr = buffer->buffer_nr + 1; 323 } else { 324 b->consecutive = true; 325 } 326 327 return 0; 328 } 329 330 /* Do not drop buffers with references - refer intel_pt_get_trace() */ 331 static void intel_pt_lookahead_drop_buffer(struct intel_pt_queue *ptq, 332 struct auxtrace_buffer *buffer) 333 { 334 if (!buffer || buffer == ptq->buffer || buffer == ptq->old_buffer) 335 return; 336 337 auxtrace_buffer__drop_data(buffer); 338 } 339 340 /* Must be serialized with respect to intel_pt_get_trace() */ 341 static int intel_pt_lookahead(void *data, intel_pt_lookahead_cb_t cb, 342 void *cb_data) 343 { 344 struct intel_pt_queue *ptq = data; 345 struct auxtrace_buffer *buffer = ptq->buffer; 346 struct auxtrace_buffer *old_buffer = ptq->old_buffer; 347 struct auxtrace_queue *queue; 348 int err = 0; 349 350 queue = &ptq->pt->queues.queue_array[ptq->queue_nr]; 351 352 while (1) { 353 struct intel_pt_buffer b = { .len = 0 }; 354 355 buffer = auxtrace_buffer__next(queue, buffer); 356 if (!buffer) 357 break; 358 359 err = intel_pt_get_buffer(ptq, buffer, old_buffer, &b); 360 if (err) 361 break; 362 363 if (b.len) { 364 intel_pt_lookahead_drop_buffer(ptq, old_buffer); 365 old_buffer = buffer; 366 } else { 367 intel_pt_lookahead_drop_buffer(ptq, buffer); 368 continue; 369 } 370 371 err = cb(&b, cb_data); 372 if (err) 373 break; 374 } 375 376 if (buffer != old_buffer) 377 intel_pt_lookahead_drop_buffer(ptq, buffer); 378 intel_pt_lookahead_drop_buffer(ptq, old_buffer); 379 380 return err; 381 } 382 383 /* 384 * This function assumes data is processed sequentially only. 385 * Must be serialized with respect to intel_pt_lookahead() 386 */ 387 static int intel_pt_get_trace(struct intel_pt_buffer *b, void *data) 388 { 389 struct intel_pt_queue *ptq = data; 390 struct auxtrace_buffer *buffer = ptq->buffer; 391 struct auxtrace_buffer *old_buffer = ptq->old_buffer; 392 struct auxtrace_queue *queue; 393 int err; 394 395 if (ptq->stop) { 396 b->len = 0; 397 return 0; 398 } 399 400 queue = &ptq->pt->queues.queue_array[ptq->queue_nr]; 401 402 buffer = auxtrace_buffer__next(queue, buffer); 403 if (!buffer) { 404 if (old_buffer) 405 auxtrace_buffer__drop_data(old_buffer); 406 b->len = 0; 407 return 0; 408 } 409 410 ptq->buffer = buffer; 411 412 err = intel_pt_get_buffer(ptq, buffer, old_buffer, b); 413 if (err) 414 return err; 415 416 if (ptq->step_through_buffers) 417 ptq->stop = true; 418 419 if (b->len) { 420 if (old_buffer) 421 auxtrace_buffer__drop_data(old_buffer); 422 ptq->old_buffer = buffer; 423 } else { 424 auxtrace_buffer__drop_data(buffer); 425 return intel_pt_get_trace(b, data); 426 } 427 428 return 0; 429 } 430 431 struct intel_pt_cache_entry { 432 struct auxtrace_cache_entry entry; 433 u64 insn_cnt; 434 u64 byte_cnt; 435 enum intel_pt_insn_op op; 436 enum intel_pt_insn_branch branch; 437 int length; 438 int32_t rel; 439 char insn[INTEL_PT_INSN_BUF_SZ]; 440 }; 441 442 static int intel_pt_config_div(const char *var, const char *value, void *data) 443 { 444 int *d = data; 445 long val; 446 447 if (!strcmp(var, "intel-pt.cache-divisor")) { 448 val = strtol(value, NULL, 0); 449 if (val > 0 && val <= INT_MAX) 450 *d = val; 451 } 452 453 return 0; 454 } 455 456 static int intel_pt_cache_divisor(void) 457 { 458 static int d; 459 460 if (d) 461 return d; 462 463 perf_config(intel_pt_config_div, &d); 464 465 if (!d) 466 d = 64; 467 468 return d; 469 } 470 471 static unsigned int intel_pt_cache_size(struct dso *dso, 472 struct machine *machine) 473 { 474 off_t size; 475 476 size = dso__data_size(dso, machine); 477 size /= intel_pt_cache_divisor(); 478 if (size < 1000) 479 return 10; 480 if (size > (1 << 21)) 481 return 21; 482 return 32 - __builtin_clz(size); 483 } 484 485 static struct auxtrace_cache *intel_pt_cache(struct dso *dso, 486 struct machine *machine) 487 { 488 struct auxtrace_cache *c; 489 unsigned int bits; 490 491 if (dso->auxtrace_cache) 492 return dso->auxtrace_cache; 493 494 bits = intel_pt_cache_size(dso, machine); 495 496 /* Ignoring cache creation failure */ 497 c = auxtrace_cache__new(bits, sizeof(struct intel_pt_cache_entry), 200); 498 499 dso->auxtrace_cache = c; 500 501 return c; 502 } 503 504 static int intel_pt_cache_add(struct dso *dso, struct machine *machine, 505 u64 offset, u64 insn_cnt, u64 byte_cnt, 506 struct intel_pt_insn *intel_pt_insn) 507 { 508 struct auxtrace_cache *c = intel_pt_cache(dso, machine); 509 struct intel_pt_cache_entry *e; 510 int err; 511 512 if (!c) 513 return -ENOMEM; 514 515 e = auxtrace_cache__alloc_entry(c); 516 if (!e) 517 return -ENOMEM; 518 519 e->insn_cnt = insn_cnt; 520 e->byte_cnt = byte_cnt; 521 e->op = intel_pt_insn->op; 522 e->branch = intel_pt_insn->branch; 523 e->length = intel_pt_insn->length; 524 e->rel = intel_pt_insn->rel; 525 memcpy(e->insn, intel_pt_insn->buf, INTEL_PT_INSN_BUF_SZ); 526 527 err = auxtrace_cache__add(c, offset, &e->entry); 528 if (err) 529 auxtrace_cache__free_entry(c, e); 530 531 return err; 532 } 533 534 static struct intel_pt_cache_entry * 535 intel_pt_cache_lookup(struct dso *dso, struct machine *machine, u64 offset) 536 { 537 struct auxtrace_cache *c = intel_pt_cache(dso, machine); 538 539 if (!c) 540 return NULL; 541 542 return auxtrace_cache__lookup(dso->auxtrace_cache, offset); 543 } 544 545 static void intel_pt_cache_invalidate(struct dso *dso, struct machine *machine, 546 u64 offset) 547 { 548 struct auxtrace_cache *c = intel_pt_cache(dso, machine); 549 550 if (!c) 551 return; 552 553 auxtrace_cache__remove(dso->auxtrace_cache, offset); 554 } 555 556 static inline bool intel_pt_guest_kernel_ip(uint64_t ip) 557 { 558 /* Assumes 64-bit kernel */ 559 return ip & (1ULL << 63); 560 } 561 562 static inline u8 intel_pt_nr_cpumode(struct intel_pt_queue *ptq, uint64_t ip, bool nr) 563 { 564 if (nr) { 565 return intel_pt_guest_kernel_ip(ip) ? 566 PERF_RECORD_MISC_GUEST_KERNEL : 567 PERF_RECORD_MISC_GUEST_USER; 568 } 569 570 return ip >= ptq->pt->kernel_start ? 571 PERF_RECORD_MISC_KERNEL : 572 PERF_RECORD_MISC_USER; 573 } 574 575 static inline u8 intel_pt_cpumode(struct intel_pt_queue *ptq, uint64_t from_ip, uint64_t to_ip) 576 { 577 /* No support for non-zero CS base */ 578 if (from_ip) 579 return intel_pt_nr_cpumode(ptq, from_ip, ptq->state->from_nr); 580 return intel_pt_nr_cpumode(ptq, to_ip, ptq->state->to_nr); 581 } 582 583 static int intel_pt_get_guest(struct intel_pt_queue *ptq) 584 { 585 struct machines *machines = &ptq->pt->session->machines; 586 struct machine *machine; 587 pid_t pid = ptq->pid <= 0 ? DEFAULT_GUEST_KERNEL_ID : ptq->pid; 588 589 if (ptq->guest_machine && pid == ptq->guest_machine_pid) 590 return 0; 591 592 ptq->guest_machine = NULL; 593 thread__zput(ptq->unknown_guest_thread); 594 595 machine = machines__find_guest(machines, pid); 596 if (!machine) 597 return -1; 598 599 ptq->unknown_guest_thread = machine__idle_thread(machine); 600 if (!ptq->unknown_guest_thread) 601 return -1; 602 603 ptq->guest_machine = machine; 604 ptq->guest_machine_pid = pid; 605 606 return 0; 607 } 608 609 static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn, 610 uint64_t *insn_cnt_ptr, uint64_t *ip, 611 uint64_t to_ip, uint64_t max_insn_cnt, 612 void *data) 613 { 614 struct intel_pt_queue *ptq = data; 615 struct machine *machine = ptq->pt->machine; 616 struct thread *thread; 617 struct addr_location al; 618 unsigned char buf[INTEL_PT_INSN_BUF_SZ]; 619 ssize_t len; 620 int x86_64; 621 u8 cpumode; 622 u64 offset, start_offset, start_ip; 623 u64 insn_cnt = 0; 624 bool one_map = true; 625 bool nr; 626 627 intel_pt_insn->length = 0; 628 629 if (to_ip && *ip == to_ip) 630 goto out_no_cache; 631 632 nr = ptq->state->to_nr; 633 cpumode = intel_pt_nr_cpumode(ptq, *ip, nr); 634 635 if (nr) { 636 if (cpumode != PERF_RECORD_MISC_GUEST_KERNEL || 637 intel_pt_get_guest(ptq)) 638 return -EINVAL; 639 machine = ptq->guest_machine; 640 thread = ptq->unknown_guest_thread; 641 } else { 642 thread = ptq->thread; 643 if (!thread) { 644 if (cpumode != PERF_RECORD_MISC_KERNEL) 645 return -EINVAL; 646 thread = ptq->pt->unknown_thread; 647 } 648 } 649 650 while (1) { 651 if (!thread__find_map(thread, cpumode, *ip, &al) || !al.map->dso) 652 return -EINVAL; 653 654 if (al.map->dso->data.status == DSO_DATA_STATUS_ERROR && 655 dso__data_status_seen(al.map->dso, 656 DSO_DATA_STATUS_SEEN_ITRACE)) 657 return -ENOENT; 658 659 offset = al.map->map_ip(al.map, *ip); 660 661 if (!to_ip && one_map) { 662 struct intel_pt_cache_entry *e; 663 664 e = intel_pt_cache_lookup(al.map->dso, machine, offset); 665 if (e && 666 (!max_insn_cnt || e->insn_cnt <= max_insn_cnt)) { 667 *insn_cnt_ptr = e->insn_cnt; 668 *ip += e->byte_cnt; 669 intel_pt_insn->op = e->op; 670 intel_pt_insn->branch = e->branch; 671 intel_pt_insn->length = e->length; 672 intel_pt_insn->rel = e->rel; 673 memcpy(intel_pt_insn->buf, e->insn, 674 INTEL_PT_INSN_BUF_SZ); 675 intel_pt_log_insn_no_data(intel_pt_insn, *ip); 676 return 0; 677 } 678 } 679 680 start_offset = offset; 681 start_ip = *ip; 682 683 /* Load maps to ensure dso->is_64_bit has been updated */ 684 map__load(al.map); 685 686 x86_64 = al.map->dso->is_64_bit; 687 688 while (1) { 689 len = dso__data_read_offset(al.map->dso, machine, 690 offset, buf, 691 INTEL_PT_INSN_BUF_SZ); 692 if (len <= 0) 693 return -EINVAL; 694 695 if (intel_pt_get_insn(buf, len, x86_64, intel_pt_insn)) 696 return -EINVAL; 697 698 intel_pt_log_insn(intel_pt_insn, *ip); 699 700 insn_cnt += 1; 701 702 if (intel_pt_insn->branch != INTEL_PT_BR_NO_BRANCH) 703 goto out; 704 705 if (max_insn_cnt && insn_cnt >= max_insn_cnt) 706 goto out_no_cache; 707 708 *ip += intel_pt_insn->length; 709 710 if (to_ip && *ip == to_ip) 711 goto out_no_cache; 712 713 if (*ip >= al.map->end) 714 break; 715 716 offset += intel_pt_insn->length; 717 } 718 one_map = false; 719 } 720 out: 721 *insn_cnt_ptr = insn_cnt; 722 723 if (!one_map) 724 goto out_no_cache; 725 726 /* 727 * Didn't lookup in the 'to_ip' case, so do it now to prevent duplicate 728 * entries. 729 */ 730 if (to_ip) { 731 struct intel_pt_cache_entry *e; 732 733 e = intel_pt_cache_lookup(al.map->dso, machine, start_offset); 734 if (e) 735 return 0; 736 } 737 738 /* Ignore cache errors */ 739 intel_pt_cache_add(al.map->dso, machine, start_offset, insn_cnt, 740 *ip - start_ip, intel_pt_insn); 741 742 return 0; 743 744 out_no_cache: 745 *insn_cnt_ptr = insn_cnt; 746 return 0; 747 } 748 749 static bool intel_pt_match_pgd_ip(struct intel_pt *pt, uint64_t ip, 750 uint64_t offset, const char *filename) 751 { 752 struct addr_filter *filt; 753 bool have_filter = false; 754 bool hit_tracestop = false; 755 bool hit_filter = false; 756 757 list_for_each_entry(filt, &pt->filts.head, list) { 758 if (filt->start) 759 have_filter = true; 760 761 if ((filename && !filt->filename) || 762 (!filename && filt->filename) || 763 (filename && strcmp(filename, filt->filename))) 764 continue; 765 766 if (!(offset >= filt->addr && offset < filt->addr + filt->size)) 767 continue; 768 769 intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s hit filter: %s offset %#"PRIx64" size %#"PRIx64"\n", 770 ip, offset, filename ? filename : "[kernel]", 771 filt->start ? "filter" : "stop", 772 filt->addr, filt->size); 773 774 if (filt->start) 775 hit_filter = true; 776 else 777 hit_tracestop = true; 778 } 779 780 if (!hit_tracestop && !hit_filter) 781 intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s is not in a filter region\n", 782 ip, offset, filename ? filename : "[kernel]"); 783 784 return hit_tracestop || (have_filter && !hit_filter); 785 } 786 787 static int __intel_pt_pgd_ip(uint64_t ip, void *data) 788 { 789 struct intel_pt_queue *ptq = data; 790 struct thread *thread; 791 struct addr_location al; 792 u8 cpumode; 793 u64 offset; 794 795 if (ptq->state->to_nr) { 796 if (intel_pt_guest_kernel_ip(ip)) 797 return intel_pt_match_pgd_ip(ptq->pt, ip, ip, NULL); 798 /* No support for decoding guest user space */ 799 return -EINVAL; 800 } else if (ip >= ptq->pt->kernel_start) { 801 return intel_pt_match_pgd_ip(ptq->pt, ip, ip, NULL); 802 } 803 804 cpumode = PERF_RECORD_MISC_USER; 805 806 thread = ptq->thread; 807 if (!thread) 808 return -EINVAL; 809 810 if (!thread__find_map(thread, cpumode, ip, &al) || !al.map->dso) 811 return -EINVAL; 812 813 offset = al.map->map_ip(al.map, ip); 814 815 return intel_pt_match_pgd_ip(ptq->pt, ip, offset, 816 al.map->dso->long_name); 817 } 818 819 static bool intel_pt_pgd_ip(uint64_t ip, void *data) 820 { 821 return __intel_pt_pgd_ip(ip, data) > 0; 822 } 823 824 static bool intel_pt_get_config(struct intel_pt *pt, 825 struct perf_event_attr *attr, u64 *config) 826 { 827 if (attr->type == pt->pmu_type) { 828 if (config) 829 *config = attr->config; 830 return true; 831 } 832 833 return false; 834 } 835 836 static bool intel_pt_exclude_kernel(struct intel_pt *pt) 837 { 838 struct evsel *evsel; 839 840 evlist__for_each_entry(pt->session->evlist, evsel) { 841 if (intel_pt_get_config(pt, &evsel->core.attr, NULL) && 842 !evsel->core.attr.exclude_kernel) 843 return false; 844 } 845 return true; 846 } 847 848 static bool intel_pt_return_compression(struct intel_pt *pt) 849 { 850 struct evsel *evsel; 851 u64 config; 852 853 if (!pt->noretcomp_bit) 854 return true; 855 856 evlist__for_each_entry(pt->session->evlist, evsel) { 857 if (intel_pt_get_config(pt, &evsel->core.attr, &config) && 858 (config & pt->noretcomp_bit)) 859 return false; 860 } 861 return true; 862 } 863 864 static bool intel_pt_branch_enable(struct intel_pt *pt) 865 { 866 struct evsel *evsel; 867 u64 config; 868 869 evlist__for_each_entry(pt->session->evlist, evsel) { 870 if (intel_pt_get_config(pt, &evsel->core.attr, &config) && 871 (config & 1) && !(config & 0x2000)) 872 return false; 873 } 874 return true; 875 } 876 877 static unsigned int intel_pt_mtc_period(struct intel_pt *pt) 878 { 879 struct evsel *evsel; 880 unsigned int shift; 881 u64 config; 882 883 if (!pt->mtc_freq_bits) 884 return 0; 885 886 for (shift = 0, config = pt->mtc_freq_bits; !(config & 1); shift++) 887 config >>= 1; 888 889 evlist__for_each_entry(pt->session->evlist, evsel) { 890 if (intel_pt_get_config(pt, &evsel->core.attr, &config)) 891 return (config & pt->mtc_freq_bits) >> shift; 892 } 893 return 0; 894 } 895 896 static bool intel_pt_timeless_decoding(struct intel_pt *pt) 897 { 898 struct evsel *evsel; 899 bool timeless_decoding = true; 900 u64 config; 901 902 if (!pt->tsc_bit || !pt->cap_user_time_zero) 903 return true; 904 905 evlist__for_each_entry(pt->session->evlist, evsel) { 906 if (!(evsel->core.attr.sample_type & PERF_SAMPLE_TIME)) 907 return true; 908 if (intel_pt_get_config(pt, &evsel->core.attr, &config)) { 909 if (config & pt->tsc_bit) 910 timeless_decoding = false; 911 else 912 return true; 913 } 914 } 915 return timeless_decoding; 916 } 917 918 static bool intel_pt_tracing_kernel(struct intel_pt *pt) 919 { 920 struct evsel *evsel; 921 922 evlist__for_each_entry(pt->session->evlist, evsel) { 923 if (intel_pt_get_config(pt, &evsel->core.attr, NULL) && 924 !evsel->core.attr.exclude_kernel) 925 return true; 926 } 927 return false; 928 } 929 930 static bool intel_pt_have_tsc(struct intel_pt *pt) 931 { 932 struct evsel *evsel; 933 bool have_tsc = false; 934 u64 config; 935 936 if (!pt->tsc_bit) 937 return false; 938 939 evlist__for_each_entry(pt->session->evlist, evsel) { 940 if (intel_pt_get_config(pt, &evsel->core.attr, &config)) { 941 if (config & pt->tsc_bit) 942 have_tsc = true; 943 else 944 return false; 945 } 946 } 947 return have_tsc; 948 } 949 950 static bool intel_pt_sampling_mode(struct intel_pt *pt) 951 { 952 struct evsel *evsel; 953 954 evlist__for_each_entry(pt->session->evlist, evsel) { 955 if ((evsel->core.attr.sample_type & PERF_SAMPLE_AUX) && 956 evsel->core.attr.aux_sample_size) 957 return true; 958 } 959 return false; 960 } 961 962 static u64 intel_pt_ctl(struct intel_pt *pt) 963 { 964 struct evsel *evsel; 965 u64 config; 966 967 evlist__for_each_entry(pt->session->evlist, evsel) { 968 if (intel_pt_get_config(pt, &evsel->core.attr, &config)) 969 return config; 970 } 971 return 0; 972 } 973 974 static u64 intel_pt_ns_to_ticks(const struct intel_pt *pt, u64 ns) 975 { 976 u64 quot, rem; 977 978 quot = ns / pt->tc.time_mult; 979 rem = ns % pt->tc.time_mult; 980 return (quot << pt->tc.time_shift) + (rem << pt->tc.time_shift) / 981 pt->tc.time_mult; 982 } 983 984 static struct ip_callchain *intel_pt_alloc_chain(struct intel_pt *pt) 985 { 986 size_t sz = sizeof(struct ip_callchain); 987 988 /* Add 1 to callchain_sz for callchain context */ 989 sz += (pt->synth_opts.callchain_sz + 1) * sizeof(u64); 990 return zalloc(sz); 991 } 992 993 static int intel_pt_callchain_init(struct intel_pt *pt) 994 { 995 struct evsel *evsel; 996 997 evlist__for_each_entry(pt->session->evlist, evsel) { 998 if (!(evsel->core.attr.sample_type & PERF_SAMPLE_CALLCHAIN)) 999 evsel->synth_sample_type |= PERF_SAMPLE_CALLCHAIN; 1000 } 1001 1002 pt->chain = intel_pt_alloc_chain(pt); 1003 if (!pt->chain) 1004 return -ENOMEM; 1005 1006 return 0; 1007 } 1008 1009 static void intel_pt_add_callchain(struct intel_pt *pt, 1010 struct perf_sample *sample) 1011 { 1012 struct thread *thread = machine__findnew_thread(pt->machine, 1013 sample->pid, 1014 sample->tid); 1015 1016 thread_stack__sample_late(thread, sample->cpu, pt->chain, 1017 pt->synth_opts.callchain_sz + 1, sample->ip, 1018 pt->kernel_start); 1019 1020 sample->callchain = pt->chain; 1021 } 1022 1023 static struct branch_stack *intel_pt_alloc_br_stack(unsigned int entry_cnt) 1024 { 1025 size_t sz = sizeof(struct branch_stack); 1026 1027 sz += entry_cnt * sizeof(struct branch_entry); 1028 return zalloc(sz); 1029 } 1030 1031 static int intel_pt_br_stack_init(struct intel_pt *pt) 1032 { 1033 struct evsel *evsel; 1034 1035 evlist__for_each_entry(pt->session->evlist, evsel) { 1036 if (!(evsel->core.attr.sample_type & PERF_SAMPLE_BRANCH_STACK)) 1037 evsel->synth_sample_type |= PERF_SAMPLE_BRANCH_STACK; 1038 } 1039 1040 pt->br_stack = intel_pt_alloc_br_stack(pt->br_stack_sz); 1041 if (!pt->br_stack) 1042 return -ENOMEM; 1043 1044 return 0; 1045 } 1046 1047 static void intel_pt_add_br_stack(struct intel_pt *pt, 1048 struct perf_sample *sample) 1049 { 1050 struct thread *thread = machine__findnew_thread(pt->machine, 1051 sample->pid, 1052 sample->tid); 1053 1054 thread_stack__br_sample_late(thread, sample->cpu, pt->br_stack, 1055 pt->br_stack_sz, sample->ip, 1056 pt->kernel_start); 1057 1058 sample->branch_stack = pt->br_stack; 1059 } 1060 1061 /* INTEL_PT_LBR_0, INTEL_PT_LBR_1 and INTEL_PT_LBR_2 */ 1062 #define LBRS_MAX (INTEL_PT_BLK_ITEM_ID_CNT * 3U) 1063 1064 static struct intel_pt_queue *intel_pt_alloc_queue(struct intel_pt *pt, 1065 unsigned int queue_nr) 1066 { 1067 struct intel_pt_params params = { .get_trace = 0, }; 1068 struct perf_env *env = pt->machine->env; 1069 struct intel_pt_queue *ptq; 1070 1071 ptq = zalloc(sizeof(struct intel_pt_queue)); 1072 if (!ptq) 1073 return NULL; 1074 1075 if (pt->synth_opts.callchain) { 1076 ptq->chain = intel_pt_alloc_chain(pt); 1077 if (!ptq->chain) 1078 goto out_free; 1079 } 1080 1081 if (pt->synth_opts.last_branch || pt->synth_opts.other_events) { 1082 unsigned int entry_cnt = max(LBRS_MAX, pt->br_stack_sz); 1083 1084 ptq->last_branch = intel_pt_alloc_br_stack(entry_cnt); 1085 if (!ptq->last_branch) 1086 goto out_free; 1087 } 1088 1089 ptq->event_buf = malloc(PERF_SAMPLE_MAX_SIZE); 1090 if (!ptq->event_buf) 1091 goto out_free; 1092 1093 ptq->pt = pt; 1094 ptq->queue_nr = queue_nr; 1095 ptq->exclude_kernel = intel_pt_exclude_kernel(pt); 1096 ptq->pid = -1; 1097 ptq->tid = -1; 1098 ptq->cpu = -1; 1099 ptq->next_tid = -1; 1100 1101 params.get_trace = intel_pt_get_trace; 1102 params.walk_insn = intel_pt_walk_next_insn; 1103 params.lookahead = intel_pt_lookahead; 1104 params.data = ptq; 1105 params.return_compression = intel_pt_return_compression(pt); 1106 params.branch_enable = intel_pt_branch_enable(pt); 1107 params.ctl = intel_pt_ctl(pt); 1108 params.max_non_turbo_ratio = pt->max_non_turbo_ratio; 1109 params.mtc_period = intel_pt_mtc_period(pt); 1110 params.tsc_ctc_ratio_n = pt->tsc_ctc_ratio_n; 1111 params.tsc_ctc_ratio_d = pt->tsc_ctc_ratio_d; 1112 params.quick = pt->synth_opts.quick; 1113 1114 if (pt->filts.cnt > 0) 1115 params.pgd_ip = intel_pt_pgd_ip; 1116 1117 if (pt->synth_opts.instructions) { 1118 if (pt->synth_opts.period) { 1119 switch (pt->synth_opts.period_type) { 1120 case PERF_ITRACE_PERIOD_INSTRUCTIONS: 1121 params.period_type = 1122 INTEL_PT_PERIOD_INSTRUCTIONS; 1123 params.period = pt->synth_opts.period; 1124 break; 1125 case PERF_ITRACE_PERIOD_TICKS: 1126 params.period_type = INTEL_PT_PERIOD_TICKS; 1127 params.period = pt->synth_opts.period; 1128 break; 1129 case PERF_ITRACE_PERIOD_NANOSECS: 1130 params.period_type = INTEL_PT_PERIOD_TICKS; 1131 params.period = intel_pt_ns_to_ticks(pt, 1132 pt->synth_opts.period); 1133 break; 1134 default: 1135 break; 1136 } 1137 } 1138 1139 if (!params.period) { 1140 params.period_type = INTEL_PT_PERIOD_INSTRUCTIONS; 1141 params.period = 1; 1142 } 1143 } 1144 1145 if (env->cpuid && !strncmp(env->cpuid, "GenuineIntel,6,92,", 18)) 1146 params.flags |= INTEL_PT_FUP_WITH_NLIP; 1147 1148 ptq->decoder = intel_pt_decoder_new(¶ms); 1149 if (!ptq->decoder) 1150 goto out_free; 1151 1152 return ptq; 1153 1154 out_free: 1155 zfree(&ptq->event_buf); 1156 zfree(&ptq->last_branch); 1157 zfree(&ptq->chain); 1158 free(ptq); 1159 return NULL; 1160 } 1161 1162 static void intel_pt_free_queue(void *priv) 1163 { 1164 struct intel_pt_queue *ptq = priv; 1165 1166 if (!ptq) 1167 return; 1168 thread__zput(ptq->thread); 1169 thread__zput(ptq->unknown_guest_thread); 1170 intel_pt_decoder_free(ptq->decoder); 1171 zfree(&ptq->event_buf); 1172 zfree(&ptq->last_branch); 1173 zfree(&ptq->chain); 1174 free(ptq); 1175 } 1176 1177 static void intel_pt_set_pid_tid_cpu(struct intel_pt *pt, 1178 struct auxtrace_queue *queue) 1179 { 1180 struct intel_pt_queue *ptq = queue->priv; 1181 1182 if (queue->tid == -1 || pt->have_sched_switch) { 1183 ptq->tid = machine__get_current_tid(pt->machine, ptq->cpu); 1184 if (ptq->tid == -1) 1185 ptq->pid = -1; 1186 thread__zput(ptq->thread); 1187 } 1188 1189 if (!ptq->thread && ptq->tid != -1) 1190 ptq->thread = machine__find_thread(pt->machine, -1, ptq->tid); 1191 1192 if (ptq->thread) { 1193 ptq->pid = ptq->thread->pid_; 1194 if (queue->cpu == -1) 1195 ptq->cpu = ptq->thread->cpu; 1196 } 1197 } 1198 1199 static void intel_pt_sample_flags(struct intel_pt_queue *ptq) 1200 { 1201 if (ptq->state->flags & INTEL_PT_ABORT_TX) { 1202 ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TX_ABORT; 1203 } else if (ptq->state->flags & INTEL_PT_ASYNC) { 1204 if (!ptq->state->to_ip) 1205 ptq->flags = PERF_IP_FLAG_BRANCH | 1206 PERF_IP_FLAG_TRACE_END; 1207 else if (ptq->state->from_nr && !ptq->state->to_nr) 1208 ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL | 1209 PERF_IP_FLAG_VMEXIT; 1210 else 1211 ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL | 1212 PERF_IP_FLAG_ASYNC | 1213 PERF_IP_FLAG_INTERRUPT; 1214 ptq->insn_len = 0; 1215 } else { 1216 if (ptq->state->from_ip) 1217 ptq->flags = intel_pt_insn_type(ptq->state->insn_op); 1218 else 1219 ptq->flags = PERF_IP_FLAG_BRANCH | 1220 PERF_IP_FLAG_TRACE_BEGIN; 1221 if (ptq->state->flags & INTEL_PT_IN_TX) 1222 ptq->flags |= PERF_IP_FLAG_IN_TX; 1223 ptq->insn_len = ptq->state->insn_len; 1224 memcpy(ptq->insn, ptq->state->insn, INTEL_PT_INSN_BUF_SZ); 1225 } 1226 1227 if (ptq->state->type & INTEL_PT_TRACE_BEGIN) 1228 ptq->flags |= PERF_IP_FLAG_TRACE_BEGIN; 1229 if (ptq->state->type & INTEL_PT_TRACE_END) 1230 ptq->flags |= PERF_IP_FLAG_TRACE_END; 1231 } 1232 1233 static void intel_pt_setup_time_range(struct intel_pt *pt, 1234 struct intel_pt_queue *ptq) 1235 { 1236 if (!pt->range_cnt) 1237 return; 1238 1239 ptq->sel_timestamp = pt->time_ranges[0].start; 1240 ptq->sel_idx = 0; 1241 1242 if (ptq->sel_timestamp) { 1243 ptq->sel_start = true; 1244 } else { 1245 ptq->sel_timestamp = pt->time_ranges[0].end; 1246 ptq->sel_start = false; 1247 } 1248 } 1249 1250 static int intel_pt_setup_queue(struct intel_pt *pt, 1251 struct auxtrace_queue *queue, 1252 unsigned int queue_nr) 1253 { 1254 struct intel_pt_queue *ptq = queue->priv; 1255 1256 if (list_empty(&queue->head)) 1257 return 0; 1258 1259 if (!ptq) { 1260 ptq = intel_pt_alloc_queue(pt, queue_nr); 1261 if (!ptq) 1262 return -ENOMEM; 1263 queue->priv = ptq; 1264 1265 if (queue->cpu != -1) 1266 ptq->cpu = queue->cpu; 1267 ptq->tid = queue->tid; 1268 1269 ptq->cbr_seen = UINT_MAX; 1270 1271 if (pt->sampling_mode && !pt->snapshot_mode && 1272 pt->timeless_decoding) 1273 ptq->step_through_buffers = true; 1274 1275 ptq->sync_switch = pt->sync_switch; 1276 1277 intel_pt_setup_time_range(pt, ptq); 1278 } 1279 1280 if (!ptq->on_heap && 1281 (!ptq->sync_switch || 1282 ptq->switch_state != INTEL_PT_SS_EXPECTING_SWITCH_EVENT)) { 1283 const struct intel_pt_state *state; 1284 int ret; 1285 1286 if (pt->timeless_decoding) 1287 return 0; 1288 1289 intel_pt_log("queue %u getting timestamp\n", queue_nr); 1290 intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n", 1291 queue_nr, ptq->cpu, ptq->pid, ptq->tid); 1292 1293 if (ptq->sel_start && ptq->sel_timestamp) { 1294 ret = intel_pt_fast_forward(ptq->decoder, 1295 ptq->sel_timestamp); 1296 if (ret) 1297 return ret; 1298 } 1299 1300 while (1) { 1301 state = intel_pt_decode(ptq->decoder); 1302 if (state->err) { 1303 if (state->err == INTEL_PT_ERR_NODATA) { 1304 intel_pt_log("queue %u has no timestamp\n", 1305 queue_nr); 1306 return 0; 1307 } 1308 continue; 1309 } 1310 if (state->timestamp) 1311 break; 1312 } 1313 1314 ptq->timestamp = state->timestamp; 1315 intel_pt_log("queue %u timestamp 0x%" PRIx64 "\n", 1316 queue_nr, ptq->timestamp); 1317 ptq->state = state; 1318 ptq->have_sample = true; 1319 if (ptq->sel_start && ptq->sel_timestamp && 1320 ptq->timestamp < ptq->sel_timestamp) 1321 ptq->have_sample = false; 1322 intel_pt_sample_flags(ptq); 1323 ret = auxtrace_heap__add(&pt->heap, queue_nr, ptq->timestamp); 1324 if (ret) 1325 return ret; 1326 ptq->on_heap = true; 1327 } 1328 1329 return 0; 1330 } 1331 1332 static int intel_pt_setup_queues(struct intel_pt *pt) 1333 { 1334 unsigned int i; 1335 int ret; 1336 1337 for (i = 0; i < pt->queues.nr_queues; i++) { 1338 ret = intel_pt_setup_queue(pt, &pt->queues.queue_array[i], i); 1339 if (ret) 1340 return ret; 1341 } 1342 return 0; 1343 } 1344 1345 static inline bool intel_pt_skip_event(struct intel_pt *pt) 1346 { 1347 return pt->synth_opts.initial_skip && 1348 pt->num_events++ < pt->synth_opts.initial_skip; 1349 } 1350 1351 /* 1352 * Cannot count CBR as skipped because it won't go away until cbr == cbr_seen. 1353 * Also ensure CBR is first non-skipped event by allowing for 4 more samples 1354 * from this decoder state. 1355 */ 1356 static inline bool intel_pt_skip_cbr_event(struct intel_pt *pt) 1357 { 1358 return pt->synth_opts.initial_skip && 1359 pt->num_events + 4 < pt->synth_opts.initial_skip; 1360 } 1361 1362 static void intel_pt_prep_a_sample(struct intel_pt_queue *ptq, 1363 union perf_event *event, 1364 struct perf_sample *sample) 1365 { 1366 event->sample.header.type = PERF_RECORD_SAMPLE; 1367 event->sample.header.size = sizeof(struct perf_event_header); 1368 1369 sample->pid = ptq->pid; 1370 sample->tid = ptq->tid; 1371 sample->cpu = ptq->cpu; 1372 sample->insn_len = ptq->insn_len; 1373 memcpy(sample->insn, ptq->insn, INTEL_PT_INSN_BUF_SZ); 1374 } 1375 1376 static void intel_pt_prep_b_sample(struct intel_pt *pt, 1377 struct intel_pt_queue *ptq, 1378 union perf_event *event, 1379 struct perf_sample *sample) 1380 { 1381 intel_pt_prep_a_sample(ptq, event, sample); 1382 1383 if (!pt->timeless_decoding) 1384 sample->time = tsc_to_perf_time(ptq->timestamp, &pt->tc); 1385 1386 sample->ip = ptq->state->from_ip; 1387 sample->addr = ptq->state->to_ip; 1388 sample->cpumode = intel_pt_cpumode(ptq, sample->ip, sample->addr); 1389 sample->period = 1; 1390 sample->flags = ptq->flags; 1391 1392 event->sample.header.misc = sample->cpumode; 1393 } 1394 1395 static int intel_pt_inject_event(union perf_event *event, 1396 struct perf_sample *sample, u64 type) 1397 { 1398 event->header.size = perf_event__sample_event_size(sample, type, 0); 1399 return perf_event__synthesize_sample(event, type, 0, sample); 1400 } 1401 1402 static inline int intel_pt_opt_inject(struct intel_pt *pt, 1403 union perf_event *event, 1404 struct perf_sample *sample, u64 type) 1405 { 1406 if (!pt->synth_opts.inject) 1407 return 0; 1408 1409 return intel_pt_inject_event(event, sample, type); 1410 } 1411 1412 static int intel_pt_deliver_synth_event(struct intel_pt *pt, 1413 union perf_event *event, 1414 struct perf_sample *sample, u64 type) 1415 { 1416 int ret; 1417 1418 ret = intel_pt_opt_inject(pt, event, sample, type); 1419 if (ret) 1420 return ret; 1421 1422 ret = perf_session__deliver_synth_event(pt->session, event, sample); 1423 if (ret) 1424 pr_err("Intel PT: failed to deliver event, error %d\n", ret); 1425 1426 return ret; 1427 } 1428 1429 static int intel_pt_synth_branch_sample(struct intel_pt_queue *ptq) 1430 { 1431 struct intel_pt *pt = ptq->pt; 1432 union perf_event *event = ptq->event_buf; 1433 struct perf_sample sample = { .ip = 0, }; 1434 struct dummy_branch_stack { 1435 u64 nr; 1436 u64 hw_idx; 1437 struct branch_entry entries; 1438 } dummy_bs; 1439 1440 if (pt->branches_filter && !(pt->branches_filter & ptq->flags)) 1441 return 0; 1442 1443 if (intel_pt_skip_event(pt)) 1444 return 0; 1445 1446 intel_pt_prep_b_sample(pt, ptq, event, &sample); 1447 1448 sample.id = ptq->pt->branches_id; 1449 sample.stream_id = ptq->pt->branches_id; 1450 1451 /* 1452 * perf report cannot handle events without a branch stack when using 1453 * SORT_MODE__BRANCH so make a dummy one. 1454 */ 1455 if (pt->synth_opts.last_branch && sort__mode == SORT_MODE__BRANCH) { 1456 dummy_bs = (struct dummy_branch_stack){ 1457 .nr = 1, 1458 .hw_idx = -1ULL, 1459 .entries = { 1460 .from = sample.ip, 1461 .to = sample.addr, 1462 }, 1463 }; 1464 sample.branch_stack = (struct branch_stack *)&dummy_bs; 1465 } 1466 1467 if (ptq->state->flags & INTEL_PT_SAMPLE_IPC) 1468 sample.cyc_cnt = ptq->ipc_cyc_cnt - ptq->last_br_cyc_cnt; 1469 if (sample.cyc_cnt) { 1470 sample.insn_cnt = ptq->ipc_insn_cnt - ptq->last_br_insn_cnt; 1471 ptq->last_br_insn_cnt = ptq->ipc_insn_cnt; 1472 ptq->last_br_cyc_cnt = ptq->ipc_cyc_cnt; 1473 } 1474 1475 return intel_pt_deliver_synth_event(pt, event, &sample, 1476 pt->branches_sample_type); 1477 } 1478 1479 static void intel_pt_prep_sample(struct intel_pt *pt, 1480 struct intel_pt_queue *ptq, 1481 union perf_event *event, 1482 struct perf_sample *sample) 1483 { 1484 intel_pt_prep_b_sample(pt, ptq, event, sample); 1485 1486 if (pt->synth_opts.callchain) { 1487 thread_stack__sample(ptq->thread, ptq->cpu, ptq->chain, 1488 pt->synth_opts.callchain_sz + 1, 1489 sample->ip, pt->kernel_start); 1490 sample->callchain = ptq->chain; 1491 } 1492 1493 if (pt->synth_opts.last_branch) { 1494 thread_stack__br_sample(ptq->thread, ptq->cpu, ptq->last_branch, 1495 pt->br_stack_sz); 1496 sample->branch_stack = ptq->last_branch; 1497 } 1498 } 1499 1500 static int intel_pt_synth_instruction_sample(struct intel_pt_queue *ptq) 1501 { 1502 struct intel_pt *pt = ptq->pt; 1503 union perf_event *event = ptq->event_buf; 1504 struct perf_sample sample = { .ip = 0, }; 1505 1506 if (intel_pt_skip_event(pt)) 1507 return 0; 1508 1509 intel_pt_prep_sample(pt, ptq, event, &sample); 1510 1511 sample.id = ptq->pt->instructions_id; 1512 sample.stream_id = ptq->pt->instructions_id; 1513 if (pt->synth_opts.quick) 1514 sample.period = 1; 1515 else 1516 sample.period = ptq->state->tot_insn_cnt - ptq->last_insn_cnt; 1517 1518 if (ptq->state->flags & INTEL_PT_SAMPLE_IPC) 1519 sample.cyc_cnt = ptq->ipc_cyc_cnt - ptq->last_in_cyc_cnt; 1520 if (sample.cyc_cnt) { 1521 sample.insn_cnt = ptq->ipc_insn_cnt - ptq->last_in_insn_cnt; 1522 ptq->last_in_insn_cnt = ptq->ipc_insn_cnt; 1523 ptq->last_in_cyc_cnt = ptq->ipc_cyc_cnt; 1524 } 1525 1526 ptq->last_insn_cnt = ptq->state->tot_insn_cnt; 1527 1528 return intel_pt_deliver_synth_event(pt, event, &sample, 1529 pt->instructions_sample_type); 1530 } 1531 1532 static int intel_pt_synth_transaction_sample(struct intel_pt_queue *ptq) 1533 { 1534 struct intel_pt *pt = ptq->pt; 1535 union perf_event *event = ptq->event_buf; 1536 struct perf_sample sample = { .ip = 0, }; 1537 1538 if (intel_pt_skip_event(pt)) 1539 return 0; 1540 1541 intel_pt_prep_sample(pt, ptq, event, &sample); 1542 1543 sample.id = ptq->pt->transactions_id; 1544 sample.stream_id = ptq->pt->transactions_id; 1545 1546 return intel_pt_deliver_synth_event(pt, event, &sample, 1547 pt->transactions_sample_type); 1548 } 1549 1550 static void intel_pt_prep_p_sample(struct intel_pt *pt, 1551 struct intel_pt_queue *ptq, 1552 union perf_event *event, 1553 struct perf_sample *sample) 1554 { 1555 intel_pt_prep_sample(pt, ptq, event, sample); 1556 1557 /* 1558 * Zero IP is used to mean "trace start" but that is not the case for 1559 * power or PTWRITE events with no IP, so clear the flags. 1560 */ 1561 if (!sample->ip) 1562 sample->flags = 0; 1563 } 1564 1565 static int intel_pt_synth_ptwrite_sample(struct intel_pt_queue *ptq) 1566 { 1567 struct intel_pt *pt = ptq->pt; 1568 union perf_event *event = ptq->event_buf; 1569 struct perf_sample sample = { .ip = 0, }; 1570 struct perf_synth_intel_ptwrite raw; 1571 1572 if (intel_pt_skip_event(pt)) 1573 return 0; 1574 1575 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1576 1577 sample.id = ptq->pt->ptwrites_id; 1578 sample.stream_id = ptq->pt->ptwrites_id; 1579 1580 raw.flags = 0; 1581 raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP); 1582 raw.payload = cpu_to_le64(ptq->state->ptw_payload); 1583 1584 sample.raw_size = perf_synth__raw_size(raw); 1585 sample.raw_data = perf_synth__raw_data(&raw); 1586 1587 return intel_pt_deliver_synth_event(pt, event, &sample, 1588 pt->ptwrites_sample_type); 1589 } 1590 1591 static int intel_pt_synth_cbr_sample(struct intel_pt_queue *ptq) 1592 { 1593 struct intel_pt *pt = ptq->pt; 1594 union perf_event *event = ptq->event_buf; 1595 struct perf_sample sample = { .ip = 0, }; 1596 struct perf_synth_intel_cbr raw; 1597 u32 flags; 1598 1599 if (intel_pt_skip_cbr_event(pt)) 1600 return 0; 1601 1602 ptq->cbr_seen = ptq->state->cbr; 1603 1604 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1605 1606 sample.id = ptq->pt->cbr_id; 1607 sample.stream_id = ptq->pt->cbr_id; 1608 1609 flags = (u16)ptq->state->cbr_payload | (pt->max_non_turbo_ratio << 16); 1610 raw.flags = cpu_to_le32(flags); 1611 raw.freq = cpu_to_le32(raw.cbr * pt->cbr2khz); 1612 raw.reserved3 = 0; 1613 1614 sample.raw_size = perf_synth__raw_size(raw); 1615 sample.raw_data = perf_synth__raw_data(&raw); 1616 1617 return intel_pt_deliver_synth_event(pt, event, &sample, 1618 pt->pwr_events_sample_type); 1619 } 1620 1621 static int intel_pt_synth_psb_sample(struct intel_pt_queue *ptq) 1622 { 1623 struct intel_pt *pt = ptq->pt; 1624 union perf_event *event = ptq->event_buf; 1625 struct perf_sample sample = { .ip = 0, }; 1626 struct perf_synth_intel_psb raw; 1627 1628 if (intel_pt_skip_event(pt)) 1629 return 0; 1630 1631 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1632 1633 sample.id = ptq->pt->psb_id; 1634 sample.stream_id = ptq->pt->psb_id; 1635 sample.flags = 0; 1636 1637 raw.reserved = 0; 1638 raw.offset = ptq->state->psb_offset; 1639 1640 sample.raw_size = perf_synth__raw_size(raw); 1641 sample.raw_data = perf_synth__raw_data(&raw); 1642 1643 return intel_pt_deliver_synth_event(pt, event, &sample, 1644 pt->pwr_events_sample_type); 1645 } 1646 1647 static int intel_pt_synth_mwait_sample(struct intel_pt_queue *ptq) 1648 { 1649 struct intel_pt *pt = ptq->pt; 1650 union perf_event *event = ptq->event_buf; 1651 struct perf_sample sample = { .ip = 0, }; 1652 struct perf_synth_intel_mwait raw; 1653 1654 if (intel_pt_skip_event(pt)) 1655 return 0; 1656 1657 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1658 1659 sample.id = ptq->pt->mwait_id; 1660 sample.stream_id = ptq->pt->mwait_id; 1661 1662 raw.reserved = 0; 1663 raw.payload = cpu_to_le64(ptq->state->mwait_payload); 1664 1665 sample.raw_size = perf_synth__raw_size(raw); 1666 sample.raw_data = perf_synth__raw_data(&raw); 1667 1668 return intel_pt_deliver_synth_event(pt, event, &sample, 1669 pt->pwr_events_sample_type); 1670 } 1671 1672 static int intel_pt_synth_pwre_sample(struct intel_pt_queue *ptq) 1673 { 1674 struct intel_pt *pt = ptq->pt; 1675 union perf_event *event = ptq->event_buf; 1676 struct perf_sample sample = { .ip = 0, }; 1677 struct perf_synth_intel_pwre raw; 1678 1679 if (intel_pt_skip_event(pt)) 1680 return 0; 1681 1682 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1683 1684 sample.id = ptq->pt->pwre_id; 1685 sample.stream_id = ptq->pt->pwre_id; 1686 1687 raw.reserved = 0; 1688 raw.payload = cpu_to_le64(ptq->state->pwre_payload); 1689 1690 sample.raw_size = perf_synth__raw_size(raw); 1691 sample.raw_data = perf_synth__raw_data(&raw); 1692 1693 return intel_pt_deliver_synth_event(pt, event, &sample, 1694 pt->pwr_events_sample_type); 1695 } 1696 1697 static int intel_pt_synth_exstop_sample(struct intel_pt_queue *ptq) 1698 { 1699 struct intel_pt *pt = ptq->pt; 1700 union perf_event *event = ptq->event_buf; 1701 struct perf_sample sample = { .ip = 0, }; 1702 struct perf_synth_intel_exstop raw; 1703 1704 if (intel_pt_skip_event(pt)) 1705 return 0; 1706 1707 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1708 1709 sample.id = ptq->pt->exstop_id; 1710 sample.stream_id = ptq->pt->exstop_id; 1711 1712 raw.flags = 0; 1713 raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP); 1714 1715 sample.raw_size = perf_synth__raw_size(raw); 1716 sample.raw_data = perf_synth__raw_data(&raw); 1717 1718 return intel_pt_deliver_synth_event(pt, event, &sample, 1719 pt->pwr_events_sample_type); 1720 } 1721 1722 static int intel_pt_synth_pwrx_sample(struct intel_pt_queue *ptq) 1723 { 1724 struct intel_pt *pt = ptq->pt; 1725 union perf_event *event = ptq->event_buf; 1726 struct perf_sample sample = { .ip = 0, }; 1727 struct perf_synth_intel_pwrx raw; 1728 1729 if (intel_pt_skip_event(pt)) 1730 return 0; 1731 1732 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1733 1734 sample.id = ptq->pt->pwrx_id; 1735 sample.stream_id = ptq->pt->pwrx_id; 1736 1737 raw.reserved = 0; 1738 raw.payload = cpu_to_le64(ptq->state->pwrx_payload); 1739 1740 sample.raw_size = perf_synth__raw_size(raw); 1741 sample.raw_data = perf_synth__raw_data(&raw); 1742 1743 return intel_pt_deliver_synth_event(pt, event, &sample, 1744 pt->pwr_events_sample_type); 1745 } 1746 1747 /* 1748 * PEBS gp_regs array indexes plus 1 so that 0 means not present. Refer 1749 * intel_pt_add_gp_regs(). 1750 */ 1751 static const int pebs_gp_regs[] = { 1752 [PERF_REG_X86_FLAGS] = 1, 1753 [PERF_REG_X86_IP] = 2, 1754 [PERF_REG_X86_AX] = 3, 1755 [PERF_REG_X86_CX] = 4, 1756 [PERF_REG_X86_DX] = 5, 1757 [PERF_REG_X86_BX] = 6, 1758 [PERF_REG_X86_SP] = 7, 1759 [PERF_REG_X86_BP] = 8, 1760 [PERF_REG_X86_SI] = 9, 1761 [PERF_REG_X86_DI] = 10, 1762 [PERF_REG_X86_R8] = 11, 1763 [PERF_REG_X86_R9] = 12, 1764 [PERF_REG_X86_R10] = 13, 1765 [PERF_REG_X86_R11] = 14, 1766 [PERF_REG_X86_R12] = 15, 1767 [PERF_REG_X86_R13] = 16, 1768 [PERF_REG_X86_R14] = 17, 1769 [PERF_REG_X86_R15] = 18, 1770 }; 1771 1772 static u64 *intel_pt_add_gp_regs(struct regs_dump *intr_regs, u64 *pos, 1773 const struct intel_pt_blk_items *items, 1774 u64 regs_mask) 1775 { 1776 const u64 *gp_regs = items->val[INTEL_PT_GP_REGS_POS]; 1777 u32 mask = items->mask[INTEL_PT_GP_REGS_POS]; 1778 u32 bit; 1779 int i; 1780 1781 for (i = 0, bit = 1; i < PERF_REG_X86_64_MAX; i++, bit <<= 1) { 1782 /* Get the PEBS gp_regs array index */ 1783 int n = pebs_gp_regs[i] - 1; 1784 1785 if (n < 0) 1786 continue; 1787 /* 1788 * Add only registers that were requested (i.e. 'regs_mask') and 1789 * that were provided (i.e. 'mask'), and update the resulting 1790 * mask (i.e. 'intr_regs->mask') accordingly. 1791 */ 1792 if (mask & 1 << n && regs_mask & bit) { 1793 intr_regs->mask |= bit; 1794 *pos++ = gp_regs[n]; 1795 } 1796 } 1797 1798 return pos; 1799 } 1800 1801 #ifndef PERF_REG_X86_XMM0 1802 #define PERF_REG_X86_XMM0 32 1803 #endif 1804 1805 static void intel_pt_add_xmm(struct regs_dump *intr_regs, u64 *pos, 1806 const struct intel_pt_blk_items *items, 1807 u64 regs_mask) 1808 { 1809 u32 mask = items->has_xmm & (regs_mask >> PERF_REG_X86_XMM0); 1810 const u64 *xmm = items->xmm; 1811 1812 /* 1813 * If there are any XMM registers, then there should be all of them. 1814 * Nevertheless, follow the logic to add only registers that were 1815 * requested (i.e. 'regs_mask') and that were provided (i.e. 'mask'), 1816 * and update the resulting mask (i.e. 'intr_regs->mask') accordingly. 1817 */ 1818 intr_regs->mask |= (u64)mask << PERF_REG_X86_XMM0; 1819 1820 for (; mask; mask >>= 1, xmm++) { 1821 if (mask & 1) 1822 *pos++ = *xmm; 1823 } 1824 } 1825 1826 #define LBR_INFO_MISPRED (1ULL << 63) 1827 #define LBR_INFO_IN_TX (1ULL << 62) 1828 #define LBR_INFO_ABORT (1ULL << 61) 1829 #define LBR_INFO_CYCLES 0xffff 1830 1831 /* Refer kernel's intel_pmu_store_pebs_lbrs() */ 1832 static u64 intel_pt_lbr_flags(u64 info) 1833 { 1834 union { 1835 struct branch_flags flags; 1836 u64 result; 1837 } u; 1838 1839 u.result = 0; 1840 u.flags.mispred = !!(info & LBR_INFO_MISPRED); 1841 u.flags.predicted = !(info & LBR_INFO_MISPRED); 1842 u.flags.in_tx = !!(info & LBR_INFO_IN_TX); 1843 u.flags.abort = !!(info & LBR_INFO_ABORT); 1844 u.flags.cycles = info & LBR_INFO_CYCLES; 1845 1846 return u.result; 1847 } 1848 1849 static void intel_pt_add_lbrs(struct branch_stack *br_stack, 1850 const struct intel_pt_blk_items *items) 1851 { 1852 u64 *to; 1853 int i; 1854 1855 br_stack->nr = 0; 1856 1857 to = &br_stack->entries[0].from; 1858 1859 for (i = INTEL_PT_LBR_0_POS; i <= INTEL_PT_LBR_2_POS; i++) { 1860 u32 mask = items->mask[i]; 1861 const u64 *from = items->val[i]; 1862 1863 for (; mask; mask >>= 3, from += 3) { 1864 if ((mask & 7) == 7) { 1865 *to++ = from[0]; 1866 *to++ = from[1]; 1867 *to++ = intel_pt_lbr_flags(from[2]); 1868 br_stack->nr += 1; 1869 } 1870 } 1871 } 1872 } 1873 1874 static int intel_pt_synth_pebs_sample(struct intel_pt_queue *ptq) 1875 { 1876 const struct intel_pt_blk_items *items = &ptq->state->items; 1877 struct perf_sample sample = { .ip = 0, }; 1878 union perf_event *event = ptq->event_buf; 1879 struct intel_pt *pt = ptq->pt; 1880 struct evsel *evsel = pt->pebs_evsel; 1881 u64 sample_type = evsel->core.attr.sample_type; 1882 u64 id = evsel->core.id[0]; 1883 u8 cpumode; 1884 u64 regs[8 * sizeof(sample.intr_regs.mask)]; 1885 1886 if (intel_pt_skip_event(pt)) 1887 return 0; 1888 1889 intel_pt_prep_a_sample(ptq, event, &sample); 1890 1891 sample.id = id; 1892 sample.stream_id = id; 1893 1894 if (!evsel->core.attr.freq) 1895 sample.period = evsel->core.attr.sample_period; 1896 1897 /* No support for non-zero CS base */ 1898 if (items->has_ip) 1899 sample.ip = items->ip; 1900 else if (items->has_rip) 1901 sample.ip = items->rip; 1902 else 1903 sample.ip = ptq->state->from_ip; 1904 1905 cpumode = intel_pt_cpumode(ptq, sample.ip, 0); 1906 1907 event->sample.header.misc = cpumode | PERF_RECORD_MISC_EXACT_IP; 1908 1909 sample.cpumode = cpumode; 1910 1911 if (sample_type & PERF_SAMPLE_TIME) { 1912 u64 timestamp = 0; 1913 1914 if (items->has_timestamp) 1915 timestamp = items->timestamp; 1916 else if (!pt->timeless_decoding) 1917 timestamp = ptq->timestamp; 1918 if (timestamp) 1919 sample.time = tsc_to_perf_time(timestamp, &pt->tc); 1920 } 1921 1922 if (sample_type & PERF_SAMPLE_CALLCHAIN && 1923 pt->synth_opts.callchain) { 1924 thread_stack__sample(ptq->thread, ptq->cpu, ptq->chain, 1925 pt->synth_opts.callchain_sz, sample.ip, 1926 pt->kernel_start); 1927 sample.callchain = ptq->chain; 1928 } 1929 1930 if (sample_type & PERF_SAMPLE_REGS_INTR && 1931 (items->mask[INTEL_PT_GP_REGS_POS] || 1932 items->mask[INTEL_PT_XMM_POS])) { 1933 u64 regs_mask = evsel->core.attr.sample_regs_intr; 1934 u64 *pos; 1935 1936 sample.intr_regs.abi = items->is_32_bit ? 1937 PERF_SAMPLE_REGS_ABI_32 : 1938 PERF_SAMPLE_REGS_ABI_64; 1939 sample.intr_regs.regs = regs; 1940 1941 pos = intel_pt_add_gp_regs(&sample.intr_regs, regs, items, regs_mask); 1942 1943 intel_pt_add_xmm(&sample.intr_regs, pos, items, regs_mask); 1944 } 1945 1946 if (sample_type & PERF_SAMPLE_BRANCH_STACK) { 1947 if (items->mask[INTEL_PT_LBR_0_POS] || 1948 items->mask[INTEL_PT_LBR_1_POS] || 1949 items->mask[INTEL_PT_LBR_2_POS]) { 1950 intel_pt_add_lbrs(ptq->last_branch, items); 1951 } else if (pt->synth_opts.last_branch) { 1952 thread_stack__br_sample(ptq->thread, ptq->cpu, 1953 ptq->last_branch, 1954 pt->br_stack_sz); 1955 } else { 1956 ptq->last_branch->nr = 0; 1957 } 1958 sample.branch_stack = ptq->last_branch; 1959 } 1960 1961 if (sample_type & PERF_SAMPLE_ADDR && items->has_mem_access_address) 1962 sample.addr = items->mem_access_address; 1963 1964 if (sample_type & PERF_SAMPLE_WEIGHT_TYPE) { 1965 /* 1966 * Refer kernel's setup_pebs_adaptive_sample_data() and 1967 * intel_hsw_weight(). 1968 */ 1969 if (items->has_mem_access_latency) { 1970 u64 weight = items->mem_access_latency >> 32; 1971 1972 /* 1973 * Starts from SPR, the mem access latency field 1974 * contains both cache latency [47:32] and instruction 1975 * latency [15:0]. The cache latency is the same as the 1976 * mem access latency on previous platforms. 1977 * 1978 * In practice, no memory access could last than 4G 1979 * cycles. Use latency >> 32 to distinguish the 1980 * different format of the mem access latency field. 1981 */ 1982 if (weight > 0) { 1983 sample.weight = weight & 0xffff; 1984 sample.ins_lat = items->mem_access_latency & 0xffff; 1985 } else 1986 sample.weight = items->mem_access_latency; 1987 } 1988 if (!sample.weight && items->has_tsx_aux_info) { 1989 /* Cycles last block */ 1990 sample.weight = (u32)items->tsx_aux_info; 1991 } 1992 } 1993 1994 if (sample_type & PERF_SAMPLE_TRANSACTION && items->has_tsx_aux_info) { 1995 u64 ax = items->has_rax ? items->rax : 0; 1996 /* Refer kernel's intel_hsw_transaction() */ 1997 u64 txn = (u8)(items->tsx_aux_info >> 32); 1998 1999 /* For RTM XABORTs also log the abort code from AX */ 2000 if (txn & PERF_TXN_TRANSACTION && ax & 1) 2001 txn |= ((ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT; 2002 sample.transaction = txn; 2003 } 2004 2005 return intel_pt_deliver_synth_event(pt, event, &sample, sample_type); 2006 } 2007 2008 static int intel_pt_synth_error(struct intel_pt *pt, int code, int cpu, 2009 pid_t pid, pid_t tid, u64 ip, u64 timestamp) 2010 { 2011 union perf_event event; 2012 char msg[MAX_AUXTRACE_ERROR_MSG]; 2013 int err; 2014 2015 if (pt->synth_opts.error_minus_flags) { 2016 if (code == INTEL_PT_ERR_OVR && 2017 pt->synth_opts.error_minus_flags & AUXTRACE_ERR_FLG_OVERFLOW) 2018 return 0; 2019 if (code == INTEL_PT_ERR_LOST && 2020 pt->synth_opts.error_minus_flags & AUXTRACE_ERR_FLG_DATA_LOST) 2021 return 0; 2022 } 2023 2024 intel_pt__strerror(code, msg, MAX_AUXTRACE_ERROR_MSG); 2025 2026 auxtrace_synth_error(&event.auxtrace_error, PERF_AUXTRACE_ERROR_ITRACE, 2027 code, cpu, pid, tid, ip, msg, timestamp); 2028 2029 err = perf_session__deliver_synth_event(pt->session, &event, NULL); 2030 if (err) 2031 pr_err("Intel Processor Trace: failed to deliver error event, error %d\n", 2032 err); 2033 2034 return err; 2035 } 2036 2037 static int intel_ptq_synth_error(struct intel_pt_queue *ptq, 2038 const struct intel_pt_state *state) 2039 { 2040 struct intel_pt *pt = ptq->pt; 2041 u64 tm = ptq->timestamp; 2042 2043 tm = pt->timeless_decoding ? 0 : tsc_to_perf_time(tm, &pt->tc); 2044 2045 return intel_pt_synth_error(pt, state->err, ptq->cpu, ptq->pid, 2046 ptq->tid, state->from_ip, tm); 2047 } 2048 2049 static int intel_pt_next_tid(struct intel_pt *pt, struct intel_pt_queue *ptq) 2050 { 2051 struct auxtrace_queue *queue; 2052 pid_t tid = ptq->next_tid; 2053 int err; 2054 2055 if (tid == -1) 2056 return 0; 2057 2058 intel_pt_log("switch: cpu %d tid %d\n", ptq->cpu, tid); 2059 2060 err = machine__set_current_tid(pt->machine, ptq->cpu, -1, tid); 2061 2062 queue = &pt->queues.queue_array[ptq->queue_nr]; 2063 intel_pt_set_pid_tid_cpu(pt, queue); 2064 2065 ptq->next_tid = -1; 2066 2067 return err; 2068 } 2069 2070 static inline bool intel_pt_is_switch_ip(struct intel_pt_queue *ptq, u64 ip) 2071 { 2072 struct intel_pt *pt = ptq->pt; 2073 2074 return ip == pt->switch_ip && 2075 (ptq->flags & PERF_IP_FLAG_BRANCH) && 2076 !(ptq->flags & (PERF_IP_FLAG_CONDITIONAL | PERF_IP_FLAG_ASYNC | 2077 PERF_IP_FLAG_INTERRUPT | PERF_IP_FLAG_TX_ABORT)); 2078 } 2079 2080 #define INTEL_PT_PWR_EVT (INTEL_PT_MWAIT_OP | INTEL_PT_PWR_ENTRY | \ 2081 INTEL_PT_EX_STOP | INTEL_PT_PWR_EXIT) 2082 2083 static int intel_pt_sample(struct intel_pt_queue *ptq) 2084 { 2085 const struct intel_pt_state *state = ptq->state; 2086 struct intel_pt *pt = ptq->pt; 2087 int err; 2088 2089 if (!ptq->have_sample) 2090 return 0; 2091 2092 ptq->have_sample = false; 2093 2094 ptq->ipc_insn_cnt = ptq->state->tot_insn_cnt; 2095 ptq->ipc_cyc_cnt = ptq->state->tot_cyc_cnt; 2096 2097 /* 2098 * Do PEBS first to allow for the possibility that the PEBS timestamp 2099 * precedes the current timestamp. 2100 */ 2101 if (pt->sample_pebs && state->type & INTEL_PT_BLK_ITEMS) { 2102 err = intel_pt_synth_pebs_sample(ptq); 2103 if (err) 2104 return err; 2105 } 2106 2107 if (pt->sample_pwr_events) { 2108 if (state->type & INTEL_PT_PSB_EVT) { 2109 err = intel_pt_synth_psb_sample(ptq); 2110 if (err) 2111 return err; 2112 } 2113 if (ptq->state->cbr != ptq->cbr_seen) { 2114 err = intel_pt_synth_cbr_sample(ptq); 2115 if (err) 2116 return err; 2117 } 2118 if (state->type & INTEL_PT_PWR_EVT) { 2119 if (state->type & INTEL_PT_MWAIT_OP) { 2120 err = intel_pt_synth_mwait_sample(ptq); 2121 if (err) 2122 return err; 2123 } 2124 if (state->type & INTEL_PT_PWR_ENTRY) { 2125 err = intel_pt_synth_pwre_sample(ptq); 2126 if (err) 2127 return err; 2128 } 2129 if (state->type & INTEL_PT_EX_STOP) { 2130 err = intel_pt_synth_exstop_sample(ptq); 2131 if (err) 2132 return err; 2133 } 2134 if (state->type & INTEL_PT_PWR_EXIT) { 2135 err = intel_pt_synth_pwrx_sample(ptq); 2136 if (err) 2137 return err; 2138 } 2139 } 2140 } 2141 2142 if (pt->sample_instructions && (state->type & INTEL_PT_INSTRUCTION)) { 2143 err = intel_pt_synth_instruction_sample(ptq); 2144 if (err) 2145 return err; 2146 } 2147 2148 if (pt->sample_transactions && (state->type & INTEL_PT_TRANSACTION)) { 2149 err = intel_pt_synth_transaction_sample(ptq); 2150 if (err) 2151 return err; 2152 } 2153 2154 if (pt->sample_ptwrites && (state->type & INTEL_PT_PTW)) { 2155 err = intel_pt_synth_ptwrite_sample(ptq); 2156 if (err) 2157 return err; 2158 } 2159 2160 if (!(state->type & INTEL_PT_BRANCH)) 2161 return 0; 2162 2163 if (pt->use_thread_stack) { 2164 thread_stack__event(ptq->thread, ptq->cpu, ptq->flags, 2165 state->from_ip, state->to_ip, ptq->insn_len, 2166 state->trace_nr, pt->callstack, 2167 pt->br_stack_sz_plus, 2168 pt->mispred_all); 2169 } else { 2170 thread_stack__set_trace_nr(ptq->thread, ptq->cpu, state->trace_nr); 2171 } 2172 2173 if (pt->sample_branches) { 2174 if (state->from_nr != state->to_nr && 2175 state->from_ip && state->to_ip) { 2176 struct intel_pt_state *st = (struct intel_pt_state *)state; 2177 u64 to_ip = st->to_ip; 2178 u64 from_ip = st->from_ip; 2179 2180 /* 2181 * perf cannot handle having different machines for ip 2182 * and addr, so create 2 branches. 2183 */ 2184 st->to_ip = 0; 2185 err = intel_pt_synth_branch_sample(ptq); 2186 if (err) 2187 return err; 2188 st->from_ip = 0; 2189 st->to_ip = to_ip; 2190 err = intel_pt_synth_branch_sample(ptq); 2191 st->from_ip = from_ip; 2192 } else { 2193 err = intel_pt_synth_branch_sample(ptq); 2194 } 2195 if (err) 2196 return err; 2197 } 2198 2199 if (!ptq->sync_switch) 2200 return 0; 2201 2202 if (intel_pt_is_switch_ip(ptq, state->to_ip)) { 2203 switch (ptq->switch_state) { 2204 case INTEL_PT_SS_NOT_TRACING: 2205 case INTEL_PT_SS_UNKNOWN: 2206 case INTEL_PT_SS_EXPECTING_SWITCH_IP: 2207 err = intel_pt_next_tid(pt, ptq); 2208 if (err) 2209 return err; 2210 ptq->switch_state = INTEL_PT_SS_TRACING; 2211 break; 2212 default: 2213 ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_EVENT; 2214 return 1; 2215 } 2216 } else if (!state->to_ip) { 2217 ptq->switch_state = INTEL_PT_SS_NOT_TRACING; 2218 } else if (ptq->switch_state == INTEL_PT_SS_NOT_TRACING) { 2219 ptq->switch_state = INTEL_PT_SS_UNKNOWN; 2220 } else if (ptq->switch_state == INTEL_PT_SS_UNKNOWN && 2221 state->to_ip == pt->ptss_ip && 2222 (ptq->flags & PERF_IP_FLAG_CALL)) { 2223 ptq->switch_state = INTEL_PT_SS_TRACING; 2224 } 2225 2226 return 0; 2227 } 2228 2229 static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip) 2230 { 2231 struct machine *machine = pt->machine; 2232 struct map *map; 2233 struct symbol *sym, *start; 2234 u64 ip, switch_ip = 0; 2235 const char *ptss; 2236 2237 if (ptss_ip) 2238 *ptss_ip = 0; 2239 2240 map = machine__kernel_map(machine); 2241 if (!map) 2242 return 0; 2243 2244 if (map__load(map)) 2245 return 0; 2246 2247 start = dso__first_symbol(map->dso); 2248 2249 for (sym = start; sym; sym = dso__next_symbol(sym)) { 2250 if (sym->binding == STB_GLOBAL && 2251 !strcmp(sym->name, "__switch_to")) { 2252 ip = map->unmap_ip(map, sym->start); 2253 if (ip >= map->start && ip < map->end) { 2254 switch_ip = ip; 2255 break; 2256 } 2257 } 2258 } 2259 2260 if (!switch_ip || !ptss_ip) 2261 return 0; 2262 2263 if (pt->have_sched_switch == 1) 2264 ptss = "perf_trace_sched_switch"; 2265 else 2266 ptss = "__perf_event_task_sched_out"; 2267 2268 for (sym = start; sym; sym = dso__next_symbol(sym)) { 2269 if (!strcmp(sym->name, ptss)) { 2270 ip = map->unmap_ip(map, sym->start); 2271 if (ip >= map->start && ip < map->end) { 2272 *ptss_ip = ip; 2273 break; 2274 } 2275 } 2276 } 2277 2278 return switch_ip; 2279 } 2280 2281 static void intel_pt_enable_sync_switch(struct intel_pt *pt) 2282 { 2283 unsigned int i; 2284 2285 pt->sync_switch = true; 2286 2287 for (i = 0; i < pt->queues.nr_queues; i++) { 2288 struct auxtrace_queue *queue = &pt->queues.queue_array[i]; 2289 struct intel_pt_queue *ptq = queue->priv; 2290 2291 if (ptq) 2292 ptq->sync_switch = true; 2293 } 2294 } 2295 2296 /* 2297 * To filter against time ranges, it is only necessary to look at the next start 2298 * or end time. 2299 */ 2300 static bool intel_pt_next_time(struct intel_pt_queue *ptq) 2301 { 2302 struct intel_pt *pt = ptq->pt; 2303 2304 if (ptq->sel_start) { 2305 /* Next time is an end time */ 2306 ptq->sel_start = false; 2307 ptq->sel_timestamp = pt->time_ranges[ptq->sel_idx].end; 2308 return true; 2309 } else if (ptq->sel_idx + 1 < pt->range_cnt) { 2310 /* Next time is a start time */ 2311 ptq->sel_start = true; 2312 ptq->sel_idx += 1; 2313 ptq->sel_timestamp = pt->time_ranges[ptq->sel_idx].start; 2314 return true; 2315 } 2316 2317 /* No next time */ 2318 return false; 2319 } 2320 2321 static int intel_pt_time_filter(struct intel_pt_queue *ptq, u64 *ff_timestamp) 2322 { 2323 int err; 2324 2325 while (1) { 2326 if (ptq->sel_start) { 2327 if (ptq->timestamp >= ptq->sel_timestamp) { 2328 /* After start time, so consider next time */ 2329 intel_pt_next_time(ptq); 2330 if (!ptq->sel_timestamp) { 2331 /* No end time */ 2332 return 0; 2333 } 2334 /* Check against end time */ 2335 continue; 2336 } 2337 /* Before start time, so fast forward */ 2338 ptq->have_sample = false; 2339 if (ptq->sel_timestamp > *ff_timestamp) { 2340 if (ptq->sync_switch) { 2341 intel_pt_next_tid(ptq->pt, ptq); 2342 ptq->switch_state = INTEL_PT_SS_UNKNOWN; 2343 } 2344 *ff_timestamp = ptq->sel_timestamp; 2345 err = intel_pt_fast_forward(ptq->decoder, 2346 ptq->sel_timestamp); 2347 if (err) 2348 return err; 2349 } 2350 return 0; 2351 } else if (ptq->timestamp > ptq->sel_timestamp) { 2352 /* After end time, so consider next time */ 2353 if (!intel_pt_next_time(ptq)) { 2354 /* No next time range, so stop decoding */ 2355 ptq->have_sample = false; 2356 ptq->switch_state = INTEL_PT_SS_NOT_TRACING; 2357 return 1; 2358 } 2359 /* Check against next start time */ 2360 continue; 2361 } else { 2362 /* Before end time */ 2363 return 0; 2364 } 2365 } 2366 } 2367 2368 static int intel_pt_run_decoder(struct intel_pt_queue *ptq, u64 *timestamp) 2369 { 2370 const struct intel_pt_state *state = ptq->state; 2371 struct intel_pt *pt = ptq->pt; 2372 u64 ff_timestamp = 0; 2373 int err; 2374 2375 if (!pt->kernel_start) { 2376 pt->kernel_start = machine__kernel_start(pt->machine); 2377 if (pt->per_cpu_mmaps && 2378 (pt->have_sched_switch == 1 || pt->have_sched_switch == 3) && 2379 !pt->timeless_decoding && intel_pt_tracing_kernel(pt) && 2380 !pt->sampling_mode) { 2381 pt->switch_ip = intel_pt_switch_ip(pt, &pt->ptss_ip); 2382 if (pt->switch_ip) { 2383 intel_pt_log("switch_ip: %"PRIx64" ptss_ip: %"PRIx64"\n", 2384 pt->switch_ip, pt->ptss_ip); 2385 intel_pt_enable_sync_switch(pt); 2386 } 2387 } 2388 } 2389 2390 intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n", 2391 ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid); 2392 while (1) { 2393 err = intel_pt_sample(ptq); 2394 if (err) 2395 return err; 2396 2397 state = intel_pt_decode(ptq->decoder); 2398 if (state->err) { 2399 if (state->err == INTEL_PT_ERR_NODATA) 2400 return 1; 2401 if (ptq->sync_switch && 2402 state->from_ip >= pt->kernel_start) { 2403 ptq->sync_switch = false; 2404 intel_pt_next_tid(pt, ptq); 2405 } 2406 if (pt->synth_opts.errors) { 2407 err = intel_ptq_synth_error(ptq, state); 2408 if (err) 2409 return err; 2410 } 2411 continue; 2412 } 2413 2414 ptq->state = state; 2415 ptq->have_sample = true; 2416 intel_pt_sample_flags(ptq); 2417 2418 /* Use estimated TSC upon return to user space */ 2419 if (pt->est_tsc && 2420 (state->from_ip >= pt->kernel_start || !state->from_ip) && 2421 state->to_ip && state->to_ip < pt->kernel_start) { 2422 intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n", 2423 state->timestamp, state->est_timestamp); 2424 ptq->timestamp = state->est_timestamp; 2425 /* Use estimated TSC in unknown switch state */ 2426 } else if (ptq->sync_switch && 2427 ptq->switch_state == INTEL_PT_SS_UNKNOWN && 2428 intel_pt_is_switch_ip(ptq, state->to_ip) && 2429 ptq->next_tid == -1) { 2430 intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n", 2431 state->timestamp, state->est_timestamp); 2432 ptq->timestamp = state->est_timestamp; 2433 } else if (state->timestamp > ptq->timestamp) { 2434 ptq->timestamp = state->timestamp; 2435 } 2436 2437 if (ptq->sel_timestamp) { 2438 err = intel_pt_time_filter(ptq, &ff_timestamp); 2439 if (err) 2440 return err; 2441 } 2442 2443 if (!pt->timeless_decoding && ptq->timestamp >= *timestamp) { 2444 *timestamp = ptq->timestamp; 2445 return 0; 2446 } 2447 } 2448 return 0; 2449 } 2450 2451 static inline int intel_pt_update_queues(struct intel_pt *pt) 2452 { 2453 if (pt->queues.new_data) { 2454 pt->queues.new_data = false; 2455 return intel_pt_setup_queues(pt); 2456 } 2457 return 0; 2458 } 2459 2460 static int intel_pt_process_queues(struct intel_pt *pt, u64 timestamp) 2461 { 2462 unsigned int queue_nr; 2463 u64 ts; 2464 int ret; 2465 2466 while (1) { 2467 struct auxtrace_queue *queue; 2468 struct intel_pt_queue *ptq; 2469 2470 if (!pt->heap.heap_cnt) 2471 return 0; 2472 2473 if (pt->heap.heap_array[0].ordinal >= timestamp) 2474 return 0; 2475 2476 queue_nr = pt->heap.heap_array[0].queue_nr; 2477 queue = &pt->queues.queue_array[queue_nr]; 2478 ptq = queue->priv; 2479 2480 intel_pt_log("queue %u processing 0x%" PRIx64 " to 0x%" PRIx64 "\n", 2481 queue_nr, pt->heap.heap_array[0].ordinal, 2482 timestamp); 2483 2484 auxtrace_heap__pop(&pt->heap); 2485 2486 if (pt->heap.heap_cnt) { 2487 ts = pt->heap.heap_array[0].ordinal + 1; 2488 if (ts > timestamp) 2489 ts = timestamp; 2490 } else { 2491 ts = timestamp; 2492 } 2493 2494 intel_pt_set_pid_tid_cpu(pt, queue); 2495 2496 ret = intel_pt_run_decoder(ptq, &ts); 2497 2498 if (ret < 0) { 2499 auxtrace_heap__add(&pt->heap, queue_nr, ts); 2500 return ret; 2501 } 2502 2503 if (!ret) { 2504 ret = auxtrace_heap__add(&pt->heap, queue_nr, ts); 2505 if (ret < 0) 2506 return ret; 2507 } else { 2508 ptq->on_heap = false; 2509 } 2510 } 2511 2512 return 0; 2513 } 2514 2515 static int intel_pt_process_timeless_queues(struct intel_pt *pt, pid_t tid, 2516 u64 time_) 2517 { 2518 struct auxtrace_queues *queues = &pt->queues; 2519 unsigned int i; 2520 u64 ts = 0; 2521 2522 for (i = 0; i < queues->nr_queues; i++) { 2523 struct auxtrace_queue *queue = &pt->queues.queue_array[i]; 2524 struct intel_pt_queue *ptq = queue->priv; 2525 2526 if (ptq && (tid == -1 || ptq->tid == tid)) { 2527 ptq->time = time_; 2528 intel_pt_set_pid_tid_cpu(pt, queue); 2529 intel_pt_run_decoder(ptq, &ts); 2530 } 2531 } 2532 return 0; 2533 } 2534 2535 static void intel_pt_sample_set_pid_tid_cpu(struct intel_pt_queue *ptq, 2536 struct auxtrace_queue *queue, 2537 struct perf_sample *sample) 2538 { 2539 struct machine *m = ptq->pt->machine; 2540 2541 ptq->pid = sample->pid; 2542 ptq->tid = sample->tid; 2543 ptq->cpu = queue->cpu; 2544 2545 intel_pt_log("queue %u cpu %d pid %d tid %d\n", 2546 ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid); 2547 2548 thread__zput(ptq->thread); 2549 2550 if (ptq->tid == -1) 2551 return; 2552 2553 if (ptq->pid == -1) { 2554 ptq->thread = machine__find_thread(m, -1, ptq->tid); 2555 if (ptq->thread) 2556 ptq->pid = ptq->thread->pid_; 2557 return; 2558 } 2559 2560 ptq->thread = machine__findnew_thread(m, ptq->pid, ptq->tid); 2561 } 2562 2563 static int intel_pt_process_timeless_sample(struct intel_pt *pt, 2564 struct perf_sample *sample) 2565 { 2566 struct auxtrace_queue *queue; 2567 struct intel_pt_queue *ptq; 2568 u64 ts = 0; 2569 2570 queue = auxtrace_queues__sample_queue(&pt->queues, sample, pt->session); 2571 if (!queue) 2572 return -EINVAL; 2573 2574 ptq = queue->priv; 2575 if (!ptq) 2576 return 0; 2577 2578 ptq->stop = false; 2579 ptq->time = sample->time; 2580 intel_pt_sample_set_pid_tid_cpu(ptq, queue, sample); 2581 intel_pt_run_decoder(ptq, &ts); 2582 return 0; 2583 } 2584 2585 static int intel_pt_lost(struct intel_pt *pt, struct perf_sample *sample) 2586 { 2587 return intel_pt_synth_error(pt, INTEL_PT_ERR_LOST, sample->cpu, 2588 sample->pid, sample->tid, 0, sample->time); 2589 } 2590 2591 static struct intel_pt_queue *intel_pt_cpu_to_ptq(struct intel_pt *pt, int cpu) 2592 { 2593 unsigned i, j; 2594 2595 if (cpu < 0 || !pt->queues.nr_queues) 2596 return NULL; 2597 2598 if ((unsigned)cpu >= pt->queues.nr_queues) 2599 i = pt->queues.nr_queues - 1; 2600 else 2601 i = cpu; 2602 2603 if (pt->queues.queue_array[i].cpu == cpu) 2604 return pt->queues.queue_array[i].priv; 2605 2606 for (j = 0; i > 0; j++) { 2607 if (pt->queues.queue_array[--i].cpu == cpu) 2608 return pt->queues.queue_array[i].priv; 2609 } 2610 2611 for (; j < pt->queues.nr_queues; j++) { 2612 if (pt->queues.queue_array[j].cpu == cpu) 2613 return pt->queues.queue_array[j].priv; 2614 } 2615 2616 return NULL; 2617 } 2618 2619 static int intel_pt_sync_switch(struct intel_pt *pt, int cpu, pid_t tid, 2620 u64 timestamp) 2621 { 2622 struct intel_pt_queue *ptq; 2623 int err; 2624 2625 if (!pt->sync_switch) 2626 return 1; 2627 2628 ptq = intel_pt_cpu_to_ptq(pt, cpu); 2629 if (!ptq || !ptq->sync_switch) 2630 return 1; 2631 2632 switch (ptq->switch_state) { 2633 case INTEL_PT_SS_NOT_TRACING: 2634 break; 2635 case INTEL_PT_SS_UNKNOWN: 2636 case INTEL_PT_SS_TRACING: 2637 ptq->next_tid = tid; 2638 ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_IP; 2639 return 0; 2640 case INTEL_PT_SS_EXPECTING_SWITCH_EVENT: 2641 if (!ptq->on_heap) { 2642 ptq->timestamp = perf_time_to_tsc(timestamp, 2643 &pt->tc); 2644 err = auxtrace_heap__add(&pt->heap, ptq->queue_nr, 2645 ptq->timestamp); 2646 if (err) 2647 return err; 2648 ptq->on_heap = true; 2649 } 2650 ptq->switch_state = INTEL_PT_SS_TRACING; 2651 break; 2652 case INTEL_PT_SS_EXPECTING_SWITCH_IP: 2653 intel_pt_log("ERROR: cpu %d expecting switch ip\n", cpu); 2654 break; 2655 default: 2656 break; 2657 } 2658 2659 ptq->next_tid = -1; 2660 2661 return 1; 2662 } 2663 2664 static int intel_pt_process_switch(struct intel_pt *pt, 2665 struct perf_sample *sample) 2666 { 2667 pid_t tid; 2668 int cpu, ret; 2669 struct evsel *evsel = evlist__id2evsel(pt->session->evlist, sample->id); 2670 2671 if (evsel != pt->switch_evsel) 2672 return 0; 2673 2674 tid = evsel__intval(evsel, sample, "next_pid"); 2675 cpu = sample->cpu; 2676 2677 intel_pt_log("sched_switch: cpu %d tid %d time %"PRIu64" tsc %#"PRIx64"\n", 2678 cpu, tid, sample->time, perf_time_to_tsc(sample->time, 2679 &pt->tc)); 2680 2681 ret = intel_pt_sync_switch(pt, cpu, tid, sample->time); 2682 if (ret <= 0) 2683 return ret; 2684 2685 return machine__set_current_tid(pt->machine, cpu, -1, tid); 2686 } 2687 2688 static int intel_pt_context_switch_in(struct intel_pt *pt, 2689 struct perf_sample *sample) 2690 { 2691 pid_t pid = sample->pid; 2692 pid_t tid = sample->tid; 2693 int cpu = sample->cpu; 2694 2695 if (pt->sync_switch) { 2696 struct intel_pt_queue *ptq; 2697 2698 ptq = intel_pt_cpu_to_ptq(pt, cpu); 2699 if (ptq && ptq->sync_switch) { 2700 ptq->next_tid = -1; 2701 switch (ptq->switch_state) { 2702 case INTEL_PT_SS_NOT_TRACING: 2703 case INTEL_PT_SS_UNKNOWN: 2704 case INTEL_PT_SS_TRACING: 2705 break; 2706 case INTEL_PT_SS_EXPECTING_SWITCH_EVENT: 2707 case INTEL_PT_SS_EXPECTING_SWITCH_IP: 2708 ptq->switch_state = INTEL_PT_SS_TRACING; 2709 break; 2710 default: 2711 break; 2712 } 2713 } 2714 } 2715 2716 /* 2717 * If the current tid has not been updated yet, ensure it is now that 2718 * a "switch in" event has occurred. 2719 */ 2720 if (machine__get_current_tid(pt->machine, cpu) == tid) 2721 return 0; 2722 2723 return machine__set_current_tid(pt->machine, cpu, pid, tid); 2724 } 2725 2726 static int intel_pt_context_switch(struct intel_pt *pt, union perf_event *event, 2727 struct perf_sample *sample) 2728 { 2729 bool out = event->header.misc & PERF_RECORD_MISC_SWITCH_OUT; 2730 pid_t pid, tid; 2731 int cpu, ret; 2732 2733 cpu = sample->cpu; 2734 2735 if (pt->have_sched_switch == 3) { 2736 if (!out) 2737 return intel_pt_context_switch_in(pt, sample); 2738 if (event->header.type != PERF_RECORD_SWITCH_CPU_WIDE) { 2739 pr_err("Expecting CPU-wide context switch event\n"); 2740 return -EINVAL; 2741 } 2742 pid = event->context_switch.next_prev_pid; 2743 tid = event->context_switch.next_prev_tid; 2744 } else { 2745 if (out) 2746 return 0; 2747 pid = sample->pid; 2748 tid = sample->tid; 2749 } 2750 2751 if (tid == -1) 2752 intel_pt_log("context_switch event has no tid\n"); 2753 2754 ret = intel_pt_sync_switch(pt, cpu, tid, sample->time); 2755 if (ret <= 0) 2756 return ret; 2757 2758 return machine__set_current_tid(pt->machine, cpu, pid, tid); 2759 } 2760 2761 static int intel_pt_process_itrace_start(struct intel_pt *pt, 2762 union perf_event *event, 2763 struct perf_sample *sample) 2764 { 2765 if (!pt->per_cpu_mmaps) 2766 return 0; 2767 2768 intel_pt_log("itrace_start: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n", 2769 sample->cpu, event->itrace_start.pid, 2770 event->itrace_start.tid, sample->time, 2771 perf_time_to_tsc(sample->time, &pt->tc)); 2772 2773 return machine__set_current_tid(pt->machine, sample->cpu, 2774 event->itrace_start.pid, 2775 event->itrace_start.tid); 2776 } 2777 2778 static int intel_pt_find_map(struct thread *thread, u8 cpumode, u64 addr, 2779 struct addr_location *al) 2780 { 2781 if (!al->map || addr < al->map->start || addr >= al->map->end) { 2782 if (!thread__find_map(thread, cpumode, addr, al)) 2783 return -1; 2784 } 2785 2786 return 0; 2787 } 2788 2789 /* Invalidate all instruction cache entries that overlap the text poke */ 2790 static int intel_pt_text_poke(struct intel_pt *pt, union perf_event *event) 2791 { 2792 u8 cpumode = event->header.misc & PERF_RECORD_MISC_CPUMODE_MASK; 2793 u64 addr = event->text_poke.addr + event->text_poke.new_len - 1; 2794 /* Assume text poke begins in a basic block no more than 4096 bytes */ 2795 int cnt = 4096 + event->text_poke.new_len; 2796 struct thread *thread = pt->unknown_thread; 2797 struct addr_location al = { .map = NULL }; 2798 struct machine *machine = pt->machine; 2799 struct intel_pt_cache_entry *e; 2800 u64 offset; 2801 2802 if (!event->text_poke.new_len) 2803 return 0; 2804 2805 for (; cnt; cnt--, addr--) { 2806 if (intel_pt_find_map(thread, cpumode, addr, &al)) { 2807 if (addr < event->text_poke.addr) 2808 return 0; 2809 continue; 2810 } 2811 2812 if (!al.map->dso || !al.map->dso->auxtrace_cache) 2813 continue; 2814 2815 offset = al.map->map_ip(al.map, addr); 2816 2817 e = intel_pt_cache_lookup(al.map->dso, machine, offset); 2818 if (!e) 2819 continue; 2820 2821 if (addr + e->byte_cnt + e->length <= event->text_poke.addr) { 2822 /* 2823 * No overlap. Working backwards there cannot be another 2824 * basic block that overlaps the text poke if there is a 2825 * branch instruction before the text poke address. 2826 */ 2827 if (e->branch != INTEL_PT_BR_NO_BRANCH) 2828 return 0; 2829 } else { 2830 intel_pt_cache_invalidate(al.map->dso, machine, offset); 2831 intel_pt_log("Invalidated instruction cache for %s at %#"PRIx64"\n", 2832 al.map->dso->long_name, addr); 2833 } 2834 } 2835 2836 return 0; 2837 } 2838 2839 static int intel_pt_process_event(struct perf_session *session, 2840 union perf_event *event, 2841 struct perf_sample *sample, 2842 struct perf_tool *tool) 2843 { 2844 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 2845 auxtrace); 2846 u64 timestamp; 2847 int err = 0; 2848 2849 if (dump_trace) 2850 return 0; 2851 2852 if (!tool->ordered_events) { 2853 pr_err("Intel Processor Trace requires ordered events\n"); 2854 return -EINVAL; 2855 } 2856 2857 if (sample->time && sample->time != (u64)-1) 2858 timestamp = perf_time_to_tsc(sample->time, &pt->tc); 2859 else 2860 timestamp = 0; 2861 2862 if (timestamp || pt->timeless_decoding) { 2863 err = intel_pt_update_queues(pt); 2864 if (err) 2865 return err; 2866 } 2867 2868 if (pt->timeless_decoding) { 2869 if (pt->sampling_mode) { 2870 if (sample->aux_sample.size) 2871 err = intel_pt_process_timeless_sample(pt, 2872 sample); 2873 } else if (event->header.type == PERF_RECORD_EXIT) { 2874 err = intel_pt_process_timeless_queues(pt, 2875 event->fork.tid, 2876 sample->time); 2877 } 2878 } else if (timestamp) { 2879 err = intel_pt_process_queues(pt, timestamp); 2880 } 2881 if (err) 2882 return err; 2883 2884 if (event->header.type == PERF_RECORD_SAMPLE) { 2885 if (pt->synth_opts.add_callchain && !sample->callchain) 2886 intel_pt_add_callchain(pt, sample); 2887 if (pt->synth_opts.add_last_branch && !sample->branch_stack) 2888 intel_pt_add_br_stack(pt, sample); 2889 } 2890 2891 if (event->header.type == PERF_RECORD_AUX && 2892 (event->aux.flags & PERF_AUX_FLAG_TRUNCATED) && 2893 pt->synth_opts.errors) { 2894 err = intel_pt_lost(pt, sample); 2895 if (err) 2896 return err; 2897 } 2898 2899 if (pt->switch_evsel && event->header.type == PERF_RECORD_SAMPLE) 2900 err = intel_pt_process_switch(pt, sample); 2901 else if (event->header.type == PERF_RECORD_ITRACE_START) 2902 err = intel_pt_process_itrace_start(pt, event, sample); 2903 else if (event->header.type == PERF_RECORD_SWITCH || 2904 event->header.type == PERF_RECORD_SWITCH_CPU_WIDE) 2905 err = intel_pt_context_switch(pt, event, sample); 2906 2907 if (!err && event->header.type == PERF_RECORD_TEXT_POKE) 2908 err = intel_pt_text_poke(pt, event); 2909 2910 if (intel_pt_enable_logging && intel_pt_log_events(pt, sample->time)) { 2911 intel_pt_log("event %u: cpu %d time %"PRIu64" tsc %#"PRIx64" ", 2912 event->header.type, sample->cpu, sample->time, timestamp); 2913 intel_pt_log_event(event); 2914 } 2915 2916 return err; 2917 } 2918 2919 static int intel_pt_flush(struct perf_session *session, struct perf_tool *tool) 2920 { 2921 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 2922 auxtrace); 2923 int ret; 2924 2925 if (dump_trace) 2926 return 0; 2927 2928 if (!tool->ordered_events) 2929 return -EINVAL; 2930 2931 ret = intel_pt_update_queues(pt); 2932 if (ret < 0) 2933 return ret; 2934 2935 if (pt->timeless_decoding) 2936 return intel_pt_process_timeless_queues(pt, -1, 2937 MAX_TIMESTAMP - 1); 2938 2939 return intel_pt_process_queues(pt, MAX_TIMESTAMP); 2940 } 2941 2942 static void intel_pt_free_events(struct perf_session *session) 2943 { 2944 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 2945 auxtrace); 2946 struct auxtrace_queues *queues = &pt->queues; 2947 unsigned int i; 2948 2949 for (i = 0; i < queues->nr_queues; i++) { 2950 intel_pt_free_queue(queues->queue_array[i].priv); 2951 queues->queue_array[i].priv = NULL; 2952 } 2953 intel_pt_log_disable(); 2954 auxtrace_queues__free(queues); 2955 } 2956 2957 static void intel_pt_free(struct perf_session *session) 2958 { 2959 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 2960 auxtrace); 2961 2962 auxtrace_heap__free(&pt->heap); 2963 intel_pt_free_events(session); 2964 session->auxtrace = NULL; 2965 thread__put(pt->unknown_thread); 2966 addr_filters__exit(&pt->filts); 2967 zfree(&pt->chain); 2968 zfree(&pt->filter); 2969 zfree(&pt->time_ranges); 2970 free(pt); 2971 } 2972 2973 static bool intel_pt_evsel_is_auxtrace(struct perf_session *session, 2974 struct evsel *evsel) 2975 { 2976 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 2977 auxtrace); 2978 2979 return evsel->core.attr.type == pt->pmu_type; 2980 } 2981 2982 static int intel_pt_process_auxtrace_event(struct perf_session *session, 2983 union perf_event *event, 2984 struct perf_tool *tool __maybe_unused) 2985 { 2986 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 2987 auxtrace); 2988 2989 if (!pt->data_queued) { 2990 struct auxtrace_buffer *buffer; 2991 off_t data_offset; 2992 int fd = perf_data__fd(session->data); 2993 int err; 2994 2995 if (perf_data__is_pipe(session->data)) { 2996 data_offset = 0; 2997 } else { 2998 data_offset = lseek(fd, 0, SEEK_CUR); 2999 if (data_offset == -1) 3000 return -errno; 3001 } 3002 3003 err = auxtrace_queues__add_event(&pt->queues, session, event, 3004 data_offset, &buffer); 3005 if (err) 3006 return err; 3007 3008 /* Dump here now we have copied a piped trace out of the pipe */ 3009 if (dump_trace) { 3010 if (auxtrace_buffer__get_data(buffer, fd)) { 3011 intel_pt_dump_event(pt, buffer->data, 3012 buffer->size); 3013 auxtrace_buffer__put_data(buffer); 3014 } 3015 } 3016 } 3017 3018 return 0; 3019 } 3020 3021 static int intel_pt_queue_data(struct perf_session *session, 3022 struct perf_sample *sample, 3023 union perf_event *event, u64 data_offset) 3024 { 3025 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 3026 auxtrace); 3027 u64 timestamp; 3028 3029 if (event) { 3030 return auxtrace_queues__add_event(&pt->queues, session, event, 3031 data_offset, NULL); 3032 } 3033 3034 if (sample->time && sample->time != (u64)-1) 3035 timestamp = perf_time_to_tsc(sample->time, &pt->tc); 3036 else 3037 timestamp = 0; 3038 3039 return auxtrace_queues__add_sample(&pt->queues, session, sample, 3040 data_offset, timestamp); 3041 } 3042 3043 struct intel_pt_synth { 3044 struct perf_tool dummy_tool; 3045 struct perf_session *session; 3046 }; 3047 3048 static int intel_pt_event_synth(struct perf_tool *tool, 3049 union perf_event *event, 3050 struct perf_sample *sample __maybe_unused, 3051 struct machine *machine __maybe_unused) 3052 { 3053 struct intel_pt_synth *intel_pt_synth = 3054 container_of(tool, struct intel_pt_synth, dummy_tool); 3055 3056 return perf_session__deliver_synth_event(intel_pt_synth->session, event, 3057 NULL); 3058 } 3059 3060 static int intel_pt_synth_event(struct perf_session *session, const char *name, 3061 struct perf_event_attr *attr, u64 id) 3062 { 3063 struct intel_pt_synth intel_pt_synth; 3064 int err; 3065 3066 pr_debug("Synthesizing '%s' event with id %" PRIu64 " sample type %#" PRIx64 "\n", 3067 name, id, (u64)attr->sample_type); 3068 3069 memset(&intel_pt_synth, 0, sizeof(struct intel_pt_synth)); 3070 intel_pt_synth.session = session; 3071 3072 err = perf_event__synthesize_attr(&intel_pt_synth.dummy_tool, attr, 1, 3073 &id, intel_pt_event_synth); 3074 if (err) 3075 pr_err("%s: failed to synthesize '%s' event type\n", 3076 __func__, name); 3077 3078 return err; 3079 } 3080 3081 static void intel_pt_set_event_name(struct evlist *evlist, u64 id, 3082 const char *name) 3083 { 3084 struct evsel *evsel; 3085 3086 evlist__for_each_entry(evlist, evsel) { 3087 if (evsel->core.id && evsel->core.id[0] == id) { 3088 if (evsel->name) 3089 zfree(&evsel->name); 3090 evsel->name = strdup(name); 3091 break; 3092 } 3093 } 3094 } 3095 3096 static struct evsel *intel_pt_evsel(struct intel_pt *pt, 3097 struct evlist *evlist) 3098 { 3099 struct evsel *evsel; 3100 3101 evlist__for_each_entry(evlist, evsel) { 3102 if (evsel->core.attr.type == pt->pmu_type && evsel->core.ids) 3103 return evsel; 3104 } 3105 3106 return NULL; 3107 } 3108 3109 static int intel_pt_synth_events(struct intel_pt *pt, 3110 struct perf_session *session) 3111 { 3112 struct evlist *evlist = session->evlist; 3113 struct evsel *evsel = intel_pt_evsel(pt, evlist); 3114 struct perf_event_attr attr; 3115 u64 id; 3116 int err; 3117 3118 if (!evsel) { 3119 pr_debug("There are no selected events with Intel Processor Trace data\n"); 3120 return 0; 3121 } 3122 3123 memset(&attr, 0, sizeof(struct perf_event_attr)); 3124 attr.size = sizeof(struct perf_event_attr); 3125 attr.type = PERF_TYPE_HARDWARE; 3126 attr.sample_type = evsel->core.attr.sample_type & PERF_SAMPLE_MASK; 3127 attr.sample_type |= PERF_SAMPLE_IP | PERF_SAMPLE_TID | 3128 PERF_SAMPLE_PERIOD; 3129 if (pt->timeless_decoding) 3130 attr.sample_type &= ~(u64)PERF_SAMPLE_TIME; 3131 else 3132 attr.sample_type |= PERF_SAMPLE_TIME; 3133 if (!pt->per_cpu_mmaps) 3134 attr.sample_type &= ~(u64)PERF_SAMPLE_CPU; 3135 attr.exclude_user = evsel->core.attr.exclude_user; 3136 attr.exclude_kernel = evsel->core.attr.exclude_kernel; 3137 attr.exclude_hv = evsel->core.attr.exclude_hv; 3138 attr.exclude_host = evsel->core.attr.exclude_host; 3139 attr.exclude_guest = evsel->core.attr.exclude_guest; 3140 attr.sample_id_all = evsel->core.attr.sample_id_all; 3141 attr.read_format = evsel->core.attr.read_format; 3142 3143 id = evsel->core.id[0] + 1000000000; 3144 if (!id) 3145 id = 1; 3146 3147 if (pt->synth_opts.branches) { 3148 attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS; 3149 attr.sample_period = 1; 3150 attr.sample_type |= PERF_SAMPLE_ADDR; 3151 err = intel_pt_synth_event(session, "branches", &attr, id); 3152 if (err) 3153 return err; 3154 pt->sample_branches = true; 3155 pt->branches_sample_type = attr.sample_type; 3156 pt->branches_id = id; 3157 id += 1; 3158 attr.sample_type &= ~(u64)PERF_SAMPLE_ADDR; 3159 } 3160 3161 if (pt->synth_opts.callchain) 3162 attr.sample_type |= PERF_SAMPLE_CALLCHAIN; 3163 if (pt->synth_opts.last_branch) { 3164 attr.sample_type |= PERF_SAMPLE_BRANCH_STACK; 3165 /* 3166 * We don't use the hardware index, but the sample generation 3167 * code uses the new format branch_stack with this field, 3168 * so the event attributes must indicate that it's present. 3169 */ 3170 attr.branch_sample_type |= PERF_SAMPLE_BRANCH_HW_INDEX; 3171 } 3172 3173 if (pt->synth_opts.instructions) { 3174 attr.config = PERF_COUNT_HW_INSTRUCTIONS; 3175 if (pt->synth_opts.period_type == PERF_ITRACE_PERIOD_NANOSECS) 3176 attr.sample_period = 3177 intel_pt_ns_to_ticks(pt, pt->synth_opts.period); 3178 else 3179 attr.sample_period = pt->synth_opts.period; 3180 err = intel_pt_synth_event(session, "instructions", &attr, id); 3181 if (err) 3182 return err; 3183 pt->sample_instructions = true; 3184 pt->instructions_sample_type = attr.sample_type; 3185 pt->instructions_id = id; 3186 id += 1; 3187 } 3188 3189 attr.sample_type &= ~(u64)PERF_SAMPLE_PERIOD; 3190 attr.sample_period = 1; 3191 3192 if (pt->synth_opts.transactions) { 3193 attr.config = PERF_COUNT_HW_INSTRUCTIONS; 3194 err = intel_pt_synth_event(session, "transactions", &attr, id); 3195 if (err) 3196 return err; 3197 pt->sample_transactions = true; 3198 pt->transactions_sample_type = attr.sample_type; 3199 pt->transactions_id = id; 3200 intel_pt_set_event_name(evlist, id, "transactions"); 3201 id += 1; 3202 } 3203 3204 attr.type = PERF_TYPE_SYNTH; 3205 attr.sample_type |= PERF_SAMPLE_RAW; 3206 3207 if (pt->synth_opts.ptwrites) { 3208 attr.config = PERF_SYNTH_INTEL_PTWRITE; 3209 err = intel_pt_synth_event(session, "ptwrite", &attr, id); 3210 if (err) 3211 return err; 3212 pt->sample_ptwrites = true; 3213 pt->ptwrites_sample_type = attr.sample_type; 3214 pt->ptwrites_id = id; 3215 intel_pt_set_event_name(evlist, id, "ptwrite"); 3216 id += 1; 3217 } 3218 3219 if (pt->synth_opts.pwr_events) { 3220 pt->sample_pwr_events = true; 3221 pt->pwr_events_sample_type = attr.sample_type; 3222 3223 attr.config = PERF_SYNTH_INTEL_CBR; 3224 err = intel_pt_synth_event(session, "cbr", &attr, id); 3225 if (err) 3226 return err; 3227 pt->cbr_id = id; 3228 intel_pt_set_event_name(evlist, id, "cbr"); 3229 id += 1; 3230 3231 attr.config = PERF_SYNTH_INTEL_PSB; 3232 err = intel_pt_synth_event(session, "psb", &attr, id); 3233 if (err) 3234 return err; 3235 pt->psb_id = id; 3236 intel_pt_set_event_name(evlist, id, "psb"); 3237 id += 1; 3238 } 3239 3240 if (pt->synth_opts.pwr_events && (evsel->core.attr.config & 0x10)) { 3241 attr.config = PERF_SYNTH_INTEL_MWAIT; 3242 err = intel_pt_synth_event(session, "mwait", &attr, id); 3243 if (err) 3244 return err; 3245 pt->mwait_id = id; 3246 intel_pt_set_event_name(evlist, id, "mwait"); 3247 id += 1; 3248 3249 attr.config = PERF_SYNTH_INTEL_PWRE; 3250 err = intel_pt_synth_event(session, "pwre", &attr, id); 3251 if (err) 3252 return err; 3253 pt->pwre_id = id; 3254 intel_pt_set_event_name(evlist, id, "pwre"); 3255 id += 1; 3256 3257 attr.config = PERF_SYNTH_INTEL_EXSTOP; 3258 err = intel_pt_synth_event(session, "exstop", &attr, id); 3259 if (err) 3260 return err; 3261 pt->exstop_id = id; 3262 intel_pt_set_event_name(evlist, id, "exstop"); 3263 id += 1; 3264 3265 attr.config = PERF_SYNTH_INTEL_PWRX; 3266 err = intel_pt_synth_event(session, "pwrx", &attr, id); 3267 if (err) 3268 return err; 3269 pt->pwrx_id = id; 3270 intel_pt_set_event_name(evlist, id, "pwrx"); 3271 id += 1; 3272 } 3273 3274 return 0; 3275 } 3276 3277 static void intel_pt_setup_pebs_events(struct intel_pt *pt) 3278 { 3279 struct evsel *evsel; 3280 3281 if (!pt->synth_opts.other_events) 3282 return; 3283 3284 evlist__for_each_entry(pt->session->evlist, evsel) { 3285 if (evsel->core.attr.aux_output && evsel->core.id) { 3286 pt->sample_pebs = true; 3287 pt->pebs_evsel = evsel; 3288 return; 3289 } 3290 } 3291 } 3292 3293 static struct evsel *intel_pt_find_sched_switch(struct evlist *evlist) 3294 { 3295 struct evsel *evsel; 3296 3297 evlist__for_each_entry_reverse(evlist, evsel) { 3298 const char *name = evsel__name(evsel); 3299 3300 if (!strcmp(name, "sched:sched_switch")) 3301 return evsel; 3302 } 3303 3304 return NULL; 3305 } 3306 3307 static bool intel_pt_find_switch(struct evlist *evlist) 3308 { 3309 struct evsel *evsel; 3310 3311 evlist__for_each_entry(evlist, evsel) { 3312 if (evsel->core.attr.context_switch) 3313 return true; 3314 } 3315 3316 return false; 3317 } 3318 3319 static int intel_pt_perf_config(const char *var, const char *value, void *data) 3320 { 3321 struct intel_pt *pt = data; 3322 3323 if (!strcmp(var, "intel-pt.mispred-all")) 3324 pt->mispred_all = perf_config_bool(var, value); 3325 3326 return 0; 3327 } 3328 3329 /* Find least TSC which converts to ns or later */ 3330 static u64 intel_pt_tsc_start(u64 ns, struct intel_pt *pt) 3331 { 3332 u64 tsc, tm; 3333 3334 tsc = perf_time_to_tsc(ns, &pt->tc); 3335 3336 while (1) { 3337 tm = tsc_to_perf_time(tsc, &pt->tc); 3338 if (tm < ns) 3339 break; 3340 tsc -= 1; 3341 } 3342 3343 while (tm < ns) 3344 tm = tsc_to_perf_time(++tsc, &pt->tc); 3345 3346 return tsc; 3347 } 3348 3349 /* Find greatest TSC which converts to ns or earlier */ 3350 static u64 intel_pt_tsc_end(u64 ns, struct intel_pt *pt) 3351 { 3352 u64 tsc, tm; 3353 3354 tsc = perf_time_to_tsc(ns, &pt->tc); 3355 3356 while (1) { 3357 tm = tsc_to_perf_time(tsc, &pt->tc); 3358 if (tm > ns) 3359 break; 3360 tsc += 1; 3361 } 3362 3363 while (tm > ns) 3364 tm = tsc_to_perf_time(--tsc, &pt->tc); 3365 3366 return tsc; 3367 } 3368 3369 static int intel_pt_setup_time_ranges(struct intel_pt *pt, 3370 struct itrace_synth_opts *opts) 3371 { 3372 struct perf_time_interval *p = opts->ptime_range; 3373 int n = opts->range_num; 3374 int i; 3375 3376 if (!n || !p || pt->timeless_decoding) 3377 return 0; 3378 3379 pt->time_ranges = calloc(n, sizeof(struct range)); 3380 if (!pt->time_ranges) 3381 return -ENOMEM; 3382 3383 pt->range_cnt = n; 3384 3385 intel_pt_log("%s: %u range(s)\n", __func__, n); 3386 3387 for (i = 0; i < n; i++) { 3388 struct range *r = &pt->time_ranges[i]; 3389 u64 ts = p[i].start; 3390 u64 te = p[i].end; 3391 3392 /* 3393 * Take care to ensure the TSC range matches the perf-time range 3394 * when converted back to perf-time. 3395 */ 3396 r->start = ts ? intel_pt_tsc_start(ts, pt) : 0; 3397 r->end = te ? intel_pt_tsc_end(te, pt) : 0; 3398 3399 intel_pt_log("range %d: perf time interval: %"PRIu64" to %"PRIu64"\n", 3400 i, ts, te); 3401 intel_pt_log("range %d: TSC time interval: %#"PRIx64" to %#"PRIx64"\n", 3402 i, r->start, r->end); 3403 } 3404 3405 return 0; 3406 } 3407 3408 static const char * const intel_pt_info_fmts[] = { 3409 [INTEL_PT_PMU_TYPE] = " PMU Type %"PRId64"\n", 3410 [INTEL_PT_TIME_SHIFT] = " Time Shift %"PRIu64"\n", 3411 [INTEL_PT_TIME_MULT] = " Time Muliplier %"PRIu64"\n", 3412 [INTEL_PT_TIME_ZERO] = " Time Zero %"PRIu64"\n", 3413 [INTEL_PT_CAP_USER_TIME_ZERO] = " Cap Time Zero %"PRId64"\n", 3414 [INTEL_PT_TSC_BIT] = " TSC bit %#"PRIx64"\n", 3415 [INTEL_PT_NORETCOMP_BIT] = " NoRETComp bit %#"PRIx64"\n", 3416 [INTEL_PT_HAVE_SCHED_SWITCH] = " Have sched_switch %"PRId64"\n", 3417 [INTEL_PT_SNAPSHOT_MODE] = " Snapshot mode %"PRId64"\n", 3418 [INTEL_PT_PER_CPU_MMAPS] = " Per-cpu maps %"PRId64"\n", 3419 [INTEL_PT_MTC_BIT] = " MTC bit %#"PRIx64"\n", 3420 [INTEL_PT_TSC_CTC_N] = " TSC:CTC numerator %"PRIu64"\n", 3421 [INTEL_PT_TSC_CTC_D] = " TSC:CTC denominator %"PRIu64"\n", 3422 [INTEL_PT_CYC_BIT] = " CYC bit %#"PRIx64"\n", 3423 [INTEL_PT_MAX_NONTURBO_RATIO] = " Max non-turbo ratio %"PRIu64"\n", 3424 [INTEL_PT_FILTER_STR_LEN] = " Filter string len. %"PRIu64"\n", 3425 }; 3426 3427 static void intel_pt_print_info(__u64 *arr, int start, int finish) 3428 { 3429 int i; 3430 3431 if (!dump_trace) 3432 return; 3433 3434 for (i = start; i <= finish; i++) 3435 fprintf(stdout, intel_pt_info_fmts[i], arr[i]); 3436 } 3437 3438 static void intel_pt_print_info_str(const char *name, const char *str) 3439 { 3440 if (!dump_trace) 3441 return; 3442 3443 fprintf(stdout, " %-20s%s\n", name, str ? str : ""); 3444 } 3445 3446 static bool intel_pt_has(struct perf_record_auxtrace_info *auxtrace_info, int pos) 3447 { 3448 return auxtrace_info->header.size >= 3449 sizeof(struct perf_record_auxtrace_info) + (sizeof(u64) * (pos + 1)); 3450 } 3451 3452 int intel_pt_process_auxtrace_info(union perf_event *event, 3453 struct perf_session *session) 3454 { 3455 struct perf_record_auxtrace_info *auxtrace_info = &event->auxtrace_info; 3456 size_t min_sz = sizeof(u64) * INTEL_PT_PER_CPU_MMAPS; 3457 struct intel_pt *pt; 3458 void *info_end; 3459 __u64 *info; 3460 int err; 3461 3462 if (auxtrace_info->header.size < sizeof(struct perf_record_auxtrace_info) + 3463 min_sz) 3464 return -EINVAL; 3465 3466 pt = zalloc(sizeof(struct intel_pt)); 3467 if (!pt) 3468 return -ENOMEM; 3469 3470 addr_filters__init(&pt->filts); 3471 3472 err = perf_config(intel_pt_perf_config, pt); 3473 if (err) 3474 goto err_free; 3475 3476 err = auxtrace_queues__init(&pt->queues); 3477 if (err) 3478 goto err_free; 3479 3480 intel_pt_log_set_name(INTEL_PT_PMU_NAME); 3481 3482 pt->session = session; 3483 pt->machine = &session->machines.host; /* No kvm support */ 3484 pt->auxtrace_type = auxtrace_info->type; 3485 pt->pmu_type = auxtrace_info->priv[INTEL_PT_PMU_TYPE]; 3486 pt->tc.time_shift = auxtrace_info->priv[INTEL_PT_TIME_SHIFT]; 3487 pt->tc.time_mult = auxtrace_info->priv[INTEL_PT_TIME_MULT]; 3488 pt->tc.time_zero = auxtrace_info->priv[INTEL_PT_TIME_ZERO]; 3489 pt->cap_user_time_zero = auxtrace_info->priv[INTEL_PT_CAP_USER_TIME_ZERO]; 3490 pt->tsc_bit = auxtrace_info->priv[INTEL_PT_TSC_BIT]; 3491 pt->noretcomp_bit = auxtrace_info->priv[INTEL_PT_NORETCOMP_BIT]; 3492 pt->have_sched_switch = auxtrace_info->priv[INTEL_PT_HAVE_SCHED_SWITCH]; 3493 pt->snapshot_mode = auxtrace_info->priv[INTEL_PT_SNAPSHOT_MODE]; 3494 pt->per_cpu_mmaps = auxtrace_info->priv[INTEL_PT_PER_CPU_MMAPS]; 3495 intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_PMU_TYPE, 3496 INTEL_PT_PER_CPU_MMAPS); 3497 3498 if (intel_pt_has(auxtrace_info, INTEL_PT_CYC_BIT)) { 3499 pt->mtc_bit = auxtrace_info->priv[INTEL_PT_MTC_BIT]; 3500 pt->mtc_freq_bits = auxtrace_info->priv[INTEL_PT_MTC_FREQ_BITS]; 3501 pt->tsc_ctc_ratio_n = auxtrace_info->priv[INTEL_PT_TSC_CTC_N]; 3502 pt->tsc_ctc_ratio_d = auxtrace_info->priv[INTEL_PT_TSC_CTC_D]; 3503 pt->cyc_bit = auxtrace_info->priv[INTEL_PT_CYC_BIT]; 3504 intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_MTC_BIT, 3505 INTEL_PT_CYC_BIT); 3506 } 3507 3508 if (intel_pt_has(auxtrace_info, INTEL_PT_MAX_NONTURBO_RATIO)) { 3509 pt->max_non_turbo_ratio = 3510 auxtrace_info->priv[INTEL_PT_MAX_NONTURBO_RATIO]; 3511 intel_pt_print_info(&auxtrace_info->priv[0], 3512 INTEL_PT_MAX_NONTURBO_RATIO, 3513 INTEL_PT_MAX_NONTURBO_RATIO); 3514 } 3515 3516 info = &auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN] + 1; 3517 info_end = (void *)info + auxtrace_info->header.size; 3518 3519 if (intel_pt_has(auxtrace_info, INTEL_PT_FILTER_STR_LEN)) { 3520 size_t len; 3521 3522 len = auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN]; 3523 intel_pt_print_info(&auxtrace_info->priv[0], 3524 INTEL_PT_FILTER_STR_LEN, 3525 INTEL_PT_FILTER_STR_LEN); 3526 if (len) { 3527 const char *filter = (const char *)info; 3528 3529 len = roundup(len + 1, 8); 3530 info += len >> 3; 3531 if ((void *)info > info_end) { 3532 pr_err("%s: bad filter string length\n", __func__); 3533 err = -EINVAL; 3534 goto err_free_queues; 3535 } 3536 pt->filter = memdup(filter, len); 3537 if (!pt->filter) { 3538 err = -ENOMEM; 3539 goto err_free_queues; 3540 } 3541 if (session->header.needs_swap) 3542 mem_bswap_64(pt->filter, len); 3543 if (pt->filter[len - 1]) { 3544 pr_err("%s: filter string not null terminated\n", __func__); 3545 err = -EINVAL; 3546 goto err_free_queues; 3547 } 3548 err = addr_filters__parse_bare_filter(&pt->filts, 3549 filter); 3550 if (err) 3551 goto err_free_queues; 3552 } 3553 intel_pt_print_info_str("Filter string", pt->filter); 3554 } 3555 3556 pt->timeless_decoding = intel_pt_timeless_decoding(pt); 3557 if (pt->timeless_decoding && !pt->tc.time_mult) 3558 pt->tc.time_mult = 1; 3559 pt->have_tsc = intel_pt_have_tsc(pt); 3560 pt->sampling_mode = intel_pt_sampling_mode(pt); 3561 pt->est_tsc = !pt->timeless_decoding; 3562 3563 pt->unknown_thread = thread__new(999999999, 999999999); 3564 if (!pt->unknown_thread) { 3565 err = -ENOMEM; 3566 goto err_free_queues; 3567 } 3568 3569 /* 3570 * Since this thread will not be kept in any rbtree not in a 3571 * list, initialize its list node so that at thread__put() the 3572 * current thread lifetime assumption is kept and we don't segfault 3573 * at list_del_init(). 3574 */ 3575 INIT_LIST_HEAD(&pt->unknown_thread->node); 3576 3577 err = thread__set_comm(pt->unknown_thread, "unknown", 0); 3578 if (err) 3579 goto err_delete_thread; 3580 if (thread__init_maps(pt->unknown_thread, pt->machine)) { 3581 err = -ENOMEM; 3582 goto err_delete_thread; 3583 } 3584 3585 pt->auxtrace.process_event = intel_pt_process_event; 3586 pt->auxtrace.process_auxtrace_event = intel_pt_process_auxtrace_event; 3587 pt->auxtrace.queue_data = intel_pt_queue_data; 3588 pt->auxtrace.dump_auxtrace_sample = intel_pt_dump_sample; 3589 pt->auxtrace.flush_events = intel_pt_flush; 3590 pt->auxtrace.free_events = intel_pt_free_events; 3591 pt->auxtrace.free = intel_pt_free; 3592 pt->auxtrace.evsel_is_auxtrace = intel_pt_evsel_is_auxtrace; 3593 session->auxtrace = &pt->auxtrace; 3594 3595 if (dump_trace) 3596 return 0; 3597 3598 if (pt->have_sched_switch == 1) { 3599 pt->switch_evsel = intel_pt_find_sched_switch(session->evlist); 3600 if (!pt->switch_evsel) { 3601 pr_err("%s: missing sched_switch event\n", __func__); 3602 err = -EINVAL; 3603 goto err_delete_thread; 3604 } 3605 } else if (pt->have_sched_switch == 2 && 3606 !intel_pt_find_switch(session->evlist)) { 3607 pr_err("%s: missing context_switch attribute flag\n", __func__); 3608 err = -EINVAL; 3609 goto err_delete_thread; 3610 } 3611 3612 if (session->itrace_synth_opts->set) { 3613 pt->synth_opts = *session->itrace_synth_opts; 3614 } else { 3615 itrace_synth_opts__set_default(&pt->synth_opts, 3616 session->itrace_synth_opts->default_no_sample); 3617 if (!session->itrace_synth_opts->default_no_sample && 3618 !session->itrace_synth_opts->inject) { 3619 pt->synth_opts.branches = false; 3620 pt->synth_opts.callchain = true; 3621 pt->synth_opts.add_callchain = true; 3622 } 3623 pt->synth_opts.thread_stack = 3624 session->itrace_synth_opts->thread_stack; 3625 } 3626 3627 if (pt->synth_opts.log) 3628 intel_pt_log_enable(); 3629 3630 /* Maximum non-turbo ratio is TSC freq / 100 MHz */ 3631 if (pt->tc.time_mult) { 3632 u64 tsc_freq = intel_pt_ns_to_ticks(pt, 1000000000); 3633 3634 if (!pt->max_non_turbo_ratio) 3635 pt->max_non_turbo_ratio = 3636 (tsc_freq + 50000000) / 100000000; 3637 intel_pt_log("TSC frequency %"PRIu64"\n", tsc_freq); 3638 intel_pt_log("Maximum non-turbo ratio %u\n", 3639 pt->max_non_turbo_ratio); 3640 pt->cbr2khz = tsc_freq / pt->max_non_turbo_ratio / 1000; 3641 } 3642 3643 err = intel_pt_setup_time_ranges(pt, session->itrace_synth_opts); 3644 if (err) 3645 goto err_delete_thread; 3646 3647 if (pt->synth_opts.calls) 3648 pt->branches_filter |= PERF_IP_FLAG_CALL | PERF_IP_FLAG_ASYNC | 3649 PERF_IP_FLAG_TRACE_END; 3650 if (pt->synth_opts.returns) 3651 pt->branches_filter |= PERF_IP_FLAG_RETURN | 3652 PERF_IP_FLAG_TRACE_BEGIN; 3653 3654 if ((pt->synth_opts.callchain || pt->synth_opts.add_callchain) && 3655 !symbol_conf.use_callchain) { 3656 symbol_conf.use_callchain = true; 3657 if (callchain_register_param(&callchain_param) < 0) { 3658 symbol_conf.use_callchain = false; 3659 pt->synth_opts.callchain = false; 3660 pt->synth_opts.add_callchain = false; 3661 } 3662 } 3663 3664 if (pt->synth_opts.add_callchain) { 3665 err = intel_pt_callchain_init(pt); 3666 if (err) 3667 goto err_delete_thread; 3668 } 3669 3670 if (pt->synth_opts.last_branch || pt->synth_opts.add_last_branch) { 3671 pt->br_stack_sz = pt->synth_opts.last_branch_sz; 3672 pt->br_stack_sz_plus = pt->br_stack_sz; 3673 } 3674 3675 if (pt->synth_opts.add_last_branch) { 3676 err = intel_pt_br_stack_init(pt); 3677 if (err) 3678 goto err_delete_thread; 3679 /* 3680 * Additional branch stack size to cater for tracing from the 3681 * actual sample ip to where the sample time is recorded. 3682 * Measured at about 200 branches, but generously set to 1024. 3683 * If kernel space is not being traced, then add just 1 for the 3684 * branch to kernel space. 3685 */ 3686 if (intel_pt_tracing_kernel(pt)) 3687 pt->br_stack_sz_plus += 1024; 3688 else 3689 pt->br_stack_sz_plus += 1; 3690 } 3691 3692 pt->use_thread_stack = pt->synth_opts.callchain || 3693 pt->synth_opts.add_callchain || 3694 pt->synth_opts.thread_stack || 3695 pt->synth_opts.last_branch || 3696 pt->synth_opts.add_last_branch; 3697 3698 pt->callstack = pt->synth_opts.callchain || 3699 pt->synth_opts.add_callchain || 3700 pt->synth_opts.thread_stack; 3701 3702 err = intel_pt_synth_events(pt, session); 3703 if (err) 3704 goto err_delete_thread; 3705 3706 intel_pt_setup_pebs_events(pt); 3707 3708 if (pt->sampling_mode || list_empty(&session->auxtrace_index)) 3709 err = auxtrace_queue_data(session, true, true); 3710 else 3711 err = auxtrace_queues__process_index(&pt->queues, session); 3712 if (err) 3713 goto err_delete_thread; 3714 3715 if (pt->queues.populated) 3716 pt->data_queued = true; 3717 3718 if (pt->timeless_decoding) 3719 pr_debug2("Intel PT decoding without timestamps\n"); 3720 3721 return 0; 3722 3723 err_delete_thread: 3724 zfree(&pt->chain); 3725 thread__zput(pt->unknown_thread); 3726 err_free_queues: 3727 intel_pt_log_disable(); 3728 auxtrace_queues__free(&pt->queues); 3729 session->auxtrace = NULL; 3730 err_free: 3731 addr_filters__exit(&pt->filts); 3732 zfree(&pt->filter); 3733 zfree(&pt->time_ranges); 3734 free(pt); 3735 return err; 3736 } 3737