1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_pt.c: Intel Processor Trace support 4 * Copyright (c) 2013-2015, Intel Corporation. 5 */ 6 7 #include <inttypes.h> 8 #include <stdio.h> 9 #include <stdbool.h> 10 #include <errno.h> 11 #include <linux/kernel.h> 12 #include <linux/string.h> 13 #include <linux/types.h> 14 #include <linux/zalloc.h> 15 16 #include "session.h" 17 #include "machine.h" 18 #include "memswap.h" 19 #include "sort.h" 20 #include "tool.h" 21 #include "event.h" 22 #include "evlist.h" 23 #include "evsel.h" 24 #include "map.h" 25 #include "color.h" 26 #include "thread.h" 27 #include "thread-stack.h" 28 #include "symbol.h" 29 #include "callchain.h" 30 #include "dso.h" 31 #include "debug.h" 32 #include "auxtrace.h" 33 #include "tsc.h" 34 #include "intel-pt.h" 35 #include "config.h" 36 #include "util/perf_api_probe.h" 37 #include "util/synthetic-events.h" 38 #include "time-utils.h" 39 40 #include "../arch/x86/include/uapi/asm/perf_regs.h" 41 42 #include "intel-pt-decoder/intel-pt-log.h" 43 #include "intel-pt-decoder/intel-pt-decoder.h" 44 #include "intel-pt-decoder/intel-pt-insn-decoder.h" 45 #include "intel-pt-decoder/intel-pt-pkt-decoder.h" 46 47 #define MAX_TIMESTAMP (~0ULL) 48 49 struct range { 50 u64 start; 51 u64 end; 52 }; 53 54 struct intel_pt { 55 struct auxtrace auxtrace; 56 struct auxtrace_queues queues; 57 struct auxtrace_heap heap; 58 u32 auxtrace_type; 59 struct perf_session *session; 60 struct machine *machine; 61 struct evsel *switch_evsel; 62 struct thread *unknown_thread; 63 bool timeless_decoding; 64 bool sampling_mode; 65 bool snapshot_mode; 66 bool per_cpu_mmaps; 67 bool have_tsc; 68 bool data_queued; 69 bool est_tsc; 70 bool sync_switch; 71 bool mispred_all; 72 bool use_thread_stack; 73 bool callstack; 74 unsigned int br_stack_sz; 75 unsigned int br_stack_sz_plus; 76 int have_sched_switch; 77 u32 pmu_type; 78 u64 kernel_start; 79 u64 switch_ip; 80 u64 ptss_ip; 81 82 struct perf_tsc_conversion tc; 83 bool cap_user_time_zero; 84 85 struct itrace_synth_opts synth_opts; 86 87 bool sample_instructions; 88 u64 instructions_sample_type; 89 u64 instructions_id; 90 91 bool sample_branches; 92 u32 branches_filter; 93 u64 branches_sample_type; 94 u64 branches_id; 95 96 bool sample_transactions; 97 u64 transactions_sample_type; 98 u64 transactions_id; 99 100 bool sample_ptwrites; 101 u64 ptwrites_sample_type; 102 u64 ptwrites_id; 103 104 bool sample_pwr_events; 105 u64 pwr_events_sample_type; 106 u64 mwait_id; 107 u64 pwre_id; 108 u64 exstop_id; 109 u64 pwrx_id; 110 u64 cbr_id; 111 112 bool sample_pebs; 113 struct evsel *pebs_evsel; 114 115 u64 tsc_bit; 116 u64 mtc_bit; 117 u64 mtc_freq_bits; 118 u32 tsc_ctc_ratio_n; 119 u32 tsc_ctc_ratio_d; 120 u64 cyc_bit; 121 u64 noretcomp_bit; 122 unsigned max_non_turbo_ratio; 123 unsigned cbr2khz; 124 125 unsigned long num_events; 126 127 char *filter; 128 struct addr_filters filts; 129 130 struct range *time_ranges; 131 unsigned int range_cnt; 132 133 struct ip_callchain *chain; 134 struct branch_stack *br_stack; 135 }; 136 137 enum switch_state { 138 INTEL_PT_SS_NOT_TRACING, 139 INTEL_PT_SS_UNKNOWN, 140 INTEL_PT_SS_TRACING, 141 INTEL_PT_SS_EXPECTING_SWITCH_EVENT, 142 INTEL_PT_SS_EXPECTING_SWITCH_IP, 143 }; 144 145 struct intel_pt_queue { 146 struct intel_pt *pt; 147 unsigned int queue_nr; 148 struct auxtrace_buffer *buffer; 149 struct auxtrace_buffer *old_buffer; 150 void *decoder; 151 const struct intel_pt_state *state; 152 struct ip_callchain *chain; 153 struct branch_stack *last_branch; 154 union perf_event *event_buf; 155 bool on_heap; 156 bool stop; 157 bool step_through_buffers; 158 bool use_buffer_pid_tid; 159 bool sync_switch; 160 pid_t pid, tid; 161 int cpu; 162 int switch_state; 163 pid_t next_tid; 164 struct thread *thread; 165 bool exclude_kernel; 166 bool have_sample; 167 u64 time; 168 u64 timestamp; 169 u64 sel_timestamp; 170 bool sel_start; 171 unsigned int sel_idx; 172 u32 flags; 173 u16 insn_len; 174 u64 last_insn_cnt; 175 u64 ipc_insn_cnt; 176 u64 ipc_cyc_cnt; 177 u64 last_in_insn_cnt; 178 u64 last_in_cyc_cnt; 179 u64 last_br_insn_cnt; 180 u64 last_br_cyc_cnt; 181 unsigned int cbr_seen; 182 char insn[INTEL_PT_INSN_BUF_SZ]; 183 }; 184 185 static void intel_pt_dump(struct intel_pt *pt __maybe_unused, 186 unsigned char *buf, size_t len) 187 { 188 struct intel_pt_pkt packet; 189 size_t pos = 0; 190 int ret, pkt_len, i; 191 char desc[INTEL_PT_PKT_DESC_MAX]; 192 const char *color = PERF_COLOR_BLUE; 193 enum intel_pt_pkt_ctx ctx = INTEL_PT_NO_CTX; 194 195 color_fprintf(stdout, color, 196 ". ... Intel Processor Trace data: size %zu bytes\n", 197 len); 198 199 while (len) { 200 ret = intel_pt_get_packet(buf, len, &packet, &ctx); 201 if (ret > 0) 202 pkt_len = ret; 203 else 204 pkt_len = 1; 205 printf("."); 206 color_fprintf(stdout, color, " %08x: ", pos); 207 for (i = 0; i < pkt_len; i++) 208 color_fprintf(stdout, color, " %02x", buf[i]); 209 for (; i < 16; i++) 210 color_fprintf(stdout, color, " "); 211 if (ret > 0) { 212 ret = intel_pt_pkt_desc(&packet, desc, 213 INTEL_PT_PKT_DESC_MAX); 214 if (ret > 0) 215 color_fprintf(stdout, color, " %s\n", desc); 216 } else { 217 color_fprintf(stdout, color, " Bad packet!\n"); 218 } 219 pos += pkt_len; 220 buf += pkt_len; 221 len -= pkt_len; 222 } 223 } 224 225 static void intel_pt_dump_event(struct intel_pt *pt, unsigned char *buf, 226 size_t len) 227 { 228 printf(".\n"); 229 intel_pt_dump(pt, buf, len); 230 } 231 232 static void intel_pt_log_event(union perf_event *event) 233 { 234 FILE *f = intel_pt_log_fp(); 235 236 if (!intel_pt_enable_logging || !f) 237 return; 238 239 perf_event__fprintf(event, NULL, f); 240 } 241 242 static void intel_pt_dump_sample(struct perf_session *session, 243 struct perf_sample *sample) 244 { 245 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 246 auxtrace); 247 248 printf("\n"); 249 intel_pt_dump(pt, sample->aux_sample.data, sample->aux_sample.size); 250 } 251 252 static bool intel_pt_log_events(struct intel_pt *pt, u64 tm) 253 { 254 struct perf_time_interval *range = pt->synth_opts.ptime_range; 255 int n = pt->synth_opts.range_num; 256 257 if (pt->synth_opts.log_plus_flags & AUXTRACE_LOG_FLG_ALL_PERF_EVTS) 258 return true; 259 260 if (pt->synth_opts.log_minus_flags & AUXTRACE_LOG_FLG_ALL_PERF_EVTS) 261 return false; 262 263 /* perf_time__ranges_skip_sample does not work if time is zero */ 264 if (!tm) 265 tm = 1; 266 267 return !n || !perf_time__ranges_skip_sample(range, n, tm); 268 } 269 270 static int intel_pt_do_fix_overlap(struct intel_pt *pt, struct auxtrace_buffer *a, 271 struct auxtrace_buffer *b) 272 { 273 bool consecutive = false; 274 void *start; 275 276 start = intel_pt_find_overlap(a->data, a->size, b->data, b->size, 277 pt->have_tsc, &consecutive); 278 if (!start) 279 return -EINVAL; 280 b->use_size = b->data + b->size - start; 281 b->use_data = start; 282 if (b->use_size && consecutive) 283 b->consecutive = true; 284 return 0; 285 } 286 287 static int intel_pt_get_buffer(struct intel_pt_queue *ptq, 288 struct auxtrace_buffer *buffer, 289 struct auxtrace_buffer *old_buffer, 290 struct intel_pt_buffer *b) 291 { 292 bool might_overlap; 293 294 if (!buffer->data) { 295 int fd = perf_data__fd(ptq->pt->session->data); 296 297 buffer->data = auxtrace_buffer__get_data(buffer, fd); 298 if (!buffer->data) 299 return -ENOMEM; 300 } 301 302 might_overlap = ptq->pt->snapshot_mode || ptq->pt->sampling_mode; 303 if (might_overlap && !buffer->consecutive && old_buffer && 304 intel_pt_do_fix_overlap(ptq->pt, old_buffer, buffer)) 305 return -ENOMEM; 306 307 if (buffer->use_data) { 308 b->len = buffer->use_size; 309 b->buf = buffer->use_data; 310 } else { 311 b->len = buffer->size; 312 b->buf = buffer->data; 313 } 314 b->ref_timestamp = buffer->reference; 315 316 if (!old_buffer || (might_overlap && !buffer->consecutive)) { 317 b->consecutive = false; 318 b->trace_nr = buffer->buffer_nr + 1; 319 } else { 320 b->consecutive = true; 321 } 322 323 return 0; 324 } 325 326 /* Do not drop buffers with references - refer intel_pt_get_trace() */ 327 static void intel_pt_lookahead_drop_buffer(struct intel_pt_queue *ptq, 328 struct auxtrace_buffer *buffer) 329 { 330 if (!buffer || buffer == ptq->buffer || buffer == ptq->old_buffer) 331 return; 332 333 auxtrace_buffer__drop_data(buffer); 334 } 335 336 /* Must be serialized with respect to intel_pt_get_trace() */ 337 static int intel_pt_lookahead(void *data, intel_pt_lookahead_cb_t cb, 338 void *cb_data) 339 { 340 struct intel_pt_queue *ptq = data; 341 struct auxtrace_buffer *buffer = ptq->buffer; 342 struct auxtrace_buffer *old_buffer = ptq->old_buffer; 343 struct auxtrace_queue *queue; 344 int err = 0; 345 346 queue = &ptq->pt->queues.queue_array[ptq->queue_nr]; 347 348 while (1) { 349 struct intel_pt_buffer b = { .len = 0 }; 350 351 buffer = auxtrace_buffer__next(queue, buffer); 352 if (!buffer) 353 break; 354 355 err = intel_pt_get_buffer(ptq, buffer, old_buffer, &b); 356 if (err) 357 break; 358 359 if (b.len) { 360 intel_pt_lookahead_drop_buffer(ptq, old_buffer); 361 old_buffer = buffer; 362 } else { 363 intel_pt_lookahead_drop_buffer(ptq, buffer); 364 continue; 365 } 366 367 err = cb(&b, cb_data); 368 if (err) 369 break; 370 } 371 372 if (buffer != old_buffer) 373 intel_pt_lookahead_drop_buffer(ptq, buffer); 374 intel_pt_lookahead_drop_buffer(ptq, old_buffer); 375 376 return err; 377 } 378 379 /* 380 * This function assumes data is processed sequentially only. 381 * Must be serialized with respect to intel_pt_lookahead() 382 */ 383 static int intel_pt_get_trace(struct intel_pt_buffer *b, void *data) 384 { 385 struct intel_pt_queue *ptq = data; 386 struct auxtrace_buffer *buffer = ptq->buffer; 387 struct auxtrace_buffer *old_buffer = ptq->old_buffer; 388 struct auxtrace_queue *queue; 389 int err; 390 391 if (ptq->stop) { 392 b->len = 0; 393 return 0; 394 } 395 396 queue = &ptq->pt->queues.queue_array[ptq->queue_nr]; 397 398 buffer = auxtrace_buffer__next(queue, buffer); 399 if (!buffer) { 400 if (old_buffer) 401 auxtrace_buffer__drop_data(old_buffer); 402 b->len = 0; 403 return 0; 404 } 405 406 ptq->buffer = buffer; 407 408 err = intel_pt_get_buffer(ptq, buffer, old_buffer, b); 409 if (err) 410 return err; 411 412 if (ptq->step_through_buffers) 413 ptq->stop = true; 414 415 if (b->len) { 416 if (old_buffer) 417 auxtrace_buffer__drop_data(old_buffer); 418 ptq->old_buffer = buffer; 419 } else { 420 auxtrace_buffer__drop_data(buffer); 421 return intel_pt_get_trace(b, data); 422 } 423 424 return 0; 425 } 426 427 struct intel_pt_cache_entry { 428 struct auxtrace_cache_entry entry; 429 u64 insn_cnt; 430 u64 byte_cnt; 431 enum intel_pt_insn_op op; 432 enum intel_pt_insn_branch branch; 433 int length; 434 int32_t rel; 435 char insn[INTEL_PT_INSN_BUF_SZ]; 436 }; 437 438 static int intel_pt_config_div(const char *var, const char *value, void *data) 439 { 440 int *d = data; 441 long val; 442 443 if (!strcmp(var, "intel-pt.cache-divisor")) { 444 val = strtol(value, NULL, 0); 445 if (val > 0 && val <= INT_MAX) 446 *d = val; 447 } 448 449 return 0; 450 } 451 452 static int intel_pt_cache_divisor(void) 453 { 454 static int d; 455 456 if (d) 457 return d; 458 459 perf_config(intel_pt_config_div, &d); 460 461 if (!d) 462 d = 64; 463 464 return d; 465 } 466 467 static unsigned int intel_pt_cache_size(struct dso *dso, 468 struct machine *machine) 469 { 470 off_t size; 471 472 size = dso__data_size(dso, machine); 473 size /= intel_pt_cache_divisor(); 474 if (size < 1000) 475 return 10; 476 if (size > (1 << 21)) 477 return 21; 478 return 32 - __builtin_clz(size); 479 } 480 481 static struct auxtrace_cache *intel_pt_cache(struct dso *dso, 482 struct machine *machine) 483 { 484 struct auxtrace_cache *c; 485 unsigned int bits; 486 487 if (dso->auxtrace_cache) 488 return dso->auxtrace_cache; 489 490 bits = intel_pt_cache_size(dso, machine); 491 492 /* Ignoring cache creation failure */ 493 c = auxtrace_cache__new(bits, sizeof(struct intel_pt_cache_entry), 200); 494 495 dso->auxtrace_cache = c; 496 497 return c; 498 } 499 500 static int intel_pt_cache_add(struct dso *dso, struct machine *machine, 501 u64 offset, u64 insn_cnt, u64 byte_cnt, 502 struct intel_pt_insn *intel_pt_insn) 503 { 504 struct auxtrace_cache *c = intel_pt_cache(dso, machine); 505 struct intel_pt_cache_entry *e; 506 int err; 507 508 if (!c) 509 return -ENOMEM; 510 511 e = auxtrace_cache__alloc_entry(c); 512 if (!e) 513 return -ENOMEM; 514 515 e->insn_cnt = insn_cnt; 516 e->byte_cnt = byte_cnt; 517 e->op = intel_pt_insn->op; 518 e->branch = intel_pt_insn->branch; 519 e->length = intel_pt_insn->length; 520 e->rel = intel_pt_insn->rel; 521 memcpy(e->insn, intel_pt_insn->buf, INTEL_PT_INSN_BUF_SZ); 522 523 err = auxtrace_cache__add(c, offset, &e->entry); 524 if (err) 525 auxtrace_cache__free_entry(c, e); 526 527 return err; 528 } 529 530 static struct intel_pt_cache_entry * 531 intel_pt_cache_lookup(struct dso *dso, struct machine *machine, u64 offset) 532 { 533 struct auxtrace_cache *c = intel_pt_cache(dso, machine); 534 535 if (!c) 536 return NULL; 537 538 return auxtrace_cache__lookup(dso->auxtrace_cache, offset); 539 } 540 541 static void intel_pt_cache_invalidate(struct dso *dso, struct machine *machine, 542 u64 offset) 543 { 544 struct auxtrace_cache *c = intel_pt_cache(dso, machine); 545 546 if (!c) 547 return; 548 549 auxtrace_cache__remove(dso->auxtrace_cache, offset); 550 } 551 552 static inline u8 intel_pt_cpumode(struct intel_pt *pt, uint64_t ip) 553 { 554 return ip >= pt->kernel_start ? 555 PERF_RECORD_MISC_KERNEL : 556 PERF_RECORD_MISC_USER; 557 } 558 559 static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn, 560 uint64_t *insn_cnt_ptr, uint64_t *ip, 561 uint64_t to_ip, uint64_t max_insn_cnt, 562 void *data) 563 { 564 struct intel_pt_queue *ptq = data; 565 struct machine *machine = ptq->pt->machine; 566 struct thread *thread; 567 struct addr_location al; 568 unsigned char buf[INTEL_PT_INSN_BUF_SZ]; 569 ssize_t len; 570 int x86_64; 571 u8 cpumode; 572 u64 offset, start_offset, start_ip; 573 u64 insn_cnt = 0; 574 bool one_map = true; 575 576 intel_pt_insn->length = 0; 577 578 if (to_ip && *ip == to_ip) 579 goto out_no_cache; 580 581 cpumode = intel_pt_cpumode(ptq->pt, *ip); 582 583 thread = ptq->thread; 584 if (!thread) { 585 if (cpumode != PERF_RECORD_MISC_KERNEL) 586 return -EINVAL; 587 thread = ptq->pt->unknown_thread; 588 } 589 590 while (1) { 591 if (!thread__find_map(thread, cpumode, *ip, &al) || !al.map->dso) 592 return -EINVAL; 593 594 if (al.map->dso->data.status == DSO_DATA_STATUS_ERROR && 595 dso__data_status_seen(al.map->dso, 596 DSO_DATA_STATUS_SEEN_ITRACE)) 597 return -ENOENT; 598 599 offset = al.map->map_ip(al.map, *ip); 600 601 if (!to_ip && one_map) { 602 struct intel_pt_cache_entry *e; 603 604 e = intel_pt_cache_lookup(al.map->dso, machine, offset); 605 if (e && 606 (!max_insn_cnt || e->insn_cnt <= max_insn_cnt)) { 607 *insn_cnt_ptr = e->insn_cnt; 608 *ip += e->byte_cnt; 609 intel_pt_insn->op = e->op; 610 intel_pt_insn->branch = e->branch; 611 intel_pt_insn->length = e->length; 612 intel_pt_insn->rel = e->rel; 613 memcpy(intel_pt_insn->buf, e->insn, 614 INTEL_PT_INSN_BUF_SZ); 615 intel_pt_log_insn_no_data(intel_pt_insn, *ip); 616 return 0; 617 } 618 } 619 620 start_offset = offset; 621 start_ip = *ip; 622 623 /* Load maps to ensure dso->is_64_bit has been updated */ 624 map__load(al.map); 625 626 x86_64 = al.map->dso->is_64_bit; 627 628 while (1) { 629 len = dso__data_read_offset(al.map->dso, machine, 630 offset, buf, 631 INTEL_PT_INSN_BUF_SZ); 632 if (len <= 0) 633 return -EINVAL; 634 635 if (intel_pt_get_insn(buf, len, x86_64, intel_pt_insn)) 636 return -EINVAL; 637 638 intel_pt_log_insn(intel_pt_insn, *ip); 639 640 insn_cnt += 1; 641 642 if (intel_pt_insn->branch != INTEL_PT_BR_NO_BRANCH) 643 goto out; 644 645 if (max_insn_cnt && insn_cnt >= max_insn_cnt) 646 goto out_no_cache; 647 648 *ip += intel_pt_insn->length; 649 650 if (to_ip && *ip == to_ip) 651 goto out_no_cache; 652 653 if (*ip >= al.map->end) 654 break; 655 656 offset += intel_pt_insn->length; 657 } 658 one_map = false; 659 } 660 out: 661 *insn_cnt_ptr = insn_cnt; 662 663 if (!one_map) 664 goto out_no_cache; 665 666 /* 667 * Didn't lookup in the 'to_ip' case, so do it now to prevent duplicate 668 * entries. 669 */ 670 if (to_ip) { 671 struct intel_pt_cache_entry *e; 672 673 e = intel_pt_cache_lookup(al.map->dso, machine, start_offset); 674 if (e) 675 return 0; 676 } 677 678 /* Ignore cache errors */ 679 intel_pt_cache_add(al.map->dso, machine, start_offset, insn_cnt, 680 *ip - start_ip, intel_pt_insn); 681 682 return 0; 683 684 out_no_cache: 685 *insn_cnt_ptr = insn_cnt; 686 return 0; 687 } 688 689 static bool intel_pt_match_pgd_ip(struct intel_pt *pt, uint64_t ip, 690 uint64_t offset, const char *filename) 691 { 692 struct addr_filter *filt; 693 bool have_filter = false; 694 bool hit_tracestop = false; 695 bool hit_filter = false; 696 697 list_for_each_entry(filt, &pt->filts.head, list) { 698 if (filt->start) 699 have_filter = true; 700 701 if ((filename && !filt->filename) || 702 (!filename && filt->filename) || 703 (filename && strcmp(filename, filt->filename))) 704 continue; 705 706 if (!(offset >= filt->addr && offset < filt->addr + filt->size)) 707 continue; 708 709 intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s hit filter: %s offset %#"PRIx64" size %#"PRIx64"\n", 710 ip, offset, filename ? filename : "[kernel]", 711 filt->start ? "filter" : "stop", 712 filt->addr, filt->size); 713 714 if (filt->start) 715 hit_filter = true; 716 else 717 hit_tracestop = true; 718 } 719 720 if (!hit_tracestop && !hit_filter) 721 intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s is not in a filter region\n", 722 ip, offset, filename ? filename : "[kernel]"); 723 724 return hit_tracestop || (have_filter && !hit_filter); 725 } 726 727 static int __intel_pt_pgd_ip(uint64_t ip, void *data) 728 { 729 struct intel_pt_queue *ptq = data; 730 struct thread *thread; 731 struct addr_location al; 732 u8 cpumode; 733 u64 offset; 734 735 if (ip >= ptq->pt->kernel_start) 736 return intel_pt_match_pgd_ip(ptq->pt, ip, ip, NULL); 737 738 cpumode = PERF_RECORD_MISC_USER; 739 740 thread = ptq->thread; 741 if (!thread) 742 return -EINVAL; 743 744 if (!thread__find_map(thread, cpumode, ip, &al) || !al.map->dso) 745 return -EINVAL; 746 747 offset = al.map->map_ip(al.map, ip); 748 749 return intel_pt_match_pgd_ip(ptq->pt, ip, offset, 750 al.map->dso->long_name); 751 } 752 753 static bool intel_pt_pgd_ip(uint64_t ip, void *data) 754 { 755 return __intel_pt_pgd_ip(ip, data) > 0; 756 } 757 758 static bool intel_pt_get_config(struct intel_pt *pt, 759 struct perf_event_attr *attr, u64 *config) 760 { 761 if (attr->type == pt->pmu_type) { 762 if (config) 763 *config = attr->config; 764 return true; 765 } 766 767 return false; 768 } 769 770 static bool intel_pt_exclude_kernel(struct intel_pt *pt) 771 { 772 struct evsel *evsel; 773 774 evlist__for_each_entry(pt->session->evlist, evsel) { 775 if (intel_pt_get_config(pt, &evsel->core.attr, NULL) && 776 !evsel->core.attr.exclude_kernel) 777 return false; 778 } 779 return true; 780 } 781 782 static bool intel_pt_return_compression(struct intel_pt *pt) 783 { 784 struct evsel *evsel; 785 u64 config; 786 787 if (!pt->noretcomp_bit) 788 return true; 789 790 evlist__for_each_entry(pt->session->evlist, evsel) { 791 if (intel_pt_get_config(pt, &evsel->core.attr, &config) && 792 (config & pt->noretcomp_bit)) 793 return false; 794 } 795 return true; 796 } 797 798 static bool intel_pt_branch_enable(struct intel_pt *pt) 799 { 800 struct evsel *evsel; 801 u64 config; 802 803 evlist__for_each_entry(pt->session->evlist, evsel) { 804 if (intel_pt_get_config(pt, &evsel->core.attr, &config) && 805 (config & 1) && !(config & 0x2000)) 806 return false; 807 } 808 return true; 809 } 810 811 static unsigned int intel_pt_mtc_period(struct intel_pt *pt) 812 { 813 struct evsel *evsel; 814 unsigned int shift; 815 u64 config; 816 817 if (!pt->mtc_freq_bits) 818 return 0; 819 820 for (shift = 0, config = pt->mtc_freq_bits; !(config & 1); shift++) 821 config >>= 1; 822 823 evlist__for_each_entry(pt->session->evlist, evsel) { 824 if (intel_pt_get_config(pt, &evsel->core.attr, &config)) 825 return (config & pt->mtc_freq_bits) >> shift; 826 } 827 return 0; 828 } 829 830 static bool intel_pt_timeless_decoding(struct intel_pt *pt) 831 { 832 struct evsel *evsel; 833 bool timeless_decoding = true; 834 u64 config; 835 836 if (!pt->tsc_bit || !pt->cap_user_time_zero) 837 return true; 838 839 evlist__for_each_entry(pt->session->evlist, evsel) { 840 if (!(evsel->core.attr.sample_type & PERF_SAMPLE_TIME)) 841 return true; 842 if (intel_pt_get_config(pt, &evsel->core.attr, &config)) { 843 if (config & pt->tsc_bit) 844 timeless_decoding = false; 845 else 846 return true; 847 } 848 } 849 return timeless_decoding; 850 } 851 852 static bool intel_pt_tracing_kernel(struct intel_pt *pt) 853 { 854 struct evsel *evsel; 855 856 evlist__for_each_entry(pt->session->evlist, evsel) { 857 if (intel_pt_get_config(pt, &evsel->core.attr, NULL) && 858 !evsel->core.attr.exclude_kernel) 859 return true; 860 } 861 return false; 862 } 863 864 static bool intel_pt_have_tsc(struct intel_pt *pt) 865 { 866 struct evsel *evsel; 867 bool have_tsc = false; 868 u64 config; 869 870 if (!pt->tsc_bit) 871 return false; 872 873 evlist__for_each_entry(pt->session->evlist, evsel) { 874 if (intel_pt_get_config(pt, &evsel->core.attr, &config)) { 875 if (config & pt->tsc_bit) 876 have_tsc = true; 877 else 878 return false; 879 } 880 } 881 return have_tsc; 882 } 883 884 static bool intel_pt_sampling_mode(struct intel_pt *pt) 885 { 886 struct evsel *evsel; 887 888 evlist__for_each_entry(pt->session->evlist, evsel) { 889 if ((evsel->core.attr.sample_type & PERF_SAMPLE_AUX) && 890 evsel->core.attr.aux_sample_size) 891 return true; 892 } 893 return false; 894 } 895 896 static u64 intel_pt_ns_to_ticks(const struct intel_pt *pt, u64 ns) 897 { 898 u64 quot, rem; 899 900 quot = ns / pt->tc.time_mult; 901 rem = ns % pt->tc.time_mult; 902 return (quot << pt->tc.time_shift) + (rem << pt->tc.time_shift) / 903 pt->tc.time_mult; 904 } 905 906 static struct ip_callchain *intel_pt_alloc_chain(struct intel_pt *pt) 907 { 908 size_t sz = sizeof(struct ip_callchain); 909 910 /* Add 1 to callchain_sz for callchain context */ 911 sz += (pt->synth_opts.callchain_sz + 1) * sizeof(u64); 912 return zalloc(sz); 913 } 914 915 static int intel_pt_callchain_init(struct intel_pt *pt) 916 { 917 struct evsel *evsel; 918 919 evlist__for_each_entry(pt->session->evlist, evsel) { 920 if (!(evsel->core.attr.sample_type & PERF_SAMPLE_CALLCHAIN)) 921 evsel->synth_sample_type |= PERF_SAMPLE_CALLCHAIN; 922 } 923 924 pt->chain = intel_pt_alloc_chain(pt); 925 if (!pt->chain) 926 return -ENOMEM; 927 928 return 0; 929 } 930 931 static void intel_pt_add_callchain(struct intel_pt *pt, 932 struct perf_sample *sample) 933 { 934 struct thread *thread = machine__findnew_thread(pt->machine, 935 sample->pid, 936 sample->tid); 937 938 thread_stack__sample_late(thread, sample->cpu, pt->chain, 939 pt->synth_opts.callchain_sz + 1, sample->ip, 940 pt->kernel_start); 941 942 sample->callchain = pt->chain; 943 } 944 945 static struct branch_stack *intel_pt_alloc_br_stack(unsigned int entry_cnt) 946 { 947 size_t sz = sizeof(struct branch_stack); 948 949 sz += entry_cnt * sizeof(struct branch_entry); 950 return zalloc(sz); 951 } 952 953 static int intel_pt_br_stack_init(struct intel_pt *pt) 954 { 955 struct evsel *evsel; 956 957 evlist__for_each_entry(pt->session->evlist, evsel) { 958 if (!(evsel->core.attr.sample_type & PERF_SAMPLE_BRANCH_STACK)) 959 evsel->synth_sample_type |= PERF_SAMPLE_BRANCH_STACK; 960 } 961 962 pt->br_stack = intel_pt_alloc_br_stack(pt->br_stack_sz); 963 if (!pt->br_stack) 964 return -ENOMEM; 965 966 return 0; 967 } 968 969 static void intel_pt_add_br_stack(struct intel_pt *pt, 970 struct perf_sample *sample) 971 { 972 struct thread *thread = machine__findnew_thread(pt->machine, 973 sample->pid, 974 sample->tid); 975 976 thread_stack__br_sample_late(thread, sample->cpu, pt->br_stack, 977 pt->br_stack_sz, sample->ip, 978 pt->kernel_start); 979 980 sample->branch_stack = pt->br_stack; 981 } 982 983 /* INTEL_PT_LBR_0, INTEL_PT_LBR_1 and INTEL_PT_LBR_2 */ 984 #define LBRS_MAX (INTEL_PT_BLK_ITEM_ID_CNT * 3U) 985 986 static struct intel_pt_queue *intel_pt_alloc_queue(struct intel_pt *pt, 987 unsigned int queue_nr) 988 { 989 struct intel_pt_params params = { .get_trace = 0, }; 990 struct perf_env *env = pt->machine->env; 991 struct intel_pt_queue *ptq; 992 993 ptq = zalloc(sizeof(struct intel_pt_queue)); 994 if (!ptq) 995 return NULL; 996 997 if (pt->synth_opts.callchain) { 998 ptq->chain = intel_pt_alloc_chain(pt); 999 if (!ptq->chain) 1000 goto out_free; 1001 } 1002 1003 if (pt->synth_opts.last_branch || pt->synth_opts.other_events) { 1004 unsigned int entry_cnt = max(LBRS_MAX, pt->br_stack_sz); 1005 1006 ptq->last_branch = intel_pt_alloc_br_stack(entry_cnt); 1007 if (!ptq->last_branch) 1008 goto out_free; 1009 } 1010 1011 ptq->event_buf = malloc(PERF_SAMPLE_MAX_SIZE); 1012 if (!ptq->event_buf) 1013 goto out_free; 1014 1015 ptq->pt = pt; 1016 ptq->queue_nr = queue_nr; 1017 ptq->exclude_kernel = intel_pt_exclude_kernel(pt); 1018 ptq->pid = -1; 1019 ptq->tid = -1; 1020 ptq->cpu = -1; 1021 ptq->next_tid = -1; 1022 1023 params.get_trace = intel_pt_get_trace; 1024 params.walk_insn = intel_pt_walk_next_insn; 1025 params.lookahead = intel_pt_lookahead; 1026 params.data = ptq; 1027 params.return_compression = intel_pt_return_compression(pt); 1028 params.branch_enable = intel_pt_branch_enable(pt); 1029 params.max_non_turbo_ratio = pt->max_non_turbo_ratio; 1030 params.mtc_period = intel_pt_mtc_period(pt); 1031 params.tsc_ctc_ratio_n = pt->tsc_ctc_ratio_n; 1032 params.tsc_ctc_ratio_d = pt->tsc_ctc_ratio_d; 1033 params.quick = pt->synth_opts.quick; 1034 1035 if (pt->filts.cnt > 0) 1036 params.pgd_ip = intel_pt_pgd_ip; 1037 1038 if (pt->synth_opts.instructions) { 1039 if (pt->synth_opts.period) { 1040 switch (pt->synth_opts.period_type) { 1041 case PERF_ITRACE_PERIOD_INSTRUCTIONS: 1042 params.period_type = 1043 INTEL_PT_PERIOD_INSTRUCTIONS; 1044 params.period = pt->synth_opts.period; 1045 break; 1046 case PERF_ITRACE_PERIOD_TICKS: 1047 params.period_type = INTEL_PT_PERIOD_TICKS; 1048 params.period = pt->synth_opts.period; 1049 break; 1050 case PERF_ITRACE_PERIOD_NANOSECS: 1051 params.period_type = INTEL_PT_PERIOD_TICKS; 1052 params.period = intel_pt_ns_to_ticks(pt, 1053 pt->synth_opts.period); 1054 break; 1055 default: 1056 break; 1057 } 1058 } 1059 1060 if (!params.period) { 1061 params.period_type = INTEL_PT_PERIOD_INSTRUCTIONS; 1062 params.period = 1; 1063 } 1064 } 1065 1066 if (env->cpuid && !strncmp(env->cpuid, "GenuineIntel,6,92,", 18)) 1067 params.flags |= INTEL_PT_FUP_WITH_NLIP; 1068 1069 ptq->decoder = intel_pt_decoder_new(¶ms); 1070 if (!ptq->decoder) 1071 goto out_free; 1072 1073 return ptq; 1074 1075 out_free: 1076 zfree(&ptq->event_buf); 1077 zfree(&ptq->last_branch); 1078 zfree(&ptq->chain); 1079 free(ptq); 1080 return NULL; 1081 } 1082 1083 static void intel_pt_free_queue(void *priv) 1084 { 1085 struct intel_pt_queue *ptq = priv; 1086 1087 if (!ptq) 1088 return; 1089 thread__zput(ptq->thread); 1090 intel_pt_decoder_free(ptq->decoder); 1091 zfree(&ptq->event_buf); 1092 zfree(&ptq->last_branch); 1093 zfree(&ptq->chain); 1094 free(ptq); 1095 } 1096 1097 static void intel_pt_set_pid_tid_cpu(struct intel_pt *pt, 1098 struct auxtrace_queue *queue) 1099 { 1100 struct intel_pt_queue *ptq = queue->priv; 1101 1102 if (queue->tid == -1 || pt->have_sched_switch) { 1103 ptq->tid = machine__get_current_tid(pt->machine, ptq->cpu); 1104 thread__zput(ptq->thread); 1105 } 1106 1107 if (!ptq->thread && ptq->tid != -1) 1108 ptq->thread = machine__find_thread(pt->machine, -1, ptq->tid); 1109 1110 if (ptq->thread) { 1111 ptq->pid = ptq->thread->pid_; 1112 if (queue->cpu == -1) 1113 ptq->cpu = ptq->thread->cpu; 1114 } 1115 } 1116 1117 static void intel_pt_sample_flags(struct intel_pt_queue *ptq) 1118 { 1119 if (ptq->state->flags & INTEL_PT_ABORT_TX) { 1120 ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TX_ABORT; 1121 } else if (ptq->state->flags & INTEL_PT_ASYNC) { 1122 if (ptq->state->to_ip) 1123 ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL | 1124 PERF_IP_FLAG_ASYNC | 1125 PERF_IP_FLAG_INTERRUPT; 1126 else 1127 ptq->flags = PERF_IP_FLAG_BRANCH | 1128 PERF_IP_FLAG_TRACE_END; 1129 ptq->insn_len = 0; 1130 } else { 1131 if (ptq->state->from_ip) 1132 ptq->flags = intel_pt_insn_type(ptq->state->insn_op); 1133 else 1134 ptq->flags = PERF_IP_FLAG_BRANCH | 1135 PERF_IP_FLAG_TRACE_BEGIN; 1136 if (ptq->state->flags & INTEL_PT_IN_TX) 1137 ptq->flags |= PERF_IP_FLAG_IN_TX; 1138 ptq->insn_len = ptq->state->insn_len; 1139 memcpy(ptq->insn, ptq->state->insn, INTEL_PT_INSN_BUF_SZ); 1140 } 1141 1142 if (ptq->state->type & INTEL_PT_TRACE_BEGIN) 1143 ptq->flags |= PERF_IP_FLAG_TRACE_BEGIN; 1144 if (ptq->state->type & INTEL_PT_TRACE_END) 1145 ptq->flags |= PERF_IP_FLAG_TRACE_END; 1146 } 1147 1148 static void intel_pt_setup_time_range(struct intel_pt *pt, 1149 struct intel_pt_queue *ptq) 1150 { 1151 if (!pt->range_cnt) 1152 return; 1153 1154 ptq->sel_timestamp = pt->time_ranges[0].start; 1155 ptq->sel_idx = 0; 1156 1157 if (ptq->sel_timestamp) { 1158 ptq->sel_start = true; 1159 } else { 1160 ptq->sel_timestamp = pt->time_ranges[0].end; 1161 ptq->sel_start = false; 1162 } 1163 } 1164 1165 static int intel_pt_setup_queue(struct intel_pt *pt, 1166 struct auxtrace_queue *queue, 1167 unsigned int queue_nr) 1168 { 1169 struct intel_pt_queue *ptq = queue->priv; 1170 1171 if (list_empty(&queue->head)) 1172 return 0; 1173 1174 if (!ptq) { 1175 ptq = intel_pt_alloc_queue(pt, queue_nr); 1176 if (!ptq) 1177 return -ENOMEM; 1178 queue->priv = ptq; 1179 1180 if (queue->cpu != -1) 1181 ptq->cpu = queue->cpu; 1182 ptq->tid = queue->tid; 1183 1184 ptq->cbr_seen = UINT_MAX; 1185 1186 if (pt->sampling_mode && !pt->snapshot_mode && 1187 pt->timeless_decoding) 1188 ptq->step_through_buffers = true; 1189 1190 ptq->sync_switch = pt->sync_switch; 1191 1192 intel_pt_setup_time_range(pt, ptq); 1193 } 1194 1195 if (!ptq->on_heap && 1196 (!ptq->sync_switch || 1197 ptq->switch_state != INTEL_PT_SS_EXPECTING_SWITCH_EVENT)) { 1198 const struct intel_pt_state *state; 1199 int ret; 1200 1201 if (pt->timeless_decoding) 1202 return 0; 1203 1204 intel_pt_log("queue %u getting timestamp\n", queue_nr); 1205 intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n", 1206 queue_nr, ptq->cpu, ptq->pid, ptq->tid); 1207 1208 if (ptq->sel_start && ptq->sel_timestamp) { 1209 ret = intel_pt_fast_forward(ptq->decoder, 1210 ptq->sel_timestamp); 1211 if (ret) 1212 return ret; 1213 } 1214 1215 while (1) { 1216 state = intel_pt_decode(ptq->decoder); 1217 if (state->err) { 1218 if (state->err == INTEL_PT_ERR_NODATA) { 1219 intel_pt_log("queue %u has no timestamp\n", 1220 queue_nr); 1221 return 0; 1222 } 1223 continue; 1224 } 1225 if (state->timestamp) 1226 break; 1227 } 1228 1229 ptq->timestamp = state->timestamp; 1230 intel_pt_log("queue %u timestamp 0x%" PRIx64 "\n", 1231 queue_nr, ptq->timestamp); 1232 ptq->state = state; 1233 ptq->have_sample = true; 1234 if (ptq->sel_start && ptq->sel_timestamp && 1235 ptq->timestamp < ptq->sel_timestamp) 1236 ptq->have_sample = false; 1237 intel_pt_sample_flags(ptq); 1238 ret = auxtrace_heap__add(&pt->heap, queue_nr, ptq->timestamp); 1239 if (ret) 1240 return ret; 1241 ptq->on_heap = true; 1242 } 1243 1244 return 0; 1245 } 1246 1247 static int intel_pt_setup_queues(struct intel_pt *pt) 1248 { 1249 unsigned int i; 1250 int ret; 1251 1252 for (i = 0; i < pt->queues.nr_queues; i++) { 1253 ret = intel_pt_setup_queue(pt, &pt->queues.queue_array[i], i); 1254 if (ret) 1255 return ret; 1256 } 1257 return 0; 1258 } 1259 1260 static inline bool intel_pt_skip_event(struct intel_pt *pt) 1261 { 1262 return pt->synth_opts.initial_skip && 1263 pt->num_events++ < pt->synth_opts.initial_skip; 1264 } 1265 1266 /* 1267 * Cannot count CBR as skipped because it won't go away until cbr == cbr_seen. 1268 * Also ensure CBR is first non-skipped event by allowing for 4 more samples 1269 * from this decoder state. 1270 */ 1271 static inline bool intel_pt_skip_cbr_event(struct intel_pt *pt) 1272 { 1273 return pt->synth_opts.initial_skip && 1274 pt->num_events + 4 < pt->synth_opts.initial_skip; 1275 } 1276 1277 static void intel_pt_prep_a_sample(struct intel_pt_queue *ptq, 1278 union perf_event *event, 1279 struct perf_sample *sample) 1280 { 1281 event->sample.header.type = PERF_RECORD_SAMPLE; 1282 event->sample.header.size = sizeof(struct perf_event_header); 1283 1284 sample->pid = ptq->pid; 1285 sample->tid = ptq->tid; 1286 sample->cpu = ptq->cpu; 1287 sample->insn_len = ptq->insn_len; 1288 memcpy(sample->insn, ptq->insn, INTEL_PT_INSN_BUF_SZ); 1289 } 1290 1291 static void intel_pt_prep_b_sample(struct intel_pt *pt, 1292 struct intel_pt_queue *ptq, 1293 union perf_event *event, 1294 struct perf_sample *sample) 1295 { 1296 intel_pt_prep_a_sample(ptq, event, sample); 1297 1298 if (!pt->timeless_decoding) 1299 sample->time = tsc_to_perf_time(ptq->timestamp, &pt->tc); 1300 1301 sample->ip = ptq->state->from_ip; 1302 sample->cpumode = intel_pt_cpumode(pt, sample->ip); 1303 sample->addr = ptq->state->to_ip; 1304 sample->period = 1; 1305 sample->flags = ptq->flags; 1306 1307 event->sample.header.misc = sample->cpumode; 1308 } 1309 1310 static int intel_pt_inject_event(union perf_event *event, 1311 struct perf_sample *sample, u64 type) 1312 { 1313 event->header.size = perf_event__sample_event_size(sample, type, 0); 1314 return perf_event__synthesize_sample(event, type, 0, sample); 1315 } 1316 1317 static inline int intel_pt_opt_inject(struct intel_pt *pt, 1318 union perf_event *event, 1319 struct perf_sample *sample, u64 type) 1320 { 1321 if (!pt->synth_opts.inject) 1322 return 0; 1323 1324 return intel_pt_inject_event(event, sample, type); 1325 } 1326 1327 static int intel_pt_deliver_synth_event(struct intel_pt *pt, 1328 union perf_event *event, 1329 struct perf_sample *sample, u64 type) 1330 { 1331 int ret; 1332 1333 ret = intel_pt_opt_inject(pt, event, sample, type); 1334 if (ret) 1335 return ret; 1336 1337 ret = perf_session__deliver_synth_event(pt->session, event, sample); 1338 if (ret) 1339 pr_err("Intel PT: failed to deliver event, error %d\n", ret); 1340 1341 return ret; 1342 } 1343 1344 static int intel_pt_synth_branch_sample(struct intel_pt_queue *ptq) 1345 { 1346 struct intel_pt *pt = ptq->pt; 1347 union perf_event *event = ptq->event_buf; 1348 struct perf_sample sample = { .ip = 0, }; 1349 struct dummy_branch_stack { 1350 u64 nr; 1351 u64 hw_idx; 1352 struct branch_entry entries; 1353 } dummy_bs; 1354 1355 if (pt->branches_filter && !(pt->branches_filter & ptq->flags)) 1356 return 0; 1357 1358 if (intel_pt_skip_event(pt)) 1359 return 0; 1360 1361 intel_pt_prep_b_sample(pt, ptq, event, &sample); 1362 1363 sample.id = ptq->pt->branches_id; 1364 sample.stream_id = ptq->pt->branches_id; 1365 1366 /* 1367 * perf report cannot handle events without a branch stack when using 1368 * SORT_MODE__BRANCH so make a dummy one. 1369 */ 1370 if (pt->synth_opts.last_branch && sort__mode == SORT_MODE__BRANCH) { 1371 dummy_bs = (struct dummy_branch_stack){ 1372 .nr = 1, 1373 .hw_idx = -1ULL, 1374 .entries = { 1375 .from = sample.ip, 1376 .to = sample.addr, 1377 }, 1378 }; 1379 sample.branch_stack = (struct branch_stack *)&dummy_bs; 1380 } 1381 1382 sample.cyc_cnt = ptq->ipc_cyc_cnt - ptq->last_br_cyc_cnt; 1383 if (sample.cyc_cnt) { 1384 sample.insn_cnt = ptq->ipc_insn_cnt - ptq->last_br_insn_cnt; 1385 ptq->last_br_insn_cnt = ptq->ipc_insn_cnt; 1386 ptq->last_br_cyc_cnt = ptq->ipc_cyc_cnt; 1387 } 1388 1389 return intel_pt_deliver_synth_event(pt, event, &sample, 1390 pt->branches_sample_type); 1391 } 1392 1393 static void intel_pt_prep_sample(struct intel_pt *pt, 1394 struct intel_pt_queue *ptq, 1395 union perf_event *event, 1396 struct perf_sample *sample) 1397 { 1398 intel_pt_prep_b_sample(pt, ptq, event, sample); 1399 1400 if (pt->synth_opts.callchain) { 1401 thread_stack__sample(ptq->thread, ptq->cpu, ptq->chain, 1402 pt->synth_opts.callchain_sz + 1, 1403 sample->ip, pt->kernel_start); 1404 sample->callchain = ptq->chain; 1405 } 1406 1407 if (pt->synth_opts.last_branch) { 1408 thread_stack__br_sample(ptq->thread, ptq->cpu, ptq->last_branch, 1409 pt->br_stack_sz); 1410 sample->branch_stack = ptq->last_branch; 1411 } 1412 } 1413 1414 static int intel_pt_synth_instruction_sample(struct intel_pt_queue *ptq) 1415 { 1416 struct intel_pt *pt = ptq->pt; 1417 union perf_event *event = ptq->event_buf; 1418 struct perf_sample sample = { .ip = 0, }; 1419 1420 if (intel_pt_skip_event(pt)) 1421 return 0; 1422 1423 intel_pt_prep_sample(pt, ptq, event, &sample); 1424 1425 sample.id = ptq->pt->instructions_id; 1426 sample.stream_id = ptq->pt->instructions_id; 1427 if (pt->synth_opts.quick) 1428 sample.period = 1; 1429 else 1430 sample.period = ptq->state->tot_insn_cnt - ptq->last_insn_cnt; 1431 1432 sample.cyc_cnt = ptq->ipc_cyc_cnt - ptq->last_in_cyc_cnt; 1433 if (sample.cyc_cnt) { 1434 sample.insn_cnt = ptq->ipc_insn_cnt - ptq->last_in_insn_cnt; 1435 ptq->last_in_insn_cnt = ptq->ipc_insn_cnt; 1436 ptq->last_in_cyc_cnt = ptq->ipc_cyc_cnt; 1437 } 1438 1439 ptq->last_insn_cnt = ptq->state->tot_insn_cnt; 1440 1441 return intel_pt_deliver_synth_event(pt, event, &sample, 1442 pt->instructions_sample_type); 1443 } 1444 1445 static int intel_pt_synth_transaction_sample(struct intel_pt_queue *ptq) 1446 { 1447 struct intel_pt *pt = ptq->pt; 1448 union perf_event *event = ptq->event_buf; 1449 struct perf_sample sample = { .ip = 0, }; 1450 1451 if (intel_pt_skip_event(pt)) 1452 return 0; 1453 1454 intel_pt_prep_sample(pt, ptq, event, &sample); 1455 1456 sample.id = ptq->pt->transactions_id; 1457 sample.stream_id = ptq->pt->transactions_id; 1458 1459 return intel_pt_deliver_synth_event(pt, event, &sample, 1460 pt->transactions_sample_type); 1461 } 1462 1463 static void intel_pt_prep_p_sample(struct intel_pt *pt, 1464 struct intel_pt_queue *ptq, 1465 union perf_event *event, 1466 struct perf_sample *sample) 1467 { 1468 intel_pt_prep_sample(pt, ptq, event, sample); 1469 1470 /* 1471 * Zero IP is used to mean "trace start" but that is not the case for 1472 * power or PTWRITE events with no IP, so clear the flags. 1473 */ 1474 if (!sample->ip) 1475 sample->flags = 0; 1476 } 1477 1478 static int intel_pt_synth_ptwrite_sample(struct intel_pt_queue *ptq) 1479 { 1480 struct intel_pt *pt = ptq->pt; 1481 union perf_event *event = ptq->event_buf; 1482 struct perf_sample sample = { .ip = 0, }; 1483 struct perf_synth_intel_ptwrite raw; 1484 1485 if (intel_pt_skip_event(pt)) 1486 return 0; 1487 1488 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1489 1490 sample.id = ptq->pt->ptwrites_id; 1491 sample.stream_id = ptq->pt->ptwrites_id; 1492 1493 raw.flags = 0; 1494 raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP); 1495 raw.payload = cpu_to_le64(ptq->state->ptw_payload); 1496 1497 sample.raw_size = perf_synth__raw_size(raw); 1498 sample.raw_data = perf_synth__raw_data(&raw); 1499 1500 return intel_pt_deliver_synth_event(pt, event, &sample, 1501 pt->ptwrites_sample_type); 1502 } 1503 1504 static int intel_pt_synth_cbr_sample(struct intel_pt_queue *ptq) 1505 { 1506 struct intel_pt *pt = ptq->pt; 1507 union perf_event *event = ptq->event_buf; 1508 struct perf_sample sample = { .ip = 0, }; 1509 struct perf_synth_intel_cbr raw; 1510 u32 flags; 1511 1512 if (intel_pt_skip_cbr_event(pt)) 1513 return 0; 1514 1515 ptq->cbr_seen = ptq->state->cbr; 1516 1517 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1518 1519 sample.id = ptq->pt->cbr_id; 1520 sample.stream_id = ptq->pt->cbr_id; 1521 1522 flags = (u16)ptq->state->cbr_payload | (pt->max_non_turbo_ratio << 16); 1523 raw.flags = cpu_to_le32(flags); 1524 raw.freq = cpu_to_le32(raw.cbr * pt->cbr2khz); 1525 raw.reserved3 = 0; 1526 1527 sample.raw_size = perf_synth__raw_size(raw); 1528 sample.raw_data = perf_synth__raw_data(&raw); 1529 1530 return intel_pt_deliver_synth_event(pt, event, &sample, 1531 pt->pwr_events_sample_type); 1532 } 1533 1534 static int intel_pt_synth_mwait_sample(struct intel_pt_queue *ptq) 1535 { 1536 struct intel_pt *pt = ptq->pt; 1537 union perf_event *event = ptq->event_buf; 1538 struct perf_sample sample = { .ip = 0, }; 1539 struct perf_synth_intel_mwait raw; 1540 1541 if (intel_pt_skip_event(pt)) 1542 return 0; 1543 1544 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1545 1546 sample.id = ptq->pt->mwait_id; 1547 sample.stream_id = ptq->pt->mwait_id; 1548 1549 raw.reserved = 0; 1550 raw.payload = cpu_to_le64(ptq->state->mwait_payload); 1551 1552 sample.raw_size = perf_synth__raw_size(raw); 1553 sample.raw_data = perf_synth__raw_data(&raw); 1554 1555 return intel_pt_deliver_synth_event(pt, event, &sample, 1556 pt->pwr_events_sample_type); 1557 } 1558 1559 static int intel_pt_synth_pwre_sample(struct intel_pt_queue *ptq) 1560 { 1561 struct intel_pt *pt = ptq->pt; 1562 union perf_event *event = ptq->event_buf; 1563 struct perf_sample sample = { .ip = 0, }; 1564 struct perf_synth_intel_pwre raw; 1565 1566 if (intel_pt_skip_event(pt)) 1567 return 0; 1568 1569 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1570 1571 sample.id = ptq->pt->pwre_id; 1572 sample.stream_id = ptq->pt->pwre_id; 1573 1574 raw.reserved = 0; 1575 raw.payload = cpu_to_le64(ptq->state->pwre_payload); 1576 1577 sample.raw_size = perf_synth__raw_size(raw); 1578 sample.raw_data = perf_synth__raw_data(&raw); 1579 1580 return intel_pt_deliver_synth_event(pt, event, &sample, 1581 pt->pwr_events_sample_type); 1582 } 1583 1584 static int intel_pt_synth_exstop_sample(struct intel_pt_queue *ptq) 1585 { 1586 struct intel_pt *pt = ptq->pt; 1587 union perf_event *event = ptq->event_buf; 1588 struct perf_sample sample = { .ip = 0, }; 1589 struct perf_synth_intel_exstop raw; 1590 1591 if (intel_pt_skip_event(pt)) 1592 return 0; 1593 1594 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1595 1596 sample.id = ptq->pt->exstop_id; 1597 sample.stream_id = ptq->pt->exstop_id; 1598 1599 raw.flags = 0; 1600 raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP); 1601 1602 sample.raw_size = perf_synth__raw_size(raw); 1603 sample.raw_data = perf_synth__raw_data(&raw); 1604 1605 return intel_pt_deliver_synth_event(pt, event, &sample, 1606 pt->pwr_events_sample_type); 1607 } 1608 1609 static int intel_pt_synth_pwrx_sample(struct intel_pt_queue *ptq) 1610 { 1611 struct intel_pt *pt = ptq->pt; 1612 union perf_event *event = ptq->event_buf; 1613 struct perf_sample sample = { .ip = 0, }; 1614 struct perf_synth_intel_pwrx raw; 1615 1616 if (intel_pt_skip_event(pt)) 1617 return 0; 1618 1619 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1620 1621 sample.id = ptq->pt->pwrx_id; 1622 sample.stream_id = ptq->pt->pwrx_id; 1623 1624 raw.reserved = 0; 1625 raw.payload = cpu_to_le64(ptq->state->pwrx_payload); 1626 1627 sample.raw_size = perf_synth__raw_size(raw); 1628 sample.raw_data = perf_synth__raw_data(&raw); 1629 1630 return intel_pt_deliver_synth_event(pt, event, &sample, 1631 pt->pwr_events_sample_type); 1632 } 1633 1634 /* 1635 * PEBS gp_regs array indexes plus 1 so that 0 means not present. Refer 1636 * intel_pt_add_gp_regs(). 1637 */ 1638 static const int pebs_gp_regs[] = { 1639 [PERF_REG_X86_FLAGS] = 1, 1640 [PERF_REG_X86_IP] = 2, 1641 [PERF_REG_X86_AX] = 3, 1642 [PERF_REG_X86_CX] = 4, 1643 [PERF_REG_X86_DX] = 5, 1644 [PERF_REG_X86_BX] = 6, 1645 [PERF_REG_X86_SP] = 7, 1646 [PERF_REG_X86_BP] = 8, 1647 [PERF_REG_X86_SI] = 9, 1648 [PERF_REG_X86_DI] = 10, 1649 [PERF_REG_X86_R8] = 11, 1650 [PERF_REG_X86_R9] = 12, 1651 [PERF_REG_X86_R10] = 13, 1652 [PERF_REG_X86_R11] = 14, 1653 [PERF_REG_X86_R12] = 15, 1654 [PERF_REG_X86_R13] = 16, 1655 [PERF_REG_X86_R14] = 17, 1656 [PERF_REG_X86_R15] = 18, 1657 }; 1658 1659 static u64 *intel_pt_add_gp_regs(struct regs_dump *intr_regs, u64 *pos, 1660 const struct intel_pt_blk_items *items, 1661 u64 regs_mask) 1662 { 1663 const u64 *gp_regs = items->val[INTEL_PT_GP_REGS_POS]; 1664 u32 mask = items->mask[INTEL_PT_GP_REGS_POS]; 1665 u32 bit; 1666 int i; 1667 1668 for (i = 0, bit = 1; i < PERF_REG_X86_64_MAX; i++, bit <<= 1) { 1669 /* Get the PEBS gp_regs array index */ 1670 int n = pebs_gp_regs[i] - 1; 1671 1672 if (n < 0) 1673 continue; 1674 /* 1675 * Add only registers that were requested (i.e. 'regs_mask') and 1676 * that were provided (i.e. 'mask'), and update the resulting 1677 * mask (i.e. 'intr_regs->mask') accordingly. 1678 */ 1679 if (mask & 1 << n && regs_mask & bit) { 1680 intr_regs->mask |= bit; 1681 *pos++ = gp_regs[n]; 1682 } 1683 } 1684 1685 return pos; 1686 } 1687 1688 #ifndef PERF_REG_X86_XMM0 1689 #define PERF_REG_X86_XMM0 32 1690 #endif 1691 1692 static void intel_pt_add_xmm(struct regs_dump *intr_regs, u64 *pos, 1693 const struct intel_pt_blk_items *items, 1694 u64 regs_mask) 1695 { 1696 u32 mask = items->has_xmm & (regs_mask >> PERF_REG_X86_XMM0); 1697 const u64 *xmm = items->xmm; 1698 1699 /* 1700 * If there are any XMM registers, then there should be all of them. 1701 * Nevertheless, follow the logic to add only registers that were 1702 * requested (i.e. 'regs_mask') and that were provided (i.e. 'mask'), 1703 * and update the resulting mask (i.e. 'intr_regs->mask') accordingly. 1704 */ 1705 intr_regs->mask |= (u64)mask << PERF_REG_X86_XMM0; 1706 1707 for (; mask; mask >>= 1, xmm++) { 1708 if (mask & 1) 1709 *pos++ = *xmm; 1710 } 1711 } 1712 1713 #define LBR_INFO_MISPRED (1ULL << 63) 1714 #define LBR_INFO_IN_TX (1ULL << 62) 1715 #define LBR_INFO_ABORT (1ULL << 61) 1716 #define LBR_INFO_CYCLES 0xffff 1717 1718 /* Refer kernel's intel_pmu_store_pebs_lbrs() */ 1719 static u64 intel_pt_lbr_flags(u64 info) 1720 { 1721 union { 1722 struct branch_flags flags; 1723 u64 result; 1724 } u; 1725 1726 u.result = 0; 1727 u.flags.mispred = !!(info & LBR_INFO_MISPRED); 1728 u.flags.predicted = !(info & LBR_INFO_MISPRED); 1729 u.flags.in_tx = !!(info & LBR_INFO_IN_TX); 1730 u.flags.abort = !!(info & LBR_INFO_ABORT); 1731 u.flags.cycles = info & LBR_INFO_CYCLES; 1732 1733 return u.result; 1734 } 1735 1736 static void intel_pt_add_lbrs(struct branch_stack *br_stack, 1737 const struct intel_pt_blk_items *items) 1738 { 1739 u64 *to; 1740 int i; 1741 1742 br_stack->nr = 0; 1743 1744 to = &br_stack->entries[0].from; 1745 1746 for (i = INTEL_PT_LBR_0_POS; i <= INTEL_PT_LBR_2_POS; i++) { 1747 u32 mask = items->mask[i]; 1748 const u64 *from = items->val[i]; 1749 1750 for (; mask; mask >>= 3, from += 3) { 1751 if ((mask & 7) == 7) { 1752 *to++ = from[0]; 1753 *to++ = from[1]; 1754 *to++ = intel_pt_lbr_flags(from[2]); 1755 br_stack->nr += 1; 1756 } 1757 } 1758 } 1759 } 1760 1761 static int intel_pt_synth_pebs_sample(struct intel_pt_queue *ptq) 1762 { 1763 const struct intel_pt_blk_items *items = &ptq->state->items; 1764 struct perf_sample sample = { .ip = 0, }; 1765 union perf_event *event = ptq->event_buf; 1766 struct intel_pt *pt = ptq->pt; 1767 struct evsel *evsel = pt->pebs_evsel; 1768 u64 sample_type = evsel->core.attr.sample_type; 1769 u64 id = evsel->core.id[0]; 1770 u8 cpumode; 1771 u64 regs[8 * sizeof(sample.intr_regs.mask)]; 1772 1773 if (intel_pt_skip_event(pt)) 1774 return 0; 1775 1776 intel_pt_prep_a_sample(ptq, event, &sample); 1777 1778 sample.id = id; 1779 sample.stream_id = id; 1780 1781 if (!evsel->core.attr.freq) 1782 sample.period = evsel->core.attr.sample_period; 1783 1784 /* No support for non-zero CS base */ 1785 if (items->has_ip) 1786 sample.ip = items->ip; 1787 else if (items->has_rip) 1788 sample.ip = items->rip; 1789 else 1790 sample.ip = ptq->state->from_ip; 1791 1792 /* No support for guest mode at this time */ 1793 cpumode = sample.ip < ptq->pt->kernel_start ? 1794 PERF_RECORD_MISC_USER : 1795 PERF_RECORD_MISC_KERNEL; 1796 1797 event->sample.header.misc = cpumode | PERF_RECORD_MISC_EXACT_IP; 1798 1799 sample.cpumode = cpumode; 1800 1801 if (sample_type & PERF_SAMPLE_TIME) { 1802 u64 timestamp = 0; 1803 1804 if (items->has_timestamp) 1805 timestamp = items->timestamp; 1806 else if (!pt->timeless_decoding) 1807 timestamp = ptq->timestamp; 1808 if (timestamp) 1809 sample.time = tsc_to_perf_time(timestamp, &pt->tc); 1810 } 1811 1812 if (sample_type & PERF_SAMPLE_CALLCHAIN && 1813 pt->synth_opts.callchain) { 1814 thread_stack__sample(ptq->thread, ptq->cpu, ptq->chain, 1815 pt->synth_opts.callchain_sz, sample.ip, 1816 pt->kernel_start); 1817 sample.callchain = ptq->chain; 1818 } 1819 1820 if (sample_type & PERF_SAMPLE_REGS_INTR && 1821 (items->mask[INTEL_PT_GP_REGS_POS] || 1822 items->mask[INTEL_PT_XMM_POS])) { 1823 u64 regs_mask = evsel->core.attr.sample_regs_intr; 1824 u64 *pos; 1825 1826 sample.intr_regs.abi = items->is_32_bit ? 1827 PERF_SAMPLE_REGS_ABI_32 : 1828 PERF_SAMPLE_REGS_ABI_64; 1829 sample.intr_regs.regs = regs; 1830 1831 pos = intel_pt_add_gp_regs(&sample.intr_regs, regs, items, regs_mask); 1832 1833 intel_pt_add_xmm(&sample.intr_regs, pos, items, regs_mask); 1834 } 1835 1836 if (sample_type & PERF_SAMPLE_BRANCH_STACK) { 1837 if (items->mask[INTEL_PT_LBR_0_POS] || 1838 items->mask[INTEL_PT_LBR_1_POS] || 1839 items->mask[INTEL_PT_LBR_2_POS]) { 1840 intel_pt_add_lbrs(ptq->last_branch, items); 1841 } else if (pt->synth_opts.last_branch) { 1842 thread_stack__br_sample(ptq->thread, ptq->cpu, 1843 ptq->last_branch, 1844 pt->br_stack_sz); 1845 } else { 1846 ptq->last_branch->nr = 0; 1847 } 1848 sample.branch_stack = ptq->last_branch; 1849 } 1850 1851 if (sample_type & PERF_SAMPLE_ADDR && items->has_mem_access_address) 1852 sample.addr = items->mem_access_address; 1853 1854 if (sample_type & PERF_SAMPLE_WEIGHT) { 1855 /* 1856 * Refer kernel's setup_pebs_adaptive_sample_data() and 1857 * intel_hsw_weight(). 1858 */ 1859 if (items->has_mem_access_latency) 1860 sample.weight = items->mem_access_latency; 1861 if (!sample.weight && items->has_tsx_aux_info) { 1862 /* Cycles last block */ 1863 sample.weight = (u32)items->tsx_aux_info; 1864 } 1865 } 1866 1867 if (sample_type & PERF_SAMPLE_TRANSACTION && items->has_tsx_aux_info) { 1868 u64 ax = items->has_rax ? items->rax : 0; 1869 /* Refer kernel's intel_hsw_transaction() */ 1870 u64 txn = (u8)(items->tsx_aux_info >> 32); 1871 1872 /* For RTM XABORTs also log the abort code from AX */ 1873 if (txn & PERF_TXN_TRANSACTION && ax & 1) 1874 txn |= ((ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT; 1875 sample.transaction = txn; 1876 } 1877 1878 return intel_pt_deliver_synth_event(pt, event, &sample, sample_type); 1879 } 1880 1881 static int intel_pt_synth_error(struct intel_pt *pt, int code, int cpu, 1882 pid_t pid, pid_t tid, u64 ip, u64 timestamp) 1883 { 1884 union perf_event event; 1885 char msg[MAX_AUXTRACE_ERROR_MSG]; 1886 int err; 1887 1888 if (pt->synth_opts.error_minus_flags) { 1889 if (code == INTEL_PT_ERR_OVR && 1890 pt->synth_opts.error_minus_flags & AUXTRACE_ERR_FLG_OVERFLOW) 1891 return 0; 1892 if (code == INTEL_PT_ERR_LOST && 1893 pt->synth_opts.error_minus_flags & AUXTRACE_ERR_FLG_DATA_LOST) 1894 return 0; 1895 } 1896 1897 intel_pt__strerror(code, msg, MAX_AUXTRACE_ERROR_MSG); 1898 1899 auxtrace_synth_error(&event.auxtrace_error, PERF_AUXTRACE_ERROR_ITRACE, 1900 code, cpu, pid, tid, ip, msg, timestamp); 1901 1902 err = perf_session__deliver_synth_event(pt->session, &event, NULL); 1903 if (err) 1904 pr_err("Intel Processor Trace: failed to deliver error event, error %d\n", 1905 err); 1906 1907 return err; 1908 } 1909 1910 static int intel_ptq_synth_error(struct intel_pt_queue *ptq, 1911 const struct intel_pt_state *state) 1912 { 1913 struct intel_pt *pt = ptq->pt; 1914 u64 tm = ptq->timestamp; 1915 1916 tm = pt->timeless_decoding ? 0 : tsc_to_perf_time(tm, &pt->tc); 1917 1918 return intel_pt_synth_error(pt, state->err, ptq->cpu, ptq->pid, 1919 ptq->tid, state->from_ip, tm); 1920 } 1921 1922 static int intel_pt_next_tid(struct intel_pt *pt, struct intel_pt_queue *ptq) 1923 { 1924 struct auxtrace_queue *queue; 1925 pid_t tid = ptq->next_tid; 1926 int err; 1927 1928 if (tid == -1) 1929 return 0; 1930 1931 intel_pt_log("switch: cpu %d tid %d\n", ptq->cpu, tid); 1932 1933 err = machine__set_current_tid(pt->machine, ptq->cpu, -1, tid); 1934 1935 queue = &pt->queues.queue_array[ptq->queue_nr]; 1936 intel_pt_set_pid_tid_cpu(pt, queue); 1937 1938 ptq->next_tid = -1; 1939 1940 return err; 1941 } 1942 1943 static inline bool intel_pt_is_switch_ip(struct intel_pt_queue *ptq, u64 ip) 1944 { 1945 struct intel_pt *pt = ptq->pt; 1946 1947 return ip == pt->switch_ip && 1948 (ptq->flags & PERF_IP_FLAG_BRANCH) && 1949 !(ptq->flags & (PERF_IP_FLAG_CONDITIONAL | PERF_IP_FLAG_ASYNC | 1950 PERF_IP_FLAG_INTERRUPT | PERF_IP_FLAG_TX_ABORT)); 1951 } 1952 1953 #define INTEL_PT_PWR_EVT (INTEL_PT_MWAIT_OP | INTEL_PT_PWR_ENTRY | \ 1954 INTEL_PT_EX_STOP | INTEL_PT_PWR_EXIT) 1955 1956 static int intel_pt_sample(struct intel_pt_queue *ptq) 1957 { 1958 const struct intel_pt_state *state = ptq->state; 1959 struct intel_pt *pt = ptq->pt; 1960 int err; 1961 1962 if (!ptq->have_sample) 1963 return 0; 1964 1965 ptq->have_sample = false; 1966 1967 if (ptq->state->tot_cyc_cnt > ptq->ipc_cyc_cnt) { 1968 /* 1969 * Cycle count and instruction count only go together to create 1970 * a valid IPC ratio when the cycle count changes. 1971 */ 1972 ptq->ipc_insn_cnt = ptq->state->tot_insn_cnt; 1973 ptq->ipc_cyc_cnt = ptq->state->tot_cyc_cnt; 1974 } 1975 1976 /* 1977 * Do PEBS first to allow for the possibility that the PEBS timestamp 1978 * precedes the current timestamp. 1979 */ 1980 if (pt->sample_pebs && state->type & INTEL_PT_BLK_ITEMS) { 1981 err = intel_pt_synth_pebs_sample(ptq); 1982 if (err) 1983 return err; 1984 } 1985 1986 if (pt->sample_pwr_events) { 1987 if (ptq->state->cbr != ptq->cbr_seen) { 1988 err = intel_pt_synth_cbr_sample(ptq); 1989 if (err) 1990 return err; 1991 } 1992 if (state->type & INTEL_PT_PWR_EVT) { 1993 if (state->type & INTEL_PT_MWAIT_OP) { 1994 err = intel_pt_synth_mwait_sample(ptq); 1995 if (err) 1996 return err; 1997 } 1998 if (state->type & INTEL_PT_PWR_ENTRY) { 1999 err = intel_pt_synth_pwre_sample(ptq); 2000 if (err) 2001 return err; 2002 } 2003 if (state->type & INTEL_PT_EX_STOP) { 2004 err = intel_pt_synth_exstop_sample(ptq); 2005 if (err) 2006 return err; 2007 } 2008 if (state->type & INTEL_PT_PWR_EXIT) { 2009 err = intel_pt_synth_pwrx_sample(ptq); 2010 if (err) 2011 return err; 2012 } 2013 } 2014 } 2015 2016 if (pt->sample_instructions && (state->type & INTEL_PT_INSTRUCTION)) { 2017 err = intel_pt_synth_instruction_sample(ptq); 2018 if (err) 2019 return err; 2020 } 2021 2022 if (pt->sample_transactions && (state->type & INTEL_PT_TRANSACTION)) { 2023 err = intel_pt_synth_transaction_sample(ptq); 2024 if (err) 2025 return err; 2026 } 2027 2028 if (pt->sample_ptwrites && (state->type & INTEL_PT_PTW)) { 2029 err = intel_pt_synth_ptwrite_sample(ptq); 2030 if (err) 2031 return err; 2032 } 2033 2034 if (!(state->type & INTEL_PT_BRANCH)) 2035 return 0; 2036 2037 if (pt->use_thread_stack) { 2038 thread_stack__event(ptq->thread, ptq->cpu, ptq->flags, 2039 state->from_ip, state->to_ip, ptq->insn_len, 2040 state->trace_nr, pt->callstack, 2041 pt->br_stack_sz_plus, 2042 pt->mispred_all); 2043 } else { 2044 thread_stack__set_trace_nr(ptq->thread, ptq->cpu, state->trace_nr); 2045 } 2046 2047 if (pt->sample_branches) { 2048 err = intel_pt_synth_branch_sample(ptq); 2049 if (err) 2050 return err; 2051 } 2052 2053 if (!ptq->sync_switch) 2054 return 0; 2055 2056 if (intel_pt_is_switch_ip(ptq, state->to_ip)) { 2057 switch (ptq->switch_state) { 2058 case INTEL_PT_SS_NOT_TRACING: 2059 case INTEL_PT_SS_UNKNOWN: 2060 case INTEL_PT_SS_EXPECTING_SWITCH_IP: 2061 err = intel_pt_next_tid(pt, ptq); 2062 if (err) 2063 return err; 2064 ptq->switch_state = INTEL_PT_SS_TRACING; 2065 break; 2066 default: 2067 ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_EVENT; 2068 return 1; 2069 } 2070 } else if (!state->to_ip) { 2071 ptq->switch_state = INTEL_PT_SS_NOT_TRACING; 2072 } else if (ptq->switch_state == INTEL_PT_SS_NOT_TRACING) { 2073 ptq->switch_state = INTEL_PT_SS_UNKNOWN; 2074 } else if (ptq->switch_state == INTEL_PT_SS_UNKNOWN && 2075 state->to_ip == pt->ptss_ip && 2076 (ptq->flags & PERF_IP_FLAG_CALL)) { 2077 ptq->switch_state = INTEL_PT_SS_TRACING; 2078 } 2079 2080 return 0; 2081 } 2082 2083 static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip) 2084 { 2085 struct machine *machine = pt->machine; 2086 struct map *map; 2087 struct symbol *sym, *start; 2088 u64 ip, switch_ip = 0; 2089 const char *ptss; 2090 2091 if (ptss_ip) 2092 *ptss_ip = 0; 2093 2094 map = machine__kernel_map(machine); 2095 if (!map) 2096 return 0; 2097 2098 if (map__load(map)) 2099 return 0; 2100 2101 start = dso__first_symbol(map->dso); 2102 2103 for (sym = start; sym; sym = dso__next_symbol(sym)) { 2104 if (sym->binding == STB_GLOBAL && 2105 !strcmp(sym->name, "__switch_to")) { 2106 ip = map->unmap_ip(map, sym->start); 2107 if (ip >= map->start && ip < map->end) { 2108 switch_ip = ip; 2109 break; 2110 } 2111 } 2112 } 2113 2114 if (!switch_ip || !ptss_ip) 2115 return 0; 2116 2117 if (pt->have_sched_switch == 1) 2118 ptss = "perf_trace_sched_switch"; 2119 else 2120 ptss = "__perf_event_task_sched_out"; 2121 2122 for (sym = start; sym; sym = dso__next_symbol(sym)) { 2123 if (!strcmp(sym->name, ptss)) { 2124 ip = map->unmap_ip(map, sym->start); 2125 if (ip >= map->start && ip < map->end) { 2126 *ptss_ip = ip; 2127 break; 2128 } 2129 } 2130 } 2131 2132 return switch_ip; 2133 } 2134 2135 static void intel_pt_enable_sync_switch(struct intel_pt *pt) 2136 { 2137 unsigned int i; 2138 2139 pt->sync_switch = true; 2140 2141 for (i = 0; i < pt->queues.nr_queues; i++) { 2142 struct auxtrace_queue *queue = &pt->queues.queue_array[i]; 2143 struct intel_pt_queue *ptq = queue->priv; 2144 2145 if (ptq) 2146 ptq->sync_switch = true; 2147 } 2148 } 2149 2150 /* 2151 * To filter against time ranges, it is only necessary to look at the next start 2152 * or end time. 2153 */ 2154 static bool intel_pt_next_time(struct intel_pt_queue *ptq) 2155 { 2156 struct intel_pt *pt = ptq->pt; 2157 2158 if (ptq->sel_start) { 2159 /* Next time is an end time */ 2160 ptq->sel_start = false; 2161 ptq->sel_timestamp = pt->time_ranges[ptq->sel_idx].end; 2162 return true; 2163 } else if (ptq->sel_idx + 1 < pt->range_cnt) { 2164 /* Next time is a start time */ 2165 ptq->sel_start = true; 2166 ptq->sel_idx += 1; 2167 ptq->sel_timestamp = pt->time_ranges[ptq->sel_idx].start; 2168 return true; 2169 } 2170 2171 /* No next time */ 2172 return false; 2173 } 2174 2175 static int intel_pt_time_filter(struct intel_pt_queue *ptq, u64 *ff_timestamp) 2176 { 2177 int err; 2178 2179 while (1) { 2180 if (ptq->sel_start) { 2181 if (ptq->timestamp >= ptq->sel_timestamp) { 2182 /* After start time, so consider next time */ 2183 intel_pt_next_time(ptq); 2184 if (!ptq->sel_timestamp) { 2185 /* No end time */ 2186 return 0; 2187 } 2188 /* Check against end time */ 2189 continue; 2190 } 2191 /* Before start time, so fast forward */ 2192 ptq->have_sample = false; 2193 if (ptq->sel_timestamp > *ff_timestamp) { 2194 if (ptq->sync_switch) { 2195 intel_pt_next_tid(ptq->pt, ptq); 2196 ptq->switch_state = INTEL_PT_SS_UNKNOWN; 2197 } 2198 *ff_timestamp = ptq->sel_timestamp; 2199 err = intel_pt_fast_forward(ptq->decoder, 2200 ptq->sel_timestamp); 2201 if (err) 2202 return err; 2203 } 2204 return 0; 2205 } else if (ptq->timestamp > ptq->sel_timestamp) { 2206 /* After end time, so consider next time */ 2207 if (!intel_pt_next_time(ptq)) { 2208 /* No next time range, so stop decoding */ 2209 ptq->have_sample = false; 2210 ptq->switch_state = INTEL_PT_SS_NOT_TRACING; 2211 return 1; 2212 } 2213 /* Check against next start time */ 2214 continue; 2215 } else { 2216 /* Before end time */ 2217 return 0; 2218 } 2219 } 2220 } 2221 2222 static int intel_pt_run_decoder(struct intel_pt_queue *ptq, u64 *timestamp) 2223 { 2224 const struct intel_pt_state *state = ptq->state; 2225 struct intel_pt *pt = ptq->pt; 2226 u64 ff_timestamp = 0; 2227 int err; 2228 2229 if (!pt->kernel_start) { 2230 pt->kernel_start = machine__kernel_start(pt->machine); 2231 if (pt->per_cpu_mmaps && 2232 (pt->have_sched_switch == 1 || pt->have_sched_switch == 3) && 2233 !pt->timeless_decoding && intel_pt_tracing_kernel(pt) && 2234 !pt->sampling_mode) { 2235 pt->switch_ip = intel_pt_switch_ip(pt, &pt->ptss_ip); 2236 if (pt->switch_ip) { 2237 intel_pt_log("switch_ip: %"PRIx64" ptss_ip: %"PRIx64"\n", 2238 pt->switch_ip, pt->ptss_ip); 2239 intel_pt_enable_sync_switch(pt); 2240 } 2241 } 2242 } 2243 2244 intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n", 2245 ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid); 2246 while (1) { 2247 err = intel_pt_sample(ptq); 2248 if (err) 2249 return err; 2250 2251 state = intel_pt_decode(ptq->decoder); 2252 if (state->err) { 2253 if (state->err == INTEL_PT_ERR_NODATA) 2254 return 1; 2255 if (ptq->sync_switch && 2256 state->from_ip >= pt->kernel_start) { 2257 ptq->sync_switch = false; 2258 intel_pt_next_tid(pt, ptq); 2259 } 2260 if (pt->synth_opts.errors) { 2261 err = intel_ptq_synth_error(ptq, state); 2262 if (err) 2263 return err; 2264 } 2265 continue; 2266 } 2267 2268 ptq->state = state; 2269 ptq->have_sample = true; 2270 intel_pt_sample_flags(ptq); 2271 2272 /* Use estimated TSC upon return to user space */ 2273 if (pt->est_tsc && 2274 (state->from_ip >= pt->kernel_start || !state->from_ip) && 2275 state->to_ip && state->to_ip < pt->kernel_start) { 2276 intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n", 2277 state->timestamp, state->est_timestamp); 2278 ptq->timestamp = state->est_timestamp; 2279 /* Use estimated TSC in unknown switch state */ 2280 } else if (ptq->sync_switch && 2281 ptq->switch_state == INTEL_PT_SS_UNKNOWN && 2282 intel_pt_is_switch_ip(ptq, state->to_ip) && 2283 ptq->next_tid == -1) { 2284 intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n", 2285 state->timestamp, state->est_timestamp); 2286 ptq->timestamp = state->est_timestamp; 2287 } else if (state->timestamp > ptq->timestamp) { 2288 ptq->timestamp = state->timestamp; 2289 } 2290 2291 if (ptq->sel_timestamp) { 2292 err = intel_pt_time_filter(ptq, &ff_timestamp); 2293 if (err) 2294 return err; 2295 } 2296 2297 if (!pt->timeless_decoding && ptq->timestamp >= *timestamp) { 2298 *timestamp = ptq->timestamp; 2299 return 0; 2300 } 2301 } 2302 return 0; 2303 } 2304 2305 static inline int intel_pt_update_queues(struct intel_pt *pt) 2306 { 2307 if (pt->queues.new_data) { 2308 pt->queues.new_data = false; 2309 return intel_pt_setup_queues(pt); 2310 } 2311 return 0; 2312 } 2313 2314 static int intel_pt_process_queues(struct intel_pt *pt, u64 timestamp) 2315 { 2316 unsigned int queue_nr; 2317 u64 ts; 2318 int ret; 2319 2320 while (1) { 2321 struct auxtrace_queue *queue; 2322 struct intel_pt_queue *ptq; 2323 2324 if (!pt->heap.heap_cnt) 2325 return 0; 2326 2327 if (pt->heap.heap_array[0].ordinal >= timestamp) 2328 return 0; 2329 2330 queue_nr = pt->heap.heap_array[0].queue_nr; 2331 queue = &pt->queues.queue_array[queue_nr]; 2332 ptq = queue->priv; 2333 2334 intel_pt_log("queue %u processing 0x%" PRIx64 " to 0x%" PRIx64 "\n", 2335 queue_nr, pt->heap.heap_array[0].ordinal, 2336 timestamp); 2337 2338 auxtrace_heap__pop(&pt->heap); 2339 2340 if (pt->heap.heap_cnt) { 2341 ts = pt->heap.heap_array[0].ordinal + 1; 2342 if (ts > timestamp) 2343 ts = timestamp; 2344 } else { 2345 ts = timestamp; 2346 } 2347 2348 intel_pt_set_pid_tid_cpu(pt, queue); 2349 2350 ret = intel_pt_run_decoder(ptq, &ts); 2351 2352 if (ret < 0) { 2353 auxtrace_heap__add(&pt->heap, queue_nr, ts); 2354 return ret; 2355 } 2356 2357 if (!ret) { 2358 ret = auxtrace_heap__add(&pt->heap, queue_nr, ts); 2359 if (ret < 0) 2360 return ret; 2361 } else { 2362 ptq->on_heap = false; 2363 } 2364 } 2365 2366 return 0; 2367 } 2368 2369 static int intel_pt_process_timeless_queues(struct intel_pt *pt, pid_t tid, 2370 u64 time_) 2371 { 2372 struct auxtrace_queues *queues = &pt->queues; 2373 unsigned int i; 2374 u64 ts = 0; 2375 2376 for (i = 0; i < queues->nr_queues; i++) { 2377 struct auxtrace_queue *queue = &pt->queues.queue_array[i]; 2378 struct intel_pt_queue *ptq = queue->priv; 2379 2380 if (ptq && (tid == -1 || ptq->tid == tid)) { 2381 ptq->time = time_; 2382 intel_pt_set_pid_tid_cpu(pt, queue); 2383 intel_pt_run_decoder(ptq, &ts); 2384 } 2385 } 2386 return 0; 2387 } 2388 2389 static void intel_pt_sample_set_pid_tid_cpu(struct intel_pt_queue *ptq, 2390 struct auxtrace_queue *queue, 2391 struct perf_sample *sample) 2392 { 2393 struct machine *m = ptq->pt->machine; 2394 2395 ptq->pid = sample->pid; 2396 ptq->tid = sample->tid; 2397 ptq->cpu = queue->cpu; 2398 2399 intel_pt_log("queue %u cpu %d pid %d tid %d\n", 2400 ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid); 2401 2402 thread__zput(ptq->thread); 2403 2404 if (ptq->tid == -1) 2405 return; 2406 2407 if (ptq->pid == -1) { 2408 ptq->thread = machine__find_thread(m, -1, ptq->tid); 2409 if (ptq->thread) 2410 ptq->pid = ptq->thread->pid_; 2411 return; 2412 } 2413 2414 ptq->thread = machine__findnew_thread(m, ptq->pid, ptq->tid); 2415 } 2416 2417 static int intel_pt_process_timeless_sample(struct intel_pt *pt, 2418 struct perf_sample *sample) 2419 { 2420 struct auxtrace_queue *queue; 2421 struct intel_pt_queue *ptq; 2422 u64 ts = 0; 2423 2424 queue = auxtrace_queues__sample_queue(&pt->queues, sample, pt->session); 2425 if (!queue) 2426 return -EINVAL; 2427 2428 ptq = queue->priv; 2429 if (!ptq) 2430 return 0; 2431 2432 ptq->stop = false; 2433 ptq->time = sample->time; 2434 intel_pt_sample_set_pid_tid_cpu(ptq, queue, sample); 2435 intel_pt_run_decoder(ptq, &ts); 2436 return 0; 2437 } 2438 2439 static int intel_pt_lost(struct intel_pt *pt, struct perf_sample *sample) 2440 { 2441 return intel_pt_synth_error(pt, INTEL_PT_ERR_LOST, sample->cpu, 2442 sample->pid, sample->tid, 0, sample->time); 2443 } 2444 2445 static struct intel_pt_queue *intel_pt_cpu_to_ptq(struct intel_pt *pt, int cpu) 2446 { 2447 unsigned i, j; 2448 2449 if (cpu < 0 || !pt->queues.nr_queues) 2450 return NULL; 2451 2452 if ((unsigned)cpu >= pt->queues.nr_queues) 2453 i = pt->queues.nr_queues - 1; 2454 else 2455 i = cpu; 2456 2457 if (pt->queues.queue_array[i].cpu == cpu) 2458 return pt->queues.queue_array[i].priv; 2459 2460 for (j = 0; i > 0; j++) { 2461 if (pt->queues.queue_array[--i].cpu == cpu) 2462 return pt->queues.queue_array[i].priv; 2463 } 2464 2465 for (; j < pt->queues.nr_queues; j++) { 2466 if (pt->queues.queue_array[j].cpu == cpu) 2467 return pt->queues.queue_array[j].priv; 2468 } 2469 2470 return NULL; 2471 } 2472 2473 static int intel_pt_sync_switch(struct intel_pt *pt, int cpu, pid_t tid, 2474 u64 timestamp) 2475 { 2476 struct intel_pt_queue *ptq; 2477 int err; 2478 2479 if (!pt->sync_switch) 2480 return 1; 2481 2482 ptq = intel_pt_cpu_to_ptq(pt, cpu); 2483 if (!ptq || !ptq->sync_switch) 2484 return 1; 2485 2486 switch (ptq->switch_state) { 2487 case INTEL_PT_SS_NOT_TRACING: 2488 break; 2489 case INTEL_PT_SS_UNKNOWN: 2490 case INTEL_PT_SS_TRACING: 2491 ptq->next_tid = tid; 2492 ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_IP; 2493 return 0; 2494 case INTEL_PT_SS_EXPECTING_SWITCH_EVENT: 2495 if (!ptq->on_heap) { 2496 ptq->timestamp = perf_time_to_tsc(timestamp, 2497 &pt->tc); 2498 err = auxtrace_heap__add(&pt->heap, ptq->queue_nr, 2499 ptq->timestamp); 2500 if (err) 2501 return err; 2502 ptq->on_heap = true; 2503 } 2504 ptq->switch_state = INTEL_PT_SS_TRACING; 2505 break; 2506 case INTEL_PT_SS_EXPECTING_SWITCH_IP: 2507 intel_pt_log("ERROR: cpu %d expecting switch ip\n", cpu); 2508 break; 2509 default: 2510 break; 2511 } 2512 2513 ptq->next_tid = -1; 2514 2515 return 1; 2516 } 2517 2518 static int intel_pt_process_switch(struct intel_pt *pt, 2519 struct perf_sample *sample) 2520 { 2521 struct evsel *evsel; 2522 pid_t tid; 2523 int cpu, ret; 2524 2525 evsel = perf_evlist__id2evsel(pt->session->evlist, sample->id); 2526 if (evsel != pt->switch_evsel) 2527 return 0; 2528 2529 tid = evsel__intval(evsel, sample, "next_pid"); 2530 cpu = sample->cpu; 2531 2532 intel_pt_log("sched_switch: cpu %d tid %d time %"PRIu64" tsc %#"PRIx64"\n", 2533 cpu, tid, sample->time, perf_time_to_tsc(sample->time, 2534 &pt->tc)); 2535 2536 ret = intel_pt_sync_switch(pt, cpu, tid, sample->time); 2537 if (ret <= 0) 2538 return ret; 2539 2540 return machine__set_current_tid(pt->machine, cpu, -1, tid); 2541 } 2542 2543 static int intel_pt_context_switch_in(struct intel_pt *pt, 2544 struct perf_sample *sample) 2545 { 2546 pid_t pid = sample->pid; 2547 pid_t tid = sample->tid; 2548 int cpu = sample->cpu; 2549 2550 if (pt->sync_switch) { 2551 struct intel_pt_queue *ptq; 2552 2553 ptq = intel_pt_cpu_to_ptq(pt, cpu); 2554 if (ptq && ptq->sync_switch) { 2555 ptq->next_tid = -1; 2556 switch (ptq->switch_state) { 2557 case INTEL_PT_SS_NOT_TRACING: 2558 case INTEL_PT_SS_UNKNOWN: 2559 case INTEL_PT_SS_TRACING: 2560 break; 2561 case INTEL_PT_SS_EXPECTING_SWITCH_EVENT: 2562 case INTEL_PT_SS_EXPECTING_SWITCH_IP: 2563 ptq->switch_state = INTEL_PT_SS_TRACING; 2564 break; 2565 default: 2566 break; 2567 } 2568 } 2569 } 2570 2571 /* 2572 * If the current tid has not been updated yet, ensure it is now that 2573 * a "switch in" event has occurred. 2574 */ 2575 if (machine__get_current_tid(pt->machine, cpu) == tid) 2576 return 0; 2577 2578 return machine__set_current_tid(pt->machine, cpu, pid, tid); 2579 } 2580 2581 static int intel_pt_context_switch(struct intel_pt *pt, union perf_event *event, 2582 struct perf_sample *sample) 2583 { 2584 bool out = event->header.misc & PERF_RECORD_MISC_SWITCH_OUT; 2585 pid_t pid, tid; 2586 int cpu, ret; 2587 2588 cpu = sample->cpu; 2589 2590 if (pt->have_sched_switch == 3) { 2591 if (!out) 2592 return intel_pt_context_switch_in(pt, sample); 2593 if (event->header.type != PERF_RECORD_SWITCH_CPU_WIDE) { 2594 pr_err("Expecting CPU-wide context switch event\n"); 2595 return -EINVAL; 2596 } 2597 pid = event->context_switch.next_prev_pid; 2598 tid = event->context_switch.next_prev_tid; 2599 } else { 2600 if (out) 2601 return 0; 2602 pid = sample->pid; 2603 tid = sample->tid; 2604 } 2605 2606 if (tid == -1) { 2607 pr_err("context_switch event has no tid\n"); 2608 return -EINVAL; 2609 } 2610 2611 ret = intel_pt_sync_switch(pt, cpu, tid, sample->time); 2612 if (ret <= 0) 2613 return ret; 2614 2615 return machine__set_current_tid(pt->machine, cpu, pid, tid); 2616 } 2617 2618 static int intel_pt_process_itrace_start(struct intel_pt *pt, 2619 union perf_event *event, 2620 struct perf_sample *sample) 2621 { 2622 if (!pt->per_cpu_mmaps) 2623 return 0; 2624 2625 intel_pt_log("itrace_start: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n", 2626 sample->cpu, event->itrace_start.pid, 2627 event->itrace_start.tid, sample->time, 2628 perf_time_to_tsc(sample->time, &pt->tc)); 2629 2630 return machine__set_current_tid(pt->machine, sample->cpu, 2631 event->itrace_start.pid, 2632 event->itrace_start.tid); 2633 } 2634 2635 static int intel_pt_find_map(struct thread *thread, u8 cpumode, u64 addr, 2636 struct addr_location *al) 2637 { 2638 if (!al->map || addr < al->map->start || addr >= al->map->end) { 2639 if (!thread__find_map(thread, cpumode, addr, al)) 2640 return -1; 2641 } 2642 2643 return 0; 2644 } 2645 2646 /* Invalidate all instruction cache entries that overlap the text poke */ 2647 static int intel_pt_text_poke(struct intel_pt *pt, union perf_event *event) 2648 { 2649 u8 cpumode = event->header.misc & PERF_RECORD_MISC_CPUMODE_MASK; 2650 u64 addr = event->text_poke.addr + event->text_poke.new_len - 1; 2651 /* Assume text poke begins in a basic block no more than 4096 bytes */ 2652 int cnt = 4096 + event->text_poke.new_len; 2653 struct thread *thread = pt->unknown_thread; 2654 struct addr_location al = { .map = NULL }; 2655 struct machine *machine = pt->machine; 2656 struct intel_pt_cache_entry *e; 2657 u64 offset; 2658 2659 if (!event->text_poke.new_len) 2660 return 0; 2661 2662 for (; cnt; cnt--, addr--) { 2663 if (intel_pt_find_map(thread, cpumode, addr, &al)) { 2664 if (addr < event->text_poke.addr) 2665 return 0; 2666 continue; 2667 } 2668 2669 if (!al.map->dso || !al.map->dso->auxtrace_cache) 2670 continue; 2671 2672 offset = al.map->map_ip(al.map, addr); 2673 2674 e = intel_pt_cache_lookup(al.map->dso, machine, offset); 2675 if (!e) 2676 continue; 2677 2678 if (addr + e->byte_cnt + e->length <= event->text_poke.addr) { 2679 /* 2680 * No overlap. Working backwards there cannot be another 2681 * basic block that overlaps the text poke if there is a 2682 * branch instruction before the text poke address. 2683 */ 2684 if (e->branch != INTEL_PT_BR_NO_BRANCH) 2685 return 0; 2686 } else { 2687 intel_pt_cache_invalidate(al.map->dso, machine, offset); 2688 intel_pt_log("Invalidated instruction cache for %s at %#"PRIx64"\n", 2689 al.map->dso->long_name, addr); 2690 } 2691 } 2692 2693 return 0; 2694 } 2695 2696 static int intel_pt_process_event(struct perf_session *session, 2697 union perf_event *event, 2698 struct perf_sample *sample, 2699 struct perf_tool *tool) 2700 { 2701 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 2702 auxtrace); 2703 u64 timestamp; 2704 int err = 0; 2705 2706 if (dump_trace) 2707 return 0; 2708 2709 if (!tool->ordered_events) { 2710 pr_err("Intel Processor Trace requires ordered events\n"); 2711 return -EINVAL; 2712 } 2713 2714 if (sample->time && sample->time != (u64)-1) 2715 timestamp = perf_time_to_tsc(sample->time, &pt->tc); 2716 else 2717 timestamp = 0; 2718 2719 if (timestamp || pt->timeless_decoding) { 2720 err = intel_pt_update_queues(pt); 2721 if (err) 2722 return err; 2723 } 2724 2725 if (pt->timeless_decoding) { 2726 if (pt->sampling_mode) { 2727 if (sample->aux_sample.size) 2728 err = intel_pt_process_timeless_sample(pt, 2729 sample); 2730 } else if (event->header.type == PERF_RECORD_EXIT) { 2731 err = intel_pt_process_timeless_queues(pt, 2732 event->fork.tid, 2733 sample->time); 2734 } 2735 } else if (timestamp) { 2736 err = intel_pt_process_queues(pt, timestamp); 2737 } 2738 if (err) 2739 return err; 2740 2741 if (event->header.type == PERF_RECORD_SAMPLE) { 2742 if (pt->synth_opts.add_callchain && !sample->callchain) 2743 intel_pt_add_callchain(pt, sample); 2744 if (pt->synth_opts.add_last_branch && !sample->branch_stack) 2745 intel_pt_add_br_stack(pt, sample); 2746 } 2747 2748 if (event->header.type == PERF_RECORD_AUX && 2749 (event->aux.flags & PERF_AUX_FLAG_TRUNCATED) && 2750 pt->synth_opts.errors) { 2751 err = intel_pt_lost(pt, sample); 2752 if (err) 2753 return err; 2754 } 2755 2756 if (pt->switch_evsel && event->header.type == PERF_RECORD_SAMPLE) 2757 err = intel_pt_process_switch(pt, sample); 2758 else if (event->header.type == PERF_RECORD_ITRACE_START) 2759 err = intel_pt_process_itrace_start(pt, event, sample); 2760 else if (event->header.type == PERF_RECORD_SWITCH || 2761 event->header.type == PERF_RECORD_SWITCH_CPU_WIDE) 2762 err = intel_pt_context_switch(pt, event, sample); 2763 2764 if (!err && event->header.type == PERF_RECORD_TEXT_POKE) 2765 err = intel_pt_text_poke(pt, event); 2766 2767 if (intel_pt_enable_logging && intel_pt_log_events(pt, sample->time)) { 2768 intel_pt_log("event %u: cpu %d time %"PRIu64" tsc %#"PRIx64" ", 2769 event->header.type, sample->cpu, sample->time, timestamp); 2770 intel_pt_log_event(event); 2771 } 2772 2773 return err; 2774 } 2775 2776 static int intel_pt_flush(struct perf_session *session, struct perf_tool *tool) 2777 { 2778 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 2779 auxtrace); 2780 int ret; 2781 2782 if (dump_trace) 2783 return 0; 2784 2785 if (!tool->ordered_events) 2786 return -EINVAL; 2787 2788 ret = intel_pt_update_queues(pt); 2789 if (ret < 0) 2790 return ret; 2791 2792 if (pt->timeless_decoding) 2793 return intel_pt_process_timeless_queues(pt, -1, 2794 MAX_TIMESTAMP - 1); 2795 2796 return intel_pt_process_queues(pt, MAX_TIMESTAMP); 2797 } 2798 2799 static void intel_pt_free_events(struct perf_session *session) 2800 { 2801 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 2802 auxtrace); 2803 struct auxtrace_queues *queues = &pt->queues; 2804 unsigned int i; 2805 2806 for (i = 0; i < queues->nr_queues; i++) { 2807 intel_pt_free_queue(queues->queue_array[i].priv); 2808 queues->queue_array[i].priv = NULL; 2809 } 2810 intel_pt_log_disable(); 2811 auxtrace_queues__free(queues); 2812 } 2813 2814 static void intel_pt_free(struct perf_session *session) 2815 { 2816 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 2817 auxtrace); 2818 2819 auxtrace_heap__free(&pt->heap); 2820 intel_pt_free_events(session); 2821 session->auxtrace = NULL; 2822 thread__put(pt->unknown_thread); 2823 addr_filters__exit(&pt->filts); 2824 zfree(&pt->chain); 2825 zfree(&pt->filter); 2826 zfree(&pt->time_ranges); 2827 free(pt); 2828 } 2829 2830 static bool intel_pt_evsel_is_auxtrace(struct perf_session *session, 2831 struct evsel *evsel) 2832 { 2833 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 2834 auxtrace); 2835 2836 return evsel->core.attr.type == pt->pmu_type; 2837 } 2838 2839 static int intel_pt_process_auxtrace_event(struct perf_session *session, 2840 union perf_event *event, 2841 struct perf_tool *tool __maybe_unused) 2842 { 2843 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 2844 auxtrace); 2845 2846 if (!pt->data_queued) { 2847 struct auxtrace_buffer *buffer; 2848 off_t data_offset; 2849 int fd = perf_data__fd(session->data); 2850 int err; 2851 2852 if (perf_data__is_pipe(session->data)) { 2853 data_offset = 0; 2854 } else { 2855 data_offset = lseek(fd, 0, SEEK_CUR); 2856 if (data_offset == -1) 2857 return -errno; 2858 } 2859 2860 err = auxtrace_queues__add_event(&pt->queues, session, event, 2861 data_offset, &buffer); 2862 if (err) 2863 return err; 2864 2865 /* Dump here now we have copied a piped trace out of the pipe */ 2866 if (dump_trace) { 2867 if (auxtrace_buffer__get_data(buffer, fd)) { 2868 intel_pt_dump_event(pt, buffer->data, 2869 buffer->size); 2870 auxtrace_buffer__put_data(buffer); 2871 } 2872 } 2873 } 2874 2875 return 0; 2876 } 2877 2878 static int intel_pt_queue_data(struct perf_session *session, 2879 struct perf_sample *sample, 2880 union perf_event *event, u64 data_offset) 2881 { 2882 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 2883 auxtrace); 2884 u64 timestamp; 2885 2886 if (event) { 2887 return auxtrace_queues__add_event(&pt->queues, session, event, 2888 data_offset, NULL); 2889 } 2890 2891 if (sample->time && sample->time != (u64)-1) 2892 timestamp = perf_time_to_tsc(sample->time, &pt->tc); 2893 else 2894 timestamp = 0; 2895 2896 return auxtrace_queues__add_sample(&pt->queues, session, sample, 2897 data_offset, timestamp); 2898 } 2899 2900 struct intel_pt_synth { 2901 struct perf_tool dummy_tool; 2902 struct perf_session *session; 2903 }; 2904 2905 static int intel_pt_event_synth(struct perf_tool *tool, 2906 union perf_event *event, 2907 struct perf_sample *sample __maybe_unused, 2908 struct machine *machine __maybe_unused) 2909 { 2910 struct intel_pt_synth *intel_pt_synth = 2911 container_of(tool, struct intel_pt_synth, dummy_tool); 2912 2913 return perf_session__deliver_synth_event(intel_pt_synth->session, event, 2914 NULL); 2915 } 2916 2917 static int intel_pt_synth_event(struct perf_session *session, const char *name, 2918 struct perf_event_attr *attr, u64 id) 2919 { 2920 struct intel_pt_synth intel_pt_synth; 2921 int err; 2922 2923 pr_debug("Synthesizing '%s' event with id %" PRIu64 " sample type %#" PRIx64 "\n", 2924 name, id, (u64)attr->sample_type); 2925 2926 memset(&intel_pt_synth, 0, sizeof(struct intel_pt_synth)); 2927 intel_pt_synth.session = session; 2928 2929 err = perf_event__synthesize_attr(&intel_pt_synth.dummy_tool, attr, 1, 2930 &id, intel_pt_event_synth); 2931 if (err) 2932 pr_err("%s: failed to synthesize '%s' event type\n", 2933 __func__, name); 2934 2935 return err; 2936 } 2937 2938 static void intel_pt_set_event_name(struct evlist *evlist, u64 id, 2939 const char *name) 2940 { 2941 struct evsel *evsel; 2942 2943 evlist__for_each_entry(evlist, evsel) { 2944 if (evsel->core.id && evsel->core.id[0] == id) { 2945 if (evsel->name) 2946 zfree(&evsel->name); 2947 evsel->name = strdup(name); 2948 break; 2949 } 2950 } 2951 } 2952 2953 static struct evsel *intel_pt_evsel(struct intel_pt *pt, 2954 struct evlist *evlist) 2955 { 2956 struct evsel *evsel; 2957 2958 evlist__for_each_entry(evlist, evsel) { 2959 if (evsel->core.attr.type == pt->pmu_type && evsel->core.ids) 2960 return evsel; 2961 } 2962 2963 return NULL; 2964 } 2965 2966 static int intel_pt_synth_events(struct intel_pt *pt, 2967 struct perf_session *session) 2968 { 2969 struct evlist *evlist = session->evlist; 2970 struct evsel *evsel = intel_pt_evsel(pt, evlist); 2971 struct perf_event_attr attr; 2972 u64 id; 2973 int err; 2974 2975 if (!evsel) { 2976 pr_debug("There are no selected events with Intel Processor Trace data\n"); 2977 return 0; 2978 } 2979 2980 memset(&attr, 0, sizeof(struct perf_event_attr)); 2981 attr.size = sizeof(struct perf_event_attr); 2982 attr.type = PERF_TYPE_HARDWARE; 2983 attr.sample_type = evsel->core.attr.sample_type & PERF_SAMPLE_MASK; 2984 attr.sample_type |= PERF_SAMPLE_IP | PERF_SAMPLE_TID | 2985 PERF_SAMPLE_PERIOD; 2986 if (pt->timeless_decoding) 2987 attr.sample_type &= ~(u64)PERF_SAMPLE_TIME; 2988 else 2989 attr.sample_type |= PERF_SAMPLE_TIME; 2990 if (!pt->per_cpu_mmaps) 2991 attr.sample_type &= ~(u64)PERF_SAMPLE_CPU; 2992 attr.exclude_user = evsel->core.attr.exclude_user; 2993 attr.exclude_kernel = evsel->core.attr.exclude_kernel; 2994 attr.exclude_hv = evsel->core.attr.exclude_hv; 2995 attr.exclude_host = evsel->core.attr.exclude_host; 2996 attr.exclude_guest = evsel->core.attr.exclude_guest; 2997 attr.sample_id_all = evsel->core.attr.sample_id_all; 2998 attr.read_format = evsel->core.attr.read_format; 2999 3000 id = evsel->core.id[0] + 1000000000; 3001 if (!id) 3002 id = 1; 3003 3004 if (pt->synth_opts.branches) { 3005 attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS; 3006 attr.sample_period = 1; 3007 attr.sample_type |= PERF_SAMPLE_ADDR; 3008 err = intel_pt_synth_event(session, "branches", &attr, id); 3009 if (err) 3010 return err; 3011 pt->sample_branches = true; 3012 pt->branches_sample_type = attr.sample_type; 3013 pt->branches_id = id; 3014 id += 1; 3015 attr.sample_type &= ~(u64)PERF_SAMPLE_ADDR; 3016 } 3017 3018 if (pt->synth_opts.callchain) 3019 attr.sample_type |= PERF_SAMPLE_CALLCHAIN; 3020 if (pt->synth_opts.last_branch) 3021 attr.sample_type |= PERF_SAMPLE_BRANCH_STACK; 3022 3023 if (pt->synth_opts.instructions) { 3024 attr.config = PERF_COUNT_HW_INSTRUCTIONS; 3025 if (pt->synth_opts.period_type == PERF_ITRACE_PERIOD_NANOSECS) 3026 attr.sample_period = 3027 intel_pt_ns_to_ticks(pt, pt->synth_opts.period); 3028 else 3029 attr.sample_period = pt->synth_opts.period; 3030 err = intel_pt_synth_event(session, "instructions", &attr, id); 3031 if (err) 3032 return err; 3033 pt->sample_instructions = true; 3034 pt->instructions_sample_type = attr.sample_type; 3035 pt->instructions_id = id; 3036 id += 1; 3037 } 3038 3039 attr.sample_type &= ~(u64)PERF_SAMPLE_PERIOD; 3040 attr.sample_period = 1; 3041 3042 if (pt->synth_opts.transactions) { 3043 attr.config = PERF_COUNT_HW_INSTRUCTIONS; 3044 err = intel_pt_synth_event(session, "transactions", &attr, id); 3045 if (err) 3046 return err; 3047 pt->sample_transactions = true; 3048 pt->transactions_sample_type = attr.sample_type; 3049 pt->transactions_id = id; 3050 intel_pt_set_event_name(evlist, id, "transactions"); 3051 id += 1; 3052 } 3053 3054 attr.type = PERF_TYPE_SYNTH; 3055 attr.sample_type |= PERF_SAMPLE_RAW; 3056 3057 if (pt->synth_opts.ptwrites) { 3058 attr.config = PERF_SYNTH_INTEL_PTWRITE; 3059 err = intel_pt_synth_event(session, "ptwrite", &attr, id); 3060 if (err) 3061 return err; 3062 pt->sample_ptwrites = true; 3063 pt->ptwrites_sample_type = attr.sample_type; 3064 pt->ptwrites_id = id; 3065 intel_pt_set_event_name(evlist, id, "ptwrite"); 3066 id += 1; 3067 } 3068 3069 if (pt->synth_opts.pwr_events) { 3070 pt->sample_pwr_events = true; 3071 pt->pwr_events_sample_type = attr.sample_type; 3072 3073 attr.config = PERF_SYNTH_INTEL_CBR; 3074 err = intel_pt_synth_event(session, "cbr", &attr, id); 3075 if (err) 3076 return err; 3077 pt->cbr_id = id; 3078 intel_pt_set_event_name(evlist, id, "cbr"); 3079 id += 1; 3080 } 3081 3082 if (pt->synth_opts.pwr_events && (evsel->core.attr.config & 0x10)) { 3083 attr.config = PERF_SYNTH_INTEL_MWAIT; 3084 err = intel_pt_synth_event(session, "mwait", &attr, id); 3085 if (err) 3086 return err; 3087 pt->mwait_id = id; 3088 intel_pt_set_event_name(evlist, id, "mwait"); 3089 id += 1; 3090 3091 attr.config = PERF_SYNTH_INTEL_PWRE; 3092 err = intel_pt_synth_event(session, "pwre", &attr, id); 3093 if (err) 3094 return err; 3095 pt->pwre_id = id; 3096 intel_pt_set_event_name(evlist, id, "pwre"); 3097 id += 1; 3098 3099 attr.config = PERF_SYNTH_INTEL_EXSTOP; 3100 err = intel_pt_synth_event(session, "exstop", &attr, id); 3101 if (err) 3102 return err; 3103 pt->exstop_id = id; 3104 intel_pt_set_event_name(evlist, id, "exstop"); 3105 id += 1; 3106 3107 attr.config = PERF_SYNTH_INTEL_PWRX; 3108 err = intel_pt_synth_event(session, "pwrx", &attr, id); 3109 if (err) 3110 return err; 3111 pt->pwrx_id = id; 3112 intel_pt_set_event_name(evlist, id, "pwrx"); 3113 id += 1; 3114 } 3115 3116 return 0; 3117 } 3118 3119 static void intel_pt_setup_pebs_events(struct intel_pt *pt) 3120 { 3121 struct evsel *evsel; 3122 3123 if (!pt->synth_opts.other_events) 3124 return; 3125 3126 evlist__for_each_entry(pt->session->evlist, evsel) { 3127 if (evsel->core.attr.aux_output && evsel->core.id) { 3128 pt->sample_pebs = true; 3129 pt->pebs_evsel = evsel; 3130 return; 3131 } 3132 } 3133 } 3134 3135 static struct evsel *intel_pt_find_sched_switch(struct evlist *evlist) 3136 { 3137 struct evsel *evsel; 3138 3139 evlist__for_each_entry_reverse(evlist, evsel) { 3140 const char *name = evsel__name(evsel); 3141 3142 if (!strcmp(name, "sched:sched_switch")) 3143 return evsel; 3144 } 3145 3146 return NULL; 3147 } 3148 3149 static bool intel_pt_find_switch(struct evlist *evlist) 3150 { 3151 struct evsel *evsel; 3152 3153 evlist__for_each_entry(evlist, evsel) { 3154 if (evsel->core.attr.context_switch) 3155 return true; 3156 } 3157 3158 return false; 3159 } 3160 3161 static int intel_pt_perf_config(const char *var, const char *value, void *data) 3162 { 3163 struct intel_pt *pt = data; 3164 3165 if (!strcmp(var, "intel-pt.mispred-all")) 3166 pt->mispred_all = perf_config_bool(var, value); 3167 3168 return 0; 3169 } 3170 3171 /* Find least TSC which converts to ns or later */ 3172 static u64 intel_pt_tsc_start(u64 ns, struct intel_pt *pt) 3173 { 3174 u64 tsc, tm; 3175 3176 tsc = perf_time_to_tsc(ns, &pt->tc); 3177 3178 while (1) { 3179 tm = tsc_to_perf_time(tsc, &pt->tc); 3180 if (tm < ns) 3181 break; 3182 tsc -= 1; 3183 } 3184 3185 while (tm < ns) 3186 tm = tsc_to_perf_time(++tsc, &pt->tc); 3187 3188 return tsc; 3189 } 3190 3191 /* Find greatest TSC which converts to ns or earlier */ 3192 static u64 intel_pt_tsc_end(u64 ns, struct intel_pt *pt) 3193 { 3194 u64 tsc, tm; 3195 3196 tsc = perf_time_to_tsc(ns, &pt->tc); 3197 3198 while (1) { 3199 tm = tsc_to_perf_time(tsc, &pt->tc); 3200 if (tm > ns) 3201 break; 3202 tsc += 1; 3203 } 3204 3205 while (tm > ns) 3206 tm = tsc_to_perf_time(--tsc, &pt->tc); 3207 3208 return tsc; 3209 } 3210 3211 static int intel_pt_setup_time_ranges(struct intel_pt *pt, 3212 struct itrace_synth_opts *opts) 3213 { 3214 struct perf_time_interval *p = opts->ptime_range; 3215 int n = opts->range_num; 3216 int i; 3217 3218 if (!n || !p || pt->timeless_decoding) 3219 return 0; 3220 3221 pt->time_ranges = calloc(n, sizeof(struct range)); 3222 if (!pt->time_ranges) 3223 return -ENOMEM; 3224 3225 pt->range_cnt = n; 3226 3227 intel_pt_log("%s: %u range(s)\n", __func__, n); 3228 3229 for (i = 0; i < n; i++) { 3230 struct range *r = &pt->time_ranges[i]; 3231 u64 ts = p[i].start; 3232 u64 te = p[i].end; 3233 3234 /* 3235 * Take care to ensure the TSC range matches the perf-time range 3236 * when converted back to perf-time. 3237 */ 3238 r->start = ts ? intel_pt_tsc_start(ts, pt) : 0; 3239 r->end = te ? intel_pt_tsc_end(te, pt) : 0; 3240 3241 intel_pt_log("range %d: perf time interval: %"PRIu64" to %"PRIu64"\n", 3242 i, ts, te); 3243 intel_pt_log("range %d: TSC time interval: %#"PRIx64" to %#"PRIx64"\n", 3244 i, r->start, r->end); 3245 } 3246 3247 return 0; 3248 } 3249 3250 static const char * const intel_pt_info_fmts[] = { 3251 [INTEL_PT_PMU_TYPE] = " PMU Type %"PRId64"\n", 3252 [INTEL_PT_TIME_SHIFT] = " Time Shift %"PRIu64"\n", 3253 [INTEL_PT_TIME_MULT] = " Time Muliplier %"PRIu64"\n", 3254 [INTEL_PT_TIME_ZERO] = " Time Zero %"PRIu64"\n", 3255 [INTEL_PT_CAP_USER_TIME_ZERO] = " Cap Time Zero %"PRId64"\n", 3256 [INTEL_PT_TSC_BIT] = " TSC bit %#"PRIx64"\n", 3257 [INTEL_PT_NORETCOMP_BIT] = " NoRETComp bit %#"PRIx64"\n", 3258 [INTEL_PT_HAVE_SCHED_SWITCH] = " Have sched_switch %"PRId64"\n", 3259 [INTEL_PT_SNAPSHOT_MODE] = " Snapshot mode %"PRId64"\n", 3260 [INTEL_PT_PER_CPU_MMAPS] = " Per-cpu maps %"PRId64"\n", 3261 [INTEL_PT_MTC_BIT] = " MTC bit %#"PRIx64"\n", 3262 [INTEL_PT_TSC_CTC_N] = " TSC:CTC numerator %"PRIu64"\n", 3263 [INTEL_PT_TSC_CTC_D] = " TSC:CTC denominator %"PRIu64"\n", 3264 [INTEL_PT_CYC_BIT] = " CYC bit %#"PRIx64"\n", 3265 [INTEL_PT_MAX_NONTURBO_RATIO] = " Max non-turbo ratio %"PRIu64"\n", 3266 [INTEL_PT_FILTER_STR_LEN] = " Filter string len. %"PRIu64"\n", 3267 }; 3268 3269 static void intel_pt_print_info(__u64 *arr, int start, int finish) 3270 { 3271 int i; 3272 3273 if (!dump_trace) 3274 return; 3275 3276 for (i = start; i <= finish; i++) 3277 fprintf(stdout, intel_pt_info_fmts[i], arr[i]); 3278 } 3279 3280 static void intel_pt_print_info_str(const char *name, const char *str) 3281 { 3282 if (!dump_trace) 3283 return; 3284 3285 fprintf(stdout, " %-20s%s\n", name, str ? str : ""); 3286 } 3287 3288 static bool intel_pt_has(struct perf_record_auxtrace_info *auxtrace_info, int pos) 3289 { 3290 return auxtrace_info->header.size >= 3291 sizeof(struct perf_record_auxtrace_info) + (sizeof(u64) * (pos + 1)); 3292 } 3293 3294 int intel_pt_process_auxtrace_info(union perf_event *event, 3295 struct perf_session *session) 3296 { 3297 struct perf_record_auxtrace_info *auxtrace_info = &event->auxtrace_info; 3298 size_t min_sz = sizeof(u64) * INTEL_PT_PER_CPU_MMAPS; 3299 struct intel_pt *pt; 3300 void *info_end; 3301 __u64 *info; 3302 int err; 3303 3304 if (auxtrace_info->header.size < sizeof(struct perf_record_auxtrace_info) + 3305 min_sz) 3306 return -EINVAL; 3307 3308 pt = zalloc(sizeof(struct intel_pt)); 3309 if (!pt) 3310 return -ENOMEM; 3311 3312 addr_filters__init(&pt->filts); 3313 3314 err = perf_config(intel_pt_perf_config, pt); 3315 if (err) 3316 goto err_free; 3317 3318 err = auxtrace_queues__init(&pt->queues); 3319 if (err) 3320 goto err_free; 3321 3322 intel_pt_log_set_name(INTEL_PT_PMU_NAME); 3323 3324 pt->session = session; 3325 pt->machine = &session->machines.host; /* No kvm support */ 3326 pt->auxtrace_type = auxtrace_info->type; 3327 pt->pmu_type = auxtrace_info->priv[INTEL_PT_PMU_TYPE]; 3328 pt->tc.time_shift = auxtrace_info->priv[INTEL_PT_TIME_SHIFT]; 3329 pt->tc.time_mult = auxtrace_info->priv[INTEL_PT_TIME_MULT]; 3330 pt->tc.time_zero = auxtrace_info->priv[INTEL_PT_TIME_ZERO]; 3331 pt->cap_user_time_zero = auxtrace_info->priv[INTEL_PT_CAP_USER_TIME_ZERO]; 3332 pt->tsc_bit = auxtrace_info->priv[INTEL_PT_TSC_BIT]; 3333 pt->noretcomp_bit = auxtrace_info->priv[INTEL_PT_NORETCOMP_BIT]; 3334 pt->have_sched_switch = auxtrace_info->priv[INTEL_PT_HAVE_SCHED_SWITCH]; 3335 pt->snapshot_mode = auxtrace_info->priv[INTEL_PT_SNAPSHOT_MODE]; 3336 pt->per_cpu_mmaps = auxtrace_info->priv[INTEL_PT_PER_CPU_MMAPS]; 3337 intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_PMU_TYPE, 3338 INTEL_PT_PER_CPU_MMAPS); 3339 3340 if (intel_pt_has(auxtrace_info, INTEL_PT_CYC_BIT)) { 3341 pt->mtc_bit = auxtrace_info->priv[INTEL_PT_MTC_BIT]; 3342 pt->mtc_freq_bits = auxtrace_info->priv[INTEL_PT_MTC_FREQ_BITS]; 3343 pt->tsc_ctc_ratio_n = auxtrace_info->priv[INTEL_PT_TSC_CTC_N]; 3344 pt->tsc_ctc_ratio_d = auxtrace_info->priv[INTEL_PT_TSC_CTC_D]; 3345 pt->cyc_bit = auxtrace_info->priv[INTEL_PT_CYC_BIT]; 3346 intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_MTC_BIT, 3347 INTEL_PT_CYC_BIT); 3348 } 3349 3350 if (intel_pt_has(auxtrace_info, INTEL_PT_MAX_NONTURBO_RATIO)) { 3351 pt->max_non_turbo_ratio = 3352 auxtrace_info->priv[INTEL_PT_MAX_NONTURBO_RATIO]; 3353 intel_pt_print_info(&auxtrace_info->priv[0], 3354 INTEL_PT_MAX_NONTURBO_RATIO, 3355 INTEL_PT_MAX_NONTURBO_RATIO); 3356 } 3357 3358 info = &auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN] + 1; 3359 info_end = (void *)info + auxtrace_info->header.size; 3360 3361 if (intel_pt_has(auxtrace_info, INTEL_PT_FILTER_STR_LEN)) { 3362 size_t len; 3363 3364 len = auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN]; 3365 intel_pt_print_info(&auxtrace_info->priv[0], 3366 INTEL_PT_FILTER_STR_LEN, 3367 INTEL_PT_FILTER_STR_LEN); 3368 if (len) { 3369 const char *filter = (const char *)info; 3370 3371 len = roundup(len + 1, 8); 3372 info += len >> 3; 3373 if ((void *)info > info_end) { 3374 pr_err("%s: bad filter string length\n", __func__); 3375 err = -EINVAL; 3376 goto err_free_queues; 3377 } 3378 pt->filter = memdup(filter, len); 3379 if (!pt->filter) { 3380 err = -ENOMEM; 3381 goto err_free_queues; 3382 } 3383 if (session->header.needs_swap) 3384 mem_bswap_64(pt->filter, len); 3385 if (pt->filter[len - 1]) { 3386 pr_err("%s: filter string not null terminated\n", __func__); 3387 err = -EINVAL; 3388 goto err_free_queues; 3389 } 3390 err = addr_filters__parse_bare_filter(&pt->filts, 3391 filter); 3392 if (err) 3393 goto err_free_queues; 3394 } 3395 intel_pt_print_info_str("Filter string", pt->filter); 3396 } 3397 3398 pt->timeless_decoding = intel_pt_timeless_decoding(pt); 3399 if (pt->timeless_decoding && !pt->tc.time_mult) 3400 pt->tc.time_mult = 1; 3401 pt->have_tsc = intel_pt_have_tsc(pt); 3402 pt->sampling_mode = intel_pt_sampling_mode(pt); 3403 pt->est_tsc = !pt->timeless_decoding; 3404 3405 pt->unknown_thread = thread__new(999999999, 999999999); 3406 if (!pt->unknown_thread) { 3407 err = -ENOMEM; 3408 goto err_free_queues; 3409 } 3410 3411 /* 3412 * Since this thread will not be kept in any rbtree not in a 3413 * list, initialize its list node so that at thread__put() the 3414 * current thread lifetime assuption is kept and we don't segfault 3415 * at list_del_init(). 3416 */ 3417 INIT_LIST_HEAD(&pt->unknown_thread->node); 3418 3419 err = thread__set_comm(pt->unknown_thread, "unknown", 0); 3420 if (err) 3421 goto err_delete_thread; 3422 if (thread__init_maps(pt->unknown_thread, pt->machine)) { 3423 err = -ENOMEM; 3424 goto err_delete_thread; 3425 } 3426 3427 pt->auxtrace.process_event = intel_pt_process_event; 3428 pt->auxtrace.process_auxtrace_event = intel_pt_process_auxtrace_event; 3429 pt->auxtrace.queue_data = intel_pt_queue_data; 3430 pt->auxtrace.dump_auxtrace_sample = intel_pt_dump_sample; 3431 pt->auxtrace.flush_events = intel_pt_flush; 3432 pt->auxtrace.free_events = intel_pt_free_events; 3433 pt->auxtrace.free = intel_pt_free; 3434 pt->auxtrace.evsel_is_auxtrace = intel_pt_evsel_is_auxtrace; 3435 session->auxtrace = &pt->auxtrace; 3436 3437 if (dump_trace) 3438 return 0; 3439 3440 if (pt->have_sched_switch == 1) { 3441 pt->switch_evsel = intel_pt_find_sched_switch(session->evlist); 3442 if (!pt->switch_evsel) { 3443 pr_err("%s: missing sched_switch event\n", __func__); 3444 err = -EINVAL; 3445 goto err_delete_thread; 3446 } 3447 } else if (pt->have_sched_switch == 2 && 3448 !intel_pt_find_switch(session->evlist)) { 3449 pr_err("%s: missing context_switch attribute flag\n", __func__); 3450 err = -EINVAL; 3451 goto err_delete_thread; 3452 } 3453 3454 if (session->itrace_synth_opts->set) { 3455 pt->synth_opts = *session->itrace_synth_opts; 3456 } else { 3457 itrace_synth_opts__set_default(&pt->synth_opts, 3458 session->itrace_synth_opts->default_no_sample); 3459 if (!session->itrace_synth_opts->default_no_sample && 3460 !session->itrace_synth_opts->inject) { 3461 pt->synth_opts.branches = false; 3462 pt->synth_opts.callchain = true; 3463 pt->synth_opts.add_callchain = true; 3464 } 3465 pt->synth_opts.thread_stack = 3466 session->itrace_synth_opts->thread_stack; 3467 } 3468 3469 if (pt->synth_opts.log) 3470 intel_pt_log_enable(); 3471 3472 /* Maximum non-turbo ratio is TSC freq / 100 MHz */ 3473 if (pt->tc.time_mult) { 3474 u64 tsc_freq = intel_pt_ns_to_ticks(pt, 1000000000); 3475 3476 if (!pt->max_non_turbo_ratio) 3477 pt->max_non_turbo_ratio = 3478 (tsc_freq + 50000000) / 100000000; 3479 intel_pt_log("TSC frequency %"PRIu64"\n", tsc_freq); 3480 intel_pt_log("Maximum non-turbo ratio %u\n", 3481 pt->max_non_turbo_ratio); 3482 pt->cbr2khz = tsc_freq / pt->max_non_turbo_ratio / 1000; 3483 } 3484 3485 err = intel_pt_setup_time_ranges(pt, session->itrace_synth_opts); 3486 if (err) 3487 goto err_delete_thread; 3488 3489 if (pt->synth_opts.calls) 3490 pt->branches_filter |= PERF_IP_FLAG_CALL | PERF_IP_FLAG_ASYNC | 3491 PERF_IP_FLAG_TRACE_END; 3492 if (pt->synth_opts.returns) 3493 pt->branches_filter |= PERF_IP_FLAG_RETURN | 3494 PERF_IP_FLAG_TRACE_BEGIN; 3495 3496 if ((pt->synth_opts.callchain || pt->synth_opts.add_callchain) && 3497 !symbol_conf.use_callchain) { 3498 symbol_conf.use_callchain = true; 3499 if (callchain_register_param(&callchain_param) < 0) { 3500 symbol_conf.use_callchain = false; 3501 pt->synth_opts.callchain = false; 3502 pt->synth_opts.add_callchain = false; 3503 } 3504 } 3505 3506 if (pt->synth_opts.add_callchain) { 3507 err = intel_pt_callchain_init(pt); 3508 if (err) 3509 goto err_delete_thread; 3510 } 3511 3512 if (pt->synth_opts.last_branch || pt->synth_opts.add_last_branch) { 3513 pt->br_stack_sz = pt->synth_opts.last_branch_sz; 3514 pt->br_stack_sz_plus = pt->br_stack_sz; 3515 } 3516 3517 if (pt->synth_opts.add_last_branch) { 3518 err = intel_pt_br_stack_init(pt); 3519 if (err) 3520 goto err_delete_thread; 3521 /* 3522 * Additional branch stack size to cater for tracing from the 3523 * actual sample ip to where the sample time is recorded. 3524 * Measured at about 200 branches, but generously set to 1024. 3525 * If kernel space is not being traced, then add just 1 for the 3526 * branch to kernel space. 3527 */ 3528 if (intel_pt_tracing_kernel(pt)) 3529 pt->br_stack_sz_plus += 1024; 3530 else 3531 pt->br_stack_sz_plus += 1; 3532 } 3533 3534 pt->use_thread_stack = pt->synth_opts.callchain || 3535 pt->synth_opts.add_callchain || 3536 pt->synth_opts.thread_stack || 3537 pt->synth_opts.last_branch || 3538 pt->synth_opts.add_last_branch; 3539 3540 pt->callstack = pt->synth_opts.callchain || 3541 pt->synth_opts.add_callchain || 3542 pt->synth_opts.thread_stack; 3543 3544 err = intel_pt_synth_events(pt, session); 3545 if (err) 3546 goto err_delete_thread; 3547 3548 intel_pt_setup_pebs_events(pt); 3549 3550 if (pt->sampling_mode || list_empty(&session->auxtrace_index)) 3551 err = auxtrace_queue_data(session, true, true); 3552 else 3553 err = auxtrace_queues__process_index(&pt->queues, session); 3554 if (err) 3555 goto err_delete_thread; 3556 3557 if (pt->queues.populated) 3558 pt->data_queued = true; 3559 3560 if (pt->timeless_decoding) 3561 pr_debug2("Intel PT decoding without timestamps\n"); 3562 3563 return 0; 3564 3565 err_delete_thread: 3566 zfree(&pt->chain); 3567 thread__zput(pt->unknown_thread); 3568 err_free_queues: 3569 intel_pt_log_disable(); 3570 auxtrace_queues__free(&pt->queues); 3571 session->auxtrace = NULL; 3572 err_free: 3573 addr_filters__exit(&pt->filts); 3574 zfree(&pt->filter); 3575 zfree(&pt->time_ranges); 3576 free(pt); 3577 return err; 3578 } 3579