1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AMD specific. Provide textual annotation for IBS raw sample data. 4 */ 5 6 #include <unistd.h> 7 #include <stdio.h> 8 #include <string.h> 9 #include <inttypes.h> 10 11 #include <linux/string.h> 12 #include "../../arch/x86/include/asm/amd-ibs.h" 13 14 #include "debug.h" 15 #include "session.h" 16 #include "evlist.h" 17 #include "sample-raw.h" 18 #include "pmu-events/pmu-events.h" 19 #include "util/sample.h" 20 21 static u32 cpu_family, cpu_model, ibs_fetch_type, ibs_op_type; 22 static bool zen4_ibs_extensions; 23 24 static void pr_ibs_fetch_ctl(union ibs_fetch_ctl reg) 25 { 26 const char * const ic_miss_strs[] = { 27 " IcMiss 0", 28 " IcMiss 1", 29 }; 30 const char * const l1tlb_pgsz_strs[] = { 31 " L1TlbPgSz 4KB", 32 " L1TlbPgSz 2MB", 33 " L1TlbPgSz 1GB", 34 " L1TlbPgSz RESERVED" 35 }; 36 const char * const l1tlb_pgsz_strs_erratum1347[] = { 37 " L1TlbPgSz 4KB", 38 " L1TlbPgSz 16KB", 39 " L1TlbPgSz 2MB", 40 " L1TlbPgSz 1GB" 41 }; 42 const char *ic_miss_str = NULL; 43 const char *l1tlb_pgsz_str = NULL; 44 char l3_miss_str[sizeof(" L3MissOnly _ FetchOcMiss _ FetchL3Miss _")] = ""; 45 46 if (cpu_family == 0x19 && cpu_model < 0x10) { 47 /* 48 * Erratum #1238 workaround is to ignore MSRC001_1030[IbsIcMiss] 49 * Erratum #1347 workaround is to use table provided in erratum 50 */ 51 if (reg.phy_addr_valid) 52 l1tlb_pgsz_str = l1tlb_pgsz_strs_erratum1347[reg.l1tlb_pgsz]; 53 } else { 54 if (reg.phy_addr_valid) 55 l1tlb_pgsz_str = l1tlb_pgsz_strs[reg.l1tlb_pgsz]; 56 ic_miss_str = ic_miss_strs[reg.ic_miss]; 57 } 58 59 if (zen4_ibs_extensions) { 60 snprintf(l3_miss_str, sizeof(l3_miss_str), 61 " L3MissOnly %d FetchOcMiss %d FetchL3Miss %d", 62 reg.l3_miss_only, reg.fetch_oc_miss, reg.fetch_l3_miss); 63 } 64 65 printf("ibs_fetch_ctl:\t%016llx MaxCnt %7d Cnt %7d Lat %5d En %d Val %d Comp %d%s " 66 "PhyAddrValid %d%s L1TlbMiss %d L2TlbMiss %d RandEn %d%s%s\n", 67 reg.val, reg.fetch_maxcnt << 4, reg.fetch_cnt << 4, reg.fetch_lat, 68 reg.fetch_en, reg.fetch_val, reg.fetch_comp, ic_miss_str ? : "", 69 reg.phy_addr_valid, l1tlb_pgsz_str ? : "", reg.l1tlb_miss, reg.l2tlb_miss, 70 reg.rand_en, reg.fetch_comp ? (reg.fetch_l2_miss ? " L2Miss 1" : " L2Miss 0") : "", 71 l3_miss_str); 72 } 73 74 static void pr_ic_ibs_extd_ctl(union ic_ibs_extd_ctl reg) 75 { 76 printf("ic_ibs_ext_ctl:\t%016llx IbsItlbRefillLat %3d\n", reg.val, reg.itlb_refill_lat); 77 } 78 79 static void pr_ibs_op_ctl(union ibs_op_ctl reg) 80 { 81 char l3_miss_only[sizeof(" L3MissOnly _")] = ""; 82 83 if (zen4_ibs_extensions) 84 snprintf(l3_miss_only, sizeof(l3_miss_only), " L3MissOnly %d", reg.l3_miss_only); 85 86 printf("ibs_op_ctl:\t%016llx MaxCnt %9d%s En %d Val %d CntCtl %d=%s CurCnt %9d\n", 87 reg.val, ((reg.opmaxcnt_ext << 16) | reg.opmaxcnt) << 4, l3_miss_only, 88 reg.op_en, reg.op_val, reg.cnt_ctl, 89 reg.cnt_ctl ? "uOps" : "cycles", reg.opcurcnt); 90 } 91 92 static void pr_ibs_op_data(union ibs_op_data reg) 93 { 94 printf("ibs_op_data:\t%016llx CompToRetCtr %5d TagToRetCtr %5d%s%s%s BrnRet %d " 95 " RipInvalid %d BrnFuse %d Microcode %d\n", 96 reg.val, reg.comp_to_ret_ctr, reg.tag_to_ret_ctr, 97 reg.op_brn_ret ? (reg.op_return ? " OpReturn 1" : " OpReturn 0") : "", 98 reg.op_brn_ret ? (reg.op_brn_taken ? " OpBrnTaken 1" : " OpBrnTaken 0") : "", 99 reg.op_brn_ret ? (reg.op_brn_misp ? " OpBrnMisp 1" : " OpBrnMisp 0") : "", 100 reg.op_brn_ret, reg.op_rip_invalid, reg.op_brn_fuse, reg.op_microcode); 101 } 102 103 static void pr_ibs_op_data2_extended(union ibs_op_data2 reg) 104 { 105 static const char * const data_src_str[] = { 106 "", 107 " DataSrc 1=Local L3 or other L1/L2 in CCX", 108 " DataSrc 2=Another CCX cache in the same NUMA node", 109 " DataSrc 3=DRAM", 110 " DataSrc 4=(reserved)", 111 " DataSrc 5=Another CCX cache in a different NUMA node", 112 " DataSrc 6=Long-latency DIMM", 113 " DataSrc 7=MMIO/Config/PCI/APIC", 114 " DataSrc 8=Extension Memory", 115 " DataSrc 9=(reserved)", 116 " DataSrc 10=(reserved)", 117 " DataSrc 11=(reserved)", 118 " DataSrc 12=Coherent Memory of a different processor type", 119 /* 13 to 31 are reserved. Avoid printing them. */ 120 }; 121 int data_src = (reg.data_src_hi << 3) | reg.data_src_lo; 122 123 printf("ibs_op_data2:\t%016llx %sRmtNode %d%s\n", reg.val, 124 (data_src == 1 || data_src == 2 || data_src == 5) ? 125 (reg.cache_hit_st ? "CacheHitSt 1=O-State " : "CacheHitSt 0=M-state ") : "", 126 reg.rmt_node, 127 data_src < (int)ARRAY_SIZE(data_src_str) ? data_src_str[data_src] : ""); 128 } 129 130 static void pr_ibs_op_data2_default(union ibs_op_data2 reg) 131 { 132 static const char * const data_src_str[] = { 133 "", 134 " DataSrc 1=(reserved)", 135 " DataSrc 2=Local node cache", 136 " DataSrc 3=DRAM", 137 " DataSrc 4=Remote node cache", 138 " DataSrc 5=(reserved)", 139 " DataSrc 6=(reserved)", 140 " DataSrc 7=Other" 141 }; 142 143 printf("ibs_op_data2:\t%016llx %sRmtNode %d%s\n", reg.val, 144 reg.data_src_lo == 2 ? (reg.cache_hit_st ? "CacheHitSt 1=O-State " 145 : "CacheHitSt 0=M-state ") : "", 146 reg.rmt_node, data_src_str[reg.data_src_lo]); 147 } 148 149 static void pr_ibs_op_data2(union ibs_op_data2 reg) 150 { 151 if (zen4_ibs_extensions) 152 return pr_ibs_op_data2_extended(reg); 153 pr_ibs_op_data2_default(reg); 154 } 155 156 static void pr_ibs_op_data3(union ibs_op_data3 reg) 157 { 158 char l2_miss_str[sizeof(" L2Miss _")] = ""; 159 char op_mem_width_str[sizeof(" OpMemWidth _____ bytes")] = ""; 160 char op_dc_miss_open_mem_reqs_str[sizeof(" OpDcMissOpenMemReqs __")] = ""; 161 162 /* 163 * Erratum #1293 164 * Ignore L2Miss and OpDcMissOpenMemReqs (and opdata2) if DcMissNoMabAlloc or SwPf set 165 */ 166 if (!(cpu_family == 0x19 && cpu_model < 0x10 && (reg.dc_miss_no_mab_alloc || reg.sw_pf))) { 167 snprintf(l2_miss_str, sizeof(l2_miss_str), " L2Miss %d", reg.l2_miss); 168 snprintf(op_dc_miss_open_mem_reqs_str, sizeof(op_dc_miss_open_mem_reqs_str), 169 " OpDcMissOpenMemReqs %2d", reg.op_dc_miss_open_mem_reqs); 170 } 171 172 if (reg.op_mem_width) 173 snprintf(op_mem_width_str, sizeof(op_mem_width_str), 174 " OpMemWidth %2d bytes", 1 << (reg.op_mem_width - 1)); 175 176 printf("ibs_op_data3:\t%016llx LdOp %d StOp %d DcL1TlbMiss %d DcL2TlbMiss %d " 177 "DcL1TlbHit2M %d DcL1TlbHit1G %d DcL2TlbHit2M %d DcMiss %d DcMisAcc %d " 178 "DcWcMemAcc %d DcUcMemAcc %d DcLockedOp %d DcMissNoMabAlloc %d DcLinAddrValid %d " 179 "DcPhyAddrValid %d DcL2TlbHit1G %d%s SwPf %d%s%s DcMissLat %5d TlbRefillLat %5d\n", 180 reg.val, reg.ld_op, reg.st_op, reg.dc_l1tlb_miss, reg.dc_l2tlb_miss, 181 reg.dc_l1tlb_hit_2m, reg.dc_l1tlb_hit_1g, reg.dc_l2tlb_hit_2m, reg.dc_miss, 182 reg.dc_mis_acc, reg.dc_wc_mem_acc, reg.dc_uc_mem_acc, reg.dc_locked_op, 183 reg.dc_miss_no_mab_alloc, reg.dc_lin_addr_valid, reg.dc_phy_addr_valid, 184 reg.dc_l2_tlb_hit_1g, l2_miss_str, reg.sw_pf, op_mem_width_str, 185 op_dc_miss_open_mem_reqs_str, reg.dc_miss_lat, reg.tlb_refill_lat); 186 } 187 188 /* 189 * IBS Op/Execution MSRs always saved, in order, are: 190 * IBS_OP_CTL, IBS_OP_RIP, IBS_OP_DATA, IBS_OP_DATA2, 191 * IBS_OP_DATA3, IBS_DC_LINADDR, IBS_DC_PHYSADDR, BP_IBSTGT_RIP 192 */ 193 static void amd_dump_ibs_op(struct perf_sample *sample) 194 { 195 struct perf_ibs_data *data = sample->raw_data; 196 union ibs_op_ctl *op_ctl = (union ibs_op_ctl *)data->data; 197 __u64 *rip = (__u64 *)op_ctl + 1; 198 union ibs_op_data *op_data = (union ibs_op_data *)(rip + 1); 199 union ibs_op_data3 *op_data3 = (union ibs_op_data3 *)(rip + 3); 200 201 pr_ibs_op_ctl(*op_ctl); 202 if (!op_data->op_rip_invalid) 203 printf("IbsOpRip:\t%016llx\n", *rip); 204 pr_ibs_op_data(*op_data); 205 /* 206 * Erratum #1293: ignore op_data2 if DcMissNoMabAlloc or SwPf are set 207 */ 208 if (!(cpu_family == 0x19 && cpu_model < 0x10 && 209 (op_data3->dc_miss_no_mab_alloc || op_data3->sw_pf))) 210 pr_ibs_op_data2(*(union ibs_op_data2 *)(rip + 2)); 211 pr_ibs_op_data3(*op_data3); 212 if (op_data3->dc_lin_addr_valid) 213 printf("IbsDCLinAd:\t%016llx\n", *(rip + 4)); 214 if (op_data3->dc_phy_addr_valid) 215 printf("IbsDCPhysAd:\t%016llx\n", *(rip + 5)); 216 if (op_data->op_brn_ret && *(rip + 6)) 217 printf("IbsBrTarget:\t%016llx\n", *(rip + 6)); 218 } 219 220 /* 221 * IBS Fetch MSRs always saved, in order, are: 222 * IBS_FETCH_CTL, IBS_FETCH_LINADDR, IBS_FETCH_PHYSADDR, IC_IBS_EXTD_CTL 223 */ 224 static void amd_dump_ibs_fetch(struct perf_sample *sample) 225 { 226 struct perf_ibs_data *data = sample->raw_data; 227 union ibs_fetch_ctl *fetch_ctl = (union ibs_fetch_ctl *)data->data; 228 __u64 *addr = (__u64 *)fetch_ctl + 1; 229 union ic_ibs_extd_ctl *extd_ctl = (union ic_ibs_extd_ctl *)addr + 2; 230 231 pr_ibs_fetch_ctl(*fetch_ctl); 232 printf("IbsFetchLinAd:\t%016llx\n", *addr++); 233 if (fetch_ctl->phy_addr_valid) 234 printf("IbsFetchPhysAd:\t%016llx\n", *addr); 235 pr_ic_ibs_extd_ctl(*extd_ctl); 236 } 237 238 /* 239 * Test for enable and valid bits in captured control MSRs. 240 */ 241 static bool is_valid_ibs_fetch_sample(struct perf_sample *sample) 242 { 243 struct perf_ibs_data *data = sample->raw_data; 244 union ibs_fetch_ctl *fetch_ctl = (union ibs_fetch_ctl *)data->data; 245 246 if (fetch_ctl->fetch_en && fetch_ctl->fetch_val) 247 return true; 248 249 return false; 250 } 251 252 static bool is_valid_ibs_op_sample(struct perf_sample *sample) 253 { 254 struct perf_ibs_data *data = sample->raw_data; 255 union ibs_op_ctl *op_ctl = (union ibs_op_ctl *)data->data; 256 257 if (op_ctl->op_en && op_ctl->op_val) 258 return true; 259 260 return false; 261 } 262 263 /* AMD vendor specific raw sample function. Check for PERF_RECORD_SAMPLE events 264 * and if the event was triggered by IBS, display its raw data with decoded text. 265 * The function is only invoked when the dump flag -D is set. 266 */ 267 void evlist__amd_sample_raw(struct evlist *evlist, union perf_event *event, 268 struct perf_sample *sample) 269 { 270 struct evsel *evsel; 271 272 if (event->header.type != PERF_RECORD_SAMPLE || !sample->raw_size) 273 return; 274 275 evsel = evlist__event2evsel(evlist, event); 276 if (!evsel) 277 return; 278 279 if (evsel->core.attr.type == ibs_fetch_type) { 280 if (!is_valid_ibs_fetch_sample(sample)) { 281 pr_debug("Invalid raw IBS Fetch MSR data encountered\n"); 282 return; 283 } 284 amd_dump_ibs_fetch(sample); 285 } else if (evsel->core.attr.type == ibs_op_type) { 286 if (!is_valid_ibs_op_sample(sample)) { 287 pr_debug("Invalid raw IBS Op MSR data encountered\n"); 288 return; 289 } 290 amd_dump_ibs_op(sample); 291 } 292 } 293 294 static void parse_cpuid(struct perf_env *env) 295 { 296 const char *cpuid; 297 int ret; 298 299 cpuid = perf_env__cpuid(env); 300 /* 301 * cpuid = "AuthenticAMD,family,model,stepping" 302 */ 303 ret = sscanf(cpuid, "%*[^,],%u,%u", &cpu_family, &cpu_model); 304 if (ret != 2) 305 pr_debug("problem parsing cpuid\n"); 306 } 307 308 /* 309 * Find and assign the type number used for ibs_op or ibs_fetch samples. 310 * Device names can be large - we are only interested in the first 9 characters, 311 * to match "ibs_fetch". 312 */ 313 bool evlist__has_amd_ibs(struct evlist *evlist) 314 { 315 struct perf_env *env = evlist->env; 316 int ret, nr_pmu_mappings = perf_env__nr_pmu_mappings(env); 317 const char *pmu_mapping = perf_env__pmu_mappings(env); 318 char name[sizeof("ibs_fetch")]; 319 u32 type; 320 321 while (nr_pmu_mappings--) { 322 ret = sscanf(pmu_mapping, "%u:%9s", &type, name); 323 if (ret == 2) { 324 if (strstarts(name, "ibs_op")) 325 ibs_op_type = type; 326 else if (strstarts(name, "ibs_fetch")) 327 ibs_fetch_type = type; 328 } 329 pmu_mapping += strlen(pmu_mapping) + 1 /* '\0' */; 330 } 331 332 if (perf_env__find_pmu_cap(env, "ibs_op", "zen4_ibs_extensions")) 333 zen4_ibs_extensions = 1; 334 335 if (ibs_fetch_type || ibs_op_type) { 336 if (!cpu_family) 337 parse_cpuid(env); 338 return true; 339 } 340 341 return false; 342 } 343