18296aa0fSIan Rogers[config] 28296aa0fSIan Rogerscommand = stat 38296aa0fSIan Rogersargs = -d kill >/dev/null 2>&1 48296aa0fSIan Rogersret = 1 58296aa0fSIan Rogers 68296aa0fSIan Rogers 78296aa0fSIan Rogers# PERF_TYPE_SOFTWARE / PERF_COUNT_SW_TASK_CLOCK 88296aa0fSIan Rogers[event1:base-stat] 98296aa0fSIan Rogersfd=1 108296aa0fSIan Rogerstype=1 118296aa0fSIan Rogersconfig=1 128296aa0fSIan Rogers 138296aa0fSIan Rogers# PERF_TYPE_SOFTWARE / PERF_COUNT_SW_CONTEXT_SWITCHES 148296aa0fSIan Rogers[event2:base-stat] 158296aa0fSIan Rogersfd=2 168296aa0fSIan Rogerstype=1 178296aa0fSIan Rogersconfig=3 188296aa0fSIan Rogers 198296aa0fSIan Rogers# PERF_TYPE_SOFTWARE / PERF_COUNT_SW_CPU_MIGRATIONS 208296aa0fSIan Rogers[event3:base-stat] 218296aa0fSIan Rogersfd=3 228296aa0fSIan Rogerstype=1 238296aa0fSIan Rogersconfig=4 248296aa0fSIan Rogers 258296aa0fSIan Rogers# PERF_TYPE_SOFTWARE / PERF_COUNT_SW_PAGE_FAULTS 268296aa0fSIan Rogers[event4:base-stat] 278296aa0fSIan Rogersfd=4 288296aa0fSIan Rogerstype=1 298296aa0fSIan Rogersconfig=2 308296aa0fSIan Rogers 318296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_CPU_CYCLES 328296aa0fSIan Rogers[event5:base-stat] 338296aa0fSIan Rogersfd=5 348296aa0fSIan Rogerstype=0 358296aa0fSIan Rogersconfig=0 368296aa0fSIan Rogersoptional=1 378296aa0fSIan Rogers 388296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_STALLED_CYCLES_FRONTEND 398296aa0fSIan Rogers[event6:base-stat] 408296aa0fSIan Rogersfd=6 418296aa0fSIan Rogerstype=0 428296aa0fSIan Rogersconfig=7 438296aa0fSIan Rogersoptional=1 448296aa0fSIan Rogers 458296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_STALLED_CYCLES_BACKEND 468296aa0fSIan Rogers[event7:base-stat] 478296aa0fSIan Rogersfd=7 488296aa0fSIan Rogerstype=0 498296aa0fSIan Rogersconfig=8 508296aa0fSIan Rogersoptional=1 518296aa0fSIan Rogers 528296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_INSTRUCTIONS 538296aa0fSIan Rogers[event8:base-stat] 548296aa0fSIan Rogersfd=8 558296aa0fSIan Rogerstype=0 568296aa0fSIan Rogersconfig=1 578296aa0fSIan Rogersoptional=1 588296aa0fSIan Rogers 598296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_BRANCH_INSTRUCTIONS 608296aa0fSIan Rogers[event9:base-stat] 618296aa0fSIan Rogersfd=9 628296aa0fSIan Rogerstype=0 638296aa0fSIan Rogersconfig=4 648296aa0fSIan Rogersoptional=1 658296aa0fSIan Rogers 668296aa0fSIan Rogers# PERF_TYPE_HARDWARE / PERF_COUNT_HW_BRANCH_MISSES 678296aa0fSIan Rogers[event10:base-stat] 688296aa0fSIan Rogersfd=10 698296aa0fSIan Rogerstype=0 708296aa0fSIan Rogersconfig=5 718296aa0fSIan Rogersoptional=1 728296aa0fSIan Rogers 738296aa0fSIan Rogers# PERF_TYPE_RAW / slots (0x400) 748296aa0fSIan Rogers[event11:base-stat] 758296aa0fSIan Rogersfd=11 768296aa0fSIan Rogersgroup_fd=-1 778296aa0fSIan Rogerstype=4 788296aa0fSIan Rogersconfig=1024 798296aa0fSIan Rogersread_format=15 808296aa0fSIan Rogersoptional=1 818296aa0fSIan Rogers 828296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-retiring (0x8000) 838296aa0fSIan Rogers[event12:base-stat] 848296aa0fSIan Rogersfd=12 858296aa0fSIan Rogersgroup_fd=11 868296aa0fSIan Rogerstype=4 878296aa0fSIan Rogersconfig=32768 888296aa0fSIan Rogersdisabled=0 898296aa0fSIan Rogersenable_on_exec=0 908296aa0fSIan Rogersread_format=15 918296aa0fSIan Rogersoptional=1 928296aa0fSIan Rogers 938296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-bad-spec (0x8100) 948296aa0fSIan Rogers[event13:base-stat] 958296aa0fSIan Rogersfd=13 968296aa0fSIan Rogersgroup_fd=11 978296aa0fSIan Rogerstype=4 988296aa0fSIan Rogersconfig=33024 998296aa0fSIan Rogersdisabled=0 1008296aa0fSIan Rogersenable_on_exec=0 1018296aa0fSIan Rogersread_format=15 1028296aa0fSIan Rogersoptional=1 1038296aa0fSIan Rogers 1048296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-fe-bound (0x8200) 1058296aa0fSIan Rogers[event14:base-stat] 1068296aa0fSIan Rogersfd=14 1078296aa0fSIan Rogersgroup_fd=11 1088296aa0fSIan Rogerstype=4 1098296aa0fSIan Rogersconfig=33280 1108296aa0fSIan Rogersdisabled=0 1118296aa0fSIan Rogersenable_on_exec=0 1128296aa0fSIan Rogersread_format=15 1138296aa0fSIan Rogersoptional=1 1148296aa0fSIan Rogers 1158296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-be-bound (0x8300) 1168296aa0fSIan Rogers[event15:base-stat] 1178296aa0fSIan Rogersfd=15 1188296aa0fSIan Rogersgroup_fd=11 1198296aa0fSIan Rogerstype=4 1208296aa0fSIan Rogersconfig=33536 1218296aa0fSIan Rogersdisabled=0 1228296aa0fSIan Rogersenable_on_exec=0 1238296aa0fSIan Rogersread_format=15 1248296aa0fSIan Rogersoptional=1 1258296aa0fSIan Rogers 1268296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-heavy-ops (0x8400) 1278296aa0fSIan Rogers[event16:base-stat] 1288296aa0fSIan Rogersfd=16 1298296aa0fSIan Rogersgroup_fd=11 1308296aa0fSIan Rogerstype=4 1318296aa0fSIan Rogersconfig=33792 1328296aa0fSIan Rogersdisabled=0 1338296aa0fSIan Rogersenable_on_exec=0 1348296aa0fSIan Rogersread_format=15 1358296aa0fSIan Rogersoptional=1 1368296aa0fSIan Rogers 1378296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-br-mispredict (0x8500) 1388296aa0fSIan Rogers[event17:base-stat] 1398296aa0fSIan Rogersfd=17 1408296aa0fSIan Rogersgroup_fd=11 1418296aa0fSIan Rogerstype=4 1428296aa0fSIan Rogersconfig=34048 1438296aa0fSIan Rogersdisabled=0 1448296aa0fSIan Rogersenable_on_exec=0 1458296aa0fSIan Rogersread_format=15 1468296aa0fSIan Rogersoptional=1 1478296aa0fSIan Rogers 1488296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-fetch-lat (0x8600) 1498296aa0fSIan Rogers[event18:base-stat] 1508296aa0fSIan Rogersfd=18 1518296aa0fSIan Rogersgroup_fd=11 1528296aa0fSIan Rogerstype=4 1538296aa0fSIan Rogersconfig=34304 1548296aa0fSIan Rogersdisabled=0 1558296aa0fSIan Rogersenable_on_exec=0 1568296aa0fSIan Rogersread_format=15 1578296aa0fSIan Rogersoptional=1 1588296aa0fSIan Rogers 1598296aa0fSIan Rogers# PERF_TYPE_RAW / topdown-mem-bound (0x8700) 1608296aa0fSIan Rogers[event19:base-stat] 1618296aa0fSIan Rogersfd=19 1628296aa0fSIan Rogersgroup_fd=11 1638296aa0fSIan Rogerstype=4 1648296aa0fSIan Rogersconfig=34560 1658296aa0fSIan Rogersdisabled=0 1668296aa0fSIan Rogersenable_on_exec=0 1678296aa0fSIan Rogersread_format=15 1688296aa0fSIan Rogersoptional=1 1698296aa0fSIan Rogers 1708296aa0fSIan Rogers# PERF_TYPE_RAW / INT_MISC.UOP_DROPPING 1718296aa0fSIan Rogers[event20:base-stat] 1728296aa0fSIan Rogersfd=20 1738296aa0fSIan Rogerstype=4 1748296aa0fSIan Rogersconfig=4109 1758296aa0fSIan Rogersoptional=1 1768296aa0fSIan Rogers 1778296aa0fSIan Rogers# PERF_TYPE_RAW / cpu/INT_MISC.RECOVERY_CYCLES,cmask=1,edge/ 1788296aa0fSIan Rogers[event21:base-stat] 1798296aa0fSIan Rogersfd=21 1808296aa0fSIan Rogerstype=4 1818296aa0fSIan Rogersconfig=17039629 1828296aa0fSIan Rogersoptional=1 1838296aa0fSIan Rogers 1848296aa0fSIan Rogers# PERF_TYPE_RAW / CPU_CLK_UNHALTED.THREAD 1858296aa0fSIan Rogers[event22:base-stat] 1868296aa0fSIan Rogersfd=22 1878296aa0fSIan Rogerstype=4 1888296aa0fSIan Rogersconfig=60 1898296aa0fSIan Rogersoptional=1 1908296aa0fSIan Rogers 1918296aa0fSIan Rogers# PERF_TYPE_RAW / INT_MISC.RECOVERY_CYCLES_ANY 1928296aa0fSIan Rogers[event23:base-stat] 1938296aa0fSIan Rogersfd=23 1948296aa0fSIan Rogerstype=4 1958296aa0fSIan Rogersconfig=2097421 1968296aa0fSIan Rogersoptional=1 1978296aa0fSIan Rogers 1988296aa0fSIan Rogers# PERF_TYPE_RAW / CPU_CLK_UNHALTED.REF_XCLK 1998296aa0fSIan Rogers[event24:base-stat] 2008296aa0fSIan Rogersfd=24 2018296aa0fSIan Rogerstype=4 2028296aa0fSIan Rogersconfig=316 2038296aa0fSIan Rogersoptional=1 2048296aa0fSIan Rogers 2058296aa0fSIan Rogers# PERF_TYPE_RAW / IDQ_UOPS_NOT_DELIVERED.CORE 2068296aa0fSIan Rogers[event25:base-stat] 2078296aa0fSIan Rogersfd=25 2088296aa0fSIan Rogerstype=4 2098296aa0fSIan Rogersconfig=412 2108296aa0fSIan Rogersoptional=1 2118296aa0fSIan Rogers 2128296aa0fSIan Rogers# PERF_TYPE_RAW / CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE 2138296aa0fSIan Rogers[event26:base-stat] 2148296aa0fSIan Rogersfd=26 2158296aa0fSIan Rogerstype=4 2168296aa0fSIan Rogersconfig=572 2178296aa0fSIan Rogersoptional=1 2188296aa0fSIan Rogers 2198296aa0fSIan Rogers# PERF_TYPE_RAW / UOPS_RETIRED.RETIRE_SLOTS 2208296aa0fSIan Rogers[event27:base-stat] 2218296aa0fSIan Rogersfd=27 2228296aa0fSIan Rogerstype=4 2238296aa0fSIan Rogersconfig=706 2248296aa0fSIan Rogersoptional=1 2258296aa0fSIan Rogers 2268296aa0fSIan Rogers# PERF_TYPE_RAW / UOPS_ISSUED.ANY 2278296aa0fSIan Rogers[event28:base-stat] 2288296aa0fSIan Rogersfd=28 2298296aa0fSIan Rogerstype=4 2308296aa0fSIan Rogersconfig=270 2318296aa0fSIan Rogersoptional=1 2328296aa0fSIan Rogers 2338296aa0fSIan Rogers# PERF_TYPE_HW_CACHE / 2348296aa0fSIan Rogers# PERF_COUNT_HW_CACHE_L1D << 0 | 2358296aa0fSIan Rogers# (PERF_COUNT_HW_CACHE_OP_READ << 8) | 2368296aa0fSIan Rogers# (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16) 2378296aa0fSIan Rogers[event29:base-stat] 2388296aa0fSIan Rogersfd=29 2398296aa0fSIan Rogerstype=3 2408296aa0fSIan Rogersconfig=0 2418296aa0fSIan Rogersoptional=1 2428296aa0fSIan Rogers 2438296aa0fSIan Rogers# PERF_TYPE_HW_CACHE / 2448296aa0fSIan Rogers# PERF_COUNT_HW_CACHE_L1D << 0 | 2458296aa0fSIan Rogers# (PERF_COUNT_HW_CACHE_OP_READ << 8) | 2468296aa0fSIan Rogers# (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) 2478296aa0fSIan Rogers[event30:base-stat] 2488296aa0fSIan Rogersfd=30 2498296aa0fSIan Rogerstype=3 2508296aa0fSIan Rogersconfig=65536 2518296aa0fSIan Rogersoptional=1 2528296aa0fSIan Rogers 2538296aa0fSIan Rogers# PERF_TYPE_HW_CACHE / 2548296aa0fSIan Rogers# PERF_COUNT_HW_CACHE_LL << 0 | 2558296aa0fSIan Rogers# (PERF_COUNT_HW_CACHE_OP_READ << 8) | 2568296aa0fSIan Rogers# (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16) 2578296aa0fSIan Rogers[event31:base-stat] 2588296aa0fSIan Rogersfd=31 2598296aa0fSIan Rogerstype=3 2608296aa0fSIan Rogersconfig=2 2618296aa0fSIan Rogersoptional=1 2628296aa0fSIan Rogers 2638296aa0fSIan Rogers# PERF_TYPE_HW_CACHE, 2648296aa0fSIan Rogers# PERF_COUNT_HW_CACHE_LL << 0 | 2658296aa0fSIan Rogers# (PERF_COUNT_HW_CACHE_OP_READ << 8) | 2668296aa0fSIan Rogers# (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) 2678296aa0fSIan Rogers[event32:base-stat] 2688296aa0fSIan Rogersfd=32 2698296aa0fSIan Rogerstype=3 2708296aa0fSIan Rogersconfig=65538 2718296aa0fSIan Rogersoptional=1 272*0e9e7bc1STrevor Allison 273*0e9e7bc1STrevor Allison# PERF_TYPE_RAW / INT_MISC.UOP_DROPPING 274*0e9e7bc1STrevor Allison[event33:base-stat] 275*0e9e7bc1STrevor Allisonfd=33 276*0e9e7bc1STrevor Allisontype=4 277*0e9e7bc1STrevor Allisonconfig=4269 278*0e9e7bc1STrevor Allisonoptional=1