1[ 2 { 3 "BriefDescription": "DTLB load misses", 4 "Counter": "0,1,2,3", 5 "EventCode": "0x8", 6 "EventName": "DTLB_LOAD_MISSES.ANY", 7 "SampleAfterValue": "200000", 8 "UMask": "0x1" 9 }, 10 { 11 "BriefDescription": "DTLB load miss large page walks", 12 "Counter": "0,1,2,3", 13 "EventCode": "0x8", 14 "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", 15 "SampleAfterValue": "200000", 16 "UMask": "0x80" 17 }, 18 { 19 "BriefDescription": "DTLB load miss caused by low part of address", 20 "Counter": "0,1,2,3", 21 "EventCode": "0x8", 22 "EventName": "DTLB_LOAD_MISSES.PDE_MISS", 23 "SampleAfterValue": "200000", 24 "UMask": "0x20" 25 }, 26 { 27 "BriefDescription": "DTLB second level hit", 28 "Counter": "0,1,2,3", 29 "EventCode": "0x8", 30 "EventName": "DTLB_LOAD_MISSES.STLB_HIT", 31 "SampleAfterValue": "2000000", 32 "UMask": "0x10" 33 }, 34 { 35 "BriefDescription": "DTLB load miss page walks complete", 36 "Counter": "0,1,2,3", 37 "EventCode": "0x8", 38 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", 39 "SampleAfterValue": "200000", 40 "UMask": "0x2" 41 }, 42 { 43 "BriefDescription": "DTLB load miss page walk cycles", 44 "Counter": "0,1,2,3", 45 "EventCode": "0x8", 46 "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", 47 "SampleAfterValue": "200000", 48 "UMask": "0x4" 49 }, 50 { 51 "BriefDescription": "DTLB misses", 52 "Counter": "0,1,2,3", 53 "EventCode": "0x49", 54 "EventName": "DTLB_MISSES.ANY", 55 "SampleAfterValue": "200000", 56 "UMask": "0x1" 57 }, 58 { 59 "BriefDescription": "DTLB miss large page walks", 60 "Counter": "0,1,2,3", 61 "EventCode": "0x49", 62 "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", 63 "SampleAfterValue": "200000", 64 "UMask": "0x80" 65 }, 66 { 67 "BriefDescription": "DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE.", 68 "Counter": "0,1,2,3", 69 "EventCode": "0x49", 70 "EventName": "DTLB_MISSES.PDE_MISS", 71 "SampleAfterValue": "200000", 72 "UMask": "0x20" 73 }, 74 { 75 "BriefDescription": "DTLB first level misses but second level hit", 76 "Counter": "0,1,2,3", 77 "EventCode": "0x49", 78 "EventName": "DTLB_MISSES.STLB_HIT", 79 "SampleAfterValue": "200000", 80 "UMask": "0x10" 81 }, 82 { 83 "BriefDescription": "DTLB miss page walks", 84 "Counter": "0,1,2,3", 85 "EventCode": "0x49", 86 "EventName": "DTLB_MISSES.WALK_COMPLETED", 87 "SampleAfterValue": "200000", 88 "UMask": "0x2" 89 }, 90 { 91 "BriefDescription": "DTLB miss page walk cycles", 92 "Counter": "0,1,2,3", 93 "EventCode": "0x49", 94 "EventName": "DTLB_MISSES.WALK_CYCLES", 95 "SampleAfterValue": "2000000", 96 "UMask": "0x4" 97 }, 98 { 99 "BriefDescription": "Extended Page Table walk cycles", 100 "Counter": "0,1,2,3", 101 "EventCode": "0x4F", 102 "EventName": "EPT.WALK_CYCLES", 103 "SampleAfterValue": "2000000", 104 "UMask": "0x10" 105 }, 106 { 107 "BriefDescription": "ITLB flushes", 108 "Counter": "0,1,2,3", 109 "EventCode": "0xAE", 110 "EventName": "ITLB_FLUSH", 111 "SampleAfterValue": "2000000", 112 "UMask": "0x1" 113 }, 114 { 115 "BriefDescription": "ITLB miss", 116 "Counter": "0,1,2,3", 117 "EventCode": "0x85", 118 "EventName": "ITLB_MISSES.ANY", 119 "SampleAfterValue": "200000", 120 "UMask": "0x1" 121 }, 122 { 123 "BriefDescription": "ITLB miss large page walks", 124 "Counter": "0,1,2,3", 125 "EventCode": "0x85", 126 "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED", 127 "SampleAfterValue": "200000", 128 "UMask": "0x80" 129 }, 130 { 131 "BriefDescription": "ITLB miss page walks", 132 "Counter": "0,1,2,3", 133 "EventCode": "0x85", 134 "EventName": "ITLB_MISSES.WALK_COMPLETED", 135 "SampleAfterValue": "200000", 136 "UMask": "0x2" 137 }, 138 { 139 "BriefDescription": "ITLB miss page walk cycles", 140 "Counter": "0,1,2,3", 141 "EventCode": "0x85", 142 "EventName": "ITLB_MISSES.WALK_CYCLES", 143 "SampleAfterValue": "2000000", 144 "UMask": "0x4" 145 }, 146 { 147 "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)", 148 "Counter": "0,1,2,3", 149 "EventCode": "0xC8", 150 "EventName": "ITLB_MISS_RETIRED", 151 "PEBS": "1", 152 "SampleAfterValue": "200000", 153 "UMask": "0x20" 154 }, 155 { 156 "BriefDescription": "Retired loads that miss the DTLB (Precise Event)", 157 "Counter": "0,1,2,3", 158 "EventCode": "0xCB", 159 "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", 160 "PEBS": "1", 161 "SampleAfterValue": "200000", 162 "UMask": "0x80" 163 }, 164 { 165 "BriefDescription": "Retired stores that miss the DTLB (Precise Event)", 166 "Counter": "0,1,2,3", 167 "EventCode": "0xC", 168 "EventName": "MEM_STORE_RETIRED.DTLB_MISS", 169 "PEBS": "1", 170 "SampleAfterValue": "200000", 171 "UMask": "0x1" 172 } 173] 174