1[ 2 { 3 "BriefDescription": "DTLB load misses", 4 "EventCode": "0x8", 5 "EventName": "DTLB_LOAD_MISSES.ANY", 6 "SampleAfterValue": "200000", 7 "UMask": "0x1" 8 }, 9 { 10 "BriefDescription": "DTLB load miss caused by low part of address", 11 "EventCode": "0x8", 12 "EventName": "DTLB_LOAD_MISSES.PDE_MISS", 13 "SampleAfterValue": "200000", 14 "UMask": "0x20" 15 }, 16 { 17 "BriefDescription": "DTLB second level hit", 18 "EventCode": "0x8", 19 "EventName": "DTLB_LOAD_MISSES.STLB_HIT", 20 "SampleAfterValue": "2000000", 21 "UMask": "0x10" 22 }, 23 { 24 "BriefDescription": "DTLB load miss page walks complete", 25 "EventCode": "0x8", 26 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", 27 "SampleAfterValue": "200000", 28 "UMask": "0x2" 29 }, 30 { 31 "BriefDescription": "DTLB load miss page walk cycles", 32 "EventCode": "0x8", 33 "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", 34 "SampleAfterValue": "200000", 35 "UMask": "0x4" 36 }, 37 { 38 "BriefDescription": "DTLB misses", 39 "EventCode": "0x49", 40 "EventName": "DTLB_MISSES.ANY", 41 "SampleAfterValue": "200000", 42 "UMask": "0x1" 43 }, 44 { 45 "BriefDescription": "DTLB miss large page walks", 46 "EventCode": "0x49", 47 "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", 48 "SampleAfterValue": "200000", 49 "UMask": "0x80" 50 }, 51 { 52 "BriefDescription": "DTLB first level misses but second level hit", 53 "EventCode": "0x49", 54 "EventName": "DTLB_MISSES.STLB_HIT", 55 "SampleAfterValue": "200000", 56 "UMask": "0x10" 57 }, 58 { 59 "BriefDescription": "DTLB miss page walks", 60 "EventCode": "0x49", 61 "EventName": "DTLB_MISSES.WALK_COMPLETED", 62 "SampleAfterValue": "200000", 63 "UMask": "0x2" 64 }, 65 { 66 "BriefDescription": "DTLB miss page walk cycles", 67 "EventCode": "0x49", 68 "EventName": "DTLB_MISSES.WALK_CYCLES", 69 "SampleAfterValue": "2000000", 70 "UMask": "0x4" 71 }, 72 { 73 "BriefDescription": "Extended Page Table walk cycles", 74 "EventCode": "0x4F", 75 "EventName": "EPT.WALK_CYCLES", 76 "SampleAfterValue": "2000000", 77 "UMask": "0x10" 78 }, 79 { 80 "BriefDescription": "ITLB flushes", 81 "EventCode": "0xAE", 82 "EventName": "ITLB_FLUSH", 83 "SampleAfterValue": "2000000", 84 "UMask": "0x1" 85 }, 86 { 87 "BriefDescription": "ITLB miss", 88 "EventCode": "0x85", 89 "EventName": "ITLB_MISSES.ANY", 90 "SampleAfterValue": "200000", 91 "UMask": "0x1" 92 }, 93 { 94 "BriefDescription": "ITLB miss page walks", 95 "EventCode": "0x85", 96 "EventName": "ITLB_MISSES.WALK_COMPLETED", 97 "SampleAfterValue": "200000", 98 "UMask": "0x2" 99 }, 100 { 101 "BriefDescription": "ITLB miss page walk cycles", 102 "EventCode": "0x85", 103 "EventName": "ITLB_MISSES.WALK_CYCLES", 104 "SampleAfterValue": "2000000", 105 "UMask": "0x4" 106 }, 107 { 108 "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)", 109 "EventCode": "0xC8", 110 "EventName": "ITLB_MISS_RETIRED", 111 "PEBS": "1", 112 "SampleAfterValue": "200000", 113 "UMask": "0x20" 114 }, 115 { 116 "BriefDescription": "Retired loads that miss the DTLB (Precise Event)", 117 "EventCode": "0xCB", 118 "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", 119 "PEBS": "1", 120 "SampleAfterValue": "200000", 121 "UMask": "0x80" 122 }, 123 { 124 "BriefDescription": "Retired stores that miss the DTLB (Precise Event)", 125 "EventCode": "0xC", 126 "EventName": "MEM_STORE_RETIRED.DTLB_MISS", 127 "PEBS": "1", 128 "SampleAfterValue": "200000", 129 "UMask": "0x1" 130 } 131] 132