1[ 2 { 3 "BriefDescription": "DTLB load misses", 4 "Counter": "0,1,2,3", 5 "EventCode": "0x8", 6 "EventName": "DTLB_LOAD_MISSES.ANY", 7 "SampleAfterValue": "200000", 8 "UMask": "0x1" 9 }, 10 { 11 "BriefDescription": "DTLB load miss caused by low part of address", 12 "Counter": "0,1,2,3", 13 "EventCode": "0x8", 14 "EventName": "DTLB_LOAD_MISSES.PDE_MISS", 15 "SampleAfterValue": "200000", 16 "UMask": "0x20" 17 }, 18 { 19 "BriefDescription": "DTLB second level hit", 20 "Counter": "0,1,2,3", 21 "EventCode": "0x8", 22 "EventName": "DTLB_LOAD_MISSES.STLB_HIT", 23 "SampleAfterValue": "2000000", 24 "UMask": "0x10" 25 }, 26 { 27 "BriefDescription": "DTLB load miss page walks complete", 28 "Counter": "0,1,2,3", 29 "EventCode": "0x8", 30 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", 31 "SampleAfterValue": "200000", 32 "UMask": "0x2" 33 }, 34 { 35 "BriefDescription": "DTLB load miss page walk cycles", 36 "Counter": "0,1,2,3", 37 "EventCode": "0x8", 38 "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", 39 "SampleAfterValue": "200000", 40 "UMask": "0x4" 41 }, 42 { 43 "BriefDescription": "DTLB misses", 44 "Counter": "0,1,2,3", 45 "EventCode": "0x49", 46 "EventName": "DTLB_MISSES.ANY", 47 "SampleAfterValue": "200000", 48 "UMask": "0x1" 49 }, 50 { 51 "BriefDescription": "DTLB miss large page walks", 52 "Counter": "0,1,2,3", 53 "EventCode": "0x49", 54 "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", 55 "SampleAfterValue": "200000", 56 "UMask": "0x80" 57 }, 58 { 59 "BriefDescription": "DTLB first level misses but second level hit", 60 "Counter": "0,1,2,3", 61 "EventCode": "0x49", 62 "EventName": "DTLB_MISSES.STLB_HIT", 63 "SampleAfterValue": "200000", 64 "UMask": "0x10" 65 }, 66 { 67 "BriefDescription": "DTLB miss page walks", 68 "Counter": "0,1,2,3", 69 "EventCode": "0x49", 70 "EventName": "DTLB_MISSES.WALK_COMPLETED", 71 "SampleAfterValue": "200000", 72 "UMask": "0x2" 73 }, 74 { 75 "BriefDescription": "DTLB miss page walk cycles", 76 "Counter": "0,1,2,3", 77 "EventCode": "0x49", 78 "EventName": "DTLB_MISSES.WALK_CYCLES", 79 "SampleAfterValue": "2000000", 80 "UMask": "0x4" 81 }, 82 { 83 "BriefDescription": "Extended Page Table walk cycles", 84 "Counter": "0,1,2,3", 85 "EventCode": "0x4F", 86 "EventName": "EPT.WALK_CYCLES", 87 "SampleAfterValue": "2000000", 88 "UMask": "0x10" 89 }, 90 { 91 "BriefDescription": "ITLB flushes", 92 "Counter": "0,1,2,3", 93 "EventCode": "0xAE", 94 "EventName": "ITLB_FLUSH", 95 "SampleAfterValue": "2000000", 96 "UMask": "0x1" 97 }, 98 { 99 "BriefDescription": "ITLB miss", 100 "Counter": "0,1,2,3", 101 "EventCode": "0x85", 102 "EventName": "ITLB_MISSES.ANY", 103 "SampleAfterValue": "200000", 104 "UMask": "0x1" 105 }, 106 { 107 "BriefDescription": "ITLB miss page walks", 108 "Counter": "0,1,2,3", 109 "EventCode": "0x85", 110 "EventName": "ITLB_MISSES.WALK_COMPLETED", 111 "SampleAfterValue": "200000", 112 "UMask": "0x2" 113 }, 114 { 115 "BriefDescription": "ITLB miss page walk cycles", 116 "Counter": "0,1,2,3", 117 "EventCode": "0x85", 118 "EventName": "ITLB_MISSES.WALK_CYCLES", 119 "SampleAfterValue": "2000000", 120 "UMask": "0x4" 121 }, 122 { 123 "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)", 124 "Counter": "0,1,2,3", 125 "EventCode": "0xC8", 126 "EventName": "ITLB_MISS_RETIRED", 127 "PEBS": "1", 128 "SampleAfterValue": "200000", 129 "UMask": "0x20" 130 }, 131 { 132 "BriefDescription": "Retired loads that miss the DTLB (Precise Event)", 133 "Counter": "0,1,2,3", 134 "EventCode": "0xCB", 135 "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", 136 "PEBS": "1", 137 "SampleAfterValue": "200000", 138 "UMask": "0x80" 139 }, 140 { 141 "BriefDescription": "Retired stores that miss the DTLB (Precise Event)", 142 "Counter": "0,1,2,3", 143 "EventCode": "0xC", 144 "EventName": "MEM_STORE_RETIRED.DTLB_MISS", 145 "PEBS": "1", 146 "SampleAfterValue": "200000", 147 "UMask": "0x1" 148 } 149] 150