1[ 2 { 3 "BriefDescription": "Cycles L1D locked", 4 "Counter": "0,1", 5 "EventCode": "0x63", 6 "EventName": "CACHE_LOCK_CYCLES.L1D", 7 "SampleAfterValue": "2000000", 8 "UMask": "0x2" 9 }, 10 { 11 "BriefDescription": "Cycles L1D and L2 locked", 12 "Counter": "0,1", 13 "EventCode": "0x63", 14 "EventName": "CACHE_LOCK_CYCLES.L1D_L2", 15 "SampleAfterValue": "2000000", 16 "UMask": "0x1" 17 }, 18 { 19 "BriefDescription": "L1D cache lines replaced in M state", 20 "Counter": "0,1", 21 "EventCode": "0x51", 22 "EventName": "L1D.M_EVICT", 23 "SampleAfterValue": "2000000", 24 "UMask": "0x4" 25 }, 26 { 27 "BriefDescription": "L1D cache lines allocated in the M state", 28 "Counter": "0,1", 29 "EventCode": "0x51", 30 "EventName": "L1D.M_REPL", 31 "SampleAfterValue": "2000000", 32 "UMask": "0x2" 33 }, 34 { 35 "BriefDescription": "L1D snoop eviction of cache lines in M state", 36 "Counter": "0,1", 37 "EventCode": "0x51", 38 "EventName": "L1D.M_SNOOP_EVICT", 39 "SampleAfterValue": "2000000", 40 "UMask": "0x8" 41 }, 42 { 43 "BriefDescription": "L1 data cache lines allocated", 44 "Counter": "0,1", 45 "EventCode": "0x51", 46 "EventName": "L1D.REPL", 47 "SampleAfterValue": "2000000", 48 "UMask": "0x1" 49 }, 50 { 51 "BriefDescription": "L1D prefetch load lock accepted in fill buffer", 52 "Counter": "0,1", 53 "EventCode": "0x52", 54 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", 55 "SampleAfterValue": "2000000", 56 "UMask": "0x1" 57 }, 58 { 59 "BriefDescription": "L1D hardware prefetch misses", 60 "Counter": "0,1", 61 "EventCode": "0x4E", 62 "EventName": "L1D_PREFETCH.MISS", 63 "SampleAfterValue": "200000", 64 "UMask": "0x2" 65 }, 66 { 67 "BriefDescription": "L1D hardware prefetch requests", 68 "Counter": "0,1", 69 "EventCode": "0x4E", 70 "EventName": "L1D_PREFETCH.REQUESTS", 71 "SampleAfterValue": "200000", 72 "UMask": "0x1" 73 }, 74 { 75 "BriefDescription": "L1D hardware prefetch requests triggered", 76 "Counter": "0,1", 77 "EventCode": "0x4E", 78 "EventName": "L1D_PREFETCH.TRIGGERS", 79 "SampleAfterValue": "200000", 80 "UMask": "0x4" 81 }, 82 { 83 "BriefDescription": "L1 writebacks to L2 in E state", 84 "Counter": "0,1,2,3", 85 "EventCode": "0x28", 86 "EventName": "L1D_WB_L2.E_STATE", 87 "SampleAfterValue": "100000", 88 "UMask": "0x4" 89 }, 90 { 91 "BriefDescription": "L1 writebacks to L2 in I state (misses)", 92 "Counter": "0,1,2,3", 93 "EventCode": "0x28", 94 "EventName": "L1D_WB_L2.I_STATE", 95 "SampleAfterValue": "100000", 96 "UMask": "0x1" 97 }, 98 { 99 "BriefDescription": "All L1 writebacks to L2", 100 "Counter": "0,1,2,3", 101 "EventCode": "0x28", 102 "EventName": "L1D_WB_L2.MESI", 103 "SampleAfterValue": "100000", 104 "UMask": "0xf" 105 }, 106 { 107 "BriefDescription": "L1 writebacks to L2 in M state", 108 "Counter": "0,1,2,3", 109 "EventCode": "0x28", 110 "EventName": "L1D_WB_L2.M_STATE", 111 "SampleAfterValue": "100000", 112 "UMask": "0x8" 113 }, 114 { 115 "BriefDescription": "L1 writebacks to L2 in S state", 116 "Counter": "0,1,2,3", 117 "EventCode": "0x28", 118 "EventName": "L1D_WB_L2.S_STATE", 119 "SampleAfterValue": "100000", 120 "UMask": "0x2" 121 }, 122 { 123 "BriefDescription": "All L2 data requests", 124 "Counter": "0,1,2,3", 125 "EventCode": "0x26", 126 "EventName": "L2_DATA_RQSTS.ANY", 127 "SampleAfterValue": "200000", 128 "UMask": "0xff" 129 }, 130 { 131 "BriefDescription": "L2 data demand loads in E state", 132 "Counter": "0,1,2,3", 133 "EventCode": "0x26", 134 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", 135 "SampleAfterValue": "200000", 136 "UMask": "0x4" 137 }, 138 { 139 "BriefDescription": "L2 data demand loads in I state (misses)", 140 "Counter": "0,1,2,3", 141 "EventCode": "0x26", 142 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", 143 "SampleAfterValue": "200000", 144 "UMask": "0x1" 145 }, 146 { 147 "BriefDescription": "L2 data demand requests", 148 "Counter": "0,1,2,3", 149 "EventCode": "0x26", 150 "EventName": "L2_DATA_RQSTS.DEMAND.MESI", 151 "SampleAfterValue": "200000", 152 "UMask": "0xf" 153 }, 154 { 155 "BriefDescription": "L2 data demand loads in M state", 156 "Counter": "0,1,2,3", 157 "EventCode": "0x26", 158 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", 159 "SampleAfterValue": "200000", 160 "UMask": "0x8" 161 }, 162 { 163 "BriefDescription": "L2 data demand loads in S state", 164 "Counter": "0,1,2,3", 165 "EventCode": "0x26", 166 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", 167 "SampleAfterValue": "200000", 168 "UMask": "0x2" 169 }, 170 { 171 "BriefDescription": "L2 data prefetches in E state", 172 "Counter": "0,1,2,3", 173 "EventCode": "0x26", 174 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", 175 "SampleAfterValue": "200000", 176 "UMask": "0x40" 177 }, 178 { 179 "BriefDescription": "L2 data prefetches in the I state (misses)", 180 "Counter": "0,1,2,3", 181 "EventCode": "0x26", 182 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", 183 "SampleAfterValue": "200000", 184 "UMask": "0x10" 185 }, 186 { 187 "BriefDescription": "All L2 data prefetches", 188 "Counter": "0,1,2,3", 189 "EventCode": "0x26", 190 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", 191 "SampleAfterValue": "200000", 192 "UMask": "0xf0" 193 }, 194 { 195 "BriefDescription": "L2 data prefetches in M state", 196 "Counter": "0,1,2,3", 197 "EventCode": "0x26", 198 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", 199 "SampleAfterValue": "200000", 200 "UMask": "0x80" 201 }, 202 { 203 "BriefDescription": "L2 data prefetches in the S state", 204 "Counter": "0,1,2,3", 205 "EventCode": "0x26", 206 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", 207 "SampleAfterValue": "200000", 208 "UMask": "0x20" 209 }, 210 { 211 "BriefDescription": "L2 lines allocated", 212 "Counter": "0,1,2,3", 213 "EventCode": "0xF1", 214 "EventName": "L2_LINES_IN.ANY", 215 "SampleAfterValue": "100000", 216 "UMask": "0x7" 217 }, 218 { 219 "BriefDescription": "L2 lines allocated in the E state", 220 "Counter": "0,1,2,3", 221 "EventCode": "0xF1", 222 "EventName": "L2_LINES_IN.E_STATE", 223 "SampleAfterValue": "100000", 224 "UMask": "0x4" 225 }, 226 { 227 "BriefDescription": "L2 lines allocated in the S state", 228 "Counter": "0,1,2,3", 229 "EventCode": "0xF1", 230 "EventName": "L2_LINES_IN.S_STATE", 231 "SampleAfterValue": "100000", 232 "UMask": "0x2" 233 }, 234 { 235 "BriefDescription": "L2 lines evicted", 236 "Counter": "0,1,2,3", 237 "EventCode": "0xF2", 238 "EventName": "L2_LINES_OUT.ANY", 239 "SampleAfterValue": "100000", 240 "UMask": "0xf" 241 }, 242 { 243 "BriefDescription": "L2 lines evicted by a demand request", 244 "Counter": "0,1,2,3", 245 "EventCode": "0xF2", 246 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 247 "SampleAfterValue": "100000", 248 "UMask": "0x1" 249 }, 250 { 251 "BriefDescription": "L2 modified lines evicted by a demand request", 252 "Counter": "0,1,2,3", 253 "EventCode": "0xF2", 254 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 255 "SampleAfterValue": "100000", 256 "UMask": "0x2" 257 }, 258 { 259 "BriefDescription": "L2 lines evicted by a prefetch request", 260 "Counter": "0,1,2,3", 261 "EventCode": "0xF2", 262 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", 263 "SampleAfterValue": "100000", 264 "UMask": "0x4" 265 }, 266 { 267 "BriefDescription": "L2 modified lines evicted by a prefetch request", 268 "Counter": "0,1,2,3", 269 "EventCode": "0xF2", 270 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", 271 "SampleAfterValue": "100000", 272 "UMask": "0x8" 273 }, 274 { 275 "BriefDescription": "L2 instruction fetches", 276 "Counter": "0,1,2,3", 277 "EventCode": "0x24", 278 "EventName": "L2_RQSTS.IFETCHES", 279 "SampleAfterValue": "200000", 280 "UMask": "0x30" 281 }, 282 { 283 "BriefDescription": "L2 instruction fetch hits", 284 "Counter": "0,1,2,3", 285 "EventCode": "0x24", 286 "EventName": "L2_RQSTS.IFETCH_HIT", 287 "SampleAfterValue": "200000", 288 "UMask": "0x10" 289 }, 290 { 291 "BriefDescription": "L2 instruction fetch misses", 292 "Counter": "0,1,2,3", 293 "EventCode": "0x24", 294 "EventName": "L2_RQSTS.IFETCH_MISS", 295 "SampleAfterValue": "200000", 296 "UMask": "0x20" 297 }, 298 { 299 "BriefDescription": "L2 load hits", 300 "Counter": "0,1,2,3", 301 "EventCode": "0x24", 302 "EventName": "L2_RQSTS.LD_HIT", 303 "SampleAfterValue": "200000", 304 "UMask": "0x1" 305 }, 306 { 307 "BriefDescription": "L2 load misses", 308 "Counter": "0,1,2,3", 309 "EventCode": "0x24", 310 "EventName": "L2_RQSTS.LD_MISS", 311 "SampleAfterValue": "200000", 312 "UMask": "0x2" 313 }, 314 { 315 "BriefDescription": "L2 requests", 316 "Counter": "0,1,2,3", 317 "EventCode": "0x24", 318 "EventName": "L2_RQSTS.LOADS", 319 "SampleAfterValue": "200000", 320 "UMask": "0x3" 321 }, 322 { 323 "BriefDescription": "All L2 misses", 324 "Counter": "0,1,2,3", 325 "EventCode": "0x24", 326 "EventName": "L2_RQSTS.MISS", 327 "SampleAfterValue": "200000", 328 "UMask": "0xaa" 329 }, 330 { 331 "BriefDescription": "All L2 prefetches", 332 "Counter": "0,1,2,3", 333 "EventCode": "0x24", 334 "EventName": "L2_RQSTS.PREFETCHES", 335 "SampleAfterValue": "200000", 336 "UMask": "0xc0" 337 }, 338 { 339 "BriefDescription": "L2 prefetch hits", 340 "Counter": "0,1,2,3", 341 "EventCode": "0x24", 342 "EventName": "L2_RQSTS.PREFETCH_HIT", 343 "SampleAfterValue": "200000", 344 "UMask": "0x40" 345 }, 346 { 347 "BriefDescription": "L2 prefetch misses", 348 "Counter": "0,1,2,3", 349 "EventCode": "0x24", 350 "EventName": "L2_RQSTS.PREFETCH_MISS", 351 "SampleAfterValue": "200000", 352 "UMask": "0x80" 353 }, 354 { 355 "BriefDescription": "All L2 requests", 356 "Counter": "0,1,2,3", 357 "EventCode": "0x24", 358 "EventName": "L2_RQSTS.REFERENCES", 359 "SampleAfterValue": "200000", 360 "UMask": "0xff" 361 }, 362 { 363 "BriefDescription": "L2 RFO requests", 364 "Counter": "0,1,2,3", 365 "EventCode": "0x24", 366 "EventName": "L2_RQSTS.RFOS", 367 "SampleAfterValue": "200000", 368 "UMask": "0xc" 369 }, 370 { 371 "BriefDescription": "L2 RFO hits", 372 "Counter": "0,1,2,3", 373 "EventCode": "0x24", 374 "EventName": "L2_RQSTS.RFO_HIT", 375 "SampleAfterValue": "200000", 376 "UMask": "0x4" 377 }, 378 { 379 "BriefDescription": "L2 RFO misses", 380 "Counter": "0,1,2,3", 381 "EventCode": "0x24", 382 "EventName": "L2_RQSTS.RFO_MISS", 383 "SampleAfterValue": "200000", 384 "UMask": "0x8" 385 }, 386 { 387 "BriefDescription": "All L2 transactions", 388 "Counter": "0,1,2,3", 389 "EventCode": "0xF0", 390 "EventName": "L2_TRANSACTIONS.ANY", 391 "SampleAfterValue": "200000", 392 "UMask": "0x80" 393 }, 394 { 395 "BriefDescription": "L2 fill transactions", 396 "Counter": "0,1,2,3", 397 "EventCode": "0xF0", 398 "EventName": "L2_TRANSACTIONS.FILL", 399 "SampleAfterValue": "200000", 400 "UMask": "0x20" 401 }, 402 { 403 "BriefDescription": "L2 instruction fetch transactions", 404 "Counter": "0,1,2,3", 405 "EventCode": "0xF0", 406 "EventName": "L2_TRANSACTIONS.IFETCH", 407 "SampleAfterValue": "200000", 408 "UMask": "0x4" 409 }, 410 { 411 "BriefDescription": "L1D writeback to L2 transactions", 412 "Counter": "0,1,2,3", 413 "EventCode": "0xF0", 414 "EventName": "L2_TRANSACTIONS.L1D_WB", 415 "SampleAfterValue": "200000", 416 "UMask": "0x10" 417 }, 418 { 419 "BriefDescription": "L2 Load transactions", 420 "Counter": "0,1,2,3", 421 "EventCode": "0xF0", 422 "EventName": "L2_TRANSACTIONS.LOAD", 423 "SampleAfterValue": "200000", 424 "UMask": "0x1" 425 }, 426 { 427 "BriefDescription": "L2 prefetch transactions", 428 "Counter": "0,1,2,3", 429 "EventCode": "0xF0", 430 "EventName": "L2_TRANSACTIONS.PREFETCH", 431 "SampleAfterValue": "200000", 432 "UMask": "0x8" 433 }, 434 { 435 "BriefDescription": "L2 RFO transactions", 436 "Counter": "0,1,2,3", 437 "EventCode": "0xF0", 438 "EventName": "L2_TRANSACTIONS.RFO", 439 "SampleAfterValue": "200000", 440 "UMask": "0x2" 441 }, 442 { 443 "BriefDescription": "L2 writeback to LLC transactions", 444 "Counter": "0,1,2,3", 445 "EventCode": "0xF0", 446 "EventName": "L2_TRANSACTIONS.WB", 447 "SampleAfterValue": "200000", 448 "UMask": "0x40" 449 }, 450 { 451 "BriefDescription": "L2 demand lock RFOs in E state", 452 "Counter": "0,1,2,3", 453 "EventCode": "0x27", 454 "EventName": "L2_WRITE.LOCK.E_STATE", 455 "SampleAfterValue": "100000", 456 "UMask": "0x40" 457 }, 458 { 459 "BriefDescription": "All demand L2 lock RFOs that hit the cache", 460 "Counter": "0,1,2,3", 461 "EventCode": "0x27", 462 "EventName": "L2_WRITE.LOCK.HIT", 463 "SampleAfterValue": "100000", 464 "UMask": "0xe0" 465 }, 466 { 467 "BriefDescription": "L2 demand lock RFOs in I state (misses)", 468 "Counter": "0,1,2,3", 469 "EventCode": "0x27", 470 "EventName": "L2_WRITE.LOCK.I_STATE", 471 "SampleAfterValue": "100000", 472 "UMask": "0x10" 473 }, 474 { 475 "BriefDescription": "All demand L2 lock RFOs", 476 "Counter": "0,1,2,3", 477 "EventCode": "0x27", 478 "EventName": "L2_WRITE.LOCK.MESI", 479 "SampleAfterValue": "100000", 480 "UMask": "0xf0" 481 }, 482 { 483 "BriefDescription": "L2 demand lock RFOs in M state", 484 "Counter": "0,1,2,3", 485 "EventCode": "0x27", 486 "EventName": "L2_WRITE.LOCK.M_STATE", 487 "SampleAfterValue": "100000", 488 "UMask": "0x80" 489 }, 490 { 491 "BriefDescription": "L2 demand lock RFOs in S state", 492 "Counter": "0,1,2,3", 493 "EventCode": "0x27", 494 "EventName": "L2_WRITE.LOCK.S_STATE", 495 "SampleAfterValue": "100000", 496 "UMask": "0x20" 497 }, 498 { 499 "BriefDescription": "All L2 demand store RFOs that hit the cache", 500 "Counter": "0,1,2,3", 501 "EventCode": "0x27", 502 "EventName": "L2_WRITE.RFO.HIT", 503 "SampleAfterValue": "100000", 504 "UMask": "0xe" 505 }, 506 { 507 "BriefDescription": "L2 demand store RFOs in I state (misses)", 508 "Counter": "0,1,2,3", 509 "EventCode": "0x27", 510 "EventName": "L2_WRITE.RFO.I_STATE", 511 "SampleAfterValue": "100000", 512 "UMask": "0x1" 513 }, 514 { 515 "BriefDescription": "All L2 demand store RFOs", 516 "Counter": "0,1,2,3", 517 "EventCode": "0x27", 518 "EventName": "L2_WRITE.RFO.MESI", 519 "SampleAfterValue": "100000", 520 "UMask": "0xf" 521 }, 522 { 523 "BriefDescription": "L2 demand store RFOs in M state", 524 "Counter": "0,1,2,3", 525 "EventCode": "0x27", 526 "EventName": "L2_WRITE.RFO.M_STATE", 527 "SampleAfterValue": "100000", 528 "UMask": "0x8" 529 }, 530 { 531 "BriefDescription": "L2 demand store RFOs in S state", 532 "Counter": "0,1,2,3", 533 "EventCode": "0x27", 534 "EventName": "L2_WRITE.RFO.S_STATE", 535 "SampleAfterValue": "100000", 536 "UMask": "0x2" 537 }, 538 { 539 "BriefDescription": "Longest latency cache miss", 540 "Counter": "0,1,2,3", 541 "EventCode": "0x2E", 542 "EventName": "LONGEST_LAT_CACHE.MISS", 543 "SampleAfterValue": "100000", 544 "UMask": "0x41" 545 }, 546 { 547 "BriefDescription": "Longest latency cache reference", 548 "Counter": "0,1,2,3", 549 "EventCode": "0x2E", 550 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 551 "SampleAfterValue": "200000", 552 "UMask": "0x4f" 553 }, 554 { 555 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", 556 "Counter": "3", 557 "EventCode": "0xB", 558 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", 559 "MSRIndex": "0x3F6", 560 "PEBS": "2", 561 "SampleAfterValue": "2000000", 562 "UMask": "0x10" 563 }, 564 { 565 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", 566 "Counter": "3", 567 "EventCode": "0xB", 568 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", 569 "MSRIndex": "0x3F6", 570 "MSRValue": "0x400", 571 "PEBS": "2", 572 "SampleAfterValue": "100", 573 "UMask": "0x10" 574 }, 575 { 576 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", 577 "Counter": "3", 578 "EventCode": "0xB", 579 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", 580 "MSRIndex": "0x3F6", 581 "MSRValue": "0x80", 582 "PEBS": "2", 583 "SampleAfterValue": "1000", 584 "UMask": "0x10" 585 }, 586 { 587 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", 588 "Counter": "3", 589 "EventCode": "0xB", 590 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", 591 "MSRIndex": "0x3F6", 592 "MSRValue": "0x10", 593 "PEBS": "2", 594 "SampleAfterValue": "10000", 595 "UMask": "0x10" 596 }, 597 { 598 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", 599 "Counter": "3", 600 "EventCode": "0xB", 601 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", 602 "MSRIndex": "0x3F6", 603 "MSRValue": "0x4000", 604 "PEBS": "2", 605 "SampleAfterValue": "5", 606 "UMask": "0x10" 607 }, 608 { 609 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", 610 "Counter": "3", 611 "EventCode": "0xB", 612 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", 613 "MSRIndex": "0x3F6", 614 "MSRValue": "0x800", 615 "PEBS": "2", 616 "SampleAfterValue": "50", 617 "UMask": "0x10" 618 }, 619 { 620 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", 621 "Counter": "3", 622 "EventCode": "0xB", 623 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", 624 "MSRIndex": "0x3F6", 625 "MSRValue": "0x100", 626 "PEBS": "2", 627 "SampleAfterValue": "500", 628 "UMask": "0x10" 629 }, 630 { 631 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", 632 "Counter": "3", 633 "EventCode": "0xB", 634 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", 635 "MSRIndex": "0x3F6", 636 "MSRValue": "0x20", 637 "PEBS": "2", 638 "SampleAfterValue": "5000", 639 "UMask": "0x10" 640 }, 641 { 642 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", 643 "Counter": "3", 644 "EventCode": "0xB", 645 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", 646 "MSRIndex": "0x3F6", 647 "MSRValue": "0x8000", 648 "PEBS": "2", 649 "SampleAfterValue": "3", 650 "UMask": "0x10" 651 }, 652 { 653 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", 654 "Counter": "3", 655 "EventCode": "0xB", 656 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", 657 "MSRIndex": "0x3F6", 658 "MSRValue": "0x4", 659 "PEBS": "2", 660 "SampleAfterValue": "50000", 661 "UMask": "0x10" 662 }, 663 { 664 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", 665 "Counter": "3", 666 "EventCode": "0xB", 667 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", 668 "MSRIndex": "0x3F6", 669 "MSRValue": "0x1000", 670 "PEBS": "2", 671 "SampleAfterValue": "20", 672 "UMask": "0x10" 673 }, 674 { 675 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", 676 "Counter": "3", 677 "EventCode": "0xB", 678 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", 679 "MSRIndex": "0x3F6", 680 "MSRValue": "0x200", 681 "PEBS": "2", 682 "SampleAfterValue": "200", 683 "UMask": "0x10" 684 }, 685 { 686 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", 687 "Counter": "3", 688 "EventCode": "0xB", 689 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", 690 "MSRIndex": "0x3F6", 691 "MSRValue": "0x40", 692 "PEBS": "2", 693 "SampleAfterValue": "2000", 694 "UMask": "0x10" 695 }, 696 { 697 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", 698 "Counter": "3", 699 "EventCode": "0xB", 700 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", 701 "MSRIndex": "0x3F6", 702 "MSRValue": "0x8", 703 "PEBS": "2", 704 "SampleAfterValue": "20000", 705 "UMask": "0x10" 706 }, 707 { 708 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", 709 "Counter": "3", 710 "EventCode": "0xB", 711 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", 712 "MSRIndex": "0x3F6", 713 "MSRValue": "0x2000", 714 "PEBS": "2", 715 "SampleAfterValue": "10", 716 "UMask": "0x10" 717 }, 718 { 719 "BriefDescription": "Instructions retired which contains a load (Precise Event)", 720 "Counter": "0,1,2,3", 721 "EventCode": "0xB", 722 "EventName": "MEM_INST_RETIRED.LOADS", 723 "PEBS": "1", 724 "SampleAfterValue": "2000000", 725 "UMask": "0x1" 726 }, 727 { 728 "BriefDescription": "Instructions retired which contains a store (Precise Event)", 729 "Counter": "0,1,2,3", 730 "EventCode": "0xB", 731 "EventName": "MEM_INST_RETIRED.STORES", 732 "PEBS": "1", 733 "SampleAfterValue": "2000000", 734 "UMask": "0x2" 735 }, 736 { 737 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", 738 "Counter": "0,1,2,3", 739 "EventCode": "0xCB", 740 "EventName": "MEM_LOAD_RETIRED.HIT_LFB", 741 "PEBS": "1", 742 "SampleAfterValue": "200000", 743 "UMask": "0x40" 744 }, 745 { 746 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", 747 "Counter": "0,1,2,3", 748 "EventCode": "0xCB", 749 "EventName": "MEM_LOAD_RETIRED.L1D_HIT", 750 "PEBS": "1", 751 "SampleAfterValue": "2000000", 752 "UMask": "0x1" 753 }, 754 { 755 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", 756 "Counter": "0,1,2,3", 757 "EventCode": "0xCB", 758 "EventName": "MEM_LOAD_RETIRED.L2_HIT", 759 "PEBS": "1", 760 "SampleAfterValue": "200000", 761 "UMask": "0x2" 762 }, 763 { 764 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", 765 "Counter": "0,1,2,3", 766 "EventCode": "0xCB", 767 "EventName": "MEM_LOAD_RETIRED.LLC_MISS", 768 "PEBS": "1", 769 "SampleAfterValue": "10000", 770 "UMask": "0x10" 771 }, 772 { 773 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", 774 "Counter": "0,1,2,3", 775 "EventCode": "0xCB", 776 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", 777 "PEBS": "1", 778 "SampleAfterValue": "40000", 779 "UMask": "0x4" 780 }, 781 { 782 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", 783 "Counter": "0,1,2,3", 784 "EventCode": "0xCB", 785 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", 786 "PEBS": "1", 787 "SampleAfterValue": "40000", 788 "UMask": "0x8" 789 }, 790 { 791 "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)", 792 "Counter": "0,1,2,3", 793 "EventCode": "0xF", 794 "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", 795 "PEBS": "1", 796 "SampleAfterValue": "10000", 797 "UMask": "0x10" 798 }, 799 { 800 "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)", 801 "Counter": "0,1,2,3", 802 "EventCode": "0xF", 803 "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", 804 "PEBS": "1", 805 "SampleAfterValue": "40000", 806 "UMask": "0x2" 807 }, 808 { 809 "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)", 810 "Counter": "0,1,2,3", 811 "EventCode": "0xF", 812 "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", 813 "PEBS": "1", 814 "SampleAfterValue": "20000", 815 "UMask": "0x8" 816 }, 817 { 818 "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)", 819 "Counter": "0,1,2,3", 820 "EventCode": "0xF", 821 "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", 822 "PEBS": "1", 823 "SampleAfterValue": "10000", 824 "UMask": "0x20" 825 }, 826 { 827 "BriefDescription": "Load instructions retired IO (Precise Event)", 828 "Counter": "0,1,2,3", 829 "EventCode": "0xF", 830 "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", 831 "PEBS": "1", 832 "SampleAfterValue": "4000", 833 "UMask": "0x80" 834 }, 835 { 836 "BriefDescription": "All offcore requests", 837 "Counter": "0,1,2,3", 838 "EventCode": "0xB0", 839 "EventName": "OFFCORE_REQUESTS.ANY", 840 "SampleAfterValue": "100000", 841 "UMask": "0x80" 842 }, 843 { 844 "BriefDescription": "Offcore read requests", 845 "Counter": "0,1,2,3", 846 "EventCode": "0xB0", 847 "EventName": "OFFCORE_REQUESTS.ANY.READ", 848 "SampleAfterValue": "100000", 849 "UMask": "0x8" 850 }, 851 { 852 "BriefDescription": "Offcore RFO requests", 853 "Counter": "0,1,2,3", 854 "EventCode": "0xB0", 855 "EventName": "OFFCORE_REQUESTS.ANY.RFO", 856 "SampleAfterValue": "100000", 857 "UMask": "0x10" 858 }, 859 { 860 "BriefDescription": "Offcore demand code read requests", 861 "Counter": "0,1,2,3", 862 "EventCode": "0xB0", 863 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", 864 "SampleAfterValue": "100000", 865 "UMask": "0x2" 866 }, 867 { 868 "BriefDescription": "Offcore demand data read requests", 869 "Counter": "0,1,2,3", 870 "EventCode": "0xB0", 871 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", 872 "SampleAfterValue": "100000", 873 "UMask": "0x1" 874 }, 875 { 876 "BriefDescription": "Offcore demand RFO requests", 877 "Counter": "0,1,2,3", 878 "EventCode": "0xB0", 879 "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", 880 "SampleAfterValue": "100000", 881 "UMask": "0x4" 882 }, 883 { 884 "BriefDescription": "Offcore L1 data cache writebacks", 885 "Counter": "0,1,2,3", 886 "EventCode": "0xB0", 887 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", 888 "SampleAfterValue": "100000", 889 "UMask": "0x40" 890 }, 891 { 892 "BriefDescription": "Offcore uncached memory accesses", 893 "Counter": "0,1,2,3", 894 "EventCode": "0xB0", 895 "EventName": "OFFCORE_REQUESTS.UNCACHED_MEM", 896 "SampleAfterValue": "100000", 897 "UMask": "0x20" 898 }, 899 { 900 "BriefDescription": "Outstanding offcore reads", 901 "Counter": "0", 902 "EventCode": "0x60", 903 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", 904 "SampleAfterValue": "2000000", 905 "UMask": "0x8" 906 }, 907 { 908 "BriefDescription": "Cycles offcore reads busy", 909 "Counter": "0", 910 "CounterMask": "1", 911 "EventCode": "0x60", 912 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", 913 "SampleAfterValue": "2000000", 914 "UMask": "0x8" 915 }, 916 { 917 "BriefDescription": "Outstanding offcore demand code reads", 918 "Counter": "0", 919 "EventCode": "0x60", 920 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", 921 "SampleAfterValue": "2000000", 922 "UMask": "0x2" 923 }, 924 { 925 "BriefDescription": "Cycles offcore demand code read busy", 926 "Counter": "0", 927 "CounterMask": "1", 928 "EventCode": "0x60", 929 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", 930 "SampleAfterValue": "2000000", 931 "UMask": "0x2" 932 }, 933 { 934 "BriefDescription": "Outstanding offcore demand data reads", 935 "Counter": "0", 936 "EventCode": "0x60", 937 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", 938 "SampleAfterValue": "2000000", 939 "UMask": "0x1" 940 }, 941 { 942 "BriefDescription": "Cycles offcore demand data read busy", 943 "Counter": "0", 944 "CounterMask": "1", 945 "EventCode": "0x60", 946 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", 947 "SampleAfterValue": "2000000", 948 "UMask": "0x1" 949 }, 950 { 951 "BriefDescription": "Outstanding offcore demand RFOs", 952 "Counter": "0", 953 "EventCode": "0x60", 954 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", 955 "SampleAfterValue": "2000000", 956 "UMask": "0x4" 957 }, 958 { 959 "BriefDescription": "Cycles offcore demand RFOs busy", 960 "Counter": "0", 961 "CounterMask": "1", 962 "EventCode": "0x60", 963 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", 964 "SampleAfterValue": "2000000", 965 "UMask": "0x4" 966 }, 967 { 968 "BriefDescription": "Offcore requests blocked due to Super Queue full", 969 "Counter": "0,1,2,3", 970 "EventCode": "0xB2", 971 "EventName": "OFFCORE_REQUESTS_SQ_FULL", 972 "SampleAfterValue": "100000", 973 "UMask": "0x1" 974 }, 975 { 976 "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", 977 "Counter": "0,1,2,3", 978 "EventCode": "0xB7, 0xBB", 979 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", 980 "MSRIndex": "0x1a6,0x1a7", 981 "MSRValue": "0x7F11", 982 "SampleAfterValue": "100000", 983 "UMask": "0x1" 984 }, 985 { 986 "BriefDescription": "All offcore data reads", 987 "Counter": "0,1,2,3", 988 "EventCode": "0xB7, 0xBB", 989 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", 990 "MSRIndex": "0x1a6,0x1a7", 991 "MSRValue": "0xFF11", 992 "SampleAfterValue": "100000", 993 "UMask": "0x1" 994 }, 995 { 996 "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", 997 "Counter": "0,1,2,3", 998 "EventCode": "0xB7, 0xBB", 999 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", 1000 "MSRIndex": "0x1a6,0x1a7", 1001 "MSRValue": "0x8011", 1002 "SampleAfterValue": "100000", 1003 "UMask": "0x1" 1004 }, 1005 { 1006 "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", 1007 "Counter": "0,1,2,3", 1008 "EventCode": "0xB7, 0xBB", 1009 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", 1010 "MSRIndex": "0x1a6,0x1a7", 1011 "MSRValue": "0x111", 1012 "SampleAfterValue": "100000", 1013 "UMask": "0x1" 1014 }, 1015 { 1016 "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", 1017 "Counter": "0,1,2,3", 1018 "EventCode": "0xB7, 0xBB", 1019 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", 1020 "MSRIndex": "0x1a6,0x1a7", 1021 "MSRValue": "0x211", 1022 "SampleAfterValue": "100000", 1023 "UMask": "0x1" 1024 }, 1025 { 1026 "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", 1027 "Counter": "0,1,2,3", 1028 "EventCode": "0xB7, 0xBB", 1029 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", 1030 "MSRIndex": "0x1a6,0x1a7", 1031 "MSRValue": "0x411", 1032 "SampleAfterValue": "100000", 1033 "UMask": "0x1" 1034 }, 1035 { 1036 "BriefDescription": "Offcore data reads satisfied by the LLC", 1037 "Counter": "0,1,2,3", 1038 "EventCode": "0xB7, 0xBB", 1039 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", 1040 "MSRIndex": "0x1a6,0x1a7", 1041 "MSRValue": "0x711", 1042 "SampleAfterValue": "100000", 1043 "UMask": "0x1" 1044 }, 1045 { 1046 "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", 1047 "Counter": "0,1,2,3", 1048 "EventCode": "0xB7, 0xBB", 1049 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", 1050 "MSRIndex": "0x1a6,0x1a7", 1051 "MSRValue": "0x2711", 1052 "SampleAfterValue": "100000", 1053 "UMask": "0x1" 1054 }, 1055 { 1056 "BriefDescription": "Offcore data reads satisfied by a remote cache", 1057 "Counter": "0,1,2,3", 1058 "EventCode": "0xB7, 0xBB", 1059 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", 1060 "MSRIndex": "0x1a6,0x1a7", 1061 "MSRValue": "0x1811", 1062 "SampleAfterValue": "100000", 1063 "UMask": "0x1" 1064 }, 1065 { 1066 "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", 1067 "Counter": "0,1,2,3", 1068 "EventCode": "0xB7, 0xBB", 1069 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", 1070 "MSRIndex": "0x1a6,0x1a7", 1071 "MSRValue": "0x5811", 1072 "SampleAfterValue": "100000", 1073 "UMask": "0x1" 1074 }, 1075 { 1076 "BriefDescription": "Offcore data reads that HIT in a remote cache", 1077 "Counter": "0,1,2,3", 1078 "EventCode": "0xB7, 0xBB", 1079 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", 1080 "MSRIndex": "0x1a6,0x1a7", 1081 "MSRValue": "0x1011", 1082 "SampleAfterValue": "100000", 1083 "UMask": "0x1" 1084 }, 1085 { 1086 "BriefDescription": "Offcore data reads that HITM in a remote cache", 1087 "Counter": "0,1,2,3", 1088 "EventCode": "0xB7, 0xBB", 1089 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", 1090 "MSRIndex": "0x1a6,0x1a7", 1091 "MSRValue": "0x811", 1092 "SampleAfterValue": "100000", 1093 "UMask": "0x1" 1094 }, 1095 { 1096 "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", 1097 "Counter": "0,1,2,3", 1098 "EventCode": "0xB7, 0xBB", 1099 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", 1100 "MSRIndex": "0x1a6,0x1a7", 1101 "MSRValue": "0x7F44", 1102 "SampleAfterValue": "100000", 1103 "UMask": "0x1" 1104 }, 1105 { 1106 "BriefDescription": "All offcore code reads", 1107 "Counter": "0,1,2,3", 1108 "EventCode": "0xB7, 0xBB", 1109 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", 1110 "MSRIndex": "0x1a6,0x1a7", 1111 "MSRValue": "0xFF44", 1112 "SampleAfterValue": "100000", 1113 "UMask": "0x1" 1114 }, 1115 { 1116 "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", 1117 "Counter": "0,1,2,3", 1118 "EventCode": "0xB7, 0xBB", 1119 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", 1120 "MSRIndex": "0x1a6,0x1a7", 1121 "MSRValue": "0x8044", 1122 "SampleAfterValue": "100000", 1123 "UMask": "0x1" 1124 }, 1125 { 1126 "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", 1127 "Counter": "0,1,2,3", 1128 "EventCode": "0xB7, 0xBB", 1129 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", 1130 "MSRIndex": "0x1a6,0x1a7", 1131 "MSRValue": "0x144", 1132 "SampleAfterValue": "100000", 1133 "UMask": "0x1" 1134 }, 1135 { 1136 "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", 1137 "Counter": "0,1,2,3", 1138 "EventCode": "0xB7, 0xBB", 1139 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1140 "MSRIndex": "0x1a6,0x1a7", 1141 "MSRValue": "0x244", 1142 "SampleAfterValue": "100000", 1143 "UMask": "0x1" 1144 }, 1145 { 1146 "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", 1147 "Counter": "0,1,2,3", 1148 "EventCode": "0xB7, 0xBB", 1149 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1150 "MSRIndex": "0x1a6,0x1a7", 1151 "MSRValue": "0x444", 1152 "SampleAfterValue": "100000", 1153 "UMask": "0x1" 1154 }, 1155 { 1156 "BriefDescription": "Offcore code reads satisfied by the LLC", 1157 "Counter": "0,1,2,3", 1158 "EventCode": "0xB7, 0xBB", 1159 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", 1160 "MSRIndex": "0x1a6,0x1a7", 1161 "MSRValue": "0x744", 1162 "SampleAfterValue": "100000", 1163 "UMask": "0x1" 1164 }, 1165 { 1166 "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", 1167 "Counter": "0,1,2,3", 1168 "EventCode": "0xB7, 0xBB", 1169 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", 1170 "MSRIndex": "0x1a6,0x1a7", 1171 "MSRValue": "0x2744", 1172 "SampleAfterValue": "100000", 1173 "UMask": "0x1" 1174 }, 1175 { 1176 "BriefDescription": "Offcore code reads satisfied by a remote cache", 1177 "Counter": "0,1,2,3", 1178 "EventCode": "0xB7, 0xBB", 1179 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", 1180 "MSRIndex": "0x1a6,0x1a7", 1181 "MSRValue": "0x1844", 1182 "SampleAfterValue": "100000", 1183 "UMask": "0x1" 1184 }, 1185 { 1186 "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", 1187 "Counter": "0,1,2,3", 1188 "EventCode": "0xB7, 0xBB", 1189 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", 1190 "MSRIndex": "0x1a6,0x1a7", 1191 "MSRValue": "0x5844", 1192 "SampleAfterValue": "100000", 1193 "UMask": "0x1" 1194 }, 1195 { 1196 "BriefDescription": "Offcore code reads that HIT in a remote cache", 1197 "Counter": "0,1,2,3", 1198 "EventCode": "0xB7, 0xBB", 1199 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", 1200 "MSRIndex": "0x1a6,0x1a7", 1201 "MSRValue": "0x1044", 1202 "SampleAfterValue": "100000", 1203 "UMask": "0x1" 1204 }, 1205 { 1206 "BriefDescription": "Offcore code reads that HITM in a remote cache", 1207 "Counter": "0,1,2,3", 1208 "EventCode": "0xB7, 0xBB", 1209 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", 1210 "MSRIndex": "0x1a6,0x1a7", 1211 "MSRValue": "0x844", 1212 "SampleAfterValue": "100000", 1213 "UMask": "0x1" 1214 }, 1215 { 1216 "BriefDescription": "Offcore requests satisfied by any cache or DRAM", 1217 "Counter": "0,1,2,3", 1218 "EventCode": "0xB7, 0xBB", 1219 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", 1220 "MSRIndex": "0x1a6,0x1a7", 1221 "MSRValue": "0x7FFF", 1222 "SampleAfterValue": "100000", 1223 "UMask": "0x1" 1224 }, 1225 { 1226 "BriefDescription": "All offcore requests", 1227 "Counter": "0,1,2,3", 1228 "EventCode": "0xB7, 0xBB", 1229 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", 1230 "MSRIndex": "0x1a6,0x1a7", 1231 "MSRValue": "0xFFFF", 1232 "SampleAfterValue": "100000", 1233 "UMask": "0x1" 1234 }, 1235 { 1236 "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", 1237 "Counter": "0,1,2,3", 1238 "EventCode": "0xB7, 0xBB", 1239 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", 1240 "MSRIndex": "0x1a6,0x1a7", 1241 "MSRValue": "0x80FF", 1242 "SampleAfterValue": "100000", 1243 "UMask": "0x1" 1244 }, 1245 { 1246 "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", 1247 "Counter": "0,1,2,3", 1248 "EventCode": "0xB7, 0xBB", 1249 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", 1250 "MSRIndex": "0x1a6,0x1a7", 1251 "MSRValue": "0x1FF", 1252 "SampleAfterValue": "100000", 1253 "UMask": "0x1" 1254 }, 1255 { 1256 "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", 1257 "Counter": "0,1,2,3", 1258 "EventCode": "0xB7, 0xBB", 1259 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", 1260 "MSRIndex": "0x1a6,0x1a7", 1261 "MSRValue": "0x2FF", 1262 "SampleAfterValue": "100000", 1263 "UMask": "0x1" 1264 }, 1265 { 1266 "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", 1267 "Counter": "0,1,2,3", 1268 "EventCode": "0xB7, 0xBB", 1269 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", 1270 "MSRIndex": "0x1a6,0x1a7", 1271 "MSRValue": "0x4FF", 1272 "SampleAfterValue": "100000", 1273 "UMask": "0x1" 1274 }, 1275 { 1276 "BriefDescription": "Offcore requests satisfied by the LLC", 1277 "Counter": "0,1,2,3", 1278 "EventCode": "0xB7, 0xBB", 1279 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", 1280 "MSRIndex": "0x1a6,0x1a7", 1281 "MSRValue": "0x7FF", 1282 "SampleAfterValue": "100000", 1283 "UMask": "0x1" 1284 }, 1285 { 1286 "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", 1287 "Counter": "0,1,2,3", 1288 "EventCode": "0xB7, 0xBB", 1289 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", 1290 "MSRIndex": "0x1a6,0x1a7", 1291 "MSRValue": "0x27FF", 1292 "SampleAfterValue": "100000", 1293 "UMask": "0x1" 1294 }, 1295 { 1296 "BriefDescription": "Offcore requests satisfied by a remote cache", 1297 "Counter": "0,1,2,3", 1298 "EventCode": "0xB7, 0xBB", 1299 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", 1300 "MSRIndex": "0x1a6,0x1a7", 1301 "MSRValue": "0x18FF", 1302 "SampleAfterValue": "100000", 1303 "UMask": "0x1" 1304 }, 1305 { 1306 "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", 1307 "Counter": "0,1,2,3", 1308 "EventCode": "0xB7, 0xBB", 1309 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", 1310 "MSRIndex": "0x1a6,0x1a7", 1311 "MSRValue": "0x58FF", 1312 "SampleAfterValue": "100000", 1313 "UMask": "0x1" 1314 }, 1315 { 1316 "BriefDescription": "Offcore requests that HIT in a remote cache", 1317 "Counter": "0,1,2,3", 1318 "EventCode": "0xB7, 0xBB", 1319 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", 1320 "MSRIndex": "0x1a6,0x1a7", 1321 "MSRValue": "0x10FF", 1322 "SampleAfterValue": "100000", 1323 "UMask": "0x1" 1324 }, 1325 { 1326 "BriefDescription": "Offcore requests that HITM in a remote cache", 1327 "Counter": "0,1,2,3", 1328 "EventCode": "0xB7, 0xBB", 1329 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", 1330 "MSRIndex": "0x1a6,0x1a7", 1331 "MSRValue": "0x8FF", 1332 "SampleAfterValue": "100000", 1333 "UMask": "0x1" 1334 }, 1335 { 1336 "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", 1337 "Counter": "0,1,2,3", 1338 "EventCode": "0xB7, 0xBB", 1339 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", 1340 "MSRIndex": "0x1a6,0x1a7", 1341 "MSRValue": "0x7F22", 1342 "SampleAfterValue": "100000", 1343 "UMask": "0x1" 1344 }, 1345 { 1346 "BriefDescription": "All offcore RFO requests", 1347 "Counter": "0,1,2,3", 1348 "EventCode": "0xB7, 0xBB", 1349 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", 1350 "MSRIndex": "0x1a6,0x1a7", 1351 "MSRValue": "0xFF22", 1352 "SampleAfterValue": "100000", 1353 "UMask": "0x1" 1354 }, 1355 { 1356 "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", 1357 "Counter": "0,1,2,3", 1358 "EventCode": "0xB7, 0xBB", 1359 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", 1360 "MSRIndex": "0x1a6,0x1a7", 1361 "MSRValue": "0x8022", 1362 "SampleAfterValue": "100000", 1363 "UMask": "0x1" 1364 }, 1365 { 1366 "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", 1367 "Counter": "0,1,2,3", 1368 "EventCode": "0xB7, 0xBB", 1369 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", 1370 "MSRIndex": "0x1a6,0x1a7", 1371 "MSRValue": "0x122", 1372 "SampleAfterValue": "100000", 1373 "UMask": "0x1" 1374 }, 1375 { 1376 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", 1377 "Counter": "0,1,2,3", 1378 "EventCode": "0xB7, 0xBB", 1379 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", 1380 "MSRIndex": "0x1a6,0x1a7", 1381 "MSRValue": "0x222", 1382 "SampleAfterValue": "100000", 1383 "UMask": "0x1" 1384 }, 1385 { 1386 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", 1387 "Counter": "0,1,2,3", 1388 "EventCode": "0xB7, 0xBB", 1389 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", 1390 "MSRIndex": "0x1a6,0x1a7", 1391 "MSRValue": "0x422", 1392 "SampleAfterValue": "100000", 1393 "UMask": "0x1" 1394 }, 1395 { 1396 "BriefDescription": "Offcore RFO requests satisfied by the LLC", 1397 "Counter": "0,1,2,3", 1398 "EventCode": "0xB7, 0xBB", 1399 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", 1400 "MSRIndex": "0x1a6,0x1a7", 1401 "MSRValue": "0x722", 1402 "SampleAfterValue": "100000", 1403 "UMask": "0x1" 1404 }, 1405 { 1406 "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", 1407 "Counter": "0,1,2,3", 1408 "EventCode": "0xB7, 0xBB", 1409 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", 1410 "MSRIndex": "0x1a6,0x1a7", 1411 "MSRValue": "0x2722", 1412 "SampleAfterValue": "100000", 1413 "UMask": "0x1" 1414 }, 1415 { 1416 "BriefDescription": "Offcore RFO requests satisfied by a remote cache", 1417 "Counter": "0,1,2,3", 1418 "EventCode": "0xB7, 0xBB", 1419 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", 1420 "MSRIndex": "0x1a6,0x1a7", 1421 "MSRValue": "0x1822", 1422 "SampleAfterValue": "100000", 1423 "UMask": "0x1" 1424 }, 1425 { 1426 "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", 1427 "Counter": "0,1,2,3", 1428 "EventCode": "0xB7, 0xBB", 1429 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", 1430 "MSRIndex": "0x1a6,0x1a7", 1431 "MSRValue": "0x5822", 1432 "SampleAfterValue": "100000", 1433 "UMask": "0x1" 1434 }, 1435 { 1436 "BriefDescription": "Offcore RFO requests that HIT in a remote cache", 1437 "Counter": "0,1,2,3", 1438 "EventCode": "0xB7, 0xBB", 1439 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", 1440 "MSRIndex": "0x1a6,0x1a7", 1441 "MSRValue": "0x1022", 1442 "SampleAfterValue": "100000", 1443 "UMask": "0x1" 1444 }, 1445 { 1446 "BriefDescription": "Offcore RFO requests that HITM in a remote cache", 1447 "Counter": "0,1,2,3", 1448 "EventCode": "0xB7, 0xBB", 1449 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", 1450 "MSRIndex": "0x1a6,0x1a7", 1451 "MSRValue": "0x822", 1452 "SampleAfterValue": "100000", 1453 "UMask": "0x1" 1454 }, 1455 { 1456 "BriefDescription": "Offcore writebacks to any cache or DRAM.", 1457 "Counter": "0,1,2,3", 1458 "EventCode": "0xB7, 0xBB", 1459 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", 1460 "MSRIndex": "0x1a6,0x1a7", 1461 "MSRValue": "0x7F08", 1462 "SampleAfterValue": "100000", 1463 "UMask": "0x1" 1464 }, 1465 { 1466 "BriefDescription": "All offcore writebacks", 1467 "Counter": "0,1,2,3", 1468 "EventCode": "0xB7, 0xBB", 1469 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", 1470 "MSRIndex": "0x1a6,0x1a7", 1471 "MSRValue": "0xFF08", 1472 "SampleAfterValue": "100000", 1473 "UMask": "0x1" 1474 }, 1475 { 1476 "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", 1477 "Counter": "0,1,2,3", 1478 "EventCode": "0xB7, 0xBB", 1479 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", 1480 "MSRIndex": "0x1a6,0x1a7", 1481 "MSRValue": "0x8008", 1482 "SampleAfterValue": "100000", 1483 "UMask": "0x1" 1484 }, 1485 { 1486 "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", 1487 "Counter": "0,1,2,3", 1488 "EventCode": "0xB7, 0xBB", 1489 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", 1490 "MSRIndex": "0x1a6,0x1a7", 1491 "MSRValue": "0x108", 1492 "SampleAfterValue": "100000", 1493 "UMask": "0x1" 1494 }, 1495 { 1496 "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", 1497 "Counter": "0,1,2,3", 1498 "EventCode": "0xB7, 0xBB", 1499 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", 1500 "MSRIndex": "0x1a6,0x1a7", 1501 "MSRValue": "0x408", 1502 "SampleAfterValue": "100000", 1503 "UMask": "0x1" 1504 }, 1505 { 1506 "BriefDescription": "Offcore writebacks to the LLC", 1507 "Counter": "0,1,2,3", 1508 "EventCode": "0xB7, 0xBB", 1509 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", 1510 "MSRIndex": "0x1a6,0x1a7", 1511 "MSRValue": "0x708", 1512 "SampleAfterValue": "100000", 1513 "UMask": "0x1" 1514 }, 1515 { 1516 "BriefDescription": "Offcore writebacks to the LLC or local DRAM", 1517 "Counter": "0,1,2,3", 1518 "EventCode": "0xB7, 0xBB", 1519 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", 1520 "MSRIndex": "0x1a6,0x1a7", 1521 "MSRValue": "0x2708", 1522 "SampleAfterValue": "100000", 1523 "UMask": "0x1" 1524 }, 1525 { 1526 "BriefDescription": "Offcore writebacks to a remote cache", 1527 "Counter": "0,1,2,3", 1528 "EventCode": "0xB7, 0xBB", 1529 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", 1530 "MSRIndex": "0x1a6,0x1a7", 1531 "MSRValue": "0x1808", 1532 "SampleAfterValue": "100000", 1533 "UMask": "0x1" 1534 }, 1535 { 1536 "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", 1537 "Counter": "0,1,2,3", 1538 "EventCode": "0xB7, 0xBB", 1539 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", 1540 "MSRIndex": "0x1a6,0x1a7", 1541 "MSRValue": "0x5808", 1542 "SampleAfterValue": "100000", 1543 "UMask": "0x1" 1544 }, 1545 { 1546 "BriefDescription": "Offcore writebacks that HIT in a remote cache", 1547 "Counter": "0,1,2,3", 1548 "EventCode": "0xB7, 0xBB", 1549 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", 1550 "MSRIndex": "0x1a6,0x1a7", 1551 "MSRValue": "0x1008", 1552 "SampleAfterValue": "100000", 1553 "UMask": "0x1" 1554 }, 1555 { 1556 "BriefDescription": "Offcore writebacks that HITM in a remote cache", 1557 "Counter": "0,1,2,3", 1558 "EventCode": "0xB7, 0xBB", 1559 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", 1560 "MSRIndex": "0x1a6,0x1a7", 1561 "MSRValue": "0x808", 1562 "SampleAfterValue": "100000", 1563 "UMask": "0x1" 1564 }, 1565 { 1566 "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", 1567 "Counter": "0,1,2,3", 1568 "EventCode": "0xB7, 0xBB", 1569 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", 1570 "MSRIndex": "0x1a6,0x1a7", 1571 "MSRValue": "0x7F77", 1572 "SampleAfterValue": "100000", 1573 "UMask": "0x1" 1574 }, 1575 { 1576 "BriefDescription": "All offcore code or data read requests", 1577 "Counter": "0,1,2,3", 1578 "EventCode": "0xB7, 0xBB", 1579 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", 1580 "MSRIndex": "0x1a6,0x1a7", 1581 "MSRValue": "0xFF77", 1582 "SampleAfterValue": "100000", 1583 "UMask": "0x1" 1584 }, 1585 { 1586 "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", 1587 "Counter": "0,1,2,3", 1588 "EventCode": "0xB7, 0xBB", 1589 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", 1590 "MSRIndex": "0x1a6,0x1a7", 1591 "MSRValue": "0x8077", 1592 "SampleAfterValue": "100000", 1593 "UMask": "0x1" 1594 }, 1595 { 1596 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", 1597 "Counter": "0,1,2,3", 1598 "EventCode": "0xB7, 0xBB", 1599 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", 1600 "MSRIndex": "0x1a6,0x1a7", 1601 "MSRValue": "0x177", 1602 "SampleAfterValue": "100000", 1603 "UMask": "0x1" 1604 }, 1605 { 1606 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", 1607 "Counter": "0,1,2,3", 1608 "EventCode": "0xB7, 0xBB", 1609 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1610 "MSRIndex": "0x1a6,0x1a7", 1611 "MSRValue": "0x277", 1612 "SampleAfterValue": "100000", 1613 "UMask": "0x1" 1614 }, 1615 { 1616 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", 1617 "Counter": "0,1,2,3", 1618 "EventCode": "0xB7, 0xBB", 1619 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1620 "MSRIndex": "0x1a6,0x1a7", 1621 "MSRValue": "0x477", 1622 "SampleAfterValue": "100000", 1623 "UMask": "0x1" 1624 }, 1625 { 1626 "BriefDescription": "Offcore code or data read requests satisfied by the LLC", 1627 "Counter": "0,1,2,3", 1628 "EventCode": "0xB7, 0xBB", 1629 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", 1630 "MSRIndex": "0x1a6,0x1a7", 1631 "MSRValue": "0x777", 1632 "SampleAfterValue": "100000", 1633 "UMask": "0x1" 1634 }, 1635 { 1636 "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", 1637 "Counter": "0,1,2,3", 1638 "EventCode": "0xB7, 0xBB", 1639 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", 1640 "MSRIndex": "0x1a6,0x1a7", 1641 "MSRValue": "0x2777", 1642 "SampleAfterValue": "100000", 1643 "UMask": "0x1" 1644 }, 1645 { 1646 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", 1647 "Counter": "0,1,2,3", 1648 "EventCode": "0xB7, 0xBB", 1649 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", 1650 "MSRIndex": "0x1a6,0x1a7", 1651 "MSRValue": "0x1877", 1652 "SampleAfterValue": "100000", 1653 "UMask": "0x1" 1654 }, 1655 { 1656 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", 1657 "Counter": "0,1,2,3", 1658 "EventCode": "0xB7, 0xBB", 1659 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", 1660 "MSRIndex": "0x1a6,0x1a7", 1661 "MSRValue": "0x5877", 1662 "SampleAfterValue": "100000", 1663 "UMask": "0x1" 1664 }, 1665 { 1666 "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", 1667 "Counter": "0,1,2,3", 1668 "EventCode": "0xB7, 0xBB", 1669 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", 1670 "MSRIndex": "0x1a6,0x1a7", 1671 "MSRValue": "0x1077", 1672 "SampleAfterValue": "100000", 1673 "UMask": "0x1" 1674 }, 1675 { 1676 "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", 1677 "Counter": "0,1,2,3", 1678 "EventCode": "0xB7, 0xBB", 1679 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", 1680 "MSRIndex": "0x1a6,0x1a7", 1681 "MSRValue": "0x877", 1682 "SampleAfterValue": "100000", 1683 "UMask": "0x1" 1684 }, 1685 { 1686 "BriefDescription": "Offcore request = all data, response = any cache_dram", 1687 "Counter": "0,1,2,3", 1688 "EventCode": "0xB7, 0xBB", 1689 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", 1690 "MSRIndex": "0x1a6,0x1a7", 1691 "MSRValue": "0x7F33", 1692 "SampleAfterValue": "100000", 1693 "UMask": "0x1" 1694 }, 1695 { 1696 "BriefDescription": "Offcore request = all data, response = any location", 1697 "Counter": "0,1,2,3", 1698 "EventCode": "0xB7, 0xBB", 1699 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", 1700 "MSRIndex": "0x1a6,0x1a7", 1701 "MSRValue": "0xFF33", 1702 "SampleAfterValue": "100000", 1703 "UMask": "0x1" 1704 }, 1705 { 1706 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit", 1707 "Counter": "0,1,2,3", 1708 "EventCode": "0xB7, 0xBB", 1709 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", 1710 "MSRIndex": "0x1a6,0x1a7", 1711 "MSRValue": "0x8033", 1712 "SampleAfterValue": "100000", 1713 "UMask": "0x1" 1714 }, 1715 { 1716 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core", 1717 "Counter": "0,1,2,3", 1718 "EventCode": "0xB7, 0xBB", 1719 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", 1720 "MSRIndex": "0x1a6,0x1a7", 1721 "MSRValue": "0x133", 1722 "SampleAfterValue": "100000", 1723 "UMask": "0x1" 1724 }, 1725 { 1726 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core", 1727 "Counter": "0,1,2,3", 1728 "EventCode": "0xB7, 0xBB", 1729 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", 1730 "MSRIndex": "0x1a6,0x1a7", 1731 "MSRValue": "0x233", 1732 "SampleAfterValue": "100000", 1733 "UMask": "0x1" 1734 }, 1735 { 1736 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core", 1737 "Counter": "0,1,2,3", 1738 "EventCode": "0xB7, 0xBB", 1739 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", 1740 "MSRIndex": "0x1a6,0x1a7", 1741 "MSRValue": "0x433", 1742 "SampleAfterValue": "100000", 1743 "UMask": "0x1" 1744 }, 1745 { 1746 "BriefDescription": "Offcore request = all data, response = local cache", 1747 "Counter": "0,1,2,3", 1748 "EventCode": "0xB7, 0xBB", 1749 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", 1750 "MSRIndex": "0x1a6,0x1a7", 1751 "MSRValue": "0x733", 1752 "SampleAfterValue": "100000", 1753 "UMask": "0x1" 1754 }, 1755 { 1756 "BriefDescription": "Offcore request = all data, response = local cache or dram", 1757 "Counter": "0,1,2,3", 1758 "EventCode": "0xB7, 0xBB", 1759 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", 1760 "MSRIndex": "0x1a6,0x1a7", 1761 "MSRValue": "0x2733", 1762 "SampleAfterValue": "100000", 1763 "UMask": "0x1" 1764 }, 1765 { 1766 "BriefDescription": "Offcore request = all data, response = remote cache", 1767 "Counter": "0,1,2,3", 1768 "EventCode": "0xB7, 0xBB", 1769 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", 1770 "MSRIndex": "0x1a6,0x1a7", 1771 "MSRValue": "0x1833", 1772 "SampleAfterValue": "100000", 1773 "UMask": "0x1" 1774 }, 1775 { 1776 "BriefDescription": "Offcore request = all data, response = remote cache or dram", 1777 "Counter": "0,1,2,3", 1778 "EventCode": "0xB7, 0xBB", 1779 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", 1780 "MSRIndex": "0x1a6,0x1a7", 1781 "MSRValue": "0x5833", 1782 "SampleAfterValue": "100000", 1783 "UMask": "0x1" 1784 }, 1785 { 1786 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache", 1787 "Counter": "0,1,2,3", 1788 "EventCode": "0xB7, 0xBB", 1789 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", 1790 "MSRIndex": "0x1a6,0x1a7", 1791 "MSRValue": "0x1033", 1792 "SampleAfterValue": "100000", 1793 "UMask": "0x1" 1794 }, 1795 { 1796 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache", 1797 "Counter": "0,1,2,3", 1798 "EventCode": "0xB7, 0xBB", 1799 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", 1800 "MSRIndex": "0x1a6,0x1a7", 1801 "MSRValue": "0x833", 1802 "SampleAfterValue": "100000", 1803 "UMask": "0x1" 1804 }, 1805 { 1806 "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", 1807 "Counter": "0,1,2,3", 1808 "EventCode": "0xB7, 0xBB", 1809 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", 1810 "MSRIndex": "0x1a6,0x1a7", 1811 "MSRValue": "0x7F03", 1812 "SampleAfterValue": "100000", 1813 "UMask": "0x1" 1814 }, 1815 { 1816 "BriefDescription": "All offcore demand data requests", 1817 "Counter": "0,1,2,3", 1818 "EventCode": "0xB7, 0xBB", 1819 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", 1820 "MSRIndex": "0x1a6,0x1a7", 1821 "MSRValue": "0xFF03", 1822 "SampleAfterValue": "100000", 1823 "UMask": "0x1" 1824 }, 1825 { 1826 "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", 1827 "Counter": "0,1,2,3", 1828 "EventCode": "0xB7, 0xBB", 1829 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", 1830 "MSRIndex": "0x1a6,0x1a7", 1831 "MSRValue": "0x8003", 1832 "SampleAfterValue": "100000", 1833 "UMask": "0x1" 1834 }, 1835 { 1836 "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", 1837 "Counter": "0,1,2,3", 1838 "EventCode": "0xB7, 0xBB", 1839 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", 1840 "MSRIndex": "0x1a6,0x1a7", 1841 "MSRValue": "0x103", 1842 "SampleAfterValue": "100000", 1843 "UMask": "0x1" 1844 }, 1845 { 1846 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", 1847 "Counter": "0,1,2,3", 1848 "EventCode": "0xB7, 0xBB", 1849 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", 1850 "MSRIndex": "0x1a6,0x1a7", 1851 "MSRValue": "0x203", 1852 "SampleAfterValue": "100000", 1853 "UMask": "0x1" 1854 }, 1855 { 1856 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", 1857 "Counter": "0,1,2,3", 1858 "EventCode": "0xB7, 0xBB", 1859 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", 1860 "MSRIndex": "0x1a6,0x1a7", 1861 "MSRValue": "0x403", 1862 "SampleAfterValue": "100000", 1863 "UMask": "0x1" 1864 }, 1865 { 1866 "BriefDescription": "Offcore demand data requests satisfied by the LLC", 1867 "Counter": "0,1,2,3", 1868 "EventCode": "0xB7, 0xBB", 1869 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", 1870 "MSRIndex": "0x1a6,0x1a7", 1871 "MSRValue": "0x703", 1872 "SampleAfterValue": "100000", 1873 "UMask": "0x1" 1874 }, 1875 { 1876 "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", 1877 "Counter": "0,1,2,3", 1878 "EventCode": "0xB7, 0xBB", 1879 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", 1880 "MSRIndex": "0x1a6,0x1a7", 1881 "MSRValue": "0x2703", 1882 "SampleAfterValue": "100000", 1883 "UMask": "0x1" 1884 }, 1885 { 1886 "BriefDescription": "Offcore demand data requests satisfied by a remote cache", 1887 "Counter": "0,1,2,3", 1888 "EventCode": "0xB7, 0xBB", 1889 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", 1890 "MSRIndex": "0x1a6,0x1a7", 1891 "MSRValue": "0x1803", 1892 "SampleAfterValue": "100000", 1893 "UMask": "0x1" 1894 }, 1895 { 1896 "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", 1897 "Counter": "0,1,2,3", 1898 "EventCode": "0xB7, 0xBB", 1899 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", 1900 "MSRIndex": "0x1a6,0x1a7", 1901 "MSRValue": "0x5803", 1902 "SampleAfterValue": "100000", 1903 "UMask": "0x1" 1904 }, 1905 { 1906 "BriefDescription": "Offcore demand data requests that HIT in a remote cache", 1907 "Counter": "0,1,2,3", 1908 "EventCode": "0xB7, 0xBB", 1909 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", 1910 "MSRIndex": "0x1a6,0x1a7", 1911 "MSRValue": "0x1003", 1912 "SampleAfterValue": "100000", 1913 "UMask": "0x1" 1914 }, 1915 { 1916 "BriefDescription": "Offcore demand data requests that HITM in a remote cache", 1917 "Counter": "0,1,2,3", 1918 "EventCode": "0xB7, 0xBB", 1919 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", 1920 "MSRIndex": "0x1a6,0x1a7", 1921 "MSRValue": "0x803", 1922 "SampleAfterValue": "100000", 1923 "UMask": "0x1" 1924 }, 1925 { 1926 "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", 1927 "Counter": "0,1,2,3", 1928 "EventCode": "0xB7, 0xBB", 1929 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", 1930 "MSRIndex": "0x1a6,0x1a7", 1931 "MSRValue": "0x7F01", 1932 "SampleAfterValue": "100000", 1933 "UMask": "0x1" 1934 }, 1935 { 1936 "BriefDescription": "All offcore demand data reads", 1937 "Counter": "0,1,2,3", 1938 "EventCode": "0xB7, 0xBB", 1939 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", 1940 "MSRIndex": "0x1a6,0x1a7", 1941 "MSRValue": "0xFF01", 1942 "SampleAfterValue": "100000", 1943 "UMask": "0x1" 1944 }, 1945 { 1946 "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", 1947 "Counter": "0,1,2,3", 1948 "EventCode": "0xB7, 0xBB", 1949 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", 1950 "MSRIndex": "0x1a6,0x1a7", 1951 "MSRValue": "0x8001", 1952 "SampleAfterValue": "100000", 1953 "UMask": "0x1" 1954 }, 1955 { 1956 "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", 1957 "Counter": "0,1,2,3", 1958 "EventCode": "0xB7, 0xBB", 1959 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", 1960 "MSRIndex": "0x1a6,0x1a7", 1961 "MSRValue": "0x101", 1962 "SampleAfterValue": "100000", 1963 "UMask": "0x1" 1964 }, 1965 { 1966 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", 1967 "Counter": "0,1,2,3", 1968 "EventCode": "0xB7, 0xBB", 1969 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 1970 "MSRIndex": "0x1a6,0x1a7", 1971 "MSRValue": "0x201", 1972 "SampleAfterValue": "100000", 1973 "UMask": "0x1" 1974 }, 1975 { 1976 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", 1977 "Counter": "0,1,2,3", 1978 "EventCode": "0xB7, 0xBB", 1979 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 1980 "MSRIndex": "0x1a6,0x1a7", 1981 "MSRValue": "0x401", 1982 "SampleAfterValue": "100000", 1983 "UMask": "0x1" 1984 }, 1985 { 1986 "BriefDescription": "Offcore demand data reads satisfied by the LLC", 1987 "Counter": "0,1,2,3", 1988 "EventCode": "0xB7, 0xBB", 1989 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", 1990 "MSRIndex": "0x1a6,0x1a7", 1991 "MSRValue": "0x701", 1992 "SampleAfterValue": "100000", 1993 "UMask": "0x1" 1994 }, 1995 { 1996 "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", 1997 "Counter": "0,1,2,3", 1998 "EventCode": "0xB7, 0xBB", 1999 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", 2000 "MSRIndex": "0x1a6,0x1a7", 2001 "MSRValue": "0x2701", 2002 "SampleAfterValue": "100000", 2003 "UMask": "0x1" 2004 }, 2005 { 2006 "BriefDescription": "Offcore demand data reads satisfied by a remote cache", 2007 "Counter": "0,1,2,3", 2008 "EventCode": "0xB7, 0xBB", 2009 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", 2010 "MSRIndex": "0x1a6,0x1a7", 2011 "MSRValue": "0x1801", 2012 "SampleAfterValue": "100000", 2013 "UMask": "0x1" 2014 }, 2015 { 2016 "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", 2017 "Counter": "0,1,2,3", 2018 "EventCode": "0xB7, 0xBB", 2019 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", 2020 "MSRIndex": "0x1a6,0x1a7", 2021 "MSRValue": "0x5801", 2022 "SampleAfterValue": "100000", 2023 "UMask": "0x1" 2024 }, 2025 { 2026 "BriefDescription": "Offcore demand data reads that HIT in a remote cache", 2027 "Counter": "0,1,2,3", 2028 "EventCode": "0xB7, 0xBB", 2029 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", 2030 "MSRIndex": "0x1a6,0x1a7", 2031 "MSRValue": "0x1001", 2032 "SampleAfterValue": "100000", 2033 "UMask": "0x1" 2034 }, 2035 { 2036 "BriefDescription": "Offcore demand data reads that HITM in a remote cache", 2037 "Counter": "0,1,2,3", 2038 "EventCode": "0xB7, 0xBB", 2039 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", 2040 "MSRIndex": "0x1a6,0x1a7", 2041 "MSRValue": "0x801", 2042 "SampleAfterValue": "100000", 2043 "UMask": "0x1" 2044 }, 2045 { 2046 "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", 2047 "Counter": "0,1,2,3", 2048 "EventCode": "0xB7, 0xBB", 2049 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", 2050 "MSRIndex": "0x1a6,0x1a7", 2051 "MSRValue": "0x7F04", 2052 "SampleAfterValue": "100000", 2053 "UMask": "0x1" 2054 }, 2055 { 2056 "BriefDescription": "All offcore demand code reads", 2057 "Counter": "0,1,2,3", 2058 "EventCode": "0xB7, 0xBB", 2059 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", 2060 "MSRIndex": "0x1a6,0x1a7", 2061 "MSRValue": "0xFF04", 2062 "SampleAfterValue": "100000", 2063 "UMask": "0x1" 2064 }, 2065 { 2066 "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", 2067 "Counter": "0,1,2,3", 2068 "EventCode": "0xB7, 0xBB", 2069 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", 2070 "MSRIndex": "0x1a6,0x1a7", 2071 "MSRValue": "0x8004", 2072 "SampleAfterValue": "100000", 2073 "UMask": "0x1" 2074 }, 2075 { 2076 "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", 2077 "Counter": "0,1,2,3", 2078 "EventCode": "0xB7, 0xBB", 2079 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", 2080 "MSRIndex": "0x1a6,0x1a7", 2081 "MSRValue": "0x104", 2082 "SampleAfterValue": "100000", 2083 "UMask": "0x1" 2084 }, 2085 { 2086 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", 2087 "Counter": "0,1,2,3", 2088 "EventCode": "0xB7, 0xBB", 2089 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2090 "MSRIndex": "0x1a6,0x1a7", 2091 "MSRValue": "0x204", 2092 "SampleAfterValue": "100000", 2093 "UMask": "0x1" 2094 }, 2095 { 2096 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", 2097 "Counter": "0,1,2,3", 2098 "EventCode": "0xB7, 0xBB", 2099 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2100 "MSRIndex": "0x1a6,0x1a7", 2101 "MSRValue": "0x404", 2102 "SampleAfterValue": "100000", 2103 "UMask": "0x1" 2104 }, 2105 { 2106 "BriefDescription": "Offcore demand code reads satisfied by the LLC", 2107 "Counter": "0,1,2,3", 2108 "EventCode": "0xB7, 0xBB", 2109 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", 2110 "MSRIndex": "0x1a6,0x1a7", 2111 "MSRValue": "0x704", 2112 "SampleAfterValue": "100000", 2113 "UMask": "0x1" 2114 }, 2115 { 2116 "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", 2117 "Counter": "0,1,2,3", 2118 "EventCode": "0xB7, 0xBB", 2119 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", 2120 "MSRIndex": "0x1a6,0x1a7", 2121 "MSRValue": "0x2704", 2122 "SampleAfterValue": "100000", 2123 "UMask": "0x1" 2124 }, 2125 { 2126 "BriefDescription": "Offcore demand code reads satisfied by a remote cache", 2127 "Counter": "0,1,2,3", 2128 "EventCode": "0xB7, 0xBB", 2129 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", 2130 "MSRIndex": "0x1a6,0x1a7", 2131 "MSRValue": "0x1804", 2132 "SampleAfterValue": "100000", 2133 "UMask": "0x1" 2134 }, 2135 { 2136 "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", 2137 "Counter": "0,1,2,3", 2138 "EventCode": "0xB7, 0xBB", 2139 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", 2140 "MSRIndex": "0x1a6,0x1a7", 2141 "MSRValue": "0x5804", 2142 "SampleAfterValue": "100000", 2143 "UMask": "0x1" 2144 }, 2145 { 2146 "BriefDescription": "Offcore demand code reads that HIT in a remote cache", 2147 "Counter": "0,1,2,3", 2148 "EventCode": "0xB7, 0xBB", 2149 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", 2150 "MSRIndex": "0x1a6,0x1a7", 2151 "MSRValue": "0x1004", 2152 "SampleAfterValue": "100000", 2153 "UMask": "0x1" 2154 }, 2155 { 2156 "BriefDescription": "Offcore demand code reads that HITM in a remote cache", 2157 "Counter": "0,1,2,3", 2158 "EventCode": "0xB7, 0xBB", 2159 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", 2160 "MSRIndex": "0x1a6,0x1a7", 2161 "MSRValue": "0x804", 2162 "SampleAfterValue": "100000", 2163 "UMask": "0x1" 2164 }, 2165 { 2166 "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", 2167 "Counter": "0,1,2,3", 2168 "EventCode": "0xB7, 0xBB", 2169 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", 2170 "MSRIndex": "0x1a6,0x1a7", 2171 "MSRValue": "0x7F02", 2172 "SampleAfterValue": "100000", 2173 "UMask": "0x1" 2174 }, 2175 { 2176 "BriefDescription": "All offcore demand RFO requests", 2177 "Counter": "0,1,2,3", 2178 "EventCode": "0xB7, 0xBB", 2179 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", 2180 "MSRIndex": "0x1a6,0x1a7", 2181 "MSRValue": "0xFF02", 2182 "SampleAfterValue": "100000", 2183 "UMask": "0x1" 2184 }, 2185 { 2186 "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", 2187 "Counter": "0,1,2,3", 2188 "EventCode": "0xB7, 0xBB", 2189 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", 2190 "MSRIndex": "0x1a6,0x1a7", 2191 "MSRValue": "0x8002", 2192 "SampleAfterValue": "100000", 2193 "UMask": "0x1" 2194 }, 2195 { 2196 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", 2197 "Counter": "0,1,2,3", 2198 "EventCode": "0xB7, 0xBB", 2199 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", 2200 "MSRIndex": "0x1a6,0x1a7", 2201 "MSRValue": "0x102", 2202 "SampleAfterValue": "100000", 2203 "UMask": "0x1" 2204 }, 2205 { 2206 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", 2207 "Counter": "0,1,2,3", 2208 "EventCode": "0xB7, 0xBB", 2209 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", 2210 "MSRIndex": "0x1a6,0x1a7", 2211 "MSRValue": "0x202", 2212 "SampleAfterValue": "100000", 2213 "UMask": "0x1" 2214 }, 2215 { 2216 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", 2217 "Counter": "0,1,2,3", 2218 "EventCode": "0xB7, 0xBB", 2219 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", 2220 "MSRIndex": "0x1a6,0x1a7", 2221 "MSRValue": "0x402", 2222 "SampleAfterValue": "100000", 2223 "UMask": "0x1" 2224 }, 2225 { 2226 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", 2227 "Counter": "0,1,2,3", 2228 "EventCode": "0xB7, 0xBB", 2229 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", 2230 "MSRIndex": "0x1a6,0x1a7", 2231 "MSRValue": "0x702", 2232 "SampleAfterValue": "100000", 2233 "UMask": "0x1" 2234 }, 2235 { 2236 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", 2237 "Counter": "0,1,2,3", 2238 "EventCode": "0xB7, 0xBB", 2239 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", 2240 "MSRIndex": "0x1a6,0x1a7", 2241 "MSRValue": "0x2702", 2242 "SampleAfterValue": "100000", 2243 "UMask": "0x1" 2244 }, 2245 { 2246 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", 2247 "Counter": "0,1,2,3", 2248 "EventCode": "0xB7, 0xBB", 2249 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", 2250 "MSRIndex": "0x1a6,0x1a7", 2251 "MSRValue": "0x1802", 2252 "SampleAfterValue": "100000", 2253 "UMask": "0x1" 2254 }, 2255 { 2256 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", 2257 "Counter": "0,1,2,3", 2258 "EventCode": "0xB7, 0xBB", 2259 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", 2260 "MSRIndex": "0x1a6,0x1a7", 2261 "MSRValue": "0x5802", 2262 "SampleAfterValue": "100000", 2263 "UMask": "0x1" 2264 }, 2265 { 2266 "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", 2267 "Counter": "0,1,2,3", 2268 "EventCode": "0xB7, 0xBB", 2269 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", 2270 "MSRIndex": "0x1a6,0x1a7", 2271 "MSRValue": "0x1002", 2272 "SampleAfterValue": "100000", 2273 "UMask": "0x1" 2274 }, 2275 { 2276 "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", 2277 "Counter": "0,1,2,3", 2278 "EventCode": "0xB7, 0xBB", 2279 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", 2280 "MSRIndex": "0x1a6,0x1a7", 2281 "MSRValue": "0x802", 2282 "SampleAfterValue": "100000", 2283 "UMask": "0x1" 2284 }, 2285 { 2286 "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", 2287 "Counter": "0,1,2,3", 2288 "EventCode": "0xB7, 0xBB", 2289 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", 2290 "MSRIndex": "0x1a6,0x1a7", 2291 "MSRValue": "0x7F80", 2292 "SampleAfterValue": "100000", 2293 "UMask": "0x1" 2294 }, 2295 { 2296 "BriefDescription": "All offcore other requests", 2297 "Counter": "0,1,2,3", 2298 "EventCode": "0xB7, 0xBB", 2299 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", 2300 "MSRIndex": "0x1a6,0x1a7", 2301 "MSRValue": "0xFF80", 2302 "SampleAfterValue": "100000", 2303 "UMask": "0x1" 2304 }, 2305 { 2306 "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", 2307 "Counter": "0,1,2,3", 2308 "EventCode": "0xB7, 0xBB", 2309 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", 2310 "MSRIndex": "0x1a6,0x1a7", 2311 "MSRValue": "0x8080", 2312 "SampleAfterValue": "100000", 2313 "UMask": "0x1" 2314 }, 2315 { 2316 "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", 2317 "Counter": "0,1,2,3", 2318 "EventCode": "0xB7, 0xBB", 2319 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", 2320 "MSRIndex": "0x1a6,0x1a7", 2321 "MSRValue": "0x180", 2322 "SampleAfterValue": "100000", 2323 "UMask": "0x1" 2324 }, 2325 { 2326 "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", 2327 "Counter": "0,1,2,3", 2328 "EventCode": "0xB7, 0xBB", 2329 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", 2330 "MSRIndex": "0x1a6,0x1a7", 2331 "MSRValue": "0x280", 2332 "SampleAfterValue": "100000", 2333 "UMask": "0x1" 2334 }, 2335 { 2336 "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", 2337 "Counter": "0,1,2,3", 2338 "EventCode": "0xB7, 0xBB", 2339 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", 2340 "MSRIndex": "0x1a6,0x1a7", 2341 "MSRValue": "0x480", 2342 "SampleAfterValue": "100000", 2343 "UMask": "0x1" 2344 }, 2345 { 2346 "BriefDescription": "Offcore other requests satisfied by the LLC", 2347 "Counter": "0,1,2,3", 2348 "EventCode": "0xB7, 0xBB", 2349 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", 2350 "MSRIndex": "0x1a6,0x1a7", 2351 "MSRValue": "0x780", 2352 "SampleAfterValue": "100000", 2353 "UMask": "0x1" 2354 }, 2355 { 2356 "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", 2357 "Counter": "0,1,2,3", 2358 "EventCode": "0xB7, 0xBB", 2359 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", 2360 "MSRIndex": "0x1a6,0x1a7", 2361 "MSRValue": "0x2780", 2362 "SampleAfterValue": "100000", 2363 "UMask": "0x1" 2364 }, 2365 { 2366 "BriefDescription": "Offcore other requests satisfied by a remote cache", 2367 "Counter": "0,1,2,3", 2368 "EventCode": "0xB7, 0xBB", 2369 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", 2370 "MSRIndex": "0x1a6,0x1a7", 2371 "MSRValue": "0x1880", 2372 "SampleAfterValue": "100000", 2373 "UMask": "0x1" 2374 }, 2375 { 2376 "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", 2377 "Counter": "0,1,2,3", 2378 "EventCode": "0xB7, 0xBB", 2379 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", 2380 "MSRIndex": "0x1a6,0x1a7", 2381 "MSRValue": "0x5880", 2382 "SampleAfterValue": "100000", 2383 "UMask": "0x1" 2384 }, 2385 { 2386 "BriefDescription": "Offcore other requests that HIT in a remote cache", 2387 "Counter": "0,1,2,3", 2388 "EventCode": "0xB7, 0xBB", 2389 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", 2390 "MSRIndex": "0x1a6,0x1a7", 2391 "MSRValue": "0x1080", 2392 "SampleAfterValue": "100000", 2393 "UMask": "0x1" 2394 }, 2395 { 2396 "BriefDescription": "Offcore other requests that HITM in a remote cache", 2397 "Counter": "0,1,2,3", 2398 "EventCode": "0xB7, 0xBB", 2399 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", 2400 "MSRIndex": "0x1a6,0x1a7", 2401 "MSRValue": "0x880", 2402 "SampleAfterValue": "100000", 2403 "UMask": "0x1" 2404 }, 2405 { 2406 "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", 2407 "Counter": "0,1,2,3", 2408 "EventCode": "0xB7, 0xBB", 2409 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", 2410 "MSRIndex": "0x1a6,0x1a7", 2411 "MSRValue": "0x7F50", 2412 "SampleAfterValue": "100000", 2413 "UMask": "0x1" 2414 }, 2415 { 2416 "BriefDescription": "All offcore prefetch data requests", 2417 "Counter": "0,1,2,3", 2418 "EventCode": "0xB7, 0xBB", 2419 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", 2420 "MSRIndex": "0x1a6,0x1a7", 2421 "MSRValue": "0xFF50", 2422 "SampleAfterValue": "100000", 2423 "UMask": "0x1" 2424 }, 2425 { 2426 "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", 2427 "Counter": "0,1,2,3", 2428 "EventCode": "0xB7, 0xBB", 2429 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", 2430 "MSRIndex": "0x1a6,0x1a7", 2431 "MSRValue": "0x8050", 2432 "SampleAfterValue": "100000", 2433 "UMask": "0x1" 2434 }, 2435 { 2436 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", 2437 "Counter": "0,1,2,3", 2438 "EventCode": "0xB7, 0xBB", 2439 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", 2440 "MSRIndex": "0x1a6,0x1a7", 2441 "MSRValue": "0x150", 2442 "SampleAfterValue": "100000", 2443 "UMask": "0x1" 2444 }, 2445 { 2446 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", 2447 "Counter": "0,1,2,3", 2448 "EventCode": "0xB7, 0xBB", 2449 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", 2450 "MSRIndex": "0x1a6,0x1a7", 2451 "MSRValue": "0x250", 2452 "SampleAfterValue": "100000", 2453 "UMask": "0x1" 2454 }, 2455 { 2456 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", 2457 "Counter": "0,1,2,3", 2458 "EventCode": "0xB7, 0xBB", 2459 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", 2460 "MSRIndex": "0x1a6,0x1a7", 2461 "MSRValue": "0x450", 2462 "SampleAfterValue": "100000", 2463 "UMask": "0x1" 2464 }, 2465 { 2466 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", 2467 "Counter": "0,1,2,3", 2468 "EventCode": "0xB7, 0xBB", 2469 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", 2470 "MSRIndex": "0x1a6,0x1a7", 2471 "MSRValue": "0x750", 2472 "SampleAfterValue": "100000", 2473 "UMask": "0x1" 2474 }, 2475 { 2476 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", 2477 "Counter": "0,1,2,3", 2478 "EventCode": "0xB7, 0xBB", 2479 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", 2480 "MSRIndex": "0x1a6,0x1a7", 2481 "MSRValue": "0x2750", 2482 "SampleAfterValue": "100000", 2483 "UMask": "0x1" 2484 }, 2485 { 2486 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", 2487 "Counter": "0,1,2,3", 2488 "EventCode": "0xB7, 0xBB", 2489 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", 2490 "MSRIndex": "0x1a6,0x1a7", 2491 "MSRValue": "0x1850", 2492 "SampleAfterValue": "100000", 2493 "UMask": "0x1" 2494 }, 2495 { 2496 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", 2497 "Counter": "0,1,2,3", 2498 "EventCode": "0xB7, 0xBB", 2499 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", 2500 "MSRIndex": "0x1a6,0x1a7", 2501 "MSRValue": "0x5850", 2502 "SampleAfterValue": "100000", 2503 "UMask": "0x1" 2504 }, 2505 { 2506 "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", 2507 "Counter": "0,1,2,3", 2508 "EventCode": "0xB7, 0xBB", 2509 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", 2510 "MSRIndex": "0x1a6,0x1a7", 2511 "MSRValue": "0x1050", 2512 "SampleAfterValue": "100000", 2513 "UMask": "0x1" 2514 }, 2515 { 2516 "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", 2517 "Counter": "0,1,2,3", 2518 "EventCode": "0xB7, 0xBB", 2519 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", 2520 "MSRIndex": "0x1a6,0x1a7", 2521 "MSRValue": "0x850", 2522 "SampleAfterValue": "100000", 2523 "UMask": "0x1" 2524 }, 2525 { 2526 "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", 2527 "Counter": "0,1,2,3", 2528 "EventCode": "0xB7, 0xBB", 2529 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", 2530 "MSRIndex": "0x1a6,0x1a7", 2531 "MSRValue": "0x7F10", 2532 "SampleAfterValue": "100000", 2533 "UMask": "0x1" 2534 }, 2535 { 2536 "BriefDescription": "All offcore prefetch data reads", 2537 "Counter": "0,1,2,3", 2538 "EventCode": "0xB7, 0xBB", 2539 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", 2540 "MSRIndex": "0x1a6,0x1a7", 2541 "MSRValue": "0xFF10", 2542 "SampleAfterValue": "100000", 2543 "UMask": "0x1" 2544 }, 2545 { 2546 "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", 2547 "Counter": "0,1,2,3", 2548 "EventCode": "0xB7, 0xBB", 2549 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", 2550 "MSRIndex": "0x1a6,0x1a7", 2551 "MSRValue": "0x8010", 2552 "SampleAfterValue": "100000", 2553 "UMask": "0x1" 2554 }, 2555 { 2556 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", 2557 "Counter": "0,1,2,3", 2558 "EventCode": "0xB7, 0xBB", 2559 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", 2560 "MSRIndex": "0x1a6,0x1a7", 2561 "MSRValue": "0x110", 2562 "SampleAfterValue": "100000", 2563 "UMask": "0x1" 2564 }, 2565 { 2566 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", 2567 "Counter": "0,1,2,3", 2568 "EventCode": "0xB7, 0xBB", 2569 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 2570 "MSRIndex": "0x1a6,0x1a7", 2571 "MSRValue": "0x210", 2572 "SampleAfterValue": "100000", 2573 "UMask": "0x1" 2574 }, 2575 { 2576 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", 2577 "Counter": "0,1,2,3", 2578 "EventCode": "0xB7, 0xBB", 2579 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2580 "MSRIndex": "0x1a6,0x1a7", 2581 "MSRValue": "0x410", 2582 "SampleAfterValue": "100000", 2583 "UMask": "0x1" 2584 }, 2585 { 2586 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", 2587 "Counter": "0,1,2,3", 2588 "EventCode": "0xB7, 0xBB", 2589 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", 2590 "MSRIndex": "0x1a6,0x1a7", 2591 "MSRValue": "0x710", 2592 "SampleAfterValue": "100000", 2593 "UMask": "0x1" 2594 }, 2595 { 2596 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", 2597 "Counter": "0,1,2,3", 2598 "EventCode": "0xB7, 0xBB", 2599 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", 2600 "MSRIndex": "0x1a6,0x1a7", 2601 "MSRValue": "0x2710", 2602 "SampleAfterValue": "100000", 2603 "UMask": "0x1" 2604 }, 2605 { 2606 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", 2607 "Counter": "0,1,2,3", 2608 "EventCode": "0xB7, 0xBB", 2609 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", 2610 "MSRIndex": "0x1a6,0x1a7", 2611 "MSRValue": "0x1810", 2612 "SampleAfterValue": "100000", 2613 "UMask": "0x1" 2614 }, 2615 { 2616 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", 2617 "Counter": "0,1,2,3", 2618 "EventCode": "0xB7, 0xBB", 2619 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", 2620 "MSRIndex": "0x1a6,0x1a7", 2621 "MSRValue": "0x5810", 2622 "SampleAfterValue": "100000", 2623 "UMask": "0x1" 2624 }, 2625 { 2626 "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", 2627 "Counter": "0,1,2,3", 2628 "EventCode": "0xB7, 0xBB", 2629 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", 2630 "MSRIndex": "0x1a6,0x1a7", 2631 "MSRValue": "0x1010", 2632 "SampleAfterValue": "100000", 2633 "UMask": "0x1" 2634 }, 2635 { 2636 "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", 2637 "Counter": "0,1,2,3", 2638 "EventCode": "0xB7, 0xBB", 2639 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", 2640 "MSRIndex": "0x1a6,0x1a7", 2641 "MSRValue": "0x810", 2642 "SampleAfterValue": "100000", 2643 "UMask": "0x1" 2644 }, 2645 { 2646 "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", 2647 "Counter": "0,1,2,3", 2648 "EventCode": "0xB7, 0xBB", 2649 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", 2650 "MSRIndex": "0x1a6,0x1a7", 2651 "MSRValue": "0x7F40", 2652 "SampleAfterValue": "100000", 2653 "UMask": "0x1" 2654 }, 2655 { 2656 "BriefDescription": "All offcore prefetch code reads", 2657 "Counter": "0,1,2,3", 2658 "EventCode": "0xB7, 0xBB", 2659 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", 2660 "MSRIndex": "0x1a6,0x1a7", 2661 "MSRValue": "0xFF40", 2662 "SampleAfterValue": "100000", 2663 "UMask": "0x1" 2664 }, 2665 { 2666 "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", 2667 "Counter": "0,1,2,3", 2668 "EventCode": "0xB7, 0xBB", 2669 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", 2670 "MSRIndex": "0x1a6,0x1a7", 2671 "MSRValue": "0x8040", 2672 "SampleAfterValue": "100000", 2673 "UMask": "0x1" 2674 }, 2675 { 2676 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", 2677 "Counter": "0,1,2,3", 2678 "EventCode": "0xB7, 0xBB", 2679 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", 2680 "MSRIndex": "0x1a6,0x1a7", 2681 "MSRValue": "0x140", 2682 "SampleAfterValue": "100000", 2683 "UMask": "0x1" 2684 }, 2685 { 2686 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", 2687 "Counter": "0,1,2,3", 2688 "EventCode": "0xB7, 0xBB", 2689 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2690 "MSRIndex": "0x1a6,0x1a7", 2691 "MSRValue": "0x240", 2692 "SampleAfterValue": "100000", 2693 "UMask": "0x1" 2694 }, 2695 { 2696 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", 2697 "Counter": "0,1,2,3", 2698 "EventCode": "0xB7, 0xBB", 2699 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2700 "MSRIndex": "0x1a6,0x1a7", 2701 "MSRValue": "0x440", 2702 "SampleAfterValue": "100000", 2703 "UMask": "0x1" 2704 }, 2705 { 2706 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", 2707 "Counter": "0,1,2,3", 2708 "EventCode": "0xB7, 0xBB", 2709 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", 2710 "MSRIndex": "0x1a6,0x1a7", 2711 "MSRValue": "0x740", 2712 "SampleAfterValue": "100000", 2713 "UMask": "0x1" 2714 }, 2715 { 2716 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", 2717 "Counter": "0,1,2,3", 2718 "EventCode": "0xB7, 0xBB", 2719 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", 2720 "MSRIndex": "0x1a6,0x1a7", 2721 "MSRValue": "0x2740", 2722 "SampleAfterValue": "100000", 2723 "UMask": "0x1" 2724 }, 2725 { 2726 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", 2727 "Counter": "0,1,2,3", 2728 "EventCode": "0xB7, 0xBB", 2729 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", 2730 "MSRIndex": "0x1a6,0x1a7", 2731 "MSRValue": "0x1840", 2732 "SampleAfterValue": "100000", 2733 "UMask": "0x1" 2734 }, 2735 { 2736 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", 2737 "Counter": "0,1,2,3", 2738 "EventCode": "0xB7, 0xBB", 2739 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", 2740 "MSRIndex": "0x1a6,0x1a7", 2741 "MSRValue": "0x5840", 2742 "SampleAfterValue": "100000", 2743 "UMask": "0x1" 2744 }, 2745 { 2746 "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", 2747 "Counter": "0,1,2,3", 2748 "EventCode": "0xB7, 0xBB", 2749 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", 2750 "MSRIndex": "0x1a6,0x1a7", 2751 "MSRValue": "0x1040", 2752 "SampleAfterValue": "100000", 2753 "UMask": "0x1" 2754 }, 2755 { 2756 "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", 2757 "Counter": "0,1,2,3", 2758 "EventCode": "0xB7, 0xBB", 2759 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", 2760 "MSRIndex": "0x1a6,0x1a7", 2761 "MSRValue": "0x840", 2762 "SampleAfterValue": "100000", 2763 "UMask": "0x1" 2764 }, 2765 { 2766 "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", 2767 "Counter": "0,1,2,3", 2768 "EventCode": "0xB7, 0xBB", 2769 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", 2770 "MSRIndex": "0x1a6,0x1a7", 2771 "MSRValue": "0x7F20", 2772 "SampleAfterValue": "100000", 2773 "UMask": "0x1" 2774 }, 2775 { 2776 "BriefDescription": "All offcore prefetch RFO requests", 2777 "Counter": "0,1,2,3", 2778 "EventCode": "0xB7, 0xBB", 2779 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", 2780 "MSRIndex": "0x1a6,0x1a7", 2781 "MSRValue": "0xFF20", 2782 "SampleAfterValue": "100000", 2783 "UMask": "0x1" 2784 }, 2785 { 2786 "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", 2787 "Counter": "0,1,2,3", 2788 "EventCode": "0xB7, 0xBB", 2789 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", 2790 "MSRIndex": "0x1a6,0x1a7", 2791 "MSRValue": "0x8020", 2792 "SampleAfterValue": "100000", 2793 "UMask": "0x1" 2794 }, 2795 { 2796 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", 2797 "Counter": "0,1,2,3", 2798 "EventCode": "0xB7, 0xBB", 2799 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", 2800 "MSRIndex": "0x1a6,0x1a7", 2801 "MSRValue": "0x120", 2802 "SampleAfterValue": "100000", 2803 "UMask": "0x1" 2804 }, 2805 { 2806 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", 2807 "Counter": "0,1,2,3", 2808 "EventCode": "0xB7, 0xBB", 2809 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", 2810 "MSRIndex": "0x1a6,0x1a7", 2811 "MSRValue": "0x220", 2812 "SampleAfterValue": "100000", 2813 "UMask": "0x1" 2814 }, 2815 { 2816 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", 2817 "Counter": "0,1,2,3", 2818 "EventCode": "0xB7, 0xBB", 2819 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", 2820 "MSRIndex": "0x1a6,0x1a7", 2821 "MSRValue": "0x420", 2822 "SampleAfterValue": "100000", 2823 "UMask": "0x1" 2824 }, 2825 { 2826 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", 2827 "Counter": "0,1,2,3", 2828 "EventCode": "0xB7, 0xBB", 2829 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", 2830 "MSRIndex": "0x1a6,0x1a7", 2831 "MSRValue": "0x720", 2832 "SampleAfterValue": "100000", 2833 "UMask": "0x1" 2834 }, 2835 { 2836 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", 2837 "Counter": "0,1,2,3", 2838 "EventCode": "0xB7, 0xBB", 2839 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", 2840 "MSRIndex": "0x1a6,0x1a7", 2841 "MSRValue": "0x2720", 2842 "SampleAfterValue": "100000", 2843 "UMask": "0x1" 2844 }, 2845 { 2846 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", 2847 "Counter": "0,1,2,3", 2848 "EventCode": "0xB7, 0xBB", 2849 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", 2850 "MSRIndex": "0x1a6,0x1a7", 2851 "MSRValue": "0x1820", 2852 "SampleAfterValue": "100000", 2853 "UMask": "0x1" 2854 }, 2855 { 2856 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", 2857 "Counter": "0,1,2,3", 2858 "EventCode": "0xB7, 0xBB", 2859 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", 2860 "MSRIndex": "0x1a6,0x1a7", 2861 "MSRValue": "0x5820", 2862 "SampleAfterValue": "100000", 2863 "UMask": "0x1" 2864 }, 2865 { 2866 "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", 2867 "Counter": "0,1,2,3", 2868 "EventCode": "0xB7, 0xBB", 2869 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", 2870 "MSRIndex": "0x1a6,0x1a7", 2871 "MSRValue": "0x1020", 2872 "SampleAfterValue": "100000", 2873 "UMask": "0x1" 2874 }, 2875 { 2876 "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", 2877 "Counter": "0,1,2,3", 2878 "EventCode": "0xB7, 0xBB", 2879 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", 2880 "MSRIndex": "0x1a6,0x1a7", 2881 "MSRValue": "0x820", 2882 "SampleAfterValue": "100000", 2883 "UMask": "0x1" 2884 }, 2885 { 2886 "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", 2887 "Counter": "0,1,2,3", 2888 "EventCode": "0xB7, 0xBB", 2889 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", 2890 "MSRIndex": "0x1a6,0x1a7", 2891 "MSRValue": "0x7F70", 2892 "SampleAfterValue": "100000", 2893 "UMask": "0x1" 2894 }, 2895 { 2896 "BriefDescription": "All offcore prefetch requests", 2897 "Counter": "0,1,2,3", 2898 "EventCode": "0xB7, 0xBB", 2899 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", 2900 "MSRIndex": "0x1a6,0x1a7", 2901 "MSRValue": "0xFF70", 2902 "SampleAfterValue": "100000", 2903 "UMask": "0x1" 2904 }, 2905 { 2906 "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", 2907 "Counter": "0,1,2,3", 2908 "EventCode": "0xB7, 0xBB", 2909 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", 2910 "MSRIndex": "0x1a6,0x1a7", 2911 "MSRValue": "0x8070", 2912 "SampleAfterValue": "100000", 2913 "UMask": "0x1" 2914 }, 2915 { 2916 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", 2917 "Counter": "0,1,2,3", 2918 "EventCode": "0xB7, 0xBB", 2919 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", 2920 "MSRIndex": "0x1a6,0x1a7", 2921 "MSRValue": "0x170", 2922 "SampleAfterValue": "100000", 2923 "UMask": "0x1" 2924 }, 2925 { 2926 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", 2927 "Counter": "0,1,2,3", 2928 "EventCode": "0xB7, 0xBB", 2929 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", 2930 "MSRIndex": "0x1a6,0x1a7", 2931 "MSRValue": "0x270", 2932 "SampleAfterValue": "100000", 2933 "UMask": "0x1" 2934 }, 2935 { 2936 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", 2937 "Counter": "0,1,2,3", 2938 "EventCode": "0xB7, 0xBB", 2939 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", 2940 "MSRIndex": "0x1a6,0x1a7", 2941 "MSRValue": "0x470", 2942 "SampleAfterValue": "100000", 2943 "UMask": "0x1" 2944 }, 2945 { 2946 "BriefDescription": "Offcore prefetch requests satisfied by the LLC", 2947 "Counter": "0,1,2,3", 2948 "EventCode": "0xB7, 0xBB", 2949 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", 2950 "MSRIndex": "0x1a6,0x1a7", 2951 "MSRValue": "0x770", 2952 "SampleAfterValue": "100000", 2953 "UMask": "0x1" 2954 }, 2955 { 2956 "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", 2957 "Counter": "0,1,2,3", 2958 "EventCode": "0xB7, 0xBB", 2959 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", 2960 "MSRIndex": "0x1a6,0x1a7", 2961 "MSRValue": "0x2770", 2962 "SampleAfterValue": "100000", 2963 "UMask": "0x1" 2964 }, 2965 { 2966 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", 2967 "Counter": "0,1,2,3", 2968 "EventCode": "0xB7, 0xBB", 2969 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", 2970 "MSRIndex": "0x1a6,0x1a7", 2971 "MSRValue": "0x1870", 2972 "SampleAfterValue": "100000", 2973 "UMask": "0x1" 2974 }, 2975 { 2976 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", 2977 "Counter": "0,1,2,3", 2978 "EventCode": "0xB7, 0xBB", 2979 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", 2980 "MSRIndex": "0x1a6,0x1a7", 2981 "MSRValue": "0x5870", 2982 "SampleAfterValue": "100000", 2983 "UMask": "0x1" 2984 }, 2985 { 2986 "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", 2987 "Counter": "0,1,2,3", 2988 "EventCode": "0xB7, 0xBB", 2989 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", 2990 "MSRIndex": "0x1a6,0x1a7", 2991 "MSRValue": "0x1070", 2992 "SampleAfterValue": "100000", 2993 "UMask": "0x1" 2994 }, 2995 { 2996 "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", 2997 "Counter": "0,1,2,3", 2998 "EventCode": "0xB7, 0xBB", 2999 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", 3000 "MSRIndex": "0x1a6,0x1a7", 3001 "MSRValue": "0x870", 3002 "SampleAfterValue": "100000", 3003 "UMask": "0x1" 3004 }, 3005 { 3006 "BriefDescription": "Super Queue LRU hints sent to LLC", 3007 "Counter": "0,1,2,3", 3008 "EventCode": "0xF4", 3009 "EventName": "SQ_MISC.LRU_HINTS", 3010 "SampleAfterValue": "2000000", 3011 "UMask": "0x4" 3012 }, 3013 { 3014 "BriefDescription": "Super Queue lock splits across a cache line", 3015 "Counter": "0,1,2,3", 3016 "EventCode": "0xF4", 3017 "EventName": "SQ_MISC.SPLIT_LOCK", 3018 "SampleAfterValue": "2000000", 3019 "UMask": "0x10" 3020 }, 3021 { 3022 "BriefDescription": "Loads delayed with at-Retirement block code", 3023 "Counter": "0,1,2,3", 3024 "EventCode": "0x6", 3025 "EventName": "STORE_BLOCKS.AT_RET", 3026 "SampleAfterValue": "200000", 3027 "UMask": "0x4" 3028 }, 3029 { 3030 "BriefDescription": "Cacheable loads delayed with L1D block code", 3031 "Counter": "0,1,2,3", 3032 "EventCode": "0x6", 3033 "EventName": "STORE_BLOCKS.L1D_BLOCK", 3034 "SampleAfterValue": "200000", 3035 "UMask": "0x8" 3036 } 3037] 3038