1[ 2 { 3 "BriefDescription": "Cycles L1D locked", 4 "Counter": "0,1", 5 "EventCode": "0x63", 6 "EventName": "CACHE_LOCK_CYCLES.L1D", 7 "SampleAfterValue": "2000000", 8 "UMask": "0x2" 9 }, 10 { 11 "BriefDescription": "Cycles L1D and L2 locked", 12 "Counter": "0,1", 13 "EventCode": "0x63", 14 "EventName": "CACHE_LOCK_CYCLES.L1D_L2", 15 "SampleAfterValue": "2000000", 16 "UMask": "0x1" 17 }, 18 { 19 "BriefDescription": "L1D cache lines replaced in M state", 20 "Counter": "0,1", 21 "EventCode": "0x51", 22 "EventName": "L1D.M_EVICT", 23 "SampleAfterValue": "2000000", 24 "UMask": "0x4" 25 }, 26 { 27 "BriefDescription": "L1D cache lines allocated in the M state", 28 "Counter": "0,1", 29 "EventCode": "0x51", 30 "EventName": "L1D.M_REPL", 31 "SampleAfterValue": "2000000", 32 "UMask": "0x2" 33 }, 34 { 35 "BriefDescription": "L1D snoop eviction of cache lines in M state", 36 "Counter": "0,1", 37 "EventCode": "0x51", 38 "EventName": "L1D.M_SNOOP_EVICT", 39 "SampleAfterValue": "2000000", 40 "UMask": "0x8" 41 }, 42 { 43 "BriefDescription": "L1 data cache lines allocated", 44 "Counter": "0,1", 45 "EventCode": "0x51", 46 "EventName": "L1D.REPL", 47 "SampleAfterValue": "2000000", 48 "UMask": "0x1" 49 }, 50 { 51 "BriefDescription": "L1D prefetch load lock accepted in fill buffer", 52 "Counter": "0,1", 53 "EventCode": "0x52", 54 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", 55 "SampleAfterValue": "2000000", 56 "UMask": "0x1" 57 }, 58 { 59 "BriefDescription": "L1D hardware prefetch misses", 60 "Counter": "0,1", 61 "EventCode": "0x4E", 62 "EventName": "L1D_PREFETCH.MISS", 63 "SampleAfterValue": "200000", 64 "UMask": "0x2" 65 }, 66 { 67 "BriefDescription": "L1D hardware prefetch requests", 68 "Counter": "0,1", 69 "EventCode": "0x4E", 70 "EventName": "L1D_PREFETCH.REQUESTS", 71 "SampleAfterValue": "200000", 72 "UMask": "0x1" 73 }, 74 { 75 "BriefDescription": "L1D hardware prefetch requests triggered", 76 "Counter": "0,1", 77 "EventCode": "0x4E", 78 "EventName": "L1D_PREFETCH.TRIGGERS", 79 "SampleAfterValue": "200000", 80 "UMask": "0x4" 81 }, 82 { 83 "BriefDescription": "L1 writebacks to L2 in E state", 84 "Counter": "0,1,2,3", 85 "EventCode": "0x28", 86 "EventName": "L1D_WB_L2.E_STATE", 87 "SampleAfterValue": "100000", 88 "UMask": "0x4" 89 }, 90 { 91 "BriefDescription": "L1 writebacks to L2 in I state (misses)", 92 "Counter": "0,1,2,3", 93 "EventCode": "0x28", 94 "EventName": "L1D_WB_L2.I_STATE", 95 "SampleAfterValue": "100000", 96 "UMask": "0x1" 97 }, 98 { 99 "BriefDescription": "All L1 writebacks to L2", 100 "Counter": "0,1,2,3", 101 "EventCode": "0x28", 102 "EventName": "L1D_WB_L2.MESI", 103 "SampleAfterValue": "100000", 104 "UMask": "0xf" 105 }, 106 { 107 "BriefDescription": "L1 writebacks to L2 in M state", 108 "Counter": "0,1,2,3", 109 "EventCode": "0x28", 110 "EventName": "L1D_WB_L2.M_STATE", 111 "SampleAfterValue": "100000", 112 "UMask": "0x8" 113 }, 114 { 115 "BriefDescription": "L1 writebacks to L2 in S state", 116 "Counter": "0,1,2,3", 117 "EventCode": "0x28", 118 "EventName": "L1D_WB_L2.S_STATE", 119 "SampleAfterValue": "100000", 120 "UMask": "0x2" 121 }, 122 { 123 "BriefDescription": "All L2 data requests", 124 "Counter": "0,1,2,3", 125 "EventCode": "0x26", 126 "EventName": "L2_DATA_RQSTS.ANY", 127 "SampleAfterValue": "200000", 128 "UMask": "0xff" 129 }, 130 { 131 "BriefDescription": "L2 data demand loads in E state", 132 "Counter": "0,1,2,3", 133 "EventCode": "0x26", 134 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", 135 "SampleAfterValue": "200000", 136 "UMask": "0x4" 137 }, 138 { 139 "BriefDescription": "L2 data demand loads in I state (misses)", 140 "Counter": "0,1,2,3", 141 "EventCode": "0x26", 142 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", 143 "SampleAfterValue": "200000", 144 "UMask": "0x1" 145 }, 146 { 147 "BriefDescription": "L2 data demand requests", 148 "Counter": "0,1,2,3", 149 "EventCode": "0x26", 150 "EventName": "L2_DATA_RQSTS.DEMAND.MESI", 151 "SampleAfterValue": "200000", 152 "UMask": "0xf" 153 }, 154 { 155 "BriefDescription": "L2 data demand loads in M state", 156 "Counter": "0,1,2,3", 157 "EventCode": "0x26", 158 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", 159 "SampleAfterValue": "200000", 160 "UMask": "0x8" 161 }, 162 { 163 "BriefDescription": "L2 data demand loads in S state", 164 "Counter": "0,1,2,3", 165 "EventCode": "0x26", 166 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", 167 "SampleAfterValue": "200000", 168 "UMask": "0x2" 169 }, 170 { 171 "BriefDescription": "L2 data prefetches in E state", 172 "Counter": "0,1,2,3", 173 "EventCode": "0x26", 174 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", 175 "SampleAfterValue": "200000", 176 "UMask": "0x40" 177 }, 178 { 179 "BriefDescription": "L2 data prefetches in the I state (misses)", 180 "Counter": "0,1,2,3", 181 "EventCode": "0x26", 182 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", 183 "SampleAfterValue": "200000", 184 "UMask": "0x10" 185 }, 186 { 187 "BriefDescription": "All L2 data prefetches", 188 "Counter": "0,1,2,3", 189 "EventCode": "0x26", 190 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", 191 "SampleAfterValue": "200000", 192 "UMask": "0xf0" 193 }, 194 { 195 "BriefDescription": "L2 data prefetches in M state", 196 "Counter": "0,1,2,3", 197 "EventCode": "0x26", 198 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", 199 "SampleAfterValue": "200000", 200 "UMask": "0x80" 201 }, 202 { 203 "BriefDescription": "L2 data prefetches in the S state", 204 "Counter": "0,1,2,3", 205 "EventCode": "0x26", 206 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", 207 "SampleAfterValue": "200000", 208 "UMask": "0x20" 209 }, 210 { 211 "BriefDescription": "L2 lines allocated", 212 "Counter": "0,1,2,3", 213 "EventCode": "0xF1", 214 "EventName": "L2_LINES_IN.ANY", 215 "SampleAfterValue": "100000", 216 "UMask": "0x7" 217 }, 218 { 219 "BriefDescription": "L2 lines allocated in the E state", 220 "Counter": "0,1,2,3", 221 "EventCode": "0xF1", 222 "EventName": "L2_LINES_IN.E_STATE", 223 "SampleAfterValue": "100000", 224 "UMask": "0x4" 225 }, 226 { 227 "BriefDescription": "L2 lines allocated in the S state", 228 "Counter": "0,1,2,3", 229 "EventCode": "0xF1", 230 "EventName": "L2_LINES_IN.S_STATE", 231 "SampleAfterValue": "100000", 232 "UMask": "0x2" 233 }, 234 { 235 "BriefDescription": "L2 lines evicted", 236 "Counter": "0,1,2,3", 237 "EventCode": "0xF2", 238 "EventName": "L2_LINES_OUT.ANY", 239 "SampleAfterValue": "100000", 240 "UMask": "0xf" 241 }, 242 { 243 "BriefDescription": "L2 lines evicted by a demand request", 244 "Counter": "0,1,2,3", 245 "EventCode": "0xF2", 246 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 247 "SampleAfterValue": "100000", 248 "UMask": "0x1" 249 }, 250 { 251 "BriefDescription": "L2 modified lines evicted by a demand request", 252 "Counter": "0,1,2,3", 253 "EventCode": "0xF2", 254 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 255 "SampleAfterValue": "100000", 256 "UMask": "0x2" 257 }, 258 { 259 "BriefDescription": "L2 lines evicted by a prefetch request", 260 "Counter": "0,1,2,3", 261 "EventCode": "0xF2", 262 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", 263 "SampleAfterValue": "100000", 264 "UMask": "0x4" 265 }, 266 { 267 "BriefDescription": "L2 modified lines evicted by a prefetch request", 268 "Counter": "0,1,2,3", 269 "EventCode": "0xF2", 270 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", 271 "SampleAfterValue": "100000", 272 "UMask": "0x8" 273 }, 274 { 275 "BriefDescription": "L2 instruction fetches", 276 "Counter": "0,1,2,3", 277 "EventCode": "0x24", 278 "EventName": "L2_RQSTS.IFETCHES", 279 "SampleAfterValue": "200000", 280 "UMask": "0x30" 281 }, 282 { 283 "BriefDescription": "L2 instruction fetch hits", 284 "Counter": "0,1,2,3", 285 "EventCode": "0x24", 286 "EventName": "L2_RQSTS.IFETCH_HIT", 287 "SampleAfterValue": "200000", 288 "UMask": "0x10" 289 }, 290 { 291 "BriefDescription": "L2 instruction fetch misses", 292 "Counter": "0,1,2,3", 293 "EventCode": "0x24", 294 "EventName": "L2_RQSTS.IFETCH_MISS", 295 "SampleAfterValue": "200000", 296 "UMask": "0x20" 297 }, 298 { 299 "BriefDescription": "L2 load hits", 300 "Counter": "0,1,2,3", 301 "EventCode": "0x24", 302 "EventName": "L2_RQSTS.LD_HIT", 303 "SampleAfterValue": "200000", 304 "UMask": "0x1" 305 }, 306 { 307 "BriefDescription": "L2 load misses", 308 "Counter": "0,1,2,3", 309 "EventCode": "0x24", 310 "EventName": "L2_RQSTS.LD_MISS", 311 "SampleAfterValue": "200000", 312 "UMask": "0x2" 313 }, 314 { 315 "BriefDescription": "L2 requests", 316 "Counter": "0,1,2,3", 317 "EventCode": "0x24", 318 "EventName": "L2_RQSTS.LOADS", 319 "SampleAfterValue": "200000", 320 "UMask": "0x3" 321 }, 322 { 323 "BriefDescription": "All L2 misses", 324 "Counter": "0,1,2,3", 325 "EventCode": "0x24", 326 "EventName": "L2_RQSTS.MISS", 327 "SampleAfterValue": "200000", 328 "UMask": "0xaa" 329 }, 330 { 331 "BriefDescription": "All L2 prefetches", 332 "Counter": "0,1,2,3", 333 "EventCode": "0x24", 334 "EventName": "L2_RQSTS.PREFETCHES", 335 "SampleAfterValue": "200000", 336 "UMask": "0xc0" 337 }, 338 { 339 "BriefDescription": "L2 prefetch hits", 340 "Counter": "0,1,2,3", 341 "EventCode": "0x24", 342 "EventName": "L2_RQSTS.PREFETCH_HIT", 343 "SampleAfterValue": "200000", 344 "UMask": "0x40" 345 }, 346 { 347 "BriefDescription": "L2 prefetch misses", 348 "Counter": "0,1,2,3", 349 "EventCode": "0x24", 350 "EventName": "L2_RQSTS.PREFETCH_MISS", 351 "SampleAfterValue": "200000", 352 "UMask": "0x80" 353 }, 354 { 355 "BriefDescription": "All L2 requests", 356 "Counter": "0,1,2,3", 357 "EventCode": "0x24", 358 "EventName": "L2_RQSTS.REFERENCES", 359 "SampleAfterValue": "200000", 360 "UMask": "0xff" 361 }, 362 { 363 "BriefDescription": "L2 RFO requests", 364 "Counter": "0,1,2,3", 365 "EventCode": "0x24", 366 "EventName": "L2_RQSTS.RFOS", 367 "SampleAfterValue": "200000", 368 "UMask": "0xc" 369 }, 370 { 371 "BriefDescription": "L2 RFO hits", 372 "Counter": "0,1,2,3", 373 "EventCode": "0x24", 374 "EventName": "L2_RQSTS.RFO_HIT", 375 "SampleAfterValue": "200000", 376 "UMask": "0x4" 377 }, 378 { 379 "BriefDescription": "L2 RFO misses", 380 "Counter": "0,1,2,3", 381 "EventCode": "0x24", 382 "EventName": "L2_RQSTS.RFO_MISS", 383 "SampleAfterValue": "200000", 384 "UMask": "0x8" 385 }, 386 { 387 "BriefDescription": "All L2 transactions", 388 "Counter": "0,1,2,3", 389 "EventCode": "0xF0", 390 "EventName": "L2_TRANSACTIONS.ANY", 391 "SampleAfterValue": "200000", 392 "UMask": "0x80" 393 }, 394 { 395 "BriefDescription": "L2 fill transactions", 396 "Counter": "0,1,2,3", 397 "EventCode": "0xF0", 398 "EventName": "L2_TRANSACTIONS.FILL", 399 "SampleAfterValue": "200000", 400 "UMask": "0x20" 401 }, 402 { 403 "BriefDescription": "L2 instruction fetch transactions", 404 "Counter": "0,1,2,3", 405 "EventCode": "0xF0", 406 "EventName": "L2_TRANSACTIONS.IFETCH", 407 "SampleAfterValue": "200000", 408 "UMask": "0x4" 409 }, 410 { 411 "BriefDescription": "L1D writeback to L2 transactions", 412 "Counter": "0,1,2,3", 413 "EventCode": "0xF0", 414 "EventName": "L2_TRANSACTIONS.L1D_WB", 415 "SampleAfterValue": "200000", 416 "UMask": "0x10" 417 }, 418 { 419 "BriefDescription": "L2 Load transactions", 420 "Counter": "0,1,2,3", 421 "EventCode": "0xF0", 422 "EventName": "L2_TRANSACTIONS.LOAD", 423 "SampleAfterValue": "200000", 424 "UMask": "0x1" 425 }, 426 { 427 "BriefDescription": "L2 prefetch transactions", 428 "Counter": "0,1,2,3", 429 "EventCode": "0xF0", 430 "EventName": "L2_TRANSACTIONS.PREFETCH", 431 "SampleAfterValue": "200000", 432 "UMask": "0x8" 433 }, 434 { 435 "BriefDescription": "L2 RFO transactions", 436 "Counter": "0,1,2,3", 437 "EventCode": "0xF0", 438 "EventName": "L2_TRANSACTIONS.RFO", 439 "SampleAfterValue": "200000", 440 "UMask": "0x2" 441 }, 442 { 443 "BriefDescription": "L2 writeback to LLC transactions", 444 "Counter": "0,1,2,3", 445 "EventCode": "0xF0", 446 "EventName": "L2_TRANSACTIONS.WB", 447 "SampleAfterValue": "200000", 448 "UMask": "0x40" 449 }, 450 { 451 "BriefDescription": "L2 demand lock RFOs in E state", 452 "Counter": "0,1,2,3", 453 "EventCode": "0x27", 454 "EventName": "L2_WRITE.LOCK.E_STATE", 455 "SampleAfterValue": "100000", 456 "UMask": "0x40" 457 }, 458 { 459 "BriefDescription": "All demand L2 lock RFOs that hit the cache", 460 "Counter": "0,1,2,3", 461 "EventCode": "0x27", 462 "EventName": "L2_WRITE.LOCK.HIT", 463 "SampleAfterValue": "100000", 464 "UMask": "0xe0" 465 }, 466 { 467 "BriefDescription": "L2 demand lock RFOs in I state (misses)", 468 "Counter": "0,1,2,3", 469 "EventCode": "0x27", 470 "EventName": "L2_WRITE.LOCK.I_STATE", 471 "SampleAfterValue": "100000", 472 "UMask": "0x10" 473 }, 474 { 475 "BriefDescription": "All demand L2 lock RFOs", 476 "Counter": "0,1,2,3", 477 "EventCode": "0x27", 478 "EventName": "L2_WRITE.LOCK.MESI", 479 "SampleAfterValue": "100000", 480 "UMask": "0xf0" 481 }, 482 { 483 "BriefDescription": "L2 demand lock RFOs in M state", 484 "Counter": "0,1,2,3", 485 "EventCode": "0x27", 486 "EventName": "L2_WRITE.LOCK.M_STATE", 487 "SampleAfterValue": "100000", 488 "UMask": "0x80" 489 }, 490 { 491 "BriefDescription": "L2 demand lock RFOs in S state", 492 "Counter": "0,1,2,3", 493 "EventCode": "0x27", 494 "EventName": "L2_WRITE.LOCK.S_STATE", 495 "SampleAfterValue": "100000", 496 "UMask": "0x20" 497 }, 498 { 499 "BriefDescription": "All L2 demand store RFOs that hit the cache", 500 "Counter": "0,1,2,3", 501 "EventCode": "0x27", 502 "EventName": "L2_WRITE.RFO.HIT", 503 "SampleAfterValue": "100000", 504 "UMask": "0xe" 505 }, 506 { 507 "BriefDescription": "L2 demand store RFOs in I state (misses)", 508 "Counter": "0,1,2,3", 509 "EventCode": "0x27", 510 "EventName": "L2_WRITE.RFO.I_STATE", 511 "SampleAfterValue": "100000", 512 "UMask": "0x1" 513 }, 514 { 515 "BriefDescription": "All L2 demand store RFOs", 516 "Counter": "0,1,2,3", 517 "EventCode": "0x27", 518 "EventName": "L2_WRITE.RFO.MESI", 519 "SampleAfterValue": "100000", 520 "UMask": "0xf" 521 }, 522 { 523 "BriefDescription": "L2 demand store RFOs in M state", 524 "Counter": "0,1,2,3", 525 "EventCode": "0x27", 526 "EventName": "L2_WRITE.RFO.M_STATE", 527 "SampleAfterValue": "100000", 528 "UMask": "0x8" 529 }, 530 { 531 "BriefDescription": "L2 demand store RFOs in S state", 532 "Counter": "0,1,2,3", 533 "EventCode": "0x27", 534 "EventName": "L2_WRITE.RFO.S_STATE", 535 "SampleAfterValue": "100000", 536 "UMask": "0x2" 537 }, 538 { 539 "BriefDescription": "Longest latency cache miss", 540 "Counter": "0,1,2,3", 541 "EventCode": "0x2E", 542 "EventName": "LONGEST_LAT_CACHE.MISS", 543 "SampleAfterValue": "100000", 544 "UMask": "0x41" 545 }, 546 { 547 "BriefDescription": "Longest latency cache reference", 548 "Counter": "0,1,2,3", 549 "EventCode": "0x2E", 550 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 551 "SampleAfterValue": "200000", 552 "UMask": "0x4f" 553 }, 554 { 555 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", 556 "Counter": "3", 557 "EventCode": "0xB", 558 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", 559 "MSRIndex": "0x3F6", 560 "PEBS": "2", 561 "SampleAfterValue": "2000000", 562 "UMask": "0x10" 563 }, 564 { 565 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", 566 "Counter": "3", 567 "EventCode": "0xB", 568 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", 569 "MSRIndex": "0x3F6", 570 "MSRValue": "0x400", 571 "PEBS": "2", 572 "SampleAfterValue": "100", 573 "UMask": "0x10" 574 }, 575 { 576 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", 577 "Counter": "3", 578 "EventCode": "0xB", 579 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", 580 "MSRIndex": "0x3F6", 581 "MSRValue": "0x80", 582 "PEBS": "2", 583 "SampleAfterValue": "1000", 584 "UMask": "0x10" 585 }, 586 { 587 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", 588 "Counter": "3", 589 "EventCode": "0xB", 590 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", 591 "MSRIndex": "0x3F6", 592 "MSRValue": "0x10", 593 "PEBS": "2", 594 "SampleAfterValue": "10000", 595 "UMask": "0x10" 596 }, 597 { 598 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", 599 "Counter": "3", 600 "EventCode": "0xB", 601 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", 602 "MSRIndex": "0x3F6", 603 "MSRValue": "0x4000", 604 "PEBS": "2", 605 "SampleAfterValue": "5", 606 "UMask": "0x10" 607 }, 608 { 609 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", 610 "Counter": "3", 611 "EventCode": "0xB", 612 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", 613 "MSRIndex": "0x3F6", 614 "MSRValue": "0x800", 615 "PEBS": "2", 616 "SampleAfterValue": "50", 617 "UMask": "0x10" 618 }, 619 { 620 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", 621 "Counter": "3", 622 "EventCode": "0xB", 623 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", 624 "MSRIndex": "0x3F6", 625 "MSRValue": "0x100", 626 "PEBS": "2", 627 "SampleAfterValue": "500", 628 "UMask": "0x10" 629 }, 630 { 631 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", 632 "Counter": "3", 633 "EventCode": "0xB", 634 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", 635 "MSRIndex": "0x3F6", 636 "MSRValue": "0x20", 637 "PEBS": "2", 638 "SampleAfterValue": "5000", 639 "UMask": "0x10" 640 }, 641 { 642 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", 643 "Counter": "3", 644 "EventCode": "0xB", 645 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", 646 "MSRIndex": "0x3F6", 647 "MSRValue": "0x8000", 648 "PEBS": "2", 649 "SampleAfterValue": "3", 650 "UMask": "0x10" 651 }, 652 { 653 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", 654 "Counter": "3", 655 "EventCode": "0xB", 656 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", 657 "MSRIndex": "0x3F6", 658 "MSRValue": "0x4", 659 "PEBS": "2", 660 "SampleAfterValue": "50000", 661 "UMask": "0x10" 662 }, 663 { 664 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", 665 "Counter": "3", 666 "EventCode": "0xB", 667 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", 668 "MSRIndex": "0x3F6", 669 "MSRValue": "0x1000", 670 "PEBS": "2", 671 "SampleAfterValue": "20", 672 "UMask": "0x10" 673 }, 674 { 675 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", 676 "Counter": "3", 677 "EventCode": "0xB", 678 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", 679 "MSRIndex": "0x3F6", 680 "MSRValue": "0x200", 681 "PEBS": "2", 682 "SampleAfterValue": "200", 683 "UMask": "0x10" 684 }, 685 { 686 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", 687 "Counter": "3", 688 "EventCode": "0xB", 689 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", 690 "MSRIndex": "0x3F6", 691 "MSRValue": "0x40", 692 "PEBS": "2", 693 "SampleAfterValue": "2000", 694 "UMask": "0x10" 695 }, 696 { 697 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", 698 "Counter": "3", 699 "EventCode": "0xB", 700 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", 701 "MSRIndex": "0x3F6", 702 "MSRValue": "0x8", 703 "PEBS": "2", 704 "SampleAfterValue": "20000", 705 "UMask": "0x10" 706 }, 707 { 708 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", 709 "Counter": "3", 710 "EventCode": "0xB", 711 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", 712 "MSRIndex": "0x3F6", 713 "MSRValue": "0x2000", 714 "PEBS": "2", 715 "SampleAfterValue": "10", 716 "UMask": "0x10" 717 }, 718 { 719 "BriefDescription": "Instructions retired which contains a load (Precise Event)", 720 "Counter": "0,1,2,3", 721 "EventCode": "0xB", 722 "EventName": "MEM_INST_RETIRED.LOADS", 723 "PEBS": "1", 724 "SampleAfterValue": "2000000", 725 "UMask": "0x1" 726 }, 727 { 728 "BriefDescription": "Instructions retired which contains a store (Precise Event)", 729 "Counter": "0,1,2,3", 730 "EventCode": "0xB", 731 "EventName": "MEM_INST_RETIRED.STORES", 732 "PEBS": "1", 733 "SampleAfterValue": "2000000", 734 "UMask": "0x2" 735 }, 736 { 737 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", 738 "Counter": "0,1,2,3", 739 "EventCode": "0xCB", 740 "EventName": "MEM_LOAD_RETIRED.HIT_LFB", 741 "PEBS": "1", 742 "SampleAfterValue": "200000", 743 "UMask": "0x40" 744 }, 745 { 746 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", 747 "Counter": "0,1,2,3", 748 "EventCode": "0xCB", 749 "EventName": "MEM_LOAD_RETIRED.L1D_HIT", 750 "PEBS": "1", 751 "SampleAfterValue": "2000000", 752 "UMask": "0x1" 753 }, 754 { 755 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", 756 "Counter": "0,1,2,3", 757 "EventCode": "0xCB", 758 "EventName": "MEM_LOAD_RETIRED.L2_HIT", 759 "PEBS": "1", 760 "SampleAfterValue": "200000", 761 "UMask": "0x2" 762 }, 763 { 764 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", 765 "Counter": "0,1,2,3", 766 "EventCode": "0xCB", 767 "EventName": "MEM_LOAD_RETIRED.LLC_MISS", 768 "PEBS": "1", 769 "SampleAfterValue": "10000", 770 "UMask": "0x10" 771 }, 772 { 773 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", 774 "Counter": "0,1,2,3", 775 "EventCode": "0xCB", 776 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", 777 "PEBS": "1", 778 "SampleAfterValue": "40000", 779 "UMask": "0x4" 780 }, 781 { 782 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", 783 "Counter": "0,1,2,3", 784 "EventCode": "0xCB", 785 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", 786 "PEBS": "1", 787 "SampleAfterValue": "40000", 788 "UMask": "0x8" 789 }, 790 { 791 "BriefDescription": "All offcore requests", 792 "Counter": "0,1,2,3", 793 "EventCode": "0xB0", 794 "EventName": "OFFCORE_REQUESTS.ANY", 795 "SampleAfterValue": "100000", 796 "UMask": "0x80" 797 }, 798 { 799 "BriefDescription": "Offcore read requests", 800 "Counter": "0,1,2,3", 801 "EventCode": "0xB0", 802 "EventName": "OFFCORE_REQUESTS.ANY.READ", 803 "SampleAfterValue": "100000", 804 "UMask": "0x8" 805 }, 806 { 807 "BriefDescription": "Offcore RFO requests", 808 "Counter": "0,1,2,3", 809 "EventCode": "0xB0", 810 "EventName": "OFFCORE_REQUESTS.ANY.RFO", 811 "SampleAfterValue": "100000", 812 "UMask": "0x10" 813 }, 814 { 815 "BriefDescription": "Offcore demand code read requests", 816 "Counter": "0,1,2,3", 817 "EventCode": "0xB0", 818 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", 819 "SampleAfterValue": "100000", 820 "UMask": "0x2" 821 }, 822 { 823 "BriefDescription": "Offcore demand data read requests", 824 "Counter": "0,1,2,3", 825 "EventCode": "0xB0", 826 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", 827 "SampleAfterValue": "100000", 828 "UMask": "0x1" 829 }, 830 { 831 "BriefDescription": "Offcore demand RFO requests", 832 "Counter": "0,1,2,3", 833 "EventCode": "0xB0", 834 "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", 835 "SampleAfterValue": "100000", 836 "UMask": "0x4" 837 }, 838 { 839 "BriefDescription": "Offcore L1 data cache writebacks", 840 "Counter": "0,1,2,3", 841 "EventCode": "0xB0", 842 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", 843 "SampleAfterValue": "100000", 844 "UMask": "0x40" 845 }, 846 { 847 "BriefDescription": "Outstanding offcore reads", 848 "Counter": "0", 849 "EventCode": "0x60", 850 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", 851 "SampleAfterValue": "2000000", 852 "UMask": "0x8" 853 }, 854 { 855 "BriefDescription": "Cycles offcore reads busy", 856 "Counter": "0", 857 "CounterMask": "1", 858 "EventCode": "0x60", 859 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", 860 "SampleAfterValue": "2000000", 861 "UMask": "0x8" 862 }, 863 { 864 "BriefDescription": "Outstanding offcore demand code reads", 865 "Counter": "0", 866 "EventCode": "0x60", 867 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", 868 "SampleAfterValue": "2000000", 869 "UMask": "0x2" 870 }, 871 { 872 "BriefDescription": "Cycles offcore demand code read busy", 873 "Counter": "0", 874 "CounterMask": "1", 875 "EventCode": "0x60", 876 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", 877 "SampleAfterValue": "2000000", 878 "UMask": "0x2" 879 }, 880 { 881 "BriefDescription": "Outstanding offcore demand data reads", 882 "Counter": "0", 883 "EventCode": "0x60", 884 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", 885 "SampleAfterValue": "2000000", 886 "UMask": "0x1" 887 }, 888 { 889 "BriefDescription": "Cycles offcore demand data read busy", 890 "Counter": "0", 891 "CounterMask": "1", 892 "EventCode": "0x60", 893 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", 894 "SampleAfterValue": "2000000", 895 "UMask": "0x1" 896 }, 897 { 898 "BriefDescription": "Outstanding offcore demand RFOs", 899 "Counter": "0", 900 "EventCode": "0x60", 901 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", 902 "SampleAfterValue": "2000000", 903 "UMask": "0x4" 904 }, 905 { 906 "BriefDescription": "Cycles offcore demand RFOs busy", 907 "Counter": "0", 908 "CounterMask": "1", 909 "EventCode": "0x60", 910 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", 911 "SampleAfterValue": "2000000", 912 "UMask": "0x4" 913 }, 914 { 915 "BriefDescription": "Offcore requests blocked due to Super Queue full", 916 "Counter": "0,1,2,3", 917 "EventCode": "0xB2", 918 "EventName": "OFFCORE_REQUESTS_SQ_FULL", 919 "SampleAfterValue": "100000", 920 "UMask": "0x1" 921 }, 922 { 923 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 924 "Counter": "0,1,2,3", 925 "EventCode": "0xB7, 0xBB", 926 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 927 "MSRIndex": "0x1a6,0x1a7", 928 "MSRValue": "0x5011", 929 "SampleAfterValue": "100000", 930 "UMask": "0x1" 931 }, 932 { 933 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM", 934 "Counter": "0,1,2,3", 935 "EventCode": "0xB7, 0xBB", 936 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", 937 "MSRIndex": "0x1a6,0x1a7", 938 "MSRValue": "0x7f11", 939 "SampleAfterValue": "100000", 940 "UMask": "0x1" 941 }, 942 { 943 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION", 944 "Counter": "0,1,2,3", 945 "EventCode": "0xB7, 0xBB", 946 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", 947 "MSRIndex": "0x1a6,0x1a7", 948 "MSRValue": "0xff11", 949 "SampleAfterValue": "100000", 950 "UMask": "0x1" 951 }, 952 { 953 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO", 954 "Counter": "0,1,2,3", 955 "EventCode": "0xB7, 0xBB", 956 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", 957 "MSRIndex": "0x1a6,0x1a7", 958 "MSRValue": "0x8011", 959 "SampleAfterValue": "100000", 960 "UMask": "0x1" 961 }, 962 { 963 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE", 964 "Counter": "0,1,2,3", 965 "EventCode": "0xB7, 0xBB", 966 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", 967 "MSRIndex": "0x1a6,0x1a7", 968 "MSRValue": "0x111", 969 "SampleAfterValue": "100000", 970 "UMask": "0x1" 971 }, 972 { 973 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 974 "Counter": "0,1,2,3", 975 "EventCode": "0xB7, 0xBB", 976 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", 977 "MSRIndex": "0x1a6,0x1a7", 978 "MSRValue": "0x211", 979 "SampleAfterValue": "100000", 980 "UMask": "0x1" 981 }, 982 { 983 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 984 "Counter": "0,1,2,3", 985 "EventCode": "0xB7, 0xBB", 986 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", 987 "MSRIndex": "0x1a6,0x1a7", 988 "MSRValue": "0x411", 989 "SampleAfterValue": "100000", 990 "UMask": "0x1" 991 }, 992 { 993 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE", 994 "Counter": "0,1,2,3", 995 "EventCode": "0xB7, 0xBB", 996 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", 997 "MSRIndex": "0x1a6,0x1a7", 998 "MSRValue": "0x711", 999 "SampleAfterValue": "100000", 1000 "UMask": "0x1" 1001 }, 1002 { 1003 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1004 "Counter": "0,1,2,3", 1005 "EventCode": "0xB7, 0xBB", 1006 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1007 "MSRIndex": "0x1a6,0x1a7", 1008 "MSRValue": "0x1011", 1009 "SampleAfterValue": "100000", 1010 "UMask": "0x1" 1011 }, 1012 { 1013 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM", 1014 "Counter": "0,1,2,3", 1015 "EventCode": "0xB7, 0xBB", 1016 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", 1017 "MSRIndex": "0x1a6,0x1a7", 1018 "MSRValue": "0x811", 1019 "SampleAfterValue": "100000", 1020 "UMask": "0x1" 1021 }, 1022 { 1023 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1024 "Counter": "0,1,2,3", 1025 "EventCode": "0xB7, 0xBB", 1026 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1027 "MSRIndex": "0x1a6,0x1a7", 1028 "MSRValue": "0x5044", 1029 "SampleAfterValue": "100000", 1030 "UMask": "0x1" 1031 }, 1032 { 1033 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM", 1034 "Counter": "0,1,2,3", 1035 "EventCode": "0xB7, 0xBB", 1036 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", 1037 "MSRIndex": "0x1a6,0x1a7", 1038 "MSRValue": "0x7f44", 1039 "SampleAfterValue": "100000", 1040 "UMask": "0x1" 1041 }, 1042 { 1043 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION", 1044 "Counter": "0,1,2,3", 1045 "EventCode": "0xB7, 0xBB", 1046 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", 1047 "MSRIndex": "0x1a6,0x1a7", 1048 "MSRValue": "0xff44", 1049 "SampleAfterValue": "100000", 1050 "UMask": "0x1" 1051 }, 1052 { 1053 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO", 1054 "Counter": "0,1,2,3", 1055 "EventCode": "0xB7, 0xBB", 1056 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", 1057 "MSRIndex": "0x1a6,0x1a7", 1058 "MSRValue": "0x8044", 1059 "SampleAfterValue": "100000", 1060 "UMask": "0x1" 1061 }, 1062 { 1063 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1064 "Counter": "0,1,2,3", 1065 "EventCode": "0xB7, 0xBB", 1066 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", 1067 "MSRIndex": "0x1a6,0x1a7", 1068 "MSRValue": "0x144", 1069 "SampleAfterValue": "100000", 1070 "UMask": "0x1" 1071 }, 1072 { 1073 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1074 "Counter": "0,1,2,3", 1075 "EventCode": "0xB7, 0xBB", 1076 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1077 "MSRIndex": "0x1a6,0x1a7", 1078 "MSRValue": "0x244", 1079 "SampleAfterValue": "100000", 1080 "UMask": "0x1" 1081 }, 1082 { 1083 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1084 "Counter": "0,1,2,3", 1085 "EventCode": "0xB7, 0xBB", 1086 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1087 "MSRIndex": "0x1a6,0x1a7", 1088 "MSRValue": "0x444", 1089 "SampleAfterValue": "100000", 1090 "UMask": "0x1" 1091 }, 1092 { 1093 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE", 1094 "Counter": "0,1,2,3", 1095 "EventCode": "0xB7, 0xBB", 1096 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", 1097 "MSRIndex": "0x1a6,0x1a7", 1098 "MSRValue": "0x744", 1099 "SampleAfterValue": "100000", 1100 "UMask": "0x1" 1101 }, 1102 { 1103 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1104 "Counter": "0,1,2,3", 1105 "EventCode": "0xB7, 0xBB", 1106 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1107 "MSRIndex": "0x1a6,0x1a7", 1108 "MSRValue": "0x1044", 1109 "SampleAfterValue": "100000", 1110 "UMask": "0x1" 1111 }, 1112 { 1113 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM", 1114 "Counter": "0,1,2,3", 1115 "EventCode": "0xB7, 0xBB", 1116 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", 1117 "MSRIndex": "0x1a6,0x1a7", 1118 "MSRValue": "0x844", 1119 "SampleAfterValue": "100000", 1120 "UMask": "0x1" 1121 }, 1122 { 1123 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1124 "Counter": "0,1,2,3", 1125 "EventCode": "0xB7, 0xBB", 1126 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1127 "MSRIndex": "0x1a6,0x1a7", 1128 "MSRValue": "0x50ff", 1129 "SampleAfterValue": "100000", 1130 "UMask": "0x1" 1131 }, 1132 { 1133 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM", 1134 "Counter": "0,1,2,3", 1135 "EventCode": "0xB7, 0xBB", 1136 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", 1137 "MSRIndex": "0x1a6,0x1a7", 1138 "MSRValue": "0x7fff", 1139 "SampleAfterValue": "100000", 1140 "UMask": "0x1" 1141 }, 1142 { 1143 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION", 1144 "Counter": "0,1,2,3", 1145 "EventCode": "0xB7, 0xBB", 1146 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", 1147 "MSRIndex": "0x1a6,0x1a7", 1148 "MSRValue": "0xffff", 1149 "SampleAfterValue": "100000", 1150 "UMask": "0x1" 1151 }, 1152 { 1153 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO", 1154 "Counter": "0,1,2,3", 1155 "EventCode": "0xB7, 0xBB", 1156 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", 1157 "MSRIndex": "0x1a6,0x1a7", 1158 "MSRValue": "0x80ff", 1159 "SampleAfterValue": "100000", 1160 "UMask": "0x1" 1161 }, 1162 { 1163 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1164 "Counter": "0,1,2,3", 1165 "EventCode": "0xB7, 0xBB", 1166 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", 1167 "MSRIndex": "0x1a6,0x1a7", 1168 "MSRValue": "0x1ff", 1169 "SampleAfterValue": "100000", 1170 "UMask": "0x1" 1171 }, 1172 { 1173 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1174 "Counter": "0,1,2,3", 1175 "EventCode": "0xB7, 0xBB", 1176 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", 1177 "MSRIndex": "0x1a6,0x1a7", 1178 "MSRValue": "0x2ff", 1179 "SampleAfterValue": "100000", 1180 "UMask": "0x1" 1181 }, 1182 { 1183 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1184 "Counter": "0,1,2,3", 1185 "EventCode": "0xB7, 0xBB", 1186 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", 1187 "MSRIndex": "0x1a6,0x1a7", 1188 "MSRValue": "0x4ff", 1189 "SampleAfterValue": "100000", 1190 "UMask": "0x1" 1191 }, 1192 { 1193 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE", 1194 "Counter": "0,1,2,3", 1195 "EventCode": "0xB7, 0xBB", 1196 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", 1197 "MSRIndex": "0x1a6,0x1a7", 1198 "MSRValue": "0x7ff", 1199 "SampleAfterValue": "100000", 1200 "UMask": "0x1" 1201 }, 1202 { 1203 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1204 "Counter": "0,1,2,3", 1205 "EventCode": "0xB7, 0xBB", 1206 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1207 "MSRIndex": "0x1a6,0x1a7", 1208 "MSRValue": "0x10ff", 1209 "SampleAfterValue": "100000", 1210 "UMask": "0x1" 1211 }, 1212 { 1213 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM", 1214 "Counter": "0,1,2,3", 1215 "EventCode": "0xB7, 0xBB", 1216 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", 1217 "MSRIndex": "0x1a6,0x1a7", 1218 "MSRValue": "0x8ff", 1219 "SampleAfterValue": "100000", 1220 "UMask": "0x1" 1221 }, 1222 { 1223 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1224 "Counter": "0,1,2,3", 1225 "EventCode": "0xB7, 0xBB", 1226 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1227 "MSRIndex": "0x1a6,0x1a7", 1228 "MSRValue": "0x5022", 1229 "SampleAfterValue": "100000", 1230 "UMask": "0x1" 1231 }, 1232 { 1233 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM", 1234 "Counter": "0,1,2,3", 1235 "EventCode": "0xB7, 0xBB", 1236 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", 1237 "MSRIndex": "0x1a6,0x1a7", 1238 "MSRValue": "0x7f22", 1239 "SampleAfterValue": "100000", 1240 "UMask": "0x1" 1241 }, 1242 { 1243 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LOCATION", 1244 "Counter": "0,1,2,3", 1245 "EventCode": "0xB7, 0xBB", 1246 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", 1247 "MSRIndex": "0x1a6,0x1a7", 1248 "MSRValue": "0xff22", 1249 "SampleAfterValue": "100000", 1250 "UMask": "0x1" 1251 }, 1252 { 1253 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO", 1254 "Counter": "0,1,2,3", 1255 "EventCode": "0xB7, 0xBB", 1256 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", 1257 "MSRIndex": "0x1a6,0x1a7", 1258 "MSRValue": "0x8022", 1259 "SampleAfterValue": "100000", 1260 "UMask": "0x1" 1261 }, 1262 { 1263 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1264 "Counter": "0,1,2,3", 1265 "EventCode": "0xB7, 0xBB", 1266 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", 1267 "MSRIndex": "0x1a6,0x1a7", 1268 "MSRValue": "0x122", 1269 "SampleAfterValue": "100000", 1270 "UMask": "0x1" 1271 }, 1272 { 1273 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1274 "Counter": "0,1,2,3", 1275 "EventCode": "0xB7, 0xBB", 1276 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", 1277 "MSRIndex": "0x1a6,0x1a7", 1278 "MSRValue": "0x222", 1279 "SampleAfterValue": "100000", 1280 "UMask": "0x1" 1281 }, 1282 { 1283 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1284 "Counter": "0,1,2,3", 1285 "EventCode": "0xB7, 0xBB", 1286 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", 1287 "MSRIndex": "0x1a6,0x1a7", 1288 "MSRValue": "0x422", 1289 "SampleAfterValue": "100000", 1290 "UMask": "0x1" 1291 }, 1292 { 1293 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE", 1294 "Counter": "0,1,2,3", 1295 "EventCode": "0xB7, 0xBB", 1296 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", 1297 "MSRIndex": "0x1a6,0x1a7", 1298 "MSRValue": "0x722", 1299 "SampleAfterValue": "100000", 1300 "UMask": "0x1" 1301 }, 1302 { 1303 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1304 "Counter": "0,1,2,3", 1305 "EventCode": "0xB7, 0xBB", 1306 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1307 "MSRIndex": "0x1a6,0x1a7", 1308 "MSRValue": "0x1022", 1309 "SampleAfterValue": "100000", 1310 "UMask": "0x1" 1311 }, 1312 { 1313 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM", 1314 "Counter": "0,1,2,3", 1315 "EventCode": "0xB7, 0xBB", 1316 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", 1317 "MSRIndex": "0x1a6,0x1a7", 1318 "MSRValue": "0x822", 1319 "SampleAfterValue": "100000", 1320 "UMask": "0x1" 1321 }, 1322 { 1323 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1324 "Counter": "0,1,2,3", 1325 "EventCode": "0xB7, 0xBB", 1326 "EventName": "OFFCORE_RESPONSE.COREWB.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1327 "MSRIndex": "0x1a6,0x1a7", 1328 "MSRValue": "0x5008", 1329 "SampleAfterValue": "100000", 1330 "UMask": "0x1" 1331 }, 1332 { 1333 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM", 1334 "Counter": "0,1,2,3", 1335 "EventCode": "0xB7, 0xBB", 1336 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", 1337 "MSRIndex": "0x1a6,0x1a7", 1338 "MSRValue": "0x7f08", 1339 "SampleAfterValue": "100000", 1340 "UMask": "0x1" 1341 }, 1342 { 1343 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LOCATION", 1344 "Counter": "0,1,2,3", 1345 "EventCode": "0xB7, 0xBB", 1346 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", 1347 "MSRIndex": "0x1a6,0x1a7", 1348 "MSRValue": "0xff08", 1349 "SampleAfterValue": "100000", 1350 "UMask": "0x1" 1351 }, 1352 { 1353 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO", 1354 "Counter": "0,1,2,3", 1355 "EventCode": "0xB7, 0xBB", 1356 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", 1357 "MSRIndex": "0x1a6,0x1a7", 1358 "MSRValue": "0x8008", 1359 "SampleAfterValue": "100000", 1360 "UMask": "0x1" 1361 }, 1362 { 1363 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1364 "Counter": "0,1,2,3", 1365 "EventCode": "0xB7, 0xBB", 1366 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", 1367 "MSRIndex": "0x1a6,0x1a7", 1368 "MSRValue": "0x108", 1369 "SampleAfterValue": "100000", 1370 "UMask": "0x1" 1371 }, 1372 { 1373 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1374 "Counter": "0,1,2,3", 1375 "EventCode": "0xB7, 0xBB", 1376 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HIT", 1377 "MSRIndex": "0x1a6,0x1a7", 1378 "MSRValue": "0x208", 1379 "SampleAfterValue": "100000", 1380 "UMask": "0x1" 1381 }, 1382 { 1383 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1384 "Counter": "0,1,2,3", 1385 "EventCode": "0xB7, 0xBB", 1386 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", 1387 "MSRIndex": "0x1a6,0x1a7", 1388 "MSRValue": "0x408", 1389 "SampleAfterValue": "100000", 1390 "UMask": "0x1" 1391 }, 1392 { 1393 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE", 1394 "Counter": "0,1,2,3", 1395 "EventCode": "0xB7, 0xBB", 1396 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", 1397 "MSRIndex": "0x1a6,0x1a7", 1398 "MSRValue": "0x708", 1399 "SampleAfterValue": "100000", 1400 "UMask": "0x1" 1401 }, 1402 { 1403 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1404 "Counter": "0,1,2,3", 1405 "EventCode": "0xB7, 0xBB", 1406 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1407 "MSRIndex": "0x1a6,0x1a7", 1408 "MSRValue": "0x1008", 1409 "SampleAfterValue": "100000", 1410 "UMask": "0x1" 1411 }, 1412 { 1413 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM", 1414 "Counter": "0,1,2,3", 1415 "EventCode": "0xB7, 0xBB", 1416 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", 1417 "MSRIndex": "0x1a6,0x1a7", 1418 "MSRValue": "0x808", 1419 "SampleAfterValue": "100000", 1420 "UMask": "0x1" 1421 }, 1422 { 1423 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1424 "Counter": "0,1,2,3", 1425 "EventCode": "0xB7, 0xBB", 1426 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1427 "MSRIndex": "0x1a6,0x1a7", 1428 "MSRValue": "0x5077", 1429 "SampleAfterValue": "100000", 1430 "UMask": "0x1" 1431 }, 1432 { 1433 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM", 1434 "Counter": "0,1,2,3", 1435 "EventCode": "0xB7, 0xBB", 1436 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", 1437 "MSRIndex": "0x1a6,0x1a7", 1438 "MSRValue": "0x7f77", 1439 "SampleAfterValue": "100000", 1440 "UMask": "0x1" 1441 }, 1442 { 1443 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION", 1444 "Counter": "0,1,2,3", 1445 "EventCode": "0xB7, 0xBB", 1446 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", 1447 "MSRIndex": "0x1a6,0x1a7", 1448 "MSRValue": "0xff77", 1449 "SampleAfterValue": "100000", 1450 "UMask": "0x1" 1451 }, 1452 { 1453 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO", 1454 "Counter": "0,1,2,3", 1455 "EventCode": "0xB7, 0xBB", 1456 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", 1457 "MSRIndex": "0x1a6,0x1a7", 1458 "MSRValue": "0x8077", 1459 "SampleAfterValue": "100000", 1460 "UMask": "0x1" 1461 }, 1462 { 1463 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1464 "Counter": "0,1,2,3", 1465 "EventCode": "0xB7, 0xBB", 1466 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", 1467 "MSRIndex": "0x1a6,0x1a7", 1468 "MSRValue": "0x177", 1469 "SampleAfterValue": "100000", 1470 "UMask": "0x1" 1471 }, 1472 { 1473 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1474 "Counter": "0,1,2,3", 1475 "EventCode": "0xB7, 0xBB", 1476 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1477 "MSRIndex": "0x1a6,0x1a7", 1478 "MSRValue": "0x277", 1479 "SampleAfterValue": "100000", 1480 "UMask": "0x1" 1481 }, 1482 { 1483 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1484 "Counter": "0,1,2,3", 1485 "EventCode": "0xB7, 0xBB", 1486 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1487 "MSRIndex": "0x1a6,0x1a7", 1488 "MSRValue": "0x477", 1489 "SampleAfterValue": "100000", 1490 "UMask": "0x1" 1491 }, 1492 { 1493 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE", 1494 "Counter": "0,1,2,3", 1495 "EventCode": "0xB7, 0xBB", 1496 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", 1497 "MSRIndex": "0x1a6,0x1a7", 1498 "MSRValue": "0x777", 1499 "SampleAfterValue": "100000", 1500 "UMask": "0x1" 1501 }, 1502 { 1503 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1504 "Counter": "0,1,2,3", 1505 "EventCode": "0xB7, 0xBB", 1506 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1507 "MSRIndex": "0x1a6,0x1a7", 1508 "MSRValue": "0x1077", 1509 "SampleAfterValue": "100000", 1510 "UMask": "0x1" 1511 }, 1512 { 1513 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM", 1514 "Counter": "0,1,2,3", 1515 "EventCode": "0xB7, 0xBB", 1516 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", 1517 "MSRIndex": "0x1a6,0x1a7", 1518 "MSRValue": "0x877", 1519 "SampleAfterValue": "100000", 1520 "UMask": "0x1" 1521 }, 1522 { 1523 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1524 "Counter": "0,1,2,3", 1525 "EventCode": "0xB7, 0xBB", 1526 "EventName": "OFFCORE_RESPONSE.DATA_IN.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1527 "MSRIndex": "0x1a6,0x1a7", 1528 "MSRValue": "0x5033", 1529 "SampleAfterValue": "100000", 1530 "UMask": "0x1" 1531 }, 1532 { 1533 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM", 1534 "Counter": "0,1,2,3", 1535 "EventCode": "0xB7, 0xBB", 1536 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", 1537 "MSRIndex": "0x1a6,0x1a7", 1538 "MSRValue": "0x7f33", 1539 "SampleAfterValue": "100000", 1540 "UMask": "0x1" 1541 }, 1542 { 1543 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LOCATION", 1544 "Counter": "0,1,2,3", 1545 "EventCode": "0xB7, 0xBB", 1546 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", 1547 "MSRIndex": "0x1a6,0x1a7", 1548 "MSRValue": "0xff33", 1549 "SampleAfterValue": "100000", 1550 "UMask": "0x1" 1551 }, 1552 { 1553 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO", 1554 "Counter": "0,1,2,3", 1555 "EventCode": "0xB7, 0xBB", 1556 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", 1557 "MSRIndex": "0x1a6,0x1a7", 1558 "MSRValue": "0x8033", 1559 "SampleAfterValue": "100000", 1560 "UMask": "0x1" 1561 }, 1562 { 1563 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1564 "Counter": "0,1,2,3", 1565 "EventCode": "0xB7, 0xBB", 1566 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", 1567 "MSRIndex": "0x1a6,0x1a7", 1568 "MSRValue": "0x133", 1569 "SampleAfterValue": "100000", 1570 "UMask": "0x1" 1571 }, 1572 { 1573 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1574 "Counter": "0,1,2,3", 1575 "EventCode": "0xB7, 0xBB", 1576 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", 1577 "MSRIndex": "0x1a6,0x1a7", 1578 "MSRValue": "0x233", 1579 "SampleAfterValue": "100000", 1580 "UMask": "0x1" 1581 }, 1582 { 1583 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1584 "Counter": "0,1,2,3", 1585 "EventCode": "0xB7, 0xBB", 1586 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", 1587 "MSRIndex": "0x1a6,0x1a7", 1588 "MSRValue": "0x433", 1589 "SampleAfterValue": "100000", 1590 "UMask": "0x1" 1591 }, 1592 { 1593 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE", 1594 "Counter": "0,1,2,3", 1595 "EventCode": "0xB7, 0xBB", 1596 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", 1597 "MSRIndex": "0x1a6,0x1a7", 1598 "MSRValue": "0x733", 1599 "SampleAfterValue": "100000", 1600 "UMask": "0x1" 1601 }, 1602 { 1603 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1604 "Counter": "0,1,2,3", 1605 "EventCode": "0xB7, 0xBB", 1606 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1607 "MSRIndex": "0x1a6,0x1a7", 1608 "MSRValue": "0x1033", 1609 "SampleAfterValue": "100000", 1610 "UMask": "0x1" 1611 }, 1612 { 1613 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM", 1614 "Counter": "0,1,2,3", 1615 "EventCode": "0xB7, 0xBB", 1616 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", 1617 "MSRIndex": "0x1a6,0x1a7", 1618 "MSRValue": "0x833", 1619 "SampleAfterValue": "100000", 1620 "UMask": "0x1" 1621 }, 1622 { 1623 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1624 "Counter": "0,1,2,3", 1625 "EventCode": "0xB7, 0xBB", 1626 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1627 "MSRIndex": "0x1a6,0x1a7", 1628 "MSRValue": "0x5003", 1629 "SampleAfterValue": "100000", 1630 "UMask": "0x1" 1631 }, 1632 { 1633 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM", 1634 "Counter": "0,1,2,3", 1635 "EventCode": "0xB7, 0xBB", 1636 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", 1637 "MSRIndex": "0x1a6,0x1a7", 1638 "MSRValue": "0x7f03", 1639 "SampleAfterValue": "100000", 1640 "UMask": "0x1" 1641 }, 1642 { 1643 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION", 1644 "Counter": "0,1,2,3", 1645 "EventCode": "0xB7, 0xBB", 1646 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", 1647 "MSRIndex": "0x1a6,0x1a7", 1648 "MSRValue": "0xff03", 1649 "SampleAfterValue": "100000", 1650 "UMask": "0x1" 1651 }, 1652 { 1653 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO", 1654 "Counter": "0,1,2,3", 1655 "EventCode": "0xB7, 0xBB", 1656 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", 1657 "MSRIndex": "0x1a6,0x1a7", 1658 "MSRValue": "0x8003", 1659 "SampleAfterValue": "100000", 1660 "UMask": "0x1" 1661 }, 1662 { 1663 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1664 "Counter": "0,1,2,3", 1665 "EventCode": "0xB7, 0xBB", 1666 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", 1667 "MSRIndex": "0x1a6,0x1a7", 1668 "MSRValue": "0x103", 1669 "SampleAfterValue": "100000", 1670 "UMask": "0x1" 1671 }, 1672 { 1673 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1674 "Counter": "0,1,2,3", 1675 "EventCode": "0xB7, 0xBB", 1676 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", 1677 "MSRIndex": "0x1a6,0x1a7", 1678 "MSRValue": "0x203", 1679 "SampleAfterValue": "100000", 1680 "UMask": "0x1" 1681 }, 1682 { 1683 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1684 "Counter": "0,1,2,3", 1685 "EventCode": "0xB7, 0xBB", 1686 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", 1687 "MSRIndex": "0x1a6,0x1a7", 1688 "MSRValue": "0x403", 1689 "SampleAfterValue": "100000", 1690 "UMask": "0x1" 1691 }, 1692 { 1693 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE", 1694 "Counter": "0,1,2,3", 1695 "EventCode": "0xB7, 0xBB", 1696 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", 1697 "MSRIndex": "0x1a6,0x1a7", 1698 "MSRValue": "0x703", 1699 "SampleAfterValue": "100000", 1700 "UMask": "0x1" 1701 }, 1702 { 1703 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1704 "Counter": "0,1,2,3", 1705 "EventCode": "0xB7, 0xBB", 1706 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1707 "MSRIndex": "0x1a6,0x1a7", 1708 "MSRValue": "0x1003", 1709 "SampleAfterValue": "100000", 1710 "UMask": "0x1" 1711 }, 1712 { 1713 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM", 1714 "Counter": "0,1,2,3", 1715 "EventCode": "0xB7, 0xBB", 1716 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", 1717 "MSRIndex": "0x1a6,0x1a7", 1718 "MSRValue": "0x803", 1719 "SampleAfterValue": "100000", 1720 "UMask": "0x1" 1721 }, 1722 { 1723 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1724 "Counter": "0,1,2,3", 1725 "EventCode": "0xB7, 0xBB", 1726 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1727 "MSRIndex": "0x1a6,0x1a7", 1728 "MSRValue": "0x5001", 1729 "SampleAfterValue": "100000", 1730 "UMask": "0x1" 1731 }, 1732 { 1733 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM", 1734 "Counter": "0,1,2,3", 1735 "EventCode": "0xB7, 0xBB", 1736 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", 1737 "MSRIndex": "0x1a6,0x1a7", 1738 "MSRValue": "0x7f01", 1739 "SampleAfterValue": "100000", 1740 "UMask": "0x1" 1741 }, 1742 { 1743 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION", 1744 "Counter": "0,1,2,3", 1745 "EventCode": "0xB7, 0xBB", 1746 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", 1747 "MSRIndex": "0x1a6,0x1a7", 1748 "MSRValue": "0xff01", 1749 "SampleAfterValue": "100000", 1750 "UMask": "0x1" 1751 }, 1752 { 1753 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO", 1754 "Counter": "0,1,2,3", 1755 "EventCode": "0xB7, 0xBB", 1756 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", 1757 "MSRIndex": "0x1a6,0x1a7", 1758 "MSRValue": "0x8001", 1759 "SampleAfterValue": "100000", 1760 "UMask": "0x1" 1761 }, 1762 { 1763 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1764 "Counter": "0,1,2,3", 1765 "EventCode": "0xB7, 0xBB", 1766 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", 1767 "MSRIndex": "0x1a6,0x1a7", 1768 "MSRValue": "0x101", 1769 "SampleAfterValue": "100000", 1770 "UMask": "0x1" 1771 }, 1772 { 1773 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1774 "Counter": "0,1,2,3", 1775 "EventCode": "0xB7, 0xBB", 1776 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 1777 "MSRIndex": "0x1a6,0x1a7", 1778 "MSRValue": "0x201", 1779 "SampleAfterValue": "100000", 1780 "UMask": "0x1" 1781 }, 1782 { 1783 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1784 "Counter": "0,1,2,3", 1785 "EventCode": "0xB7, 0xBB", 1786 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 1787 "MSRIndex": "0x1a6,0x1a7", 1788 "MSRValue": "0x401", 1789 "SampleAfterValue": "100000", 1790 "UMask": "0x1" 1791 }, 1792 { 1793 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE", 1794 "Counter": "0,1,2,3", 1795 "EventCode": "0xB7, 0xBB", 1796 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", 1797 "MSRIndex": "0x1a6,0x1a7", 1798 "MSRValue": "0x701", 1799 "SampleAfterValue": "100000", 1800 "UMask": "0x1" 1801 }, 1802 { 1803 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1804 "Counter": "0,1,2,3", 1805 "EventCode": "0xB7, 0xBB", 1806 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1807 "MSRIndex": "0x1a6,0x1a7", 1808 "MSRValue": "0x1001", 1809 "SampleAfterValue": "100000", 1810 "UMask": "0x1" 1811 }, 1812 { 1813 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM", 1814 "Counter": "0,1,2,3", 1815 "EventCode": "0xB7, 0xBB", 1816 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", 1817 "MSRIndex": "0x1a6,0x1a7", 1818 "MSRValue": "0x801", 1819 "SampleAfterValue": "100000", 1820 "UMask": "0x1" 1821 }, 1822 { 1823 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1824 "Counter": "0,1,2,3", 1825 "EventCode": "0xB7, 0xBB", 1826 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1827 "MSRIndex": "0x1a6,0x1a7", 1828 "MSRValue": "0x5004", 1829 "SampleAfterValue": "100000", 1830 "UMask": "0x1" 1831 }, 1832 { 1833 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM", 1834 "Counter": "0,1,2,3", 1835 "EventCode": "0xB7, 0xBB", 1836 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", 1837 "MSRIndex": "0x1a6,0x1a7", 1838 "MSRValue": "0x7f04", 1839 "SampleAfterValue": "100000", 1840 "UMask": "0x1" 1841 }, 1842 { 1843 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION", 1844 "Counter": "0,1,2,3", 1845 "EventCode": "0xB7, 0xBB", 1846 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", 1847 "MSRIndex": "0x1a6,0x1a7", 1848 "MSRValue": "0xff04", 1849 "SampleAfterValue": "100000", 1850 "UMask": "0x1" 1851 }, 1852 { 1853 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO", 1854 "Counter": "0,1,2,3", 1855 "EventCode": "0xB7, 0xBB", 1856 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", 1857 "MSRIndex": "0x1a6,0x1a7", 1858 "MSRValue": "0x8004", 1859 "SampleAfterValue": "100000", 1860 "UMask": "0x1" 1861 }, 1862 { 1863 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1864 "Counter": "0,1,2,3", 1865 "EventCode": "0xB7, 0xBB", 1866 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", 1867 "MSRIndex": "0x1a6,0x1a7", 1868 "MSRValue": "0x104", 1869 "SampleAfterValue": "100000", 1870 "UMask": "0x1" 1871 }, 1872 { 1873 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1874 "Counter": "0,1,2,3", 1875 "EventCode": "0xB7, 0xBB", 1876 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1877 "MSRIndex": "0x1a6,0x1a7", 1878 "MSRValue": "0x204", 1879 "SampleAfterValue": "100000", 1880 "UMask": "0x1" 1881 }, 1882 { 1883 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1884 "Counter": "0,1,2,3", 1885 "EventCode": "0xB7, 0xBB", 1886 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1887 "MSRIndex": "0x1a6,0x1a7", 1888 "MSRValue": "0x404", 1889 "SampleAfterValue": "100000", 1890 "UMask": "0x1" 1891 }, 1892 { 1893 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE", 1894 "Counter": "0,1,2,3", 1895 "EventCode": "0xB7, 0xBB", 1896 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", 1897 "MSRIndex": "0x1a6,0x1a7", 1898 "MSRValue": "0x704", 1899 "SampleAfterValue": "100000", 1900 "UMask": "0x1" 1901 }, 1902 { 1903 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1904 "Counter": "0,1,2,3", 1905 "EventCode": "0xB7, 0xBB", 1906 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1907 "MSRIndex": "0x1a6,0x1a7", 1908 "MSRValue": "0x1004", 1909 "SampleAfterValue": "100000", 1910 "UMask": "0x1" 1911 }, 1912 { 1913 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM", 1914 "Counter": "0,1,2,3", 1915 "EventCode": "0xB7, 0xBB", 1916 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", 1917 "MSRIndex": "0x1a6,0x1a7", 1918 "MSRValue": "0x804", 1919 "SampleAfterValue": "100000", 1920 "UMask": "0x1" 1921 }, 1922 { 1923 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1924 "Counter": "0,1,2,3", 1925 "EventCode": "0xB7, 0xBB", 1926 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1927 "MSRIndex": "0x1a6,0x1a7", 1928 "MSRValue": "0x5002", 1929 "SampleAfterValue": "100000", 1930 "UMask": "0x1" 1931 }, 1932 { 1933 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM", 1934 "Counter": "0,1,2,3", 1935 "EventCode": "0xB7, 0xBB", 1936 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", 1937 "MSRIndex": "0x1a6,0x1a7", 1938 "MSRValue": "0x7f02", 1939 "SampleAfterValue": "100000", 1940 "UMask": "0x1" 1941 }, 1942 { 1943 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION", 1944 "Counter": "0,1,2,3", 1945 "EventCode": "0xB7, 0xBB", 1946 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", 1947 "MSRIndex": "0x1a6,0x1a7", 1948 "MSRValue": "0xff02", 1949 "SampleAfterValue": "100000", 1950 "UMask": "0x1" 1951 }, 1952 { 1953 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO", 1954 "Counter": "0,1,2,3", 1955 "EventCode": "0xB7, 0xBB", 1956 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", 1957 "MSRIndex": "0x1a6,0x1a7", 1958 "MSRValue": "0x8002", 1959 "SampleAfterValue": "100000", 1960 "UMask": "0x1" 1961 }, 1962 { 1963 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1964 "Counter": "0,1,2,3", 1965 "EventCode": "0xB7, 0xBB", 1966 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", 1967 "MSRIndex": "0x1a6,0x1a7", 1968 "MSRValue": "0x102", 1969 "SampleAfterValue": "100000", 1970 "UMask": "0x1" 1971 }, 1972 { 1973 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1974 "Counter": "0,1,2,3", 1975 "EventCode": "0xB7, 0xBB", 1976 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", 1977 "MSRIndex": "0x1a6,0x1a7", 1978 "MSRValue": "0x202", 1979 "SampleAfterValue": "100000", 1980 "UMask": "0x1" 1981 }, 1982 { 1983 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1984 "Counter": "0,1,2,3", 1985 "EventCode": "0xB7, 0xBB", 1986 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", 1987 "MSRIndex": "0x1a6,0x1a7", 1988 "MSRValue": "0x402", 1989 "SampleAfterValue": "100000", 1990 "UMask": "0x1" 1991 }, 1992 { 1993 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE", 1994 "Counter": "0,1,2,3", 1995 "EventCode": "0xB7, 0xBB", 1996 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", 1997 "MSRIndex": "0x1a6,0x1a7", 1998 "MSRValue": "0x702", 1999 "SampleAfterValue": "100000", 2000 "UMask": "0x1" 2001 }, 2002 { 2003 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2004 "Counter": "0,1,2,3", 2005 "EventCode": "0xB7, 0xBB", 2006 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2007 "MSRIndex": "0x1a6,0x1a7", 2008 "MSRValue": "0x1002", 2009 "SampleAfterValue": "100000", 2010 "UMask": "0x1" 2011 }, 2012 { 2013 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM", 2014 "Counter": "0,1,2,3", 2015 "EventCode": "0xB7, 0xBB", 2016 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", 2017 "MSRIndex": "0x1a6,0x1a7", 2018 "MSRValue": "0x802", 2019 "SampleAfterValue": "100000", 2020 "UMask": "0x1" 2021 }, 2022 { 2023 "BriefDescription": "REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 2024 "Counter": "0,1,2,3", 2025 "EventCode": "0xB7, 0xBB", 2026 "EventName": "OFFCORE_RESPONSE.OTHER.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2027 "MSRIndex": "0x1a6,0x1a7", 2028 "MSRValue": "0x5080", 2029 "SampleAfterValue": "100000", 2030 "UMask": "0x1" 2031 }, 2032 { 2033 "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM", 2034 "Counter": "0,1,2,3", 2035 "EventCode": "0xB7, 0xBB", 2036 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", 2037 "MSRIndex": "0x1a6,0x1a7", 2038 "MSRValue": "0x7f80", 2039 "SampleAfterValue": "100000", 2040 "UMask": "0x1" 2041 }, 2042 { 2043 "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LOCATION", 2044 "Counter": "0,1,2,3", 2045 "EventCode": "0xB7, 0xBB", 2046 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", 2047 "MSRIndex": "0x1a6,0x1a7", 2048 "MSRValue": "0xff80", 2049 "SampleAfterValue": "100000", 2050 "UMask": "0x1" 2051 }, 2052 { 2053 "BriefDescription": "REQUEST = OTHER and RESPONSE = IO_CSR_MMIO", 2054 "Counter": "0,1,2,3", 2055 "EventCode": "0xB7, 0xBB", 2056 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", 2057 "MSRIndex": "0x1a6,0x1a7", 2058 "MSRValue": "0x8080", 2059 "SampleAfterValue": "100000", 2060 "UMask": "0x1" 2061 }, 2062 { 2063 "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE", 2064 "Counter": "0,1,2,3", 2065 "EventCode": "0xB7, 0xBB", 2066 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", 2067 "MSRIndex": "0x1a6,0x1a7", 2068 "MSRValue": "0x180", 2069 "SampleAfterValue": "100000", 2070 "UMask": "0x1" 2071 }, 2072 { 2073 "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 2074 "Counter": "0,1,2,3", 2075 "EventCode": "0xB7, 0xBB", 2076 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", 2077 "MSRIndex": "0x1a6,0x1a7", 2078 "MSRValue": "0x280", 2079 "SampleAfterValue": "100000", 2080 "UMask": "0x1" 2081 }, 2082 { 2083 "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 2084 "Counter": "0,1,2,3", 2085 "EventCode": "0xB7, 0xBB", 2086 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", 2087 "MSRIndex": "0x1a6,0x1a7", 2088 "MSRValue": "0x480", 2089 "SampleAfterValue": "100000", 2090 "UMask": "0x1" 2091 }, 2092 { 2093 "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_CACHE", 2094 "Counter": "0,1,2,3", 2095 "EventCode": "0xB7, 0xBB", 2096 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", 2097 "MSRIndex": "0x1a6,0x1a7", 2098 "MSRValue": "0x780", 2099 "SampleAfterValue": "100000", 2100 "UMask": "0x1" 2101 }, 2102 { 2103 "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2104 "Counter": "0,1,2,3", 2105 "EventCode": "0xB7, 0xBB", 2106 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2107 "MSRIndex": "0x1a6,0x1a7", 2108 "MSRValue": "0x1080", 2109 "SampleAfterValue": "100000", 2110 "UMask": "0x1" 2111 }, 2112 { 2113 "BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM", 2114 "Counter": "0,1,2,3", 2115 "EventCode": "0xB7, 0xBB", 2116 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", 2117 "MSRIndex": "0x1a6,0x1a7", 2118 "MSRValue": "0x880", 2119 "SampleAfterValue": "100000", 2120 "UMask": "0x1" 2121 }, 2122 { 2123 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 2124 "Counter": "0,1,2,3", 2125 "EventCode": "0xB7, 0xBB", 2126 "EventName": "OFFCORE_RESPONSE.PF_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2127 "MSRIndex": "0x1a6,0x1a7", 2128 "MSRValue": "0x5050", 2129 "SampleAfterValue": "100000", 2130 "UMask": "0x1" 2131 }, 2132 { 2133 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM", 2134 "Counter": "0,1,2,3", 2135 "EventCode": "0xB7, 0xBB", 2136 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", 2137 "MSRIndex": "0x1a6,0x1a7", 2138 "MSRValue": "0x7f50", 2139 "SampleAfterValue": "100000", 2140 "UMask": "0x1" 2141 }, 2142 { 2143 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LOCATION", 2144 "Counter": "0,1,2,3", 2145 "EventCode": "0xB7, 0xBB", 2146 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", 2147 "MSRIndex": "0x1a6,0x1a7", 2148 "MSRValue": "0xff50", 2149 "SampleAfterValue": "100000", 2150 "UMask": "0x1" 2151 }, 2152 { 2153 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO", 2154 "Counter": "0,1,2,3", 2155 "EventCode": "0xB7, 0xBB", 2156 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", 2157 "MSRIndex": "0x1a6,0x1a7", 2158 "MSRValue": "0x8050", 2159 "SampleAfterValue": "100000", 2160 "UMask": "0x1" 2161 }, 2162 { 2163 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE", 2164 "Counter": "0,1,2,3", 2165 "EventCode": "0xB7, 0xBB", 2166 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", 2167 "MSRIndex": "0x1a6,0x1a7", 2168 "MSRValue": "0x150", 2169 "SampleAfterValue": "100000", 2170 "UMask": "0x1" 2171 }, 2172 { 2173 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 2174 "Counter": "0,1,2,3", 2175 "EventCode": "0xB7, 0xBB", 2176 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", 2177 "MSRIndex": "0x1a6,0x1a7", 2178 "MSRValue": "0x250", 2179 "SampleAfterValue": "100000", 2180 "UMask": "0x1" 2181 }, 2182 { 2183 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 2184 "Counter": "0,1,2,3", 2185 "EventCode": "0xB7, 0xBB", 2186 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", 2187 "MSRIndex": "0x1a6,0x1a7", 2188 "MSRValue": "0x450", 2189 "SampleAfterValue": "100000", 2190 "UMask": "0x1" 2191 }, 2192 { 2193 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE", 2194 "Counter": "0,1,2,3", 2195 "EventCode": "0xB7, 0xBB", 2196 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", 2197 "MSRIndex": "0x1a6,0x1a7", 2198 "MSRValue": "0x750", 2199 "SampleAfterValue": "100000", 2200 "UMask": "0x1" 2201 }, 2202 { 2203 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2204 "Counter": "0,1,2,3", 2205 "EventCode": "0xB7, 0xBB", 2206 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2207 "MSRIndex": "0x1a6,0x1a7", 2208 "MSRValue": "0x1050", 2209 "SampleAfterValue": "100000", 2210 "UMask": "0x1" 2211 }, 2212 { 2213 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM", 2214 "Counter": "0,1,2,3", 2215 "EventCode": "0xB7, 0xBB", 2216 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", 2217 "MSRIndex": "0x1a6,0x1a7", 2218 "MSRValue": "0x850", 2219 "SampleAfterValue": "100000", 2220 "UMask": "0x1" 2221 }, 2222 { 2223 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 2224 "Counter": "0,1,2,3", 2225 "EventCode": "0xB7, 0xBB", 2226 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2227 "MSRIndex": "0x1a6,0x1a7", 2228 "MSRValue": "0x5010", 2229 "SampleAfterValue": "100000", 2230 "UMask": "0x1" 2231 }, 2232 { 2233 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM", 2234 "Counter": "0,1,2,3", 2235 "EventCode": "0xB7, 0xBB", 2236 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", 2237 "MSRIndex": "0x1a6,0x1a7", 2238 "MSRValue": "0x7f10", 2239 "SampleAfterValue": "100000", 2240 "UMask": "0x1" 2241 }, 2242 { 2243 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION", 2244 "Counter": "0,1,2,3", 2245 "EventCode": "0xB7, 0xBB", 2246 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", 2247 "MSRIndex": "0x1a6,0x1a7", 2248 "MSRValue": "0xff10", 2249 "SampleAfterValue": "100000", 2250 "UMask": "0x1" 2251 }, 2252 { 2253 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO", 2254 "Counter": "0,1,2,3", 2255 "EventCode": "0xB7, 0xBB", 2256 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", 2257 "MSRIndex": "0x1a6,0x1a7", 2258 "MSRValue": "0x8010", 2259 "SampleAfterValue": "100000", 2260 "UMask": "0x1" 2261 }, 2262 { 2263 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE", 2264 "Counter": "0,1,2,3", 2265 "EventCode": "0xB7, 0xBB", 2266 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", 2267 "MSRIndex": "0x1a6,0x1a7", 2268 "MSRValue": "0x110", 2269 "SampleAfterValue": "100000", 2270 "UMask": "0x1" 2271 }, 2272 { 2273 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 2274 "Counter": "0,1,2,3", 2275 "EventCode": "0xB7, 0xBB", 2276 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 2277 "MSRIndex": "0x1a6,0x1a7", 2278 "MSRValue": "0x210", 2279 "SampleAfterValue": "100000", 2280 "UMask": "0x1" 2281 }, 2282 { 2283 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 2284 "Counter": "0,1,2,3", 2285 "EventCode": "0xB7, 0xBB", 2286 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2287 "MSRIndex": "0x1a6,0x1a7", 2288 "MSRValue": "0x410", 2289 "SampleAfterValue": "100000", 2290 "UMask": "0x1" 2291 }, 2292 { 2293 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE", 2294 "Counter": "0,1,2,3", 2295 "EventCode": "0xB7, 0xBB", 2296 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", 2297 "MSRIndex": "0x1a6,0x1a7", 2298 "MSRValue": "0x710", 2299 "SampleAfterValue": "100000", 2300 "UMask": "0x1" 2301 }, 2302 { 2303 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2304 "Counter": "0,1,2,3", 2305 "EventCode": "0xB7, 0xBB", 2306 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2307 "MSRIndex": "0x1a6,0x1a7", 2308 "MSRValue": "0x1010", 2309 "SampleAfterValue": "100000", 2310 "UMask": "0x1" 2311 }, 2312 { 2313 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM", 2314 "Counter": "0,1,2,3", 2315 "EventCode": "0xB7, 0xBB", 2316 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", 2317 "MSRIndex": "0x1a6,0x1a7", 2318 "MSRValue": "0x810", 2319 "SampleAfterValue": "100000", 2320 "UMask": "0x1" 2321 }, 2322 { 2323 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 2324 "Counter": "0,1,2,3", 2325 "EventCode": "0xB7, 0xBB", 2326 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2327 "MSRIndex": "0x1a6,0x1a7", 2328 "MSRValue": "0x5040", 2329 "SampleAfterValue": "100000", 2330 "UMask": "0x1" 2331 }, 2332 { 2333 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM", 2334 "Counter": "0,1,2,3", 2335 "EventCode": "0xB7, 0xBB", 2336 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", 2337 "MSRIndex": "0x1a6,0x1a7", 2338 "MSRValue": "0x7f40", 2339 "SampleAfterValue": "100000", 2340 "UMask": "0x1" 2341 }, 2342 { 2343 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LOCATION", 2344 "Counter": "0,1,2,3", 2345 "EventCode": "0xB7, 0xBB", 2346 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", 2347 "MSRIndex": "0x1a6,0x1a7", 2348 "MSRValue": "0xff40", 2349 "SampleAfterValue": "100000", 2350 "UMask": "0x1" 2351 }, 2352 { 2353 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO", 2354 "Counter": "0,1,2,3", 2355 "EventCode": "0xB7, 0xBB", 2356 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", 2357 "MSRIndex": "0x1a6,0x1a7", 2358 "MSRValue": "0x8040", 2359 "SampleAfterValue": "100000", 2360 "UMask": "0x1" 2361 }, 2362 { 2363 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE", 2364 "Counter": "0,1,2,3", 2365 "EventCode": "0xB7, 0xBB", 2366 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", 2367 "MSRIndex": "0x1a6,0x1a7", 2368 "MSRValue": "0x140", 2369 "SampleAfterValue": "100000", 2370 "UMask": "0x1" 2371 }, 2372 { 2373 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 2374 "Counter": "0,1,2,3", 2375 "EventCode": "0xB7, 0xBB", 2376 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2377 "MSRIndex": "0x1a6,0x1a7", 2378 "MSRValue": "0x240", 2379 "SampleAfterValue": "100000", 2380 "UMask": "0x1" 2381 }, 2382 { 2383 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 2384 "Counter": "0,1,2,3", 2385 "EventCode": "0xB7, 0xBB", 2386 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2387 "MSRIndex": "0x1a6,0x1a7", 2388 "MSRValue": "0x440", 2389 "SampleAfterValue": "100000", 2390 "UMask": "0x1" 2391 }, 2392 { 2393 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE", 2394 "Counter": "0,1,2,3", 2395 "EventCode": "0xB7, 0xBB", 2396 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", 2397 "MSRIndex": "0x1a6,0x1a7", 2398 "MSRValue": "0x740", 2399 "SampleAfterValue": "100000", 2400 "UMask": "0x1" 2401 }, 2402 { 2403 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2404 "Counter": "0,1,2,3", 2405 "EventCode": "0xB7, 0xBB", 2406 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2407 "MSRIndex": "0x1a6,0x1a7", 2408 "MSRValue": "0x1040", 2409 "SampleAfterValue": "100000", 2410 "UMask": "0x1" 2411 }, 2412 { 2413 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM", 2414 "Counter": "0,1,2,3", 2415 "EventCode": "0xB7, 0xBB", 2416 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", 2417 "MSRIndex": "0x1a6,0x1a7", 2418 "MSRValue": "0x840", 2419 "SampleAfterValue": "100000", 2420 "UMask": "0x1" 2421 }, 2422 { 2423 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 2424 "Counter": "0,1,2,3", 2425 "EventCode": "0xB7, 0xBB", 2426 "EventName": "OFFCORE_RESPONSE.PF_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2427 "MSRIndex": "0x1a6,0x1a7", 2428 "MSRValue": "0x5020", 2429 "SampleAfterValue": "100000", 2430 "UMask": "0x1" 2431 }, 2432 { 2433 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM", 2434 "Counter": "0,1,2,3", 2435 "EventCode": "0xB7, 0xBB", 2436 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", 2437 "MSRIndex": "0x1a6,0x1a7", 2438 "MSRValue": "0x7f20", 2439 "SampleAfterValue": "100000", 2440 "UMask": "0x1" 2441 }, 2442 { 2443 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION", 2444 "Counter": "0,1,2,3", 2445 "EventCode": "0xB7, 0xBB", 2446 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", 2447 "MSRIndex": "0x1a6,0x1a7", 2448 "MSRValue": "0xff20", 2449 "SampleAfterValue": "100000", 2450 "UMask": "0x1" 2451 }, 2452 { 2453 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO", 2454 "Counter": "0,1,2,3", 2455 "EventCode": "0xB7, 0xBB", 2456 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", 2457 "MSRIndex": "0x1a6,0x1a7", 2458 "MSRValue": "0x8020", 2459 "SampleAfterValue": "100000", 2460 "UMask": "0x1" 2461 }, 2462 { 2463 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", 2464 "Counter": "0,1,2,3", 2465 "EventCode": "0xB7, 0xBB", 2466 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", 2467 "MSRIndex": "0x1a6,0x1a7", 2468 "MSRValue": "0x120", 2469 "SampleAfterValue": "100000", 2470 "UMask": "0x1" 2471 }, 2472 { 2473 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 2474 "Counter": "0,1,2,3", 2475 "EventCode": "0xB7, 0xBB", 2476 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", 2477 "MSRIndex": "0x1a6,0x1a7", 2478 "MSRValue": "0x220", 2479 "SampleAfterValue": "100000", 2480 "UMask": "0x1" 2481 }, 2482 { 2483 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 2484 "Counter": "0,1,2,3", 2485 "EventCode": "0xB7, 0xBB", 2486 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", 2487 "MSRIndex": "0x1a6,0x1a7", 2488 "MSRValue": "0x420", 2489 "SampleAfterValue": "100000", 2490 "UMask": "0x1" 2491 }, 2492 { 2493 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE", 2494 "Counter": "0,1,2,3", 2495 "EventCode": "0xB7, 0xBB", 2496 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", 2497 "MSRIndex": "0x1a6,0x1a7", 2498 "MSRValue": "0x720", 2499 "SampleAfterValue": "100000", 2500 "UMask": "0x1" 2501 }, 2502 { 2503 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2504 "Counter": "0,1,2,3", 2505 "EventCode": "0xB7, 0xBB", 2506 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2507 "MSRIndex": "0x1a6,0x1a7", 2508 "MSRValue": "0x1020", 2509 "SampleAfterValue": "100000", 2510 "UMask": "0x1" 2511 }, 2512 { 2513 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM", 2514 "Counter": "0,1,2,3", 2515 "EventCode": "0xB7, 0xBB", 2516 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", 2517 "MSRIndex": "0x1a6,0x1a7", 2518 "MSRValue": "0x820", 2519 "SampleAfterValue": "100000", 2520 "UMask": "0x1" 2521 }, 2522 { 2523 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 2524 "Counter": "0,1,2,3", 2525 "EventCode": "0xB7, 0xBB", 2526 "EventName": "OFFCORE_RESPONSE.PREFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2527 "MSRIndex": "0x1a6,0x1a7", 2528 "MSRValue": "0x5070", 2529 "SampleAfterValue": "100000", 2530 "UMask": "0x1" 2531 }, 2532 { 2533 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM", 2534 "Counter": "0,1,2,3", 2535 "EventCode": "0xB7, 0xBB", 2536 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", 2537 "MSRIndex": "0x1a6,0x1a7", 2538 "MSRValue": "0x7f70", 2539 "SampleAfterValue": "100000", 2540 "UMask": "0x1" 2541 }, 2542 { 2543 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LOCATION", 2544 "Counter": "0,1,2,3", 2545 "EventCode": "0xB7, 0xBB", 2546 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", 2547 "MSRIndex": "0x1a6,0x1a7", 2548 "MSRValue": "0xff70", 2549 "SampleAfterValue": "100000", 2550 "UMask": "0x1" 2551 }, 2552 { 2553 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO", 2554 "Counter": "0,1,2,3", 2555 "EventCode": "0xB7, 0xBB", 2556 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", 2557 "MSRIndex": "0x1a6,0x1a7", 2558 "MSRValue": "0x8070", 2559 "SampleAfterValue": "100000", 2560 "UMask": "0x1" 2561 }, 2562 { 2563 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", 2564 "Counter": "0,1,2,3", 2565 "EventCode": "0xB7, 0xBB", 2566 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", 2567 "MSRIndex": "0x1a6,0x1a7", 2568 "MSRValue": "0x170", 2569 "SampleAfterValue": "100000", 2570 "UMask": "0x1" 2571 }, 2572 { 2573 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 2574 "Counter": "0,1,2,3", 2575 "EventCode": "0xB7, 0xBB", 2576 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", 2577 "MSRIndex": "0x1a6,0x1a7", 2578 "MSRValue": "0x270", 2579 "SampleAfterValue": "100000", 2580 "UMask": "0x1" 2581 }, 2582 { 2583 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 2584 "Counter": "0,1,2,3", 2585 "EventCode": "0xB7, 0xBB", 2586 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", 2587 "MSRIndex": "0x1a6,0x1a7", 2588 "MSRValue": "0x470", 2589 "SampleAfterValue": "100000", 2590 "UMask": "0x1" 2591 }, 2592 { 2593 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE", 2594 "Counter": "0,1,2,3", 2595 "EventCode": "0xB7, 0xBB", 2596 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", 2597 "MSRIndex": "0x1a6,0x1a7", 2598 "MSRValue": "0x770", 2599 "SampleAfterValue": "100000", 2600 "UMask": "0x1" 2601 }, 2602 { 2603 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2604 "Counter": "0,1,2,3", 2605 "EventCode": "0xB7, 0xBB", 2606 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2607 "MSRIndex": "0x1a6,0x1a7", 2608 "MSRValue": "0x1070", 2609 "SampleAfterValue": "100000", 2610 "UMask": "0x1" 2611 }, 2612 { 2613 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM", 2614 "Counter": "0,1,2,3", 2615 "EventCode": "0xB7, 0xBB", 2616 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", 2617 "MSRIndex": "0x1a6,0x1a7", 2618 "MSRValue": "0x870", 2619 "SampleAfterValue": "100000", 2620 "UMask": "0x1" 2621 }, 2622 { 2623 "BriefDescription": "Super Queue LRU hints sent to LLC", 2624 "Counter": "0,1,2,3", 2625 "EventCode": "0xF4", 2626 "EventName": "SQ_MISC.LRU_HINTS", 2627 "SampleAfterValue": "2000000", 2628 "UMask": "0x4" 2629 }, 2630 { 2631 "BriefDescription": "Super Queue lock splits across a cache line", 2632 "Counter": "0,1,2,3", 2633 "EventCode": "0xF4", 2634 "EventName": "SQ_MISC.SPLIT_LOCK", 2635 "SampleAfterValue": "2000000", 2636 "UMask": "0x10" 2637 }, 2638 { 2639 "BriefDescription": "Loads delayed with at-Retirement block code", 2640 "Counter": "0,1,2,3", 2641 "EventCode": "0x6", 2642 "EventName": "STORE_BLOCKS.AT_RET", 2643 "SampleAfterValue": "200000", 2644 "UMask": "0x4" 2645 }, 2646 { 2647 "BriefDescription": "Cacheable loads delayed with L1D block code", 2648 "Counter": "0,1,2,3", 2649 "EventCode": "0x6", 2650 "EventName": "STORE_BLOCKS.L1D_BLOCK", 2651 "SampleAfterValue": "200000", 2652 "UMask": "0x8" 2653 } 2654] 2655